PPG33F DATADELAY | Alldatasheet

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Technical content

(SERIES PPG33F) data delay devices, inc.

FEATURES

Digitally programmable in 7 steps TRIG N/C OUT N/C N/C N/C RES GND VCC OUT/ N/C N/C N/C Monotonic pulse-width-vs-address variation TRIG OUT N/C N/C N/C RES GND VCC OUT/ N/C N/C Rising edge triggered Two separate outputs: inverting & non-inverting Precise and stable pulse width Input & outputs fully TTL interfaced & buffered

10 T2L fan-out capability

Fits standard 14-pin DIP socket Auto-insertable DIP PPG33F-xx Commercial PPG33F-xxM Military Gull-Wing PPG33F-xxC3 Commercial PPG33F-xxMC3 Military FUNCTIONAL DESCRIPTION The PPG33F-series device is a 3-bit digitally programmable pulse generator. The width, PWA, depends on the address code (A2-A0) according to the following formula: PWA = PW0 + TINC * A where A is the address code, TINC is the incremental pulse width of the device, and PW0 is the inherent pulse width of the device. The incremental width is specified by the dash number of the device and can range from 0.5ns through 50ns, inclusively. RESET is held LOW during normal operation. When it is brought HIGH, OUT and OUT/ are forced into LOW and HIGH states, respectively, and the unit is ready for the next trigger input. The address is not latched and must remain asserted while the output pulse is active. PIN DESCRIPTIONS TRIG Trigger Input OUT Non-inverted Output OUT/ Inverted Output A0-A2 Address Bits RES Reset VCC +5 Volts GND Ground SERIES SPECIFICATIONS DASH NUMBER SPECIFICATIONS Part Number Incremental Width Per Step (ns) Total Width Change (ns) PPG33F-.5 0.5 ± 0.3 3.50 ± 1.00 PPG33F-1 1 ± 0.4 7.00 ± 1.00 PPG33F-2 2 ± 0.4 14.0 ± 1.00 PPG33F-3 3 ± 0.5 21.0 ± 1.05 PPG33F-4 4 ± 0.5 28.0 ± 1.40 PPG33F-5 5 ± 0.6 35.0 ± 1.75 PPG33F-6 6 ± 0.7 42.0 ± 2.10 PPG33F-8 8 ± 0.8 56.0 ± 2.80 PPG33F-10 10 ± 1.0 70.0 ± 3.50 PPG33F-20 20 ± 1.5 140 ± 7.00 PPG33F-30 30 ± 1.8 210 ± 10.5 PPG33F-40 40 ± 2.0 280 ± 14.0 PPG33F-50 50 ± 2.5 350 ± 17.5 NOTE: Any dash number between .5 and 50 not shown is also available. Programmed pulse width tolerance: 5% or 1ns, whichever is greater Inherent width (PW0): 9ns typical Inherent delay (TTO): 3.5ns ± 2ns Operating temperature: 0° to 70° C Supply voltage VCC: 5VDC ± 5% Supply current: ICC = 41ma typical 1997 Data Delay Devices Doc #97010 DATA DELAY DEVICES, INC. 1/15/97 3 Mt. Prospect Ave. Clifton, NJ 07013

The timing definitions and restrictions for the PPG33F are shown in Figure 1. The unit is activated by a rising edge on the TRIG input. After a time, TTO (called the inherent delay), the rising edge of the pulse appears at OUT. The duration of the pulse is given by the above equation. For the duration of the pulse, the device ignores subsequent triggers. Once the falling edge of the pulse has appeared at OUT, an additional time, TOTR, is required before the device can respond to the next trigger. At power-up, the state of the PPG33F is unknown. Consequently, after power is applied, the unit may not respond to input triggers for a time equal to the maximum pulse width, PWT. After this time, the unit will function properly. If your application requires that the device function immediately, issue a quick reset at power-up. POWER SUPPLY BYPASSING The PPG33F relies on a stable power supply to produce repeatable pulses within the stated tolerances. A 0.1uf capacitor from VCC to GND, located as close as possible to each VCC pin, is recommended. A wide VCC trace should connect all VCC pins externally, and a clean ground plane should be used. INCREMENT TOLERANCES Please note that the increment tolerances listed represent a design goal. Although most increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. Monotonicity is, however, guaranteed over all addresses. TOAX TRTS TTW TTO PWA A2-A0 RES TRIG OUT OUT/ Figure 1: Timing Diagram A i Ai+1 TSKEW TATS TRO TOTR TTW TRW Doc #97010 DATA DELAY DEVICES, INC. 1/15/97 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

TABLE 1: AC CHARACTERISTICS PARAMETER SYMBOL MIN TYP MAX UNITS Total Programmable Pulse Width PWT TINC Inherent Pulse Width PW0 6.0 9.0 12.0 ns Trigger to Output Delay TTO 1.5 3.5 5.5 ns Reset to Output Delay TRO 17.0 ns Output Skew TSKEW 1.5 ns Trigger Pulse Width TTW 5.0 ns Reset Pulse Width TRW 10.0 ns Reset to Trigger Setup Time TRTS 9.0 ns Address to Trigger Setup Time TATS 6.0 ns Output Low to Address Change TOAX 0.0 ns Output to Trigger Recovery Time TOTR % of PWT* *or 10ns, whichever is greater TABLE 2: ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN MAX UNITS NOTES DC Supply Voltage VCC -0.3 7.0 V Input Pin Voltage VIN -0.3 VDD+0.3 V Storage Temperature TSTRG -55 150 C Lead Temperature TLEAD 300 C 10 sec TABLE 3: DC ELECTRICAL CHARACTERISTICS (0C to 70C, 4.75V to 5.25V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES High Level Output Voltage VOH 2.5 3.4 V VCC = MIN, IOH = MAX VIH = MIN, VIL = MAX Low Level Output Voltage VOL 0.35 0.5 V VCC = MIN, IOL = MAX VIH = MIN, VIL = MAX High Level Output Current IOH -1.0 mA Low Level Output Current IOL 20.0 mA High Level Input Voltage VIH 2.0 V Low Level Input Voltage VIL 0.8 V Input Clamp Voltage VIK -1.2 V VCC = MIN, II = IIK Input Current at Maximum Input Voltage IIHH 0.1 mA VCC = MAX, VI = 7.0V High Level Input Current IIH µA VCC = MAX, VI = 2.7V Low Level Input Current IIL -0.6 mA VCC = MAX, VI = 0.5V Short-circuit Output Current IOS -60 -150 mA VCC = MAX Output High Fan-out Unit Output Low Fan-out 12.5 Load Doc #97010 DATA DELAY DEVICES, INC. 1/15/97 3 Mt. Prospect Ave. Clifton, NJ 07013

.195 ±.010 .830 MAX. .290 MAX. .020 TYP. .440 MAX. .300 TYP. .010 TYP. .600 TYP. .030 ±.005 DIP (PPG33F-xx, PPG33F-xxM) .880±.020 .882 ±.005 .020 TYP. .040 TYP. .100 .090 .700 .280 MAX. .590 MAX. .010±.002 .050 ±.010 .710 ±.005 .007 ±.005 Gull-Wing (PPG33F-xxC3, PPG33F-xxMC3) Doc #97010 DATA DELAY DEVICES, INC. 1/15/97 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: OUTPUT: Ambient Temperature: 25oC ± 3oC Load:

1 FAST-TTL Gate

Supply Voltage (Vcc): 5.0V ± 0.1V Cload: 5pf ± 10% Input Pulse: High = 3.0V ± 0.1V Threshold: 1.5V (Rising & Falling) Low = 0.0V ± 0.1V Source Impedance: 50Ω Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V ) Pulse Width: PWIN = 10ns Period: PERIN = 2 x Max. Pulse Width NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. OUT OUT TRIG IN REF TRIG Test Setup DEVICE UNDER TEST (DUT) TIME INTERVAL COUNTER PULSE GENERATOR COMPUTER SYSTEM PRINTER IN Timing Diagram For Testing TTO PWA PERIN PWIN TRISE TFALL 0.6V 0.6V 1.5V 1.5V 2.4V 2.4V 1.5V 1.5V VIH VIL VOH VOL INPUT SIGNAL OUTPUT SIGNAL Doc #97010 DATA DELAY DEVICES, INC. 1/15/97 3 Mt. Prospect Ave. Clifton, NJ 07013