PPG323F DATADELAY | Alldatasheet
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Doc #14016 DATA DELAY DEVICES, INC. 1 6/9/2014 3 Mt. Prospect Ave. Clifton, NJ 07013 23-BIT CRYSTAL-STABILIZED PULSE GENERATOR (SERIES PPG323F) FEATURES PINOUT Digitally programmable in 8,388,608 steps Monotonic pulse-width-vs-address variation Rising edge triggered Precise and stable pulse width Low jitter over entire programmable range Input & outputs fully TTL interfaced & buffered 10 T2L fan-out capability FUNCTIONAL DESCRIPTION The PPG323F-series device is a 23-bit digitally programmable pulse generator. The width, PWA, depends on the address code (A22-A0) according to the following formula: PWA = PW0 + TINC * A where A is the address code, TINC is the incremental pulse width of the device, and PW0 is the inherent pulse width of the device. The incremental width is specified by the dash number of the device and can range from 20ns through 5us, inclusively. RES is held LOW during normal operation. When it is brought HIGH, OUT is forced into a LOW state, and the unit is ready for the next trigger input. The address is not latched and must remain asserted while the output pulse is active. The PPG323F is crystal-stabilized, providing low jitter (350ps RMS) over the entire address range. SERIES SPECIFICATIONS Pulse width tolerance: 0.05% or 100ps, whichever is greater Inherent width (PW0): 100ns typical Inherent delay (TTO): 10ns typical Operating temperature: -40 to 85 C Supply voltage VCC: 5VDC 5% Supply current: ICC = 200ma typical 2014 Data Delay Devices PIN DESCRIPTIONS TRIG Trigger Input OUT Pulse Output A0-A22 Address Bits VCC +5 Volts GND Ground DASH NUMBER SPECIFICATIONS Part Number Incremental Width Per Step (ns) Total Width Change (sec) PPG323F-20 20 0.16777 PPG323F-50 50 0.41943 PPG323F-100 100 0.83886 PPG323F-200 200 1.6777 PPG323F-500 500 4.1943 PPG323F-1000 1000 8.3886 PPG323F-2000 2000 16.777 PPG323F-5000 5000 41.943 NOTE: Any dash number between 20 and 5000 not shown is also available. A11 A10 OUT IN GND A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 RES VCC
Doc #14016 DATA DELAY DEVICES, INC. 2 6/9/2014 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com APPLICATION NOTES DEVICE TIMING The timing definitions and restrictions for the PPG323F are shown in Figure 1. The unit is activated by a rising edge on the TRIG input. After a time, TTO (called the inherent delay), the rising edge of the pulse appears at OUT. The duration of the pulse is given by the above equation. For the duration of the pulse, the device ignores subsequent triggers. Once the falling edge of the pulse has appeared at OUT, an additional time, TOTR, is required before the device can respond to the next trigger. At power-up, the state of the PPG323F is unknown. Consequently, after power is applied, the unit may not respond to input triggers for a time equal to the maximum pulse width, PWT. After this time, the unit will function properly. If your application requires that the device function immediately, issue a quick reset at power-up. POWER SUPPLY BYPASSING The PPG323F relies on a stable power supply to produce repeatable pulses within the stated tolerances. A 0.1uf capacitor from VCC to GND, located as close as possible to the VCC pin, is recommended. A wide VCC trace should connect the VCC pin externally, and a clean ground plane should be used. TRTS TTW TTO A22:0 RES TRIG OUT Figure 1: Timing Diagram A i Ai+1 TTW TOAX PWA TATS TTO TRO TOTR TRW
Doc #14016 DATA DELAY DEVICES, INC. 3 6/9/2014 3 Mt. Prospect Ave. Clifton, NJ 07013 DEVICE SPECIFICATIONS TABLE 1: AC CHARACTERISTICS PARAMETER SYMBOL MIN TYP MAX UNITS Total Programmable Pulse Width PWT 8,388,608 TINC Inherent Pulse Width PW0 100.0 ns Trigger to Output Delay TTO 10.0 ns Reset to Output Delay TRO 17.0 ns Output Skew TSKEW 1.5 ns Trigger Pulse Width TTW 5.0 ns Reset Pulse Width TRW 10.0 ns Reset to Trigger Setup Time TRTS 9.0 ns Address to Trigger Setup Time TATS 6.0 ns Output Low to Address Change TOAX 0.0 ns Output to Trigger Recovery Time TOTR 10.0 ns TABLE 2: ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN MAX UNITS NOTES DC Supply Voltage VCC -0.3 7.0 V Input Pin Voltage VIN -0.3 VDD+0.3 V Storage Temperature TSTRG -55 150 C Lead Temperature TLEAD 300 C 10 sec TABLE 3: DC ELECTRICAL CHARACTERISTICS (0C to 70C, 4.75V to 5.25V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES High Level Output Voltage VOH 2.5 3.4 V VCC = MIN, IOH = MAX VIH = MIN, VIL = MAX Low Level Output Voltage VOL 0.35 0.5 V VCC = MIN, IOL = MAX VIH = MIN, VIL = MAX High Level Output Current IOH -1.0 mA Low Level Output Current IOL 20.0 mA High Level Input Voltage VIH 2.0 V Low Level Input Voltage VIL 0.8 V Input Clamp Voltage VIK -1.2 V VCC = MIN, II = IIK Input Current at Maximum Input Voltage IIHH 0.1 mA VCC = MAX, VI = 7.0V High Level Input Current IIH 20 A VCC = MAX, VI = 2.7V Low Level Input Current IIL -0.6 mA VCC = MAX, VI = 0.5V Short-circuit Output Current IOS -60 -150 mA VCC = MAX Output High Fan-out 25 Unit Output Low Fan-out 12.5 Load
Doc #14016 DATA DELAY DEVICES, INC. 4 6/9/2014 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com PACKAGE DIMENSIONS 2.000 0.370 0.100 (26 places) 2.000 0.130 1.800 0.027 x 0.027 (28 places) 0.240 0.500
Doc #14016 DATA DELAY DEVICES, INC. 5 6/9/2014 3 Mt. Prospect Ave. Clifton, NJ 07013 DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: OUTPUT: Ambient Temperature: 25oC 3oC Load: 1 FAST-TTL Gate Supply Voltage (Vcc): 5.0V 0.1V Cload: 5pf 10% Input Pulse: High = 3.0V 0.1V Threshold: 1.5V (Rising & Falling) Low = 0.0V 0.1V Source Impedance: 50 Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V ) Pulse Width: PWIN = 10ns Period: PERIN = 2 x Max. Pulse Width NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. OUT OUT TRIG IN REF TRIG Test Setup DEVICE UNDER TEST (DUT) TIME INTERVAL COUNTER PULSE GENERATOR COMPUTER SYSTEM PRINTER TRIG Timing Diagram For Testing TTO PWA PERIN PWIN TRISE TFALL 0.6V0.6V 1.5V1.5V 2.4V 2.4V 1.5V1.5V VIH VIL VOH VOL INPUT SIGNAL OUTPUT SIGNAL