MPC5553 FREESCALE | Alldatasheet
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Technical content
Datasheet sections
- 1 Overview
- 2 Ordering Information
- 3 Electrical Characteristics
- 3.1 Maximum Ratings
- 3.2 Thermal Characteristics
- 3.3 Package
- 3.4 EMI (Electromagnetic Interference) Characteristics
- 3.5 ESD Characteristics
- 3.6 VRC/POR Electrical Specifications
- 3.7 Power Up/Down Sequencing
- 3.8 DC Electrical Specifications
- 3.9 Oscillator & FMPLL Electric al Characteristics
- 3.11 H7Fa Flash Memory Electr ical Characteristics
- 3.12 AC Specifications
- 3.13 AC Timing
- 3.14 Fast Ethernet AC Timing Specifications
- 4 Mechanicals
- 4.1 Pinouts
- 4.2 Package Dimensions
- 5 Revision History
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice Overview Freescale Semiconductor2 PowerPC instruction set. This family of parts contains many new features coupled with high performance CMOS technology to provide significant performance improvement over the MPC565. The MPC5553 of the MPC5500 family has two levels of memory hierarchy. The fastest accesses are to the 8-kilobyte unified cache. The next level in the hierarchy contains the 64-kilobyte on-chip internal SRAM and 1.5 Mbyte internal Flash memory. Both the internal SRAM and the Flash memory can hold instructions and data. The external bus interface has been designed to support most of the standard memories used with the MPC5xx family. The complex I/O timer functions of the MPC5500 family are performed by an enhanced time processor unit engine (eTPU). The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over the TPU by providing 24-bit timers, double action hardware channels, variable number of parameters per channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU can be programmed using a high-level programming language. The less complex timer functions of the MPC5500 family are performed by the enhanced modular input/output system (eMIOS). The eMIOS’ 24 hardware channels are capable of single action, double action, pulse width modulation (PWM), and modulus counter operation. Motor control capabilities include edge-aligned and center-aligned PWM. Off-chip communication is performed by a suite of serial protocols including controller area networks (FlexCANs), enhanced deserial/serial peripheral interfaces (DSPI), and enhanced serial communications interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of timer channels and general-purpose input/output (GPIO) signals. The MCU of the MPC5553 has an on-chip 40-channel enhanced queued dual analog-to-digital converter (eQADC). The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset control are also found in the SIU. The internal multiplexer submodule (SIU_DISR) provides multiplexing of eQADC trigger sources, daisy chaining the DSPIs and external interrupt signal multiplexing.
Ordering Information
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 3
2 Ordering Information
Figure 1. MPC5500 Family Part Number Example Table 1. Orderable Part Numbers Note: Not all options are available on all devices. Refer to Table 1.
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice
Electrical Characteristics
3 Electrical Characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MCU.
3.1 Maximum Ratings
MPC5553MVF80 MPC5553 Lead 208 package 80 82 -40° C to 125° C MPC5553MVM80 MPC5553 Lead free 208 package 80 82 -40° C to 125° C 1 Speed is the nominal maximum frequency. Max Speed is the maximum speed allowed including any frequency modulation. 80-MHz parts allow for 80 MHz + 2% modulation. However, 132-MHz allows only 128 MHz + 2% FM. Table 2. Absolute Maximum Ratings1
12 DC Input Voltage 5
15 VDD Differential Voltage V DD – VDDA – VDDA VDD V
19 V DDEH to VDDA Differential Voltage V DDEH – VDDA –VDDA VDDEH V
21 This spec has been moved to Table 9, spec 43a. Table 1. Orderable Part Numbers (continued)
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 5
3.2 Thermal Characteristics
23 V RCVSS to VSS Differential Voltage V RCVSS – VSS –0.1 0.1 V
24 Maximum DC Digital Input Current 10 (per pin, applies to all
digital pins)5 IMAXD –2 2 mA
25 Maximum DC Analog Input Current 11 (per pin, applies to all
analog pins) IMAXA –3 3 mA
26 Maximum Operating Temperature Range 12 — Die Junction
TJ – 40.0 150.0 oC 27 Storage Temperature Range T STG – 55.0 150.0 oC 28 Maximum Solder Temperature 13 TSDR — 260.0 oC
29 Moisture Sensitivity Level 14 MSL — 3
1 Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have not yet been determined. 3 1.5V +/– 10% for proper operation. This parameter is specified at a maximum junction temperature of 150C. 4 All functional non-supply I/O pins are clamped to VSS and VDDE or VDDEH. 5 AC signal over and undershoot of the input voltages of up to +/– 2.0 volts is permitted for a cumulative duration of 60 hours over the complete lifetime of the device (injection current does not need to be limited for this duration). 6 Internal structures will hold the voltage above –1.0 volt if the injection current limit of 1 mA is met. 7 Internal structures will not clamp to a safe voltage. External protection must be used to ensure that voltage on the pin stays above –0.3 volts. 8 Internal structures hold the input voltage below this maximum voltage on all pads powered by VDDEH supplies, if the maximum injection current specification is met (1 mA for all pins) and VDDEH is within Operating Voltage specifications. 9 Internal structures hold the input voltage below this maximum voltage on all pads powered by VDDE supplies, if the maximum injection current specification is met (1 mA for all pins) and VDDE is within Operating Voltage specifications. 10 Total injection current for all pins (including both digital and analog) must not exceed 25mA. 11 Total injection current for all analog input pins must not exceed 15mA. 12 Lifetime operation at these specification limits is not guaranteed. 13 Solder profile per CDF-AEC-Q100. 14 Moisture sensitivity per JEDEC test method A112. Table 3. Thermal Characteristics
208 MAPBGA 324 PBGA 416 PBGA
1 Junction to Ambient 1, 2
2 Junction to Ambient 1, 3
Table 2. Absolute Maximum Ratings1 (continued)
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice
3.2.1 General Notes for Specifications at Maximum Junction Temperature
An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RθJA × PD) where: TA = ambient temperature for the package (oC) RθJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) The supplied thermal resistances are provided based on JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined on the single-layer (1s) board and on the four-layer board with two signal layers and a power and a ground plane (2s2p) clearly demonstrate that the effective thermal resistance of the component is not a constant. It depends on the construction of the application board (number of planes), the effective size of the board which cools the component, how well the component is thermally and electrically connected to the planes, and the power being dissipated by adjacent components. Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal
3 Junction to Ambient 1, 3
(@200 ft./min., Single layer board) RθJMA °C/W 33 24 23
4 Junction to Ambient 1, 3
(@200 ft./min., Four layer board 2s2p) RθJMA °C/W 22 17 18
5 Junction to Board 4
(Four layer board 2s2p) RθJB °C/W 15 12 13
6 Junction to Case 5 RθJC °C/W 7 8 9
7 Junction to Package Top 6
ΨJT °C/W 2 2 2 1 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 3 Per JEDEC JESD51-6 with the board horizontal. 4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5 Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. 6 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. Table 3. Thermal Characteristics (continued)
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 7 performance. When the clearance between through vias leave the planes virtually disconnected, the thermal performance is also greatly reduced. As a general rule, the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the application board has one oz (35 micron nominal thickness) internal planes, the components are well separated, and the overall power dissipation on the board is less than 0.02 W/cm2. The thermal performance of any component depends strongly on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ = TB + (RθJB × PD) where: TJ = junction temperature (oC) TB = board temperature at the package perimeter (oC/W) RθJB = junction to board thermal resistance (oC/W) per JESD51-8 PD = power dissipation in the package (W) When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition, with the component soldered to a board with internal planes. Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: RθJA = RθJC + RθCA where: RθJA = junction to ambient thermal resistance (oC/W) RθJC = junction to case thermal resistance (oC/W) RθCA = case to ambient thermal resistance (oC/W) RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RθCA. For instance, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required. A more accurate two-resistor thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal resistance. The junction to case covers the situation where a heat sink will be used or where a substantial amount of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat is conducted
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice to the printed circuit board. This model can be used for either hand estimations or for a computational fluid dynamics (CFD) thermal model. To determine the junction temperature of the device in the application after prototypes are available, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (ΨJT × PD) where: TT = thermocouple temperature on top of the package (oC) ΨJT = thermal characterization parameter (oC/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. References: Semiconductor Equipment and Materials International
805 East Middlefield Rd
Mountain View, CA 94043 (415) 964-5111 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org.
- 1. C.E. Triplett and B. Joiner, “An Experime ntal Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
- 2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic Packaging and Production, pp. 53–58, March 1998.
- 3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.
3.3 Package
The MPC5553 is available in packaged form. Package options are listed in Section 2, “Ordering Information.” Refer to Section 4, “Mechanicals,” for pinouts and package drawings.
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 9
3.4 EMI (Electromagnetic Interference) Characteristics
3.5 ESD Characteristics
Table 4. EMI Testing Specifications1 applied to MPC5500 family as generic EMI performance data.
2 Operating Frequency — — 132 MHz
6 Maximum Amplitude — — 14 2
2 As measured with “single-chip” EMI program. 3 As measured with “expanded” EMI program.
7 Operating Temperature — — 25 oC
Table 5. ESD Ratings1, 2 1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice
3.6 VRC/POR Electrical Specifications
Table 6. VRC/POR Electrical Specifications
3 RESET Pin Supply (VDDEH6) POR Negated (Ramp Up)
4 VRC33 voltage before regulator controller allows the pass transistor
5 VRC33 voltage when regulator controller allows the pass transistor
1 User must be able to supply full operating current for the 1.5V supply when the 3.3V supply reaches this range. 2 Current limit may be reached during ramp up and should not be treated as short circuit current.
6 VRC33 voltage above which the regulator controller will keep the
3 At peak current for device. transistor to the VDD package signals should have a maximum of 100 nH inductance and minimal resistance (<1 ohm). µF , and one 1 µF capacitors should be place around the package on the VDD supply signals.
7 Current which can be sourced by VRCCTL I_VRCCTL 5
5 I_VRCCTL measured at the following conditions: VDD=1.35V, VRC33=3.1V, V_VRCCTL=2.2V.
8 Voltage differential during power up that VDD33 can lag VDDSYN or
9 Absolute value of Slew Rate on power supply pins — 50 V/ms
10 Required Gain:
6 Values are based on IDD from high use applications as explained in the IDD Electrical Specification. 8 Preliminary value. Final specification pending characterization.
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 11
3.7 Power Up/Down Sequencing
Power sequencing between the 1.5-V power supply and VDDSYN or the RESET power supplies is required if the user provides an external 1.5-V power supply and ties VRC33 to ground. To avoid this power sequencing requirement, power up VRC33 within the specified operating range, even if not using the on-chip voltage regulator controller. Refer to Section 3.7.1, “Power Up Sequence (If VRC33 Grounded)” and Section 3.7.2, “Power Down Sequence (If VRC33 Grounded).” Another power sequencing requirement is that VDD33 must be of sufficient voltage before POR negates, so that the values on certain pins are treated as 1s when POR does negate. Refer to Section 3.7.3, “Input Value of Pins During POR Dependent on VDD33.” Although there is no power sequencing required between VRC33 and VDDSYN during power up, for the VRC stage turn-on to operate within specification, VRC33 must not lead VDDSYN by more than 600 mV or lag by more than 100 mV . Higher spikes in the emitter current of the pass transistor will occur if VRC33 leads or lags VDDSYN by more than these amounts. The value of that higher spike in current depends on the board power supply circuitry and the amount of board level capacitance. Furthermore, when all of the PORs negate, the system clock will start to toggle, adding another large increase of the current consumption from VRC33. If VRC33 lags VDDSYN by more than 100 mV , this increased current consumption can drop VDD low enough to assert the 1.5-V POR again. Oscillations are even possible because when the 1.5-V POR asserts, the system clock stops, causing the voltage on VDD to rise until the 1.5-V POR negates again. Any oscillations stop when VRC33 is powered sufficiently. When powering down, VRC33 and VDDSYN do not have a delta requirement to each other, because the bypass capacitors internal and external to the device are already charged. When not powering up or down, VRC33 and VDDSYN do not have a delta requirement to each other for the VRC to operate within specification. Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc., the state of the I/O pins during power up/down varies depending on power. Table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type), and Table 8 for all pins with pad type pad_mh (medium type) and pad_sh (slow type). Table 7. Power Sequence Pin States (Fast Pads) VDDE VDD33 LOW High Impedance POR asserted.
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice
3.7.1 Power Up Sequence (If VRC33 Grounded)
In this case, the 1.5-V VDD supply must rise to 1.35-V before the 3.3-V VDDSYN and the RESET power supplies rises above 2.0 V. This ensures that digital logic in the PLL on the 1.5-V supply will not begin to operate below the specified operation range lower limit of 1.35 V . Since the internal 1.5-V POR is disabled, the internal 3.3-V POR or the RESET power POR must be depended on to hold the device in reset. Since they may negate as low as 2.0 V , it is necessary for VDD to be within spec before the 3.3-V POR and the RESET POR negate. Figure 2. Power Up Sequence if VRC33 Grounded
3.7.2 Power Down Sequen ce (If VRC33 Grounded)
falling below spec, is reset properly.
3.7.3 Input Value of Pins Du ring POR Dependent on VDD33
lag either VDDSYN or the RESET pin power (VDDEH6) by more than the VDD33 lag specification. requirements when powering down. Table 8. Power Sequence Pin States (Medium and Slow Pads)
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 13
3.8 DC Electrical Specifications
Table 9. DC Electrical Specifications
12 Fast I/O Input High Voltage V
18 Analog Input Voltage V INDC VSSA –
23 Load Capacitance (Fast I/O) 4
24 Input Capacitance (Digital Pins) C IN —7 p F
25 Input Capacitance (Analog Pins) C IN_A —1 0 p F
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice
26 Input Capacitance (Shared digital and analog pins AN12_MA0_SDS,
AN12_MA1_SDO, AN14_MA2_SDI, and AN15_FCK) CIN_M —1 2 p F 27a Operating Current 5 1.5V Supplies @ 132MHz: VDD (including VDDF max current)6, 7 @1.65V Typical Use VDD (including VDDF max current)6, 7 @1.35V Typical Use VDD (including VDDF max current) 7, 8 @1.65V High Use VDD (including VDDF max current)7, 8@1.35V High Use IDD IDD IDD IDD 550 4509 6009 4909 mA mA mA mA 27b Operating Current 51.5V Supplies @ 114MHz: VDD (including VDDF max current)6, 7@1.65V Typical Use VDD (including VDDF max current)6, 7@1.35V Typical Use VDD (including VDDF max current)7, 8 @1.65V High Use VDD (including VDDF max current)7, 8 @1.35V High Use IDD IDD IDD IDD 460 3809 5209 4209 mA mA mA mA 27c Operating Current 5 1.5V Supplies @ 82MHz: VDD (including VDDF max current)6, 7 @1.65V Typical Use VDD (including VDDF max current)6, 7 @1.35V Typical Use VDD (including VDDF max current)7, 8 @1.65V High Use VDD (including VDDF max current)7, 8 @1.35V High Use IDD IDD IDD IDD 3509 2909 4009 3309 mA mA mA mA 27d IDDSTBY @ 25C VSTBY @ 0.8V VSTBY @ 1.0V VSTBY @ 1.2V IDD STBY @ 60C VSTBY @ 0.8V VSTBY @ 1.0V VSTBY @ 1.2V IDDSTBY @ 150C (Tj) VSTBY @ 0.8V VSTBY @ 1.0V VSTBY @ 1.2V IDD STBY IDDSTBY IDDSTBY IDDSTBY IDDSTBY IDDSTBY IDDSTBY IDDSTBY IDDSTBY 100 200 1200 1500 2000 µA µA µA µA µA µA µA µA µA 28 Operating Current 3.3V Supplies @ 132MHz: VDD33
10 IDD33 — 2 + values
VFLASH I VFLASH —1 0 m A VDDSYN I DDSYN —1 5 m A Table 9. DC Electrical Specifications (continued)
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 15 29 Operating Current 5.0V Suppl ies @ 132MHz (12MHz ADCLK): VDDA (VDDA0 + VDDA1) Analog Reference Supply Current (VRH, VRL) VPP IDDA IREF IPP 20.0 1.0 mA mA mA
30 Operating Current VDDE
11 Supplies:
31 Fast I/O Weak Pull Up Current
1.62V – 1.98V 2.25V – 2.75V 3.0V – 3.6V I ACT_F 10 110 130 170 µA µA µA Fast I/O Weak Pull Down Current 1.62V – 1.98V 2.25V – 2.75V 3.0V – 3.6V 100 130 170 µA µA µA
32 Slow/Medium I/O Weak Pull Up/Down Current
3.0V – 3.6V 4.5V – 5.5V IACT_S 150 170 µA µA 33 I/O Input Leakage Current 14 IINACT_D – 2.5 2.5 µA 34 DC Injection Current (per pin) I IC – 2.0 2.0 mA
35 Analog Input Current, Channel Off 15 IINACT_A –150 150 nA
35a Analog Input Current, Shared Analog/Digital pins (AN12, AN13, AN14, AN15) IINACT_AD – 2.5 2.5 µA
36 VSS Differential Voltage 16 VSS – VSSA – 100 100 mV
37 Analog Reference Low Voltage VRL VSSA –
0.1 VSSA + 0.1 V
38 VRL Differential Voltage VRL – VSSA –100 100 mV
39 Analog Reference High Voltage VRH VDDA –
0.1 VDDA + 0.1 V 40 V REF Differential Voltage VRH – VRL 4.5 5.25 V
41 VSSSYN to VSS Differential Voltage VSSSYN – VSS –50 50 mV
42 VRCVSS to VSS Differential Voltage VRCVSS – VSS –50 50 mV
43 VDDF to VDD Differential Voltage
2 VDDF – VDD –100 100 mV
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice
3.8.1 I/O Pad Current Specifications
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 10 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 10. 43a VRC33 to VDDSYN Differential Voltage V RC33 – VDDSYN –0.1 0.1 17 V 44 Analog Input Differential Signal Range (with common mode 2.5V) V IDIFF – 2.5 2.5 V
45 Operating Temperature Range — Ambient (Packaged) T A
(TL to TH) – 40.0 125.0 οC
46 Slew rate on power supply pins — — 50 V/ms
1 | VDDA0–VDDA1 | must be < 0.1V 2 VPP can drop to 3.0 volts during read operations. 3 During standby operation. If standby operation is not required, VSTBY can be connected to ground. 4 Applies to CLKOUT, external bus pins, and Nexus pins. 5 Maximum average RMS DC current. 6 Average current measured on Automotive benchmark. 7 Peak currents may be higher on specialized code. 8 High use current measured while running optimized SPE assembly code with all code and data 100% locked in cache (0% miss rate) with all channels of the eMIOS and eTPU running autonomously, plus the eDMA transferring data continuously from SRAM to SRAM. Higher currents could be seen if an “idle” loop that crosses cache lines is run from cache. Code should be written to avoid this condition. 9 Preliminary. Final specification pending characterization. 10 Power requirements for the VDD33 supply are dependent on the frequency of operation and load of all I/O pins, and the voltages on the I/O segments. See Table 11 for values to calculate power dissipation for specific operation. 11 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O segment, and the voltage of the I/O segment. See Table 10 for values to calculate power dissipation for specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment. 14 Weak pull up/down inactive. Measured at VDDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types: pad_fc, pad_sh, and pad_mh. 15 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types: pad_a and pad_ae. 16 VSSA refers to both VSSA0 and VSSA1. | VSSA0–VSSA1 | must be < 0.1V 17 Up to 0.6 volts during power up and power down.
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 17
3.8.2 I/O Pad VDD33 Current Specifications
The power consumption of the VDD33 supply dependents on the usage of the pins on all I/O segments. The power consumption is the sum of all input and output pin VDD33 currents for all I/O segments. The output pin VDD33 current can be calculated from Table 11 based on the voltage, frequency, and load on all fast (pad_fc) pins. The input pin VDD33 current can be calculated from Table 11 based on the voltage, Table 10. I/O Pad Average DC Current1 1 These values are estimated from simulation and are not tested. Currents apply to output pins only.
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice frequency, and load on all pad_sh and pad_sh pins. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 11. Table 11. VDD33 Pad Average DC Current1 pins only for the slow and medium pads.
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 19
3.9 Oscillator & FMPLL Electrical Characteristics
Table 12. HiP7 FMPLL Electrical Specifications Num Characteristic Symbol Min.
1 PLL Reference Frequency Range:
2 System Frequency 1 fsys f ico(min) ÷ 2RFD fMAX 2 MHz
3 System Clock Period t CYC —1 / f sys ns
4 Loss of Reference Frequency 3 fLOR 100 1000 kHz
6 EXTAL Input High Voltage
7 EXTAL Input Low Voltage
11 Crystal manufacturer’s recommended
12 Discrete load capacitance to be connected
13 Discrete load capacitance to be connected
14 PLL Lock Time 9 tlpll —7 5 0 µs
15 Dual Controller (1:1) Clock Skew (between
16 Duty Cycle of reference tdc 40 60 %
19 CLKOUT Period Jitter, 12, 13
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice 3.10 eQADC Electrical Characteristics
20 Frequency Modulation Range Limit 14
(fsysMax must not be exceeded) Cmod 0.8 2.4 %f sys 21 ICO Frequency. fico=[fref*(MFD+4)]/(PREDIV+1)15 fico 48 f sys MHz
22 Predivider Output Frequency (to PLL) f PREDIV 4f MAX MHz
1 All internal registers retain data at 0 Hz. 2 Up to the maximum frequency rating of the device (see Table 1). 3 “Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode. 4 Self clocked mode (SCM) frequency is the frequency that the PLL operates at when the reference frequency falls below fLOR. This frequency is measured on the CLKOUT pin with the divider set to divide-by-2 of the system clock. NOTE: In SCM, the MFD and PREDIV have no effect and the RFD is bypassed. 5 This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case, Vextal – Vxtal >= 400mV criteria has to be met for oscillator’s comparator to produce output clock. 6 This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case, Vxtal –V extal >= 400mV criteria has to be met for oscillator’s comparator to produce output clock. 7 Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
8 CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively
9 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time will also include the crystal startup time. 10 PLL is operating in 1:1 PLL mode. 11 VDDE = 3.0 to 3.6V 12 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage for a given interval. CLKOUT divider set to divide-by-2. 13 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of jitter + Cmod. 14 Modulation depth selected must not result in fsys value greater than the fsys maximum specified value. 15 fsys = fico / (2RFD) Table 13. eQADC Conversion Specifications (Operating)
1 ADC Clock (ADCLK) Frequency 1 FADCLK 11 2 M H z
2 Conversion Cycles
3 Stop Mode Recovery Time 2 TSR 10 — µs
5 INL: 6 MHz ADC Clock INL6 –4 4 Counts 3
6 INL: 12 MHz ADC Clock INL12 –8 8 Counts
Table 12. HiP7 FMPLL Electrical Specifications (continued) Num Characteristic Symbol Min.
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 21
3.11 H7Fa Flash Memory Electrical Characteristics
7 DNL: 6 MHz ADC Clock DNL6 –3 4 3 4 Counts
8 DNL: 12 MHz ADC Clock DNL12 –6 4 64 Counts
9 Offset Error with Calibration OFFWC –4 5 4 5 Counts
10 Full Scale Gain Error with Calibration GAINWC –8 6 8 6 Counts
11 Disruptive Input Injection Current 7, 8, 9, 10 IINJ –1 1 mA
12 Incremental Error due to injection current. All channels have same 10kΩ < Rs <100kΩ Channel under test has Rs=10kΩ, IINJ=IINJMAX,IINJMIN EINJ –4 4 Counts
13 Total Unadjusted Error for single ended conversions with
calibration11, 12, 13, 14, 15 TUE –4 4 Counts 1 Conversion characteristics vary with FADCLK rate. Reduced conversion accuracy occurs at maximum FADCLK rate. The maximum value is based on 800KS/s and the minimum value is based on 20MHz oscillator clock frequency divided by a maximum 16 factor. 2 Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that the ADC is ready to perform conversions. 3 At VRH – VRL = 5.12 V, one lsb = 1.25 mV = one count
4 Guaranteed 10-bit monotonicity
5 The absolute value of the offset error without calibration ≤ 100 counts. 6 The absolute value of the full scale gain error without calibration ≤ 120 counts. 7 Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater than VRH and 0x000 for values less than VRL. This assumes that VRH ≤ VDDA and VRL ≥ VSSA due to the presence of the sample amplifier. Other channels are not affected by non-disruptive conditions. 8 Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage. 9 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using VPOSCLAMP = VDDA + 0.5V and VNEGCLAMP = – 0.3 V, then use the larger of the calculated values. 10 Condition applies to two adjacent pads on the internal pad. 11 The TUE specification will always be better than the sum of the INL, DNL, offset, and gain errors due to canceling errors. 12 TUE does not apply to differential conversions. 13 Measured at 6 MHz ADC clock. TUE with a 12 MHz ADC clock is: –16 counts < TUE < 16 counts.
14 TUE includes all internal device error such as internal reference variation (75% Ref, 25% Ref)
15 Depending on the customer input impedance, the Analog Input Leakage current (DC Electrical specification 35a) may affect the actual TUE measured on analog channels AN12, AN13, AN14, AN15. Table 14. Flash Program and Erase Specifications1
3 Double Word (64 bits) Program Time 4 Tdwprogram —1 0— 5 0 0 µs
4 Page Program Time 4 Tpprogram —2 2 4 4 5 500 µs
Table 13. eQADC Conversion Specifications (Operating) (continued)
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice Table 16 shows the FLASH_BIU settings versus frequency of operation. Refer to the device Reference Manual for definitions of these bit-fields. 10 64 Kbyte Block Pre-program and Erase Time T 64kpperase — 400 500 5000 ms 8 128 Kbyte Block Pre-program and Erase Time T 128kpperase — 500 1250 15,000 ms
11 Minimum operating frequency for program and erase
—2 5 — — — M H z 1 Typical program and erase times assume nominal supply values and operation at 25 oC. 2 Initial factory condition: ≤ 100 program/erase cycles, 25 oC, typical supply voltage, 80MHz minimum system frequency. 3 The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized but not guaranteed. 4 Actual hardware programming times. This does not include software overhead. 5 Page size is 256 bits (8 words). 6 Read frequency of the flash can be up to the maximum operating frequency of the device. There is no minimum read frequency condition. Table 15. Flash EEPROM Module Life (Full Temperature Range)
2 Data retention
Table 16. FLASH_BIU Settings vs. Frequency of Operation 1 This setting allows for 80 MHz system clock with 2% frequency modulation. Table 14. Flash Program and Erase Specifications1 (continued)
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 23
3.12 AC Specifications
3.12.1 Pad AC Specifications
2 For maximum flash performance, this should be set to 0b11. 3 For maximum flash performance, this should be set to 0b110. 4 For maximum flash performance, this should be set to 0b1. 5 This setting allows for 100 MHz system clock with 2% frequency modulation. 6 This setting allows for 128 MHz system clock with 2% frequency modulation. Table 17. Pad AC Specifications (VDDEH = 5.0V, VDDE = 1.8V)1 2 This parameter is supplied for reference and is not guaranteed by design and not tested. 3 Out delay is shown in Figure 3. Add a maximum of one system clock to the output delay for delay with respect to system clock. 4 Delay and rise/fall are measured to 20% or 80% of the respective signal. 5 This parameter is guaranteed by characterization before qualification rather than 100% tested.
1 Slow High Voltage (SH) 11 26 15 50
2 Medium High Voltage (MH) 11 16 8 50
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice Table 18. De-rated Pad AC Specifications (VDDEH = 3.3V, VDDE = 3.3V)1 2 This parameter is supplied for reference and is not guaranteed by design and not tested. 3 Delay and rise/fall are measured to 20% or 80% of the respective signal. 4 Out delay is shown in Figure 3. Add a maximum of one system clock to the output delay for delay with respect to system clock. 5 This parameter is guaranteed by characterization before qualification rather than 100% tested.
1 Slow High Voltage (SH) 11 39 23 50
2 Medium High Voltage (MH) 11 23 12 50
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 25 Figure 3. Pad Output Delay
3.13 AC Timing
3.13.1 Reset and Configuration Pin Timing
Table 19. Reset and Configuration Pin Timing1
1 RESET Pulse Width t RPW 10 — t CYC
2 RESET Glitch Detect Pulse Width t GPW 2— t CYC
3 PLLCFG, BOOTCFG, WKPCFG, RSTCFG Setup Time to RSTOUT Valid t RCSU 10 — t CYC
4 PLLCFG, BOOTCFG, WKPCFG, RSTCFG Hold Time from RSTOUT Valid t RCH 0— t CYC
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice Figure 4. Reset and Configuration Pin Timing Table 20. JTAG Pin AC Electrical Characteristics1
2 TCK Clock Pulse Width (Measured at VDDE/2) t JDC 40 60 ns
3 TCK Rise and Fall Times (40% – 70%) t TCKRISE —3 n s
4 TMS, TDI Data Setup Time t TMSS, tTDIS 5— n s
5 TMS, TDI Data Hold Time t TMSH, tTDIH 25 — ns
6 TCK Low to TDO Data Valid t TDOV —2 0 n s
7 TCK Low to TDO Data Invalid t TDOI 0— n s
8 TCK Low to TDO High Impedance t TDOHZ —2 0 n s
9 JCOMP Assertion Time t JCMPPW 100 — ns
10 JCOMP Setup Time to TCK Low t JCMPS 40 — ns
11 TCK Falling Edge to Output Valid t BSDV —5 0 n s
12 TCK Falling Edge to Output Valid out of High Impedance t BSDVZ —5 0 n s
13 TCK Falling Edge to Output High Impedance t BSDHZ —5 0 n s
14 Boundary Scan Input Valid to TCK Rising Edge t BSDST 50 — ns
15 TCK Rising Edge to Boundary Scan Input Invalid t BSDHT 50 — ns
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice Figure 7. JTAG JCOMP Timing
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 29 Figure 8. JTAG Boundary Scan Timing
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice
3.13.3 Nexus Timing
Figure 9. Nexus Output Timing Table 21. Nexus Debug Port Timing1 VDD33 and VDDSYN = 3.0V to 3.6V, TA = TL to TH, and CL = 30pF with DSC = 0b10.
1 MCKO Cycle Time t MCYC 12
2 MCKO Duty Cycle t MDC 40 60 %
3 MCKO Low to MDO Data Valid 3
3 MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
7 EVTO Pulse Width t EVTOPW 1t MCYC
8 TCK Cycle Time t TCYC 44
volts) to meet the timing specification for tJOV of 0.2 x tJCYC as outlined in the IEEE-ISTO 5001-2003 specification.
9 TCK Duty Cycle t TDC 40 60 %
10 TDI, TMS Data Setup Time t NTDIS, tNTMSS 8—n s
11 TDI, TMS Data Hold Time t NTDIH, tNTMSH 5—n s
12 TCK Low to TDO Data Valid t JOV
13 RDY Valid to MCKO5
5 The RDY pin timing is asynchronous to MCKO. The timing is guaranteed by design to function correctly.
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 31 Figure 10. Nexus TDI, TMS, TDO Timing
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice
3.13.4 External Bus Interface (EBI) Timing
Table 22. Bus Operation Timing1
40 MHz
56 MHz
66 MHz
2 CLKOUT duty cycle t CDC 45% 55% 45% 55% 45% 55% T C
3 CLKOUT rise time t CRT —— 3 —— 3 —— 3 ns
4 CLKOUT fall time t CFT —— 3 —— 3 —— 3 ns
5 CLKOUT Positive Edge to
6 CLKOUT Posedge to Output
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 33 Figure 11. CLKOUT Timing
7 Input Signal Valid to CLKOUT
8 CLKOUT Posedge to Input
to 3.6V, TA = TL to TH, and CL = 30pF with DSC = 0b10. 2 The external bus is limited to half the speed of the internal bus. 3 Refer to Fast Pad timing in Table 17 and Table 18 (different values for 1.8V vs 3.3V).
4 Internal Arbitration
5 External Arbitration
Table 22. Bus Operation Timing1 (continued)
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice Figure 12. Synchronous Output Timing
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 35 Figure 13. Synchronous Input Timing
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice
3.13.5 External Interrupt Timing (IRQ Pin)
Figure 14. External Interrupt Timing Figure 15. External Interrupt Setup Timing Table 23. External Interrupt Timing1 TA = TL to TH, and CL = 200pF with SRC = 0b11.
1 IRQ Pulse Width Low t IPWL 3— t CYC
2 IRQ Pulse Width High T IPWH 3— t CYC
3 IRQ Edge to Edge Time 2
2 Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice 3.13.7 eMIOS (MTS) Timing
3.13.8 DSPI Timing
Table 25. MTS Timing1 TA = TL to TH, and CL = 50pF with SRC = 0b11. Table 26. DSPI Timing1
80 MHz 112 MHz 132 MHz
2 PCS to SCK Delay 4 tCSC 23 — 15 — 13 — ns
3 After SCK Delay 5 tASC 22 — 14 — 12 — ns
4 SCK Duty Cycle t SDC tSCK/2
5 Slave Access Time
6 Slave SOUT Disable Time
7 PCSx to PCSS time t PCSC 4—4— 4 —n s
9 Data Setup Time for Inputs
10 Data Hold Time for Inputs
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 39 Figure 18. DSPI Classic SPI Timing — Master, CPHA = 0
11 Data Valid (after SCK edge)
12 Data Hold Time for Outputs
and CL = 50pF with SRC = 0b11. based on two MPC55xx devices communicating over a DSPI link. 3 The actual minimum SCK Cycle Time is limited by pad performance.
4 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]
5 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]
6 This number is calculated assuming the SMPL_PT bit field in DSPI_MCR is set to 0b10. Table 26. DSPI Timing1 (continued)
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice 3.13.9 eQADC SSI Timing Figure 27. EQADC SSI Timing Table 27. EQADC SSI Timing Characteristics (pads at 3.3V or at 5.0V) 1 TA = TL to TH, and CL = 50pF with SRC = 0b11. CLOAD = 25pF on all outputs. Pad drive strength set to maximum.
1 FCK Frequency 2, 3
2 Maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays. 3 FCK duty is not 50% when it is generated through the division of the system clock by an odd number.
7 EQADC Data Setup Time (Inputs) t EQ_SU 22 — — ns
8 EQADC Data Hold Time (Inputs) t EQ_HO 1— — n s
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 45
3.14 Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at 3.3 V . Note that the timing specifications for the MII signals are independent of system clock frequency (part speed designation).
3.14.1 MII Receive Signal Timing (RXD [3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed 4× the RX_CLK frequency. Table 28 lists MII receive channel timings. Figure 28 shows MII receive signal timings listed in Table 28. Figure 28. MII Receive Signal Timing Diagram Table 28. MII Receive Signal Timing
1 RXD[3:0], RX_DV, RX_ER to RX_CLK setup 5 — ns
2 RX_CLK to RXD[3:0], RX_DV, RX_ER hold 5 — ns
3 RX_CLK pulse width high 35% 65% RX_CLK period
4 RX_CLK pulse width low 35% 65% RX_CLK period
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice
3.14.2 MII Transmit Signal Timing (T XD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the TX_CLK frequency. The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of TX_CLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs. Refer to the ethernet chapter of the device Reference Manual for details of this option and how to enable it. Table 29 lists MII transmit channel timings. Figure 29 shows MII transmit signal timings listed in Table 29. Figure 29. MII Transmit Signal Timing Diagram Table 29. MII Transmit Signal Timing
5 TX_CLK to TXD[3:0], TX_EN, TX_ER invalid 5 — ns
6 TX_CLK to TXD[3:0], TX_EN, TX_ER valid — 25 ns
7 TX_CLK pulse width high 35% 65% TX_CLK period
8 TX_CLK pulse width low 35% 65% TX_CLK period
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 47
3.14.3 MII Async Inputs Sign al Timing (CRS and COL)
Table 30 lists MII asynchronous inputs signal timing. Figure 30 shows MII asynchronous input timings listed in Table 30. Figure 30. MII Async Inputs Timing Diagram
3.14.4 MII Serial Management Ch annel Timing (MDIO and MDC)
Figure 31 shows MII serial management channel timings listed in Table 31. Table 30. MII Async Inputs Signal Timing Table 31. MII Serial Management Channel Timing
10 MDC falling edge to MDIO output invalid (minimum propagation delay) 0 — ns
11 MDC falling edge to MDIO output valid (max prop delay) — 25 ns
12 MDIO (input) to MDC rising edge setup 10 — ns
13 MDIO (input) to MDC rising edge hold 0 — ns
14 MDC pulse width high 40% 60% MDC period
15 MDC pulse width low 40% 60% MDC period
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 49
4 Mechanicals
4.1 Pinouts
4.1.1 MPC5553 416 PBGA Pinout
Figure 33, Figure 34, and Figure 35 show the pinout for the MPC5553 416 PBGA package. While the MPC5553 and the MPC5554/MPC5565/MPC5566 are pin-compatible, the MPC5553 ball map is shown here to highlight the balls that are not connected to any signal on the MCP5553 (the eTPUB[0:31] and TSIZ[0:1]). The alternate Ethernet signals that are multiplexed with the data bus are not shown for the MPC5553. NOTE Some pins have names that include functions that are not available on all family members. For example, ball R25 of the 416 BGA package is named ‘SINA,’ but the MPC5553 does not have a DSPI_A module. In this case, the SINA pin can only be used for its alternate functions of GPIO94 or PCSC2. See the specific device reference manual for functions available on each device in the family.
Figure 33. MPC5553 416 Package
Figure 34. MPC5553 416 Package, Left Side
Figure 35. MPC5553 416 Package, Right Side
4.1.2 MPC5553 324 PBGA Pinout
Figure 36 is a pinout for the MPC5553 324 PBGA package. Figure 36. MPC5553 324 Package
9 MDO3
4.1.3 MPC5553 208 MAP BGA Pinout
Figure 37 is a pinout for the MPC5553 208 MAP BGA package. Figure 37. MPC5553 208 Package
8 June 2005p
4.2 Package Dimensions
4.2.1 MPC5553 416-Pin Package
Figure 38 is a package drawing of the MPC5553 416 pin TEPBGA package. Figure 38. MPC5553 416 TEPBGA Package
4.2.2 MPC5553 324-Pin Package
Figure 39 is a package drawing of the MPC5553 324-pin TEPBGA package. Figure 39. MPC5553 324 TEPBGA Package
4.2.3 MPC5553 208-Pin Package
Figure 40 is a package drawing of the MPC5553 208-pin MAP BGA package. Figure 40. MPC5553 208 MAP BGA Package
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice
Revision History
5 Revision History
Table 32 provides a revision history of this document. Table 32. Revision History Rev. 0 This is the first released version of this document.
MPC5553 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 59 THIS PAGE IS INTENTIONALL Y BLANK
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