PPC5125YVN400

MPC5125 FREESCALE | Alldatasheet

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Technical content

Data Sheet: Technical Data Document Number: MPC5125 Rev. 3, 11/2009 © Freescale Semiconductor, Inc., 2008–2009. All rights reserved. This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. MPC5125

324 TEPBGA

The MPC5125 integrates a high performance e300 CPU core based on the Power Architecture™ Technology with a rich set of peripheral functions focused on communications and systems integration. Major features of the MPC5125 are as follows:

• e300 Power Architecture processor core (enhanced version of the MPC603e core), operates as fast as

400 MHz

• Low power design
• Display interface unit (DIU)
• DDR1, DDR2, low-power mobile DDR (LPDDR), and 1.8 V/3.3 V SDR DRAM memory controllers
• 32 KB on-chip SRAM
• USB 2.0 OTG controller with ULPI interface
• DMA subsystem
• Flexible multi-function external memory bus (EMB) interface
• NAND flash controller (NFC)
• LocalPlus interface (LPC)
• 10/100Base Ethernet
• MMC/SD/SDIO card host controller (SDHC)
• Programmable serial controller (PSC)
• Inter-integrated circuit (I 2C) communication interfaces
• Controller area network (CAN)
• J1850 byte data link c ontroller (BDLC) interface
• On-chip real- time clock (RTC)
• On-chip temperature sensor
• IC Identification module (IIM) MPC5125 Microcontroller Data Sheet

MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor2 Table of Contents 4.3.10 MMC/SD/SDIO Card Host Controller (SDHC) . 67 4.3.13 I

5.2 System and CPU Core AV

DD Power Supply Filtering . 82

5.4.1 Pulldown Resistor Requirements for TEST Pin 83

Ordering Information

MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 3

1 Ordering Information

Figure 1. MPC5125 Orderable Part Number Description Table 1 shows the orderable part numbers for the MPC5125. Table 1. MPC5125 Orderable Part Numbers 1 All packaged devices are PPC5125, rather than MPC125, until product qualifications are complete. 2 The lowest ambient operating temperature (TA) is referenced by TL; the highest junction temperature is referenced by TH. 3 Maximum speed is the maximum frequency allowed including frequency modulation (FM).

400 MHz core

200 MHz bus –40 °C 125 °C

S = Fully spec. qualified, automotive flowNote: Not all options are available on all devices. Refer to Table 1.

2 MPC5125 Block Diagrams

Figure 2 shows a simplified MPC5125 block diagram. Figure 2. Simplified MPC5125 Block Diagram

200 MHz AHB (32 bits)

32 KB SRAM

32 KB instruction /

66 MHz IP BUS

200 MHz CSB Bus (64 bits)

32 KB data cache

3 Pin Assignments

This section details pin assignments. Figure 3 shows the 324-ball TEPBGA pin assignments.

4 VSS PSC1_

3 TEST TMS TRST_

21 VSS MVTT0 VDD_I

23 VSS MDQ02 MDQS0 MDQ04 MDQ08

Figure 3. Ball Map for the MPC5125 324 TEPBGA Package

3.2 Pin Muxing and Reset States

Table 2 provides the pinout listing for the MPC5125. Table 2. MPC5125 Pin Multiplexing

Table 2. MPC5125 Pin Multiplexing (continued)

1. This pin is an input only.

This pin cannot be configured.

VDD_IO 2. This pin is an input only. This pin cannot be configured.

1. This test pin must be tied to

IO_CONTROL_MEM. Pins not controlled by these registers are indicated with a “—”. 2 Offset from IOCONTROL_BASE (default is 0xFF40_A000). 3 Except where noted in the Notes column, ALT0 is the primary (default) function for each pin after reset. 4 Alternate functions are chosen by setting the values of the STD_PU[FUNCMUX] bitfields inside the I/O Control module. of STD_PU[FUNCMUX] ), it is shown as “—”. 5 Module included on the MCU.

3.2.1 Power and Ground Supply Summary

Schmitt trigger. See the MPC5125 Reference Manual (MPC5125RM), “I/O Control” chapter. Table 3. MPC5125 324 TEPBGA Power/Ground 2 Dependent on external memory type. See Table 5.

0 V B10

4 Electrical and Thermal Characteristics

4.1 DC Electrical Characteristics

4.1.1 Absolute Maximum Ratings

The tables in this section describe the MPC5125 DC electrical characteristics. Table 4 gives the absolute maximum ratings.

4.1.2 Recommended Operating Conditions

Table 5 gives the recommended operating conditions. Table 4. Absolute Maximum Ratings1 beyond those listed may affect device reliability or cause permanent damage. Table 5. Recommended Operating Conditions

4.1.3 DC Electrical Specifications

Table 6 gives the DC electrical characteristics for the MPC5125 at recommended operating conditions. 1 These are recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed. 2 The State Retention voltage can be applied to VDD after the device is placed in deep-sleep mode. 3 VBAT should not be supplied by a battery of voltage less than 3.0 V. Table 6. DC Electrical Specifications Table 5. Recommended Operating Conditions (continued)

Table 6. DC Electrical Specifications (continued)

mode. In that case, Vextal – Vxtal ≥ 400 mV criteria has to be met for oscillator’s comparator to produce the output clock. pin. Do not connect anything to any other oscillator pin. XTAL_OUT pins. Do not connect anything to the other oscillator pins. pin. Do not connect anything to any other oscillator pin. 5 Leakage current is measured with output drivers disabled and with pullups and pulldowns inactive. 6 Pullup current is measured at VIL and pulldown current is measured at VIH. power supply within the specified voltage range. cause disruption of normal operation.

4.1.4 Electrostatic Discharge

DD ). Table 11 gives package thermal characteristics for this device. Table 7. General I/O Pads1 — Drive Current, Slew Rate 1 General I/O—rise and fall times at drive load 50 pF . Table 8. DDR I/O Pads1 — Drive Current, Slew Rate 1 DDR—rise and fall times at 50 Ω transmission line impedance terminated to MVTT (0.5 × VDD_IO_MEM) + 4 pF load. 2 Rising slew rate measured between 0.5 × VDD_IO_MEM – 450 mV and 0.5 × VDD_IO_MEM + 50 mV for all modes. 3 Falling slew rate measured between 0.5 × VDD_IO_MEM + 50 mV and 0.5 × VDD_IO_MEM – 450 mV for all modes. Table 9. ESD and Latch-Up Protection Characteristics

4.1.5 Power Dissipation

• Dissipation of the internal or core digital logic (supplied by V DD)
• Dissipation of the analog circuitry (supplied by A V DD_SPLL and A VDD_CPLL)
• Dissipation of the IO logic (supplied by V DD_IO_MEM and VDD_IO) Table 10 details typical measured core and analog power dissipation figures for a range of operating modes. However, the dissipation due to the switching of the IO pins cannot be given in general, but must be calculated for each application case using the following formula: Eqn. 1 where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the IO voltage swing, f is the switching frequency, and PIOint is the power consumed by the unloaded IO stage. The total power consumption of the MPC5125 device must not exceed this value, which would cause the maximum junction temperature to be exceeded. Eqn. 2

Table 10. Power Dissipation 1 Typical core power is measured at VDD_core = 1.4 V, TJ = 25 °C.

2 Operational power is measured while running an entirely cache-resident program with floating-point

multiplication instructions in parallel with DDR write operation.

and the concrete application and clock configurations.

4.1.6 Thermal Characteristics

4.1.6.1 Heat Dissipation

3 Doze, Nap, and Sleep power are measured with the e300 core in Doze/Nap/Sleep mode; the system

oscillator, system PLL, and core PLL active; and all other system modules inactive. PLL, and other system modules are inactive. 5 PLL power is measured at AVDD_SPLL = AVDD_CPLL = AVDD_OSC_TMPS = 3.3 V, TJ = 25 °C. 6 Unloaded typical I/O power is measured at VDD_IO = 3.3 V, VDD_MEM_IO = 1.8 V, TJ = 25 °C. Table 11. Thermal Resistance Data1 1 Thermal characteristics are targets based on simulation that are subject to change per device characterization. specification for this package. for the case temperature. Reported value includes the thermal resistance of the interface layer.

Electrical and Thermal Characteristics MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 43 The junction to ambient thermal resistance is an industry standard value, which provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single-layer board, and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is correct depends on the power dissipated by other components on the board. The value obtained on a single-layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: R θJA = R θJC + R θCA Eqn. 4 where: R θJA = junction to ambient thermal resistance ( º C / W ) R θJC = junction to case thermal resistance ( º C / W ) R θCA = case to ambient thermal resistance ( º C / W ) R θJC is device related and cannot be influenced by the user. You control the thermal environment to change the case to ambient thermal resistance, R θCA. For instance, you can change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for ceramic packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required. A more accurate thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal resistance. The junction to case covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used for hand estimations or for a computational fluid dynamics (CFD) thermal model. To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = T T + ( Ψ JT × PD ) Eqn. 5 where: TT = thermocouple temperature on top of package ( º C ) Ψ JT = thermal characterization parameter ( º C / W ) PD = power dissipation in package ( W ) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over approximately one mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.

4.2 Oscillator and PLL Electrical Characteristics

The MPC5125 system requires a system-level clock input SYS_XTALI. This clock input may be driven directly from an external oscillator or with a crystal using the internal oscillator. There is a separate oscillator for the independent real-time clock (RTC) system. The MPC5125 clock generation uses two phase-locked loop (PLL) blocks.

• The system PLL (SYS_PLL) takes an ex ternal reference frequency and generates the internal system clock. The system clock frequency is determined by the external reference frequency and the settings of the SYS_PLL configuration.
• The e300 core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The e300 core clock frequency is determined by the system clock frequency and the settings of the CORE_PLL configuration.

4.2.1 System Oscillator Electrical Characteristics

The system oscillator can work in oscillator mode or in bypass mode to support an external input clock as clock reference. Figure 4. Timing Diagram — SYS_XTAL_IN

4.2.2 RTC Oscillator Electrical Characteristics

Table 12. System Oscillator Electrical Characteristics Table 13. SYS_XTAL_IN Timing their respective maximum or minimum operating frequencies. See the MPC5125 Reference Manual (MPC5125RM). Table 12 (system oscillator electrical characteristics). 3 Rise time is measured from 20% of VDD to 80% of VDD. 4 Fall time is measured from 20% of VDD to 80% of VDD. 5 SYS_XTALI duty cycle is measured at V M. Table 14. RTC Oscillator Electrical Characteristics

4.2.3 System PLL Electrical Characteristics

Table 15. System PLL Specifications frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. PLL to the internal clock circuitry. during the power-on reset sequence. re-enabled during sleep modes. Table 16. e300 PLL Specifications 2 The following hard-coded relationship exists between fcore and fVCOcore: (fcore = fVCOcore). re-enabled during sleep modes.

4.3 AC Electrical Characteristics

4.3.1 Overview

The following list provides hyperlinks to the indicated timing specification sections.

• T A = –40 to 85 oC
• V DD = 1.33 to 1.47 V VDD_IO = 3.0 to 3.6 V
• Input conditions: All inputs: trise, tfall ≤ 1 ns
• Output Loading: All outputs: 50 pF

4.3.2 AC Operating Frequency Data

Table 17 provides the operating frequency information for the MPC5125.

• AC Operating Frequency Data • DIU
• Resets • CAN
• SDRAM (DDR) • I 2C
• L P C •J 1 8 5 0
• N F C •P S C
• F E C •G P I O s a n d T i m e r s
• USB ULPI • Fusebox
• MMC/SD/SDIO Card Host Controller (SDHC) • IEEE 1149.1 (JTAG)

Table 17. Clock Frequencies

1. The SYS_XTAL_IN frequency, Sys PLL, and Core PLL settings must be chosen so that the resulting e300 clk, csb_clk, and

MCK frequencies do not exceed their respective maximum or minimum operating frequencies.

1. The values are valid for the user-operation mode. There can be deviations for test modes.
2. When selecting the peripheral clock frequencies, care needs to be taken about requirements for baud rates and minimum

4.The DDR data rate is 2x the DDR memory bus frequency. in the reset configuration word, which is loaded at power-on reset. , for more information on the clock subsystem.

4.3.3 Resets

• PORESET — Power-on reset
• H R E S E T — Hard reset
• S R E S E T — Software reset These signals are asynchronous I / O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires the same input characteristics as other MPC5125 inputs, as specified in Section 4.1, “DC Electrical Characteristics.” As long as VDD is not stable the HRESET output is not stable. The timing relationship can be seen in the following figures.

Table 18. Reset Rise / Fall Timing filter to prevent them from getting into the chip. 2 HRESET and SRESET must have a monotonous rise time.

3 The assertion of HRESET becomes active at power-on reset without any

4.3.4 External Interrupts

• IRQ interrupts
• GPIO interrupts with simple interrupt capability (not available in power-down mode)
• Wakeup interrupts IPIC inputs must be valid for at least tPICWID to ensure proper operation in edge-triggered mode.

4.3.5 SDRAM (DDR)

• DDR-1 (SSTL_2 class II interface)
• DDR-2 (SSTL_18 interface)
• LPDDR (1.8V I/O supply voltage)
• SDR D-RAM JEDEC standards define the minimum set of requirements for compliant memory devices:
• JEDEC standard, DDR2 SDRAM specification, JESD79-2C, May 2006
• JEDEC standard, Double Data Rate (DDR ) SDRAM specification, JESD79E, May 2005
• JEDEC standard, Low Power Double Data Rate (LPDDR) SDRAM specification, JESD79-4, May 2006 The MPC5125 supports the configuration of two output drive strengths for DDR2 and LPDDR:
• Full drive strength
• Half drive strength (intended for lighter loads or point-to-point environments) The MPC5125 memory controller supports dynamic on-die termination in the host device and in the DDR2 memory device. This section includes AC specifications for all DDR SDRAM pins. The DC parameters are specified in Section 4.1, “DC Electrical Characteristics.” tH_POR_CONF Reset configuration hold time after assertion of PORESET. 1 cycle A3.15 tHR_SR_DELAY Time from falling edge of HRESET to falling edge of SRESET. 4 cycles A3.16 tHRHOLD Time HRESET must be held low before a qualified reset occurs. 4 cycles A3.17 tSRHOLD Time SRESET must be held low before a qualified reset occurs. 4 cycles A3.18 tSRMIN Time SRESET is asserted after it has been qualified. 1 cycles A3.19 NOTES: 1 The timings will change when using the PLL lock detection circuit.

Table 20. IPIC Input AC Timing Specifications Table 19. Reset Timing (continued)

4.3.5.1 DDR SDRAM AC Timing Specifications

4.3.5.2 MobileDDR/LPDDR SDRAM AC Timing Specifications

Table 21. DDR SDRAM Timing Specifications 1 Measured with clock pin loaded with differential 100 Ω termination resistor. 2 Measured with all outputs except the clock loaded with 50 Ω termination resistor to VDD_IO_MEM/2. 3 All transitions measured at mid-supply (VDD_IO_MEM/2). 4 In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low. SDRAM device. For other values of tDQSEN, the window position is shifted accordingly. Table 22. MobileDDR/LPDDR SDRAM Timing Specifications

4.3.5.3 DDR2 SDRAM AC Timing Specifications

1 Measured with clock pin loaded with differential 100 Ω termination resistor. 2 Measured with all outputs except the clock loaded with 50 Ω termination resistor to VDD_IO_MEM/2. 3 All transitions measured at mid-supply (VDD_IO_MEM/2). 4 In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low. MobileDDR/LPDDR SDRAM device. For other values of tDQSEN, the window position is shifted accordingly. Table 23. DDR2 (DDR2-400) SDRAM Timing Specifications Table 22. MobileDDR/LPDDR SDRAM Timing Specifications (continued)

4.3.5.4 SDR SDRAM AC Timing Specifications

Figure 9 shows the DDR SDRAM write timing. Figure 9. DDR Write Timing 1 Measured with clock pin loaded with differential 100 Ω termination resistor. 2 Measured with all outputs except the clock loaded with 50 Ω termination resistor to VDD_IO_MEM/2. 3 All transitions measured at mid-supply (VDD_IO_MEM/2). 4 In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS should be low. SDRAM device. For other values of tDQSEN, the window position is shifted accordingly. Table 24. SDR SDRAM Timing Specifications 1 Measured with clock pin loaded with 50 Ω termination resistor to mid-supply. 2 Measured with all outputs except the clock loaded with 50 Ω termination resistor to VDD_IO_MEM/2. 3 All transitions measured at mid-supply (VDD_IO_MEM/2).

4.3.6 LPC

maximum bus frequency is 66 MHz. Table 25. LPC Timing

4.3.6.1 Non-MUXed Mode

4.3.6.1.1 Non-MUXed Non-Burst Mode

Figure 14. Timing Diagram — Non-MUXed non-Burst Mode Table 25. LPC Timing (continued)

deasserted after CS[x] is deasserted.

4.3.6.1.2 Non-MUXed Synchronous Read Burst Mode

Figure 15. Timing Diagram — Non-MUXed Synchronous Read Burst Mode

4.3.6.1.3 Non-MUXed Synchronous Write Burst Mode

Figure 16. Timing Diagram — Non-MUXed Synchronous Write Burst

4.3.6.1.4 Non-MUXed Asynchronous Read Burst Mode (Page Mode)

Figure 17. Timing Diagram — Non-MUXed Asynchronous Read Burst

4.3.6.1.5 Non-MUXed Async hronous Write Burst Mode

Figure 18. Timing Diagram — Non-MUXed Asynchronous Write Burst

4.3.6.2 MUXed Mode

4.3.6.2.1 MUXed Non-Burst Mode

Figure 19. Timing Diagram — MUXed non-Burst Mode deasserted after CS[x] is deasserted.

4.3.6.2.2 MUXed Synchr onous Read Burst Mode

Figure 20. Timing Diagram — MUXed Synchronous Read Burst

4.3.6.2.3 MUXed Synchr onous Write Burst Mode

Figure 21. Timing Diagram — MUXed Synchronous Write Burst

4.3.7 NFC

the timing parameters of the NFC. Refer to the MPC5125 Reference Manual (MPC5125RM) for more information about NFC_RATIO_H and NFC_RATIO_L. Table 26. NFC Target Timing Characteristics

Figure 25. Read Data Latch Timing in Non-Fast Mode Figure 26. Read Data Latch Timing in Fast Mode

4.3.8 FEC

• Output Loading All Outputs: 25 pF

Table 27. MII Rx Signal Timing 1 RX_CLK shall have a frequency of 25% of the data rate of the received signal. See the IEEE 802.3 specification.

Figure 27. Ethernet Timing Diagram — MII and RMII Rx Signal Table 28. RMII Rx Signal Timing 1 TX_CLK frequency shall be 50 MHz regardless of the data rate. See the RMII specification. Table 29. MII Tx Signal Timing the IEEE 802.3 specification. Table 30. RMII Tx Signal Timing 1 TX_CLK frequency shall be 50 MHz regardless of the data rate. See the RMII specification.

Figure 30. Ethernet Timing Diagram — MII Serial Management

4.3.9 USB ULPI

This section specifies the USB ULPI timing. For more information refer to UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1, October 20, 2004. Figure 31. ULPI Timing Diagram Table 33. Timing Specifications — USB Output Line 1

4.3.10 MMC/SD/SDIO Card Host Controller (SDHC)

Figure 32 depicts the timings of the SDHC. Figure 32. SDHC Timing Diagram Table 34 lists the timing parameters. 1 Output timing is specified at a nominal 50 pF load. Table 34. MMC/SD Interface Timing Parameters

4.3.11 DIU

The DIU is a display controller designed to manage the TFT LCD display.

4.3.11.1 Interface to TFT LCD Pa nels, Functional Description

• DIU_CLK latches data into the panel on its positive edge (when positive polarity is selected). In active mode, DIU_CLK runs continuously. This signal frequency could be from 5 to 66 MHz depending on the panel type.
• DIU_HSYNC causes the panel to start a new line. It always encompasses at least one DIU_CLK pulse.
• DIU_VSYNC causes the panel to start a new frame. It always encompasses at least one DIU_HSYNC pulse.
• DIU_DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off.

Figure 33. Interface Timing Diagram for TFT LCD Panels

4.3.11.2 Interface to TFT LCD Pane ls, Electrical Characteristics

1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. 2 In normal data transfer mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. 3 In normal data transfer mode for MMC card, clock frequency can be any value between 0–20 MHz. 4 In card identification mode, card clock must be 100 kHz ~ 400 kHz, voltage ranges from 2.7 to 3.6 V.

4.3.12 CAN

wakeup dominant pulse. Any high-to-low edge can cause wakeup, if configured.

4.3.13 I 2C

This section specifies the timing parameters of the inter-integrated circuit (I2C) interface. Refer to the I2C bus specification. Table 37. I2C Input Timing Specifications — SCL and SDA

1 Start condition hold time 2 — IP bus cycle 1

1 Inter-peripheral clock is defined in the MPC5125 Reference Manual (MPC5125RM)

Table 38. I2C Output Timing Specifications — SCL and SDA 1 1 Output timing is specified at a nominal 50 pF load. division values programmed in IFDR. takes to reach a high level depends on external signal capacitance and pullup resistor values. 4 Inter -peripheral Clock is defined in the MPC5125 Reference Manual (MPC5125RM).

Figure 37. Timing Diagram — I 2C Input / Output

4.3.14 J1850

See the MPC5125 Reference Manual (MPC5125RM).

4.3.15 PSC

The programmable serial controllers (PSC) support different modes of operation (UART, codec, AC97, SPI). All the timing numbers specified for different PSC modes are design targets.

4.3.15.1 Codec Mode (8-, 16-, 24-, and 32-Bit) / I2S Mode

Table 39. Timing Specifications — 8-, 16-, 24-, and 32-Bit CODEC/I 2S Master Mode1 1 Output timing is specified at a nominal 50 pF load.

2 Clock duty cycle 45 50 55 % 2

Figure 38. Timing Diagram — 8-,16-, 24-, and 32-bit CODEC/I 2S Master Mode Table 40. Timing Specifications — 8-,16-, 24-, and 32-bit CODEC/I 2S Slave Mode 1 1 Output timing is specified at a nominal 50 pF load.

2 Clock duty cycle — 50 — % 2

Figure 39. Timing Diagram — 8-, 16-, 24-, and 32-bit CODEC/I2S Slave Mode

4.3.15.2 AC97 Mode

Table 41. Timing Specifications — AC97 Mode 1 1 Output timing is specified at a nominal 50 pF load.

Figure 40. Timing Diagram — AC97 Mode

4.3.15.3 SPI Mode

Table 42. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0) 1 1 Output timing is specified at a nominal 50 pF load.

4 Output data valid af ter slave select (SS

Figure 41. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0) Table 43. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0) 1 1 Output timing is specified at a nominal 50 pF load.

6 Output data valid after SS

Figure 42. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0) Table 44. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1) 1 1 Output timing is specified at a nominal 50 pF load.

Figure 43. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1) Table 45. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1) 1 1 Output timing is specified at a nominal 50 pF load.

Figure 44. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1)

4.3.16 GPIOs and Timers

capture by the internal IP clock.

4.3.17 Fusebox

Table 47 gives the Fusebox timing specification. Table 46. GPIO/Timers Input AC Timing Specifications 1 T is the IP bus clock cycle. T = 15 ns is the minimum value (for the maximum IP bus frequency of 66 MHz). Table 47. Fusebox Timing Characteristics 1 The program length is defined by the value defined in the EPM_PGM_LENGTH bits of the IIM module.

Figure 45. Timing Diagram — JTAG Clock Input Table 48. JTAG Timing Specification 1 TRST is an asynchronous signal. The setup time is for test purposes only.

6 Input data setup time 2

2 Non-test, other than TDI and TMS, signal input timing with respect to TCK.

8 TCK to output data valid 3

3 Non-test, other than TDO, signal output timing with respect to TCK.

5 System Design Information

5.1 Power Up/Down Sequencing

• Use 12 V/ms or slower time for all supplies.
• Power up V DD_IO, A VDD_PLLs, VBAT (if not applied permanently), and VDD_IO_MEM supplies first in any order, and then power up VDD. If required A VDD_FUSEWR should be powered up afterwards.
• All the supplies must reach the specified operating conditions before the PORESET can be released.
• For power down, drop A V DD_FUSEWR to 0 V first, drop VDD to 0 V , and then drop all other supplies.
• V DD should not exceed VDD_IO, VDD_IO_MEM, VBAT, or A VDD_PLLs by more than 0.4 V at any time, including power-up.

5.2 System and CPU Core AV DD Power Supply Filtering

All traces should be as low impedance as possible, especially ground pins to the ground plane. onto the portion of that supply between the filter and the MPC5125. add a bypass capacitance of at least 1 µF for the VBAT pin. Figure 49. Power Supply Filtering

5.3 Connection Recommendations

VDD_IO. Unused active high inputs should be connected to VSS. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD and VSS pins of the MPC5125. The unused A VDD_FUSEWR power should be connected to VSS directly or via a resistor. For DDR or LPDDR modes, the unused pins VTT[3:0] for DDR2 termination voltage can be unconnected.

5.4 Pullup/Pulldown Resistor Requirements

The MPC5125 requires external pullup or pulldown resistors on certain pins.

5.4.1 Pulldown Resistor Requirements for TEST Pin

The MPC5125 requires a pulldown resistor on the test pin TEST.

5.5 JTAG

processor (COP) interface, which shares the IEEE 1149.1 JTAG port. provides a means for executing test routines and for performing software development and debug functions.

5.5.1 JTAG_TRST

performance, the JTAG_TRST signal must be asserted during power-on reset.

5.5.1.1 TRST and PORESET

be reset before the MPC5125 comes out of power-on reset; do this by asserting TRST before PORESET is released. For more details, see the Reset and JTAG Timing Specification. Figure 50. PORESET vs. TRST There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector.

5.5.2.1 Boards Interfacing the JTAG Port via a COP Connector

module, it is not recommended to wire only TRST and PORESET. Table 49. COP / BDM Interface Signals

1 With respect to the emulator tool’s perspective:

Input is really an output from the embedded e300 core. Output is really an input to the core.

15 CKSTP_OUT ckstp_out — 10 k Ω Pullup I

13 HRESET hreset Pullup 10 k Ω Pullup O

11 SRESET sreset Pullup 10 k Ω Pullup O

9 TMS tms Pullup 10 k Ω Pullup O

8 CKSTP_IN ckstp_in — 10 k Ω Pullup O

7 TCK tck Pullup 10 k Ω Pullup O

2 From the board under test, power sense for chip power.

5 See Note 3

3 HALTED is not available from e300 core.

3 TDI tdi Pullup 10 k Ω Pullup O

2 See Note pci_frame qack 4 —— O

Figure 51. COP Connector Diagram

5.5.2.2 Boards Without COP Connector

of the JTAG interface without COP connector.

8 CKSTP_IN VDD_IO

Figure 52. TRST Wiring for Boards without COP Connector

Package Information

MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 87

6 Package Information

This section details package parameters and dimensions. The MPC5125 is available in a thermally enhanced plastic ball grid array (TEPBGA). Section 6.1, “Package Parameters,” and Section 6.2, “Mechanical Dimensions,” provide information on the TEPBGA.

6.1 Package Parameters

Table 50. TEPBGA Parameters

MPC5125 Microcontroller Data Sheet, Rev. 3

6.2 Mechanical Dimensions

Figure 3 shows the mechanical dimensions and bottom surface nomenclature of the MPC5125 324 TEPBGA package. Figure 53. Mechanical Drawing of MPC5125 PBGA (1 of 3)

MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor 89 Figure 54. Mechanical Drawing of MPC5125 PBGA (2 of 3)

MPC5125 Microcontroller Data Sheet, Rev. 3 Figure 55. Mechanical Drawing of MPC5125 PBGA (3 of 3)

7 Product Documentation

types are available at: http://www.freescale.com .

• MPC5125 Microprocessor Reference Manual (document number MPC5125RM)
• MPC5125 (0M01S) Errata (document number MSE5125_0M01S)

8 Revision History

Table 51 describes the changes made to this document between revisions. Table 51. Revision History 1 October 2008 Initial public release, NDA required, Advance Information. 2 October 2009 Public release, Technical Data. — Updated specifications according to characterized data. — Updated Table 1, orderable part numbers. — Updated Table 2, pin multiplexing. 3 November 2009 Public release, Technical Data.

Document Number: MPC5125 Rev. 3 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516

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