SN74AHC245-Q1_V01 TI | Alldatasheet
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Technical content
SN74AHC245-Q1 Automotive Octal Bus Transceivers With 3-State Outputs
1 Features
- AEC-Q100 qualified for automotive applications: – Device temperature grade 1: –40°C to +125°C, TA – Device HBM ESD Classification Level 2 – Device CDM ESD Classifcation Level C6
- Operating range 2 V to 5.5 V VCC
- Latch-Up Performance Exceeds 250 mA Per JESD
2 Applications
- Enable or Disable a Digital Signal
- Hold a Signal During Controller Reset
- Debounce a Switch
3 Description
The SN74AHC245-Q1 octal bus transceiver is designed for asynchronous two-way communication between data buses. The control- function implementation minimizes external timing requirements. This device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable ( OE) input can be used to disable the device so that the buses effectively are isolated. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Package Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SN74AHC245-Q1 PW (TSSOP, 20) 6.50 mm × 4.40 mm WRKS (WQFN, 20)(2) 4.50 mm × 2.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Preview DIR OE T o Seven Other Channels Figure 3-1. Simplified Schematic ADVANCE INFORMATION SN74AHC245-Q1 SCLS527B – APRIL 2008 – REVISED NOVEMBER 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.
12.1 Receiving Notification of Documentation Updates..16
13 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (April 2008) to Revision B (November 2022) Page
- Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect SN74AHC245-Q1 SCLS527B – APRIL 2008 – REVISED NOVEMBER 2022 www.ti.com ADVANCE INFORMATION
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5 Pin Configuration and Functions
Figure 5-1. SN74AHC245-Q1 PW Package, 20-Pin TSSOP (Top View) VCC B8GND DIR OE 1 20 10 11 9 12 PAD Figure 5-2. SN74AHC245-Q1 WRKS Package, 20- Pin WQFN (Top View) Table 5-1. Pin Functions PIN I/O(1) DESCRIPTION NO. NAME
1 DIR I/O Direction control input (L = B → A, H = A → B)
2 A1 I/O Channel 1 output/input A
3 A2 I/O Channel 2 output/input A
4 A3 I/O Channel 3 output/input A
5 A4 I/O Channel 4 output/input A
6 A5 I/O Channel 5 output/input A
7 A6 I/O Channel 6 output/input A
8 A7 I/O Channel 7 output/input A
9 A8 I/O Channel 8 output/input A
10 GND G Ground
11 B8 I/O Channel 8 input/output B
12 B7 I/O Channel 7 input/output B
13 B6 I/O Channel 6input/output B
14 B5 I/O Channel 5input/output B
15 B4 I/O Channel 4input/output B
16 B I/O Channel 3input/output B
17 B2 I/O Channel 2input/output B
18 B2 I/O Channel 1input/output B
19 B1 I/O Output enable, active low
20 VCC P Positive supply
Thermal Pad PAD - Thermal Pad(2) (1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power. (2) WRKS Package Only www.ti.com SN74AHC245-Q1 SCLS527B – APRIL 2008 – REVISED NOVEMBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: SN74AHC245-Q1
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VCC Supply voltage range –0.5 7 V VI Input voltage range(2) Control inputs –0.5 7 V VO I/O, Output voltage range –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 Control inputs –20 mA IOK I/O, Output clamp current VO < 0 or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA Continuous current through VCC or GND ±75 mA (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability,functionality, performance, and shorten the device lifetime. (2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002 HBM ESD Classification Level 2(1) ±2000 V Charged device model (CDM), per AEC Q100-011 CDM ESD Classification Level C6 ±1000 (1) AEC Q100-002 indicate that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage 2 5.5 V VIH High-level input voltage VCC = 2 V 1.5 VVCC = 3 V 2.1 VCC = 5.5 V 3.85 VIL Low-level input voltage VCC = 2 V 0.5 VVCC = 3 V 0.9 VCC = 5.5 V 1.65 VI Input voltage OE or DIR 0 5.5 V VO Output voltage A or B 0 VCC V IOH High-level output current VCC = 2 V –50 µA VCC = 3.3 V ± 0.3 V –4 mA VCC = 5 V ± 0.5 V –8 IOL Low-level output current VCC = 2 V 50 µA VCC = 3.3 V ± 0.3 V 4 mA VCC = 5 V ± 0.5 V 8 ∆t/∆v Input transition rise or fall rate VCC = 3.3 V ± 0.3 V 100 ns/V VCC = 5 V ± 0.5 V 20 TA Operating free-air temperature –40 125 °C (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs. SN74AHC245-Q1 SCLS527B – APRIL 2008 – REVISED NOVEMBER 2022 www.ti.com ADVANCE INFORMATION
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6.4 Thermal Information
THERMAL METRIC(1) PW RKS UNIT
20 PINS 20 PINS
RθJA Junction-to-ambient thermal resistance 83 67.7 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C TA = -40°C to 125°C UNIT MIN TYP MAX MIN MAX VOH IOH = –50 µA 2 V 1.9 2 1.9 V 3 V 2.9 3 2.9 4.5 V 4.4 4.5 4.4 IOH = –4 mA 3 V 2.58 2.48 IOH = –8 mA 4.5 V 3.94 3.8 VOL IOL = 50 µA 2 V 0.1 0.1 V 3 V 0.1 0.1 4.5 V 0.1 0.1 IOL = 4 mA 3 V 0.36 0.44 IOL = 8 mA 4.5 V 0.36 0.44 II A or B inputs V I = VCC or GND 5.5 V ±0.1 ±1 µA OE or DIR 0 V to 5.5 V ±0.1 ±1 IOZ (1) VO = VCC or GND, VI ( OE) = VIL or VIH ICC VI = VCC or GND, IO = 0 5.5 V 4 40 µA Ci OE or DIR VI = VCC or GND 5 V 2.5 10 10 pF Cio A or B inputs VI = VCC or GND 5 V 4 pF (1) The parameter IOZ includes the input leakage current. 6.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE TA = 25°C TA = -40°C to 125°C UNIT MIN TYP MAX MIN MAX tPLH A or B B or A CL = 15 pF 5.8 8.4 1 10 ns tPHL 5.8 8.4 1 10 tPZH OE A or B CL = 15 pF 8.5 13.2 1 15.5 ns tPZL 8.5 13.2 1 15.5 tPHZ OE A or B CL = 15 pF 8.9 12.5 1 15.5 ns tPLZ 8.9 12.5 1 15.5 tPLH A or B B or A CL = 50 pF 8.3 11.9 1 13.5 ns tPHL 8.3 11.9 1 13.5 tPZH OE A or B CL = 50 pF 11 16.7 1 19 ns tPZL 11 16.7 1 19 tPHZ OE A or B CL = 50 pF 11.5 15.8 1 18 ns tPLZ 11.5 15.8 1 18 www.ti.com SN74AHC245-Q1 SCLS527B – APRIL 2008 – REVISED NOVEMBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: SN74AHC245-Q1
6.7 Switching Characteristics, VCC = 5 V ± 0.5 V over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE TA = 25°C TA = -40°C to 125°C UNIT MIN TYP MAX MIN MAX tPLH A or B B or A CL = 15 pF 4 5.5 1 6.5 ns tPHL 4 5.5 1 6.5 tPZH OE A or B CL = 15 pF 5.8 8.5 1 10 ns tPZL 5.8 8.5 1 10 tPHZ OE A or B CL = 15 pF 5.6 7.8 1 9.2 ns tPLZ 5.6 7.8 1 9.2 tPLH A or B B or A CL = 50 pF 5.5 7.5 1 8.5 ns tPHL 5.5 7.5 1 8.5 tPZH OE A or B CL = 50 pF 7.3 10.6 1 12 ns tPZL 7.3 10.6 1 12 tPHZ OE A or B CL = 50 pF 7 9.7 1 11 ns tPLZ 7 9.7 1 11
6.8 Noise Characteristics
VCC = 5 V, CL = 50 pF, TA = 25°C (1) PARAMETER MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.9 V VOL(V) Quiet output, minimum dynamic VOL –0.9 V VOH(V) Quiet output, minimum dynamic VOH 4.3 V VIH(D) High-level dynamic input voltage 3.5 V VIL(D) Low-level dynamic input voltage 1.5 V (1) Characteristics are for surface-mount packages only.
6.9 Operating Characteristics
VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load f = 1 MHz 14 pF SN74AHC245-Q1 SCLS527B – APRIL 2008 – REVISED NOVEMBER 2022 www.ti.com ADVANCE INFORMATION
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6.10 Typical Characteristics
V CC (V) ICC (nA) 100 25°C 125°C -40°C Figure 6-1. Supply Current Across Voltage Supply Voltage V IN (V) ICC (µA) 140 210 280 350 420 490 560 630 700 25°C 125°C -40°C Figure 6-2. Supply Current Across Input Voltage; 5-V Supply IOH (mA) V OH (V) 3.03 3.06 3.09 3.12 3.15 3.18 3.21 3.24 3.27 3.3 25°C 125°C -40°C Figure 6-3. Output Voltage vs Current in HIGH State; 3.3-V Supply IOL (mA) V OL (V) 0 1 2 3 4 5 6 7 8 0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 25°C 125°C -40°C Figure 6-4. Output Voltage vs Current in LOW State; 3.3-V Supply IOH (mA) V OH (V) 4.5 4.55 4.6 4.65 4.7 4.75 4.8 4.85 4.9 4.95 25°C 125°C -40°C Figure 6-5. Output Voltage vs Current in HIGH State; 5-V Supply IOL (mA) V OL (V) 0 2 4 6 8 10 12 14 16 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 25°C 125°C -40°C Figure 6-6. Output Voltage vs Current in LOW State; 5-V Supply www.ti.com SN74AHC245-Q1 SCLS527B – APRIL 2008 – REVISED NOVEMBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: SN74AHC245-Q1
7 Parameter Measurement Information
50% VCC VCC VCC 0 V 0 V th tsu VOL T AGE WAVEFORMS SETUP AND HOLD TIMES Data Input tPLH tPHL tPHL tPLH VOH VOH VOL VOL VCC 0 V 50% VCC50% VCC Input Out-of-Phase Output In-Phase Output Timing Input 50% VCC VOL T AGE WAVEFORMS PROP AGATION DELA Y TIMES INVERTING AND NONINVERTING OUTPUTS Output Control Output Waveform 1 S1 at VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) VOL VOH tPZL tPZH tPLZ tPHZ ≈ VCC 0 V 50% VCC VOL + 0.3 V 50% VCC ≈ 0 V VCC VOL T AGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC TEST S1 VCC 0 V 50% VCC tw VOL T AGE WAVEFORMS PULSE DURA TION Input NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, t r ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. From Output Under T est CL (see Note A) LOAD CIRCUIT FOR 3-ST A TE AND OPEN-DRAIN OUTPUTS VCC RL = 1 kΩ GND From Output Under T est CL (see Note A) T est Point LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS Open 50% VCC 50% VCC 50% VCC 50% VCC 50% VCC 50% VCC 50% VCC 50% VCC VOH – 0.3 V Figure 7-1. Load Circuit and Voltage Waveforms SN74AHC245-Q1 SCLS527B – APRIL 2008 – REVISED NOVEMBER 2022 www.ti.com ADVANCE INFORMATION
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8 Detailed Description
8.1 Overview
The SN74AHC245-Q1 is designed for asynchronous two-way communication between data buses. The control- function implementation minimizes external timing requirements. The SN74AHC245-Q1 allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable ( OE) input can be used to disable the device so that the buses are effectively isolated. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Standard CMOS Inputs
This device includes standard CMOS inputs. Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics . The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I). Standard CMOS inputs require that input signals transition between valid logic states quickly, as defined by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this specification will result in excessive power consumption and could cause oscillations. More details can be found in Implications of Slow or Floating CMOS Inputs. Do not leave standard CMOS inputs floating at any time during operation. Unused inputs must be terminated at VCC or GND. If a system will not be actively driving an input at all times, then a pull-up or pull-down resistor can be added to provide a valid input voltage during these times. The resistor value will depend on multiple factors; a 10-kΩ resistor, however, is recommended and will typically meet all requirements.
8.3.2 Balanced CMOS 3-State Outputs
This device includes balanced CMOS 3-state outputs. Driving high, driving low, and high impedance are the three states that these outputs can be in. The term balanced indicates that the device can sink and source similar currents. The drive capability of this device may create fast edges into light loads, so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device can drive larger currents than the device can sustain without being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. When placed into the high-impedance mode, the output will neither source nor sink current, with the exception of minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected to the node, then this is known as a floating node and the voltage is unknown. A pull-up or pull-down resistor www.ti.com SN74AHC245-Q1 SCLS527B – APRIL 2008 – REVISED NOVEMBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: SN74AHC245-Q1
can be connected to the output to provide a known voltage at the output while it is in the high-impedance state. The value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption limitations. Typically, a 10-kΩ resistor can be used to meet these requirements. Unused 3-state CMOS outputs should be left disconnected.
8.3.3 Wettable Flanks
This device includes wettable flanks for at least one package. See the Features section on the front page of the data sheet for which packages include this feature. Package We able Flank Lead PCB Pad Standard Lead Package Solder Figure 8-1. Simplified Cutaway View of Wettable-Flank QFN Package and Standard QFN Package After Soldering Wettable flanks help improve side wetting after soldering, which makes QFN packages easier to inspect with automatic optical inspection (AOI). As shown in Figure 8-1 , a wettable flank can be dimpled or step-cut to provide additional surface area for solder adhesion which assists in reliably creating a side fillet. See the mechanical drawing for additional details.
8.3.4 Clamp Diode Structure
As Figure 8-2 shows, the outputs to this device have both positive and negative clamping diodes, and the inputs to this device have negative clamping diodes only. CAUTION Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input and output voltage ratings may be exceeded if the input and output clamp- current ratings are observed. GND LogicInput Output VCCDevice -IIK +IOK -IOK Figure 8-2. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Function Table lists the functional modes of the SN74AHC245-Q1. SN74AHC245-Q1 SCLS527B – APRIL 2008 – REVISED NOVEMBER 2022 www.ti.com ADVANCE INFORMATION
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Table 8-1. Function Table INPUTS(1) OUTPUTS(2) OE DIR A B L L B Z L H Z A H X Z Z (1) H = High voltage level, L = Low voltage level, X = Don't care (2) A = Logic value at 'A' input, B = Logic value at 'B' input, Z = High impedance www.ti.com SN74AHC245-Q1 SCLS527B – APRIL 2008 – REVISED NOVEMBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: SN74AHC245-Q1
9 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
9.1 Application Information
The SN74AHC245-Q1 can be used to drive signals over relatively long traces or transmission lines. In order to reduce ringing caused by impedance mismatches between the driver, transmission line, and receiver, a series damping resistor placed in series with the transmitter’s output can be used. The figure in the Application Curve section shows the received signal with three separate resistor values. Just a small amount of resistance can make a significant impact on signal integrity in this type of application.
9.2 Typical Application
L > 12 cm Peripheral Rd Transceiver 2 Figure 9-1. Application block diagram
9.2.1 Design Requirements
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9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics section. The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the SN74AHC245-Q1 plus the maximum static supply current, I CC, listed in the Electrical Characteristics, and any transient current required for switching. The logic device can only source as much current that is provided by the positive supply source. Be sure to not exceed the maximum total current through VCC listed in the Absolute Maximum Ratings. The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the SN74AHC245-Q1 plus the maximum supply current, I CC, listed in the Electrical Characteristics , and any transient current required for switching. The logic device can only sink as much current that can be sunk into its ground connection. Be sure to not exceed the maximum total current through GND listed in the Absolute Maximum Ratings. The SN74AHC245-Q1 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed 50 pF. The SN74AHC245-Q1 can drive a load with total resistance described by R L ≥ VO / I O, with the output voltage and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state, the output voltage in the equation is defined as the difference between the measured output voltage and the supply voltage at the VCC pin. Total power consumption can be calculated using the information provided in CMOS Power Consumption and Cpd Calculation. Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices. CAUTION The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum Ratings. These limits are provided to prevent damage to the device.
9.2.1.2 Input Considerations
Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do not exceed the maximum input voltage range found in the Absolute Maximum Ratings. Unused inputs must be terminated to either V CC or ground. The unused inputs can be directly terminated if the input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used for a default state of LOW. The drive current of the controller, leakage current into the SN74AHC245-Q1 (as specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10-k Ω resistor value is often used due to these factors. The SN74AHC245-Q1 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power consumption, and reduction in device reliability. Refer to the Feature Description section for additional information regarding the inputs for this device. www.ti.com SN74AHC245-Q1 SCLS527B – APRIL 2008 – REVISED NOVEMBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: SN74AHC245-Q1
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will decrease the output voltage as specified by the V OH specification in the Electrical Characteristics. The ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as specified by the VOL specification in the Electrical Characteristics. Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected directly together. This can cause excessive current and damage to the device. Two channels within the same device with the same input signals can be connected in parallel for additional output drive strength. Unused outputs can be left floating. Do not connect outputs directly to VCC or ground. Refer to the Feature Description section for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
- Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout section. 2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit; it will, however, ensure optimal performance. This can be accomplished by providing short, appropriately sized traces from the SN74AHC245-Q1 to one or more of the receiving devices. 3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load measured in MΩ; much larger than the minimum calculated previously. 4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however, can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation.
9.2.3 Application Curves
Time (ns) 0 15 30 45 60 75 90 100 3.3 Figure 9-2. Simulated Signal Integrity at the Receiver With Different Damping Resistor (Rd) Values
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Absolute Maximum Ratings section. Each VCC terminal must have a good bypass capacitor to prevent power disturbance. For devices with a single supply, TI recommends a 0.1-μF capacitor; if there are multiple VCC terminals, then TI recommends a 0.01-μF or 0.022-μF capacitor for each power terminal. Multiple bypass capacitors can be paralleled to reject different frequencies of noise. Frequencies of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor must be installed as close as possible to the power terminal for best results. SN74AHC245-Q1 SCLS527B – APRIL 2008 – REVISED NOVEMBER 2022 www.ti.com ADVANCE INFORMATION
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11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient.
11.2 Layout Example
Avoid 90° corners for signal lines Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation VCC B8GND DIR OE 1 20 10 11 9 12 GNDVCC GND Figure 11-1. Example layout for the SN74AHC245-Q1 in the RKS package. www.ti.com SN74AHC245-Q1 SCLS527B – APRIL 2008 – REVISED NOVEMBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: SN74AHC245-Q1
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. SN74AHC245-Q1 SCLS527B – APRIL 2008 – REVISED NOVEMBER 2022 www.ti.com ADVANCE INFORMATION
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www.ti.com 9-Dec-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PN74AHC245QWRKSRQ1 ACTIVE VQFN RKS 20 3000 TBD Call TI Call TI -40 to 125 Samples SN74AHC245QPWRG4Q1 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHC245Q1 Samples SN74AHC245QPWRQ1 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHC245Q1 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1
www.ti.com 9-Dec-2022 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74AHC245-Q1 :
- Catalog : SN74AHC245
- Enhanced Product : SN74AHC245-EP
- Military : SN54AHC245 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
- Enhanced Product - Supports Defense, Aerospace and Medical Applications
- Military - QML certified for Military and Defense Applications Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2022 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AHC245QPWRG4Q1 TSSOP PW 20 2000 356.0 356.0 35.0 SN74AHC245QPWRQ1 TSSOP PW 20 2000 356.0 356.0 35.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 18X 0.65 5.85 20X 0.30 0.19 TYP6.6 6.2
1.2 MAX
0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 6.6 6.4 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0020A SMALL OUTLINE PACKAGE 4220206/A 02/2017
0.1 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
20X (1.5) 20X (0.45) 18X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0020A SMALL OUTLINE PACKAGE 4220206/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 10 11 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 20X (1.5) 20X (0.45) 18X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0020A SMALL OUTLINE PACKAGE 4220206/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 10 11
www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRKS 20 PLASTIC QUAD FLATPACK - NO LEAD2.5 x 4.5, 0.5 mm pitch 4226872/A
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