PMV117EN NEXPERIA | Alldatasheet
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Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. use http://www.nexperia.com salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e -mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia
- Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS™ technology.
1.2 Features
1.3 Applications
1.4 Quick reference data
- Pinning information PMV117EN µTrenchMOS™ enhanced logic level FET Rev. 02 — 7 April 2005 Product data sheet ■ Logic level threshold ■ Very fast switching ■ Subminiature surface-mounted package ■ Battery management ■ Low power DC-to-DC converter ■ High-speed switch ■ VDS ≤ 30 V ■ ID ≤ 2.5 A ■ R DSon ≤ 117 mΩ (VGS =1 0V ) ■ Ptot≤ 0.83 W Table 1: Pinning Pin Description Simplified outline Symbol 1 gate (G) SOT23 2 source (S) 3 drain (D) S D G mbb076
9397 750 14709 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 — 7 April 2005 2 of 12 Philips Semiconductors PMV117EN µTrenchMOS™ enhanced logic level FET 3. Ordering information 4. Limiting values Table 2: Ordering information Type number Package Name Description Version PMV117EN TO-236AB plastic surface mounted package; 3 leads SOT23 Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage (DC) 25 °C ≤ Tj≤ 150 °C - 30 V VDGR drain-gate voltage (DC) 25 °C ≤ Tj≤ 150 °C; RGS =2 0kΩ -3 0 V VGS gate-source voltage (DC) - ±20 V ID drain current (DC) T sp =2 5°C; VGS =1 0V ;Figure2 and3 - 2.5 A Tsp = 100°C; VGS =1 0V ;Figure2 - 1.6 A IDM peak drain current T sp =2 5°C; pulsed; tp ≤ 10 µs;Figure3 -1 0 A Ptot total power dissipation T sp =2 5°C; Figure1 - 0.83 W Tstg storage temperature −65 +150 °C Tj junction temperature −65 +150 °C Source-drain diode I S source (diode forward) current (DC) Tsp =2 5°C - 0.8 A ISM peak source (diode forward) current Tsp =2 5°C; pulsed; tp ≤ 10 µs - 3.3 A
9397 750 14709 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 — 7 April 2005 3 of 12 Philips Semiconductors PMV117EN µTrenchMOS™ enhanced logic level FET VGS ≥ 10 V Fig 1. Normalized total power dissipation as a function of solder point temperature Fig 2. Normalized continuous drain current as a function of solder point temperature Tsp =2 5°C; IDM is single pulse Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 03aa17 120 0 50 100 150 200 Tsp (°C) Pder (%) 03aa25 120 0 50 100 150 200 Tsp (°C) Ider (%) P der P tot P tot 25 C°() Ider ID I D2 5 C°() 03ak56 10−1 102 ID (A) 10−2 VDS (V) 10−1 102101 tp = 10 µs 100 µs 1 ms 10 ms 100 ms Limit RDSon = VDS / ID DC
9397 750 14709 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 — 7 April 2005 4 of 12 Philips Semiconductors PMV117EN µTrenchMOS™ enhanced logic level FET 5. Thermal characteristics Table 4: Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit R th(j-sp) thermal resistance from junction to solder pointFigure4 - - 100 K/W Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration 03ak55 10−4 tp (s) 11 010−110−3 10−2 102 103 Zth(j-sp) (K/W) tp tp T P t Tδ = δ = 0.5 0.2 0.1 0.05 0.02 single pulse
9397 750 14709 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 — 7 April 2005 5 of 12 Philips Semiconductors PMV117EN µTrenchMOS™ enhanced logic level FET 6. Characteristics Table 5: Characteristics Tj=2 5°C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Static characteristics V (BR)DSS drain-source breakdown voltage ID =1 0µA; VGS =0V Tj=2 5°C 3 03 7- V VGS(th) gate-source threshold voltage I D = 1 mA; VDS =V GS ;Figure9 and10 Tj=2 5°C 1.5 2 - V IDSS drain-source leakage current V DS =2 4V ; VGS =0V Tj=2 5°C - 0.01 0.5 µA Tj= 150°C --1 0 µA IGSS gate-source leakage current V GS = ±20 V; VDS = 0 V - 10 100 nA R DSon drain-source on-state resistance VGS =1 0V ; ID = 500 mA;Figure6 and8 Tj=2 5°C - 74 117 m Ω VGS = 4.5 V; ID = 500 mA;Figure6 and8 - Tj=2 5°C - 117 190 m Ω Tj= 150°C 188 300 m Ω Dynamic characteristics Q g(tot) total gate charge I D = 0.5 A; VDD =1 5V ; VGS =1 0V ; Figure11 - 4.6 - nC Q gs gate-source charge - 0.6 - nC Q gd gate-drain (Miller) charge - 1.35 - nC C iss input capacitance V GS =0V ; VDS = 10 V; f = 1 MHz; Figure13 - 147 - pF C oss output capacitance - 65 - pF C rss reverse transfer capacitance - 41 - pF td(on) turn-on delay time V DD =1 5V ; RL =1 5Ω ; VGS =1 0V - 4 - n s tr rise time - 7.5 - ns td(off) turn-off delay time - 18 - ns tf fall time -1 3 -n s Source-drain diode V SD source-drain (diode forward) voltage IS = 0.83 A; VGS =0V ;Figure12 - 0.7 1.2 V trr reverse recovery time I S = 1 A; dIS/dt =−100 A/µs; VGS =0V ; VDS =2 5V -6 9 -n s
9397 750 14709 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 — 7 April 2005 6 of 12 Philips Semiconductors PMV117EN µTrenchMOS™ enhanced logic level FET Tj=2 5°CT j=2 5°C Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values Fig 6. Drain-source on-state resistance as a function of drain current; typical values Tj=2 5°C and 150°C; VDS >ID × R DSon Fig 7. Transfer characteristics: drain current as a function of gate-source voltage; typical values Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature 03ak57 0 0.2 0.4 0.6 0.8 1 VDS (V) I D (A) 3.8 VGS (V) = 2.4 3.610 6 4.5 3.4 2.6 2.8 3.2 03ak58
0123 ID (A)
R DSon (mΩ ) Tj = 25 ˚C VGS (V) = 3 3.2 3.6 3.8 4.5 3.4 03ak59 01234 VGS (V) I D (A) VDS > ID × RDSon Tj = 150 ˚C 25 ˚C 03ad57 −60 0 60 120 180 Tj (°C) 0.5 1.5 a a R DSon R DSon 25 C°()
9397 750 14709 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 — 7 April 2005 7 of 12 Philips Semiconductors PMV117EN µTrenchMOS™ enhanced logic level FET ID = 1 mA; VDS =V GS Tj=2 5°C; VDS =5V Fig 9. Gate-source threshold voltage as a function of junction temperature Fig 10. Sub-threshold drain current as a function of gate-source voltage ID = 0.5 A; VDD =1 5V Fig 11. Gate-source voltage as a function of gate charge; typical values 03ak63 −60 0 60 120 180 Tj (°C) 0.5 1.5 2.5 VGS(th) (V) typ min 03ak64 0 0.8 1.6 2.4 3.2 VGS (V) 10−1 10−2 10−3 10−4 10−5 10−6 ID (A) typmin 03ak62
0246 Q G (nC)
(V) ID = 0.5 A Tj = 25 °C VDD = 15 V
9397 750 14709 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 — 7 April 2005 8 of 12 Philips Semiconductors PMV117EN µTrenchMOS™ enhanced logic level FET Tj=2 5°C and 150°C; VGS =0V V GS = 0 V; f = 1 MHz Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values Fig 13. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 03ak60 0 0.3 0.6 0.9 1.2 VSD (V) IS (A) VGS = 0 V Tj = 150 ˚C 25 ˚C 03ak61 10−1 11 0 1 0 2 VDS (V) 102 103 C (pF) C iss C oss C rss
9397 750 14709 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 — 7 April 2005 9 of 12 Philips Semiconductors PMV117EN µTrenchMOS™ enhanced logic level FET 7. Package outline Fig 14. Package outline SOT23 UNIT A 1 max. bp cD E e1 H E Lp Qw v REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE 99-09-13 04-11-04 IEC JEDEC JEITA mm 0.1 0.48 0.38 0.15 0.09 3.0 2.8 1.4 1.2 0.95 e 1.9 2.5 2.1 0.55 0.45 0.10.2 DIMENSIONS (mm are the original dimensions) 0.45 0.15 SOT23 TO-236AB bp D e A Lp Q detail X H E E w M v M A B AB 0 1 2 mm scale A 1.1 0.9 c X Plastic surface mounted package; 3 leads SOT23
9397 750 14709 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 — 7 April 2005 10 of 12 Philips Semiconductors PMV117EN µTrenchMOS™ enhanced logic level FET 8. Revision history Table 6: Revision history Document ID Release date Data sheet statusChange notice Doc. number Supersedes PMV117EN_2 20050407 Product data sheet - 9397 750 14709 PMV117EN-01 Modifications:
- The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors.
- Table 5 “Characteristics”; correction to VGS(th) data
- Table 2 “Ordering information”: added PMV117EN-01 20030226 Product data - 9397 750 11095 -
Philips Semiconductors PMV117EN µTrenchMOS™ enhanced logic level FET 9397 750 14709 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 — 7 April 2005 11 of 12 9. Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 10. Definitions Short-form specification —The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 11. Disclaimers Life support —These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes —Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 12. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V. 13. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com Level Data sheet status[1] Product status[2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
© Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 7 April 2005 Document number: 9397 750 14709 Published in The Netherlands Philips Semiconductors PMV117EN µTrenchMOS™ enhanced logic level FET 14. Contents