MSP430C33X_00 TI | Alldatasheet
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MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Low Supply Voltage Range 2.5 V – 5.5 V /C0068Low Operation Current, 400 /C0109A at 1 MHz, /C0068Ultralow-Power Consumption: – Standby Mode: 2 mA – RAM Retention Off Mode: 0.1 mA /C0068Five Power-Saving Modes /C0068Wake-Up From Standby Mode in 6 ms /C006816-Bit RISC Architecture, 300 ns Instruction Cycle Time /C0068Single Common 32 kHz Crystal, Internal System Clock up to 3.8 MHz /C0068Integrated LCD Driver for up to 120 Segments /C0068Integrated Hardware Multiplier Performs Signed, Unsigned on Multiply, and MAC Operations for Operands up to 16 × 16 Bits /C0068Serial Communication Interface (USART), Select Asynchronous UART or Synchronous SPI by Software /C0068Slope A/D Converter Using External Components /C006816-Bit Timer With Five Capture/Compare Registers /C0068Serial Onboard Programming /C0068Programmable Code Protection by Security Fuse /C0068Family Members Include: – MSP430C336 – 24 KB ROM, 1 KB RAM – MSP430C337 – 32 KB ROM, 1 KB RAM – MSP430P337A – 32 KB OTP, 1 KB RAM /C0068EPROM Version Available for Prototyping: – PMS430E337A /C0068Available in the Following Packages: – 100 Pin Quad Flat-Pack (QFP) – 100 Pin Ceramic Quad Flat-Pack (CFP) (EPROM Version)
description
The Texas Instruments MSP430 is an ultralow-power mixed signal microcontroller family consisting of several devices featuring different sets of modules targeted to various applications. The controller is designed to be battery-operated for an extended application lifetime. With the 16-bit RISC architecture, 16 integrated registers on the CPU, and a constant generator, the MSP430 achieves maximum code efficiency. The digital-controlled oscillator, together with the frequency lock loop (FLL), provides a wake-up from a low-power mode to an active mode in less than 6 /C0109s. The MSP430x33x series microcontrollers have built-in hardware multiplication and communication capability using asynchronous (UART) and synchronous protocols. Typical applications of the MSP430 family include electronic gas, water, and electric meters and other sensor systems that capture analog signals, convert them to digital values, process, displays, or transmits data to a host system. AVAILABLE OPTIONS PACKAGED DEVICES TA PLASTIC QFP (PJM) CERAMIC QFP (HFD) 40°Ct o8 5°C MSP430C336IPJM MSP430C337IPJM–40°C to 85°C MSP430C337IPJM MSP430P337AIPJM 25°C PMS430E337AHFD25°C — PMS430E337AHFD Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2000, Texas Instruments Incorporated
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000
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TP0.0 TP0.1 TP0.2 TP0.3 TP0.4 TP0.5 P0.0 P0.2/TXD P0.3 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.6 P1.7 Xin Xout/TCLK RST/NMI TCK TMS TDI/VPP TDO/TDI R13 S27/O27 S26/O26 S25/O25 S24/O24 S23/O23 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.3/TA0 P3.4/TA1 P3.6/TA3 P3.7/TA4 P4.0 P4.1 P4.2/STE P4.4/SOMI P4.5/UCLK VSS3 P4.3/SIMO PJM or HFD PACKAGE (TOP VIEW) CIN S29/O29/CMPI R33 R23 S20/O20 S5/O5 P3.5/TA2 P0.1/RXD P1.5 P2.1 P2.2 NC COM1 COM2 COM3 P4.7/URXD S28/O28 XBUF VCC1 P0.4 P2.0 VSS2 VCC2 P3.2/TACLK P4.6/UTXD S18/O18 S6/O6 SS1V R03 NC – No internal connection
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram Oscillator FLL System Clock ACLK MCLK 24/32 kB ROM 32 kB OPT or 1024B RAM SRAM Power-on- Reset I/O Port 1x8 Digital I/O’s I/O Port 2x8 I/O’s All Interr. Cap. 8 8 2 Int. Vectors I/O Port 1x8 Digital I/O’s I/O Port
8 I/O’s, All With
Interr. Cap. 3 Int. Vectors CPU Incl. 16 Reg. Test JTAG Bus Conv USART UART or
8 Bit Timer/Port
Applications
Timer, O/P Basic LCD
120 Segments
1, 2, 3, 4 MUXSPI Function Timer/Counter Timer1MPY Watchdog TimerA MPYS Timer MACS 16x16 Bit 8x8 Bit 15/16 Bit
16 Bit
MAB, 16 Bit MDB, 16 Bit MAB, 4 Bit MDB, 8 Bit MCB TACLK TA0–4 UTXD URXD UCLK STE SIMO SOMI TXD RXD LCDf CMPI TP0.0–0.5 CIN Com0–3 S0–28/O2–28 S29/O29/CMPI R03 R13 R23 R33 TDI/VPP TDO/TDI TMS TCK USART TimerA RXD, TXD A/D Conv. EPROM C: ROM P: OTP E: EPROM Multiplier VCC1 VCC2 VSS1 VSS2 VSS3
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000
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NAME NO. I/O DESCRIPTION CIN 2 I Input port. CIN is used as an enable for counter TPCNT1 – (Timer/Port). COM0–3 56–53 O Common outputs. COM0-3 are used for LCD backplanes – LCD P0.0 9 I/O General-purpose digital I/O P0.1/RXD 10 I/O General-purpose digital I/O, receive digital Input port – 8-Bit Timer/Counter P0.2/TXD 11 I/O General-purpose digital I/O, transmit data output port – 8-Bit Timer/Counter P0.3–P0.7 12–16 I/O Five general-purpose digital I/Os, bit 3-7 P1.0–P1.7 17–24 I/O Eight general-purpose digital I/Os, bit 0-7 P2.0–P2.7 25–27, 31–35 I/O Eight general-purpose digital I/Os, bit 0-7 P3.0, P3.1 36,37 I/O Two general-purpose digital I/Os, bit 0 and bit 1 P3.2/TACLK 38 I/O General-purpose digital I/O, clock input – Timer_A P3.3/TA0 39 I/O General-purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR0 P3.4/TA1 40 I/O General-purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR1 P3.5/TA2 41 I/O General-purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR2 P3.6/TA3 42 I/O General-purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR3 P3.7/TA4 43 I/O General-purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR4 P4.0 44 I/O General-purpose digital I/O, bit 0 P4.1 45 I/O General-purpose digital I/O, bit 1 P4.2/STE 46 I/O General-purpose digital I/O, slave transmit enable – USART/SPI mode P4.3/SIMO 47 I/O General-purpose digital I/O, slave in/master out – USART/SPI mode P4.4/SOMI 48 I/O General-purpose digital I/O, master in/slave out – USART/SPI mode P4.5/UCLK 49 I/O General-purpose digital I/O, external clock input – USART P4.6/UTXD 50 I/O General-purpose digital I/O, transmit data out – USART/UART mode P4.7/URXD 51 I/O General-purpose digital I/O, receive data in – USART/UART mode R03 88 I Input port of fourth positive (lowest) analog LCD level (V5) – LCD R13 89 I Input port of third most positive analog LCD level (V3 of V4) – LCD R23 90 I Input port of second most positive analog LCD level (V2) – LCD R33 91 O Output of most positive analog LCD level (V1) – LCD RST /NMI 96 I Reset input or non-maskable interrupt input port S0 57 O Segment line S0 – LCD S1 58 O Segment line S1 – LCD S2/O2–S5/O5 59–62 O Segment lines S2 to S5 or digital output ports, O2-O5, group 1 – LCD S6/O6–S9/O9 63–66 O Segment lines S6 to S9 or digital output ports O6-O9, group 2 – LCD S10/O10–S13/O13 67–70 O Segment lines S10 to S13 or digital output ports O10-O13, group 3 – LCD S14/O14–S17/O17 71–74 O Segment lines S14 to S17 or digital output ports O14-O17, group 4 – LCD S18/O18–S21/O21 75–78 O Segment lines S18 to S21 or digital output ports O18-O21, group 5 – LCD S22/O22–S25/O25 79, 81–83 O Segment line S22 to S25 or digital output ports O22-O25, group 6 – LCD S26/O26–S29/O29/CMPI 84–87 O Segment line S26 to S29 or digital output ports O26-O29, group 7 – LCD. Segment line S29 can be used as comparator input port CMPI – Timer/Port TCK 95 I Test clock. TCK is the clock input port for device programming and test. TDI/VPP 93 I Test data input. TDI/VPP is used as a data input port or input for programming voltage.
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION TMS 94 I Test mode select. TMS is used as an input port for device programming and test. TDO/TDI 92 I/O Test data output port. TDO/TDI data output or programming data input terminal TP0.0 3 O General-purpose 3-state digital output port, bit 0 – Timer/Port TP0.1 4 O General-purpose 3-state digital output port, bit 1 – Timer/Port TP0.2 5 O General-purpose 3-state digital output port, bit 2 – Timer/Port TP0.3 6 O General-purpose 3-state digital output port, bit 3 – Timer/Port TP0.4 7 O General-purpose 3-state digital output port, bit 4 – Timer/Port TP0.5 8 I/O General-purpose 3-state digital input/output port, bit 5 – Timer/Port VCC1 1 Positive supply voltage VCC2 29 Positive supply voltage VSS1 100 Ground reference VSS2 28 Ground reference VSS3 52 Ground reference XBUF 97 O System clock (MCLK) or crystal clock (ACLK) output Xin 99 I Input port for crystal oscillator Xout/TCLK 98 I/O Output terminal of crystal oscillator or test clock input detailed description processing unit The processing unit is based on a consistent and orthogonal designed CPU and instruction set. This design structure results in a RISC-like architecture, highly transparent to the application development, which is distinguished by ease of programming. All operations other than program-flow instructions consequently are performed as register operations in conjunction with seven addressing modes for source and four modes for destination operand. CPU registers The CPU has sixteen registers that provide reduced instruction execution time. This reduces the register-to-register operation execution time to one cycle of the processor frequency. Four of the registers are reserved for special use as a program counter, a stack pointer, a status register, and a constant generator. The remaining registers are available as general-purpose regis- ters. Peripherals are connected to the CPU using a data address and control bus and can be handled easily with all instructions for memory manipula- tion. Program Counter General-Purpose Register PC/R0 Stack Pointer SP/R1 Status Register SR/CG1/R2 Constant Generator CG2/R3 General-Purpose Register R5 General-Purpose Register R14 General-Purpose Register R15
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language. The instruction set consists of 51 instructions with three formats and seven addressing modes. Table 1. Instruction Word Formats Table 2. Address Mode Descriptions NOTE 1: S = source, D = destination. instead of using flag type programs for flow control.
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operation modes and interrupts The MSP430 operating modes support various advanced requirements for ultralow-power and ultralow-energy consumption. This is achieved by the intelligent management of the operations during the different module operation modes and CPU states. The requirements are fully supported during interrupt event handling. An interrupt event awakens the system from each of the various operating modes and returns with the RETI instruction to the mode that was selected before the interrupt event. The clocks used are ACLK and MCLK. ACLK is the crystal frequency and MCLK, a multiple of ACLK, is used as the system clock. The following five operating modes are supported: /C0068Active mode (AM). The CPU is enabled with different combinations of active peripheral modules. /C0068Low-power mode 0 (LPM0). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals are active, and loop control for MCLK is active. /C0068Low-power mode 1 (LPM1). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals are active, and loop control for MCLK is inactive. /C0068Low-power mode 2 (LPM2). The CPU is disabled, peripheral operation continues, ACLK signal is active, and MCLK and loop control for MCLK are inactive. /C0068Low-power mode 3 (LPM3). The CPU is disabled, peripheral operation continues, ACLK signal is active, MCLK and loop control for MCLK are inactive, and the dc generator for the digital controlled oscillator (DCO) (/C0179MCLK generator) is switched off. /C0068Low-power mode 4 (LPM4). The CPU is disabled, peripheral operation continues, ACLK signal is inactive (crystal oscillator stopped), MCLK and loop control for MCLK are inactive, and the dc generator for the DCO is switched off. The special function registers (SFR) include module-enable bits that stop or enable the operation of the specific peripheral module. All registers of the peripherals may be accessed if the operational function is stopped or enabled, however, some peripheral current-saving functions are accessed through the state of local register bits. An example is the enable/disable of the analog voltage generator in the LCD peripheral, which is turned on or off using one register bit. The most general bits that influence current consumption and support fast turnon from low power operating modes are located in the status register (SR). Four of these bits control the CPU and the system clock generator: SCG1, SCG0, OscOff, and CPUOff. Reserved For Future Enhancements 15 9 8 7 0 V SCG1 SCG0 OscOff CPUOff GIE N Z C rw-0 interrupts Software determines the activation of interrupts through the monitoring of hardware set interrupt flag status bits, the control of specific interrupt enable bits in SRs, the establishment of interrupt vectors, and the programming of interrupt handlers. The interrupt vectors and the power-up starting address are located in ROM address locations 0FFFFh through 0FFE0h. Each vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. Table 3 provides a summation of interrupt functions and addresses.
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Table 3. Interrupt Functions and Addresses
- Interrupt flags are located in the individual module registers.
- Non-maskable : neither the individual or the general interrupt enable bit will disable an interrupt event.
- (Non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot.
is provided with this arrangement.
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operation modes and interrupts (continued) interrupt flag registers 1 and 2 76 54 0 P0IFG.1 OFIFG WDTIFG 32 1 rw-0 rw-1 rw-0 Address 02h NMIIFG P0IFG.0 rw-0 rw-0 WDTIFG: Set on overflow or security key violation or Reset on VCC1 power-on or reset condition at RST /NMI-pin OFIFG: Flag set on oscillator fault P0IFG.0: Dedicated I/O P0.0 P0IFG.1: P0.1 or 8-Bit Timer/Counter, RXD NMIIFG: Signal at RST /NMI-pin 76 54 0 UTXIFG URXIFG rw 32 1 rw-1 rw-0 Address 03h BTIFG URXIFG: USART receive flag UTXIFG: USART transmit flag BTIFG: Basic Timer1 flag module enable registers 1 and 2 76 54 0 32 1Address 04h 76 54 0 UTXE URXE/USPIE 32 1 rw-0 rw-0 Address 05h Bit 0: USART mode: USART receive enable, URXE SPI mode: SPI enable, USPIE Bit 1: USART mode: USART transmit enable, UTXE SPI mode: not applicable Legend rw: rw-0: Bit can be read and written Bit can be read and written. It is reset by PUC. SFR bit not present in device
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000
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Int. Vector 24 kB ROM 1024B RAM 16b Per. 8b Per. SFR FFFFh FFE0h FFDFh A000h 05FFh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h MSP430C336 Int. Vector 32 kB ROM 1024B RAM 16b Per. 8b Per. SFR FFFFh FFE0h FFDFh 8000h 05FFh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h MSP430C337 Int. Vector 32 kB OTP or EPROM 1024B RAM 16b Per. 8b Per. SFR FFFFh FFE0h FFDFh 8000h 05FFh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h MSP430P337A PMS430E337A peripherals Peripherals that are connected to the CPU through a data, address, and controls bus can be handled easily with instructions for memory manipulation. oscillator and system clock Two clocks are used in the system: the system (master) clock (MCLK) and the auxiliary clock (ACLK). The MCLK is a multiple of the ACLK. The ACLK runs with the crystal oscillator frequency. The special design of the oscillator supports the feature of low current consumption and the use of a 32 768 Hz crystal. The crystal is connected across two terminals without any other external components required. The oscillator starts after applying VCC, due to a reset of the control bit (OscOff) in the status register (SR). It can be stopped by setting the OscOff bit to a 1. The enabled clock signals ACLK, ACLK/2, ACLK/4, or MCLK are accessible for use by external devices at output terminal XBUF. The controller system clocks have to deal with different requirements according to the application and system condition. Requirements include: /C0068High frequency in order to react quickly to system hardware requests or events /C0068Low frequency in order to minimize current consumption, EMI, etc. /C0068Stable frequency for timer applications e.g., real-time clock (RTC) /C0068Enable start-stop operation with minimum delay to operation function These requirements cannot all be met with fast frequency high-Q crystals or with RC-type low-Q oscillators. This compromise and selected for the MSP430, uses a low-crystal frequency, which is multiplied to achieve the desired nominal operating range: f (system)/C0043(N /C00411)/C0032f(crystal)
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 oscillator and system clock (continued) The crystal frequency multiplication is achieved with a frequency locked loop (FLL) technique. The factor N is set to 31 after a power-up clear condition. The FLL technique, in combination with a digital controlled oscillator (DCO), provides immediate start-up capability together with long term crystal stability. The frequency variation of the DCO with the FLL inactive is typically 330 ppm, which means that with a cycle time of 1 ms the maximum possible variation is 0.33 ns. For more precise timing, the FLL can be used, which forces longer cycle times if the previous cycle time was shorter than the selected one. This switching of cycle times makes it possible to meet the chosen system frequency over a long period of time. The start-up operation of the system clock depends on the previous machine state. During a PUC, the DCO is reset to its lowest possible frequency. The control logic starts operation immediately after recognition of PUC. multiplication The multiplication operation is supported by a dedicated peripheral module. The module performs 16x16, 16x8, 8x16, and 8x8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required. digital I/O Five eight-bit I/O ports (P0 thru P4) are implemented. Port P0 has six control registers, P1 and P2 have seven control registers, and P3 and P4 modules have four control registers to give maximum flexibility of digital input/output to the application: /C0068Individual I/O bits are independently programmable. /C0068Any combination of input, output, and interrupt conditions is possible. /C0068Interrupt processing of external events is fully implemented for all eight bits of the P0, P1, and P2 ports. /C0068Read/write access is available to all registers by all instructions. The seven registers are: /C0068Input register contains information at the pins /C0068Output register contains output information /C0068Direction register controls direction /C0068Interrupt edge select contains input signal change necessary for interrupt /C0068Interrupt flags indicates if interrupt(s) are pending /C0068Interrupt enable contains interrupt enable pins /C0068Function select determines if pin(s) used by module or port These registers contain eight bits each with the exception of the interrupt flag register and the interrupt enable register which are 6 bits each. The two least significant bit (LSBs) of the interrupt flag and enable registers are located in the special function register (SFR). Five interrupt vectors are implemented, one for Port P0.0, one for Port P0.1, one commonly used for any interrupt event on Port P0.2 to Port P0.7, one commonly used for any interrupt event on Port P1.0 to Port P1.7, and one commonly used for any interrupt event on Port P2.0 to Port P2.7.
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000
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The liquid crystal displays (LCDs) for static, 2-, 3-, and 4-MUX operation can be driven directly. The operation of the controller LCD logic is defined by software through memory-bit manipulation. The LCD memory is part of the LCD module, not part of data memory. Eight mode and control bits define the operation and current consumption of the LCD drive. The information for the individual digits can be easily obtained using table programming techniques combined with the proper addressing mode. The segment information is stored into LCD memory using instructions for memory manipulation. The drive capability is defined by the external resistor divider that supports analog levels for 2-, 3-, and 4-MUX operation. Groups of the LCD segment lines can be selected for digital output signals. The MSP430x33x configuration has four common lines, 30 segment lines, and four terminals for adjusting the analog levels. Basic Timer1 The Basic Timer1 (BT1) divides the frequency of MCLK or ACLK, as selected with the SSEL bit, to provide low-frequency control signals. This is done within the system by one central divider, the Basic Timer1, to support low current applications. The BTCTL control register contains the flags which control or select the different operational functions. When the supply voltage is applied or when a reset of the device (RST /NMI pin), a watchdog overflow, or a watchdog security key violation occurs, all bits in the register hold undefined or unchanged status. The user software usually configures the operational conditions on the BT during initialization. The Basic Timer1 has two eight bit timers which can be cascaded to a sixteen bit timer. Both timers can be read and written by software. Two bits in the SFR address range handle the system control interaction according to the function implemented in the Basic Timer1. These two bits are the Basic Timer1 interrupt flag (BTIFG) and the Basic Timer1 interrupt enable (BTIE) bit. Watchdog Timer The primary function of the Watchdog Timer (WDT) module is to perform a controlled system restart after a software upset has occurred. If the selected time interval expires, a system reset is generated. If this watchdog function is not needed in an application, the module can work as an interval timer, which generates an interrupt after the selected time interval. The Watchdog Timer counter (WDTCNT) is a 15/16-bit upcounter which is not directly accessible by software. The WDTCNT is controlled using the Watchdog Timer control register (WDTCTL), which is an 8-bit read/write register. Writing to WDTCTL, in both operating modes (watchdog or timer) is only possible by using the correct password in the high-byte. The low-byte stores data written to the WDTCTL. The high-byte password is 05Ah. If any value other than 05Ah is written to the high-byte of the WDTCTL, a system reset PUC is generated. When the password is read its value is 069h. This minimizes accidental write operations to the WDTCTL register. In addition to the Watchdog Timer control bits, there are two bits included in the WDTCTL that configure the NMI pin. USART The universal synchronous/asynchronous interface is a dedicated peripheral module which provides serial communications. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communications protocols, using double buffered transmit and receive channels. Data streams of 7 or 8 bits in length can be transferred at a rate determined by the program, or by a rate defined by an external clock. Low-power applications are optimized by UART mode options which allow for the receipt of only the first byte of a complete frame. The applications software then decides if the succeeding data is to be processed. This option reduces power consumption. Two dedicated interrupt vectors are assigned to the USART module, one for the receive and one for the transmit channel.
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Timer/Port The Timer/Port module has two 8-Bit Timer/Counters, an input that triggers one counter, and six digital outputs with 3-state capability. Both counters have an independent clock selector for selecting an external signal or one of the internal clocks (ACLK or MCLK). One of the counters has an extended control capability to halt, count continuously, or gate the counter by selecting one of two external signals. This gate signal sets the interrupt flag if an external signal is selected and the gate stops the counter. Both timers can be read to and written from by software. The two 8-Bit Timer/Counters can be cascaded to form a 16-bit counter. A common interrupt vector is implemented. The interrupt flag can be set by three events in the 8-Bit Timer/Counter mode (gate signal or overflow from the counters) or by two events in the 16-bit counter mode (gate signal or overflow from the MSB of the cascaded counter). slope A/D conversion Slope A/D conversion is accomplished with the Timer/Port module using external resistor(s) for reference (R ref), using external resistor(s) to the measured (Rmeas ), and an external capacitor. The external components are driven by software in such a way that the internal counter measures the time that is needed to charge or discharge the capacitor. The reference resistor’s (R ref) charge or discharge time is represented by Nref counts. The unknown resistors (Rmeas ) charge or discharge time is represented by Nmeas counts. The unknown resistor’s value Rmeas is the value of Rref multiplied by the relative number of counts (Nmeas /Nref). This value determines resistive sensor values that correspond to the physical data, for example temperature, when an NTC or PTC resistor is used. Timer_A The Timer_A module (see Figure1) offers one sixteen bit counter and five capture/compare registers. The timer clock source can be selected to come from an external source TACLK (SSEL=0), the ACLK (SSEL=1), or MCLK (SSEL=2 or SSEL=3). The clock source can be divided by one, two, four, or eight. The timer can be fully controlled (in word mode) since it can be halted, read, and written. It can be stopped or run continuously. It can count up or count up/down using one compare block to determine the period. The five capture/compare blocks are configured by the application software to run in either capture or compare mode. The capture mode is primarily used to measure external or internal events with any combination of positive, negative, or both edges of the clock. The clock can also be stopped in capture mode by software. One external event (CCISx=0) per capture block can be selected. If CCISx=1, the ACLK is the capture signal; and if CCISx=2 or CCISx=3, software capture is chosen. The compare mode is primarily used to generate timing for the software or application hardware or to generate pulse-width modulated output signals for various purposes like D/A conversion functions or motor control. An individual output module, which can run independently of the compare function or is triggered in several ways, is assigned to each of the five capture/compare registers. Two interrupt vectors are used by the Timer_A module. One individual vector is assigned to capture/compare block CCR0 and one common interrupt vector is assigned to the timer and the other four capture/compare blocks. The five interrupt events using the common vector are identified by an individual interrupt vector word. The interrupt vector word is used to add an offset to the program counter to continue the interrupt handler software at the correct location. This simplifies the interrupt handler and gives each interrupt event the same interrupt handler overhead of 5 cycles.
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Figure 1. Timer_A, MSP430x337 Configuration
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 8-Bit Timer/Counter The 8-bit interval timer supports three major functions for applications: /C0068Serial communication or data exchange /C0068Plus counting or plus accumulation /C0068Timer The 8-Bit Timer/Counter peripheral includes the following major blocks: an 8-bit up-counter with preload register, an 8-bit control register, an input clock selector, an edge detection (e.g. start bit detection for asynchronous protocols), and an input and output data latch, triggered by the carry-out-signal from the 8-Bit Timer/Counter. The 8-Bit Timer/Counter counts up with an input clock, which is selected by two control bits from the control register. The four possible clock sources are MCLK, ACLK, the external signal from terminal P0.1, and the signal from the logical AND of MCLK and terminal P0.1. Two counter inputs (load, enable) control the counter operation. The load input controls load operations. A write-access to the counter results in loading the content of the preload register into the counter. The software writes or reads the preload register with all instructions. The preload register acts as a buffer and can be written immediately after the load of the counter is completed. The enable input enables the count operation. When the enable signal is set to high, the counter will count-up each time a positive clock edge is applied to the clock input of the counter.
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000
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PERIPHERALS WITH BYTE ACCESS UART Transmit buffer, UTXBUF 077h Port P3 Port P3 selection, P3SEL 01Bh Receive buffer, URXBUF 076h Port P3 direction, P3DIR 01Ah Baud rate, UBR1 075h Port P3 output, P3OUT 019h Baud rate, UBR0 074h Port P3 input, P3IN 018h Modulation control, UMCTL 073h Port P0 Port P0 interrupt enable, P0IE 015h Receive control, URCTL 072h Port P0 interrupt edge select, P0IES 014h Transmit control, UTCTL 071h Port P0 interrupt flag, P0IFG 013h UART control, UCTL 070h Port P0 direction, P0DIR 012h EPROM EPROM control, EPCTL 054h Port P0 output, P0OUT 011h Crystal Buffer Crystal buffer control, CBCTL 053h Port P0 input, P0IN 010h System clock SCG frequency control, SCFQCTL 052h Special SFR interrupt flag2, IFG2 003h SCG frequency integrator, SCFI1 051h Function SFR interrupt flag1, IFG1 002h SCG frequency integrator, SCFI0 050h SFR interrupt enable2, IE2 001h Timer/Port Timer/Port enable, TPE 04Fh SFR interrupt enable1, IE1 000h Timer/Port data, TPD 04Eh PERIPHERALS WITH WORD ACCESS Timer/Port counter2, TPCNT2 04Dh Multiply Sum extend, SumExt 013Eh Timer/Port counter1, TPCNT1 04Ch Result high word, ResHi 013Ch Timer/Port control, TPCTL 04Bh Result low word, ResLo 013Ah Basic Timer1 Basic timer counter2, BTCNT2 047h Second operand, OP2 0138h Basic timer counter1, BTCNT1 046h Multiply+accumulate/operand1, MACS 0136h Basic timer control, BTCTL 040h Multiply+accumulate/operand1, MAC 0134h 8-bit T/C 8-Bit Timer/Counter data, TCDAT 044h Multiply signed/operand1, MPYS 0132h 8-Bit Timer/Counter preload, TCPLD 043h Multiply unsigned/operand1, MPY 0130h 8-Bit Timer/Counter control, TCCTL 042h Watchdog Watchdog Timer control, WDTCTL 0120h LCD LCD memory 15, LCDM15 03Fh Timer_A Timer_A interrupt vector, TAIV 012Eh : Timer_A control, TACTL 0160h LCD memory 1, LCDM1 031h Cap/Com control, CCTL0 0162h LCD control & mode, LCDCTL 030h Cap/Com control, CCTL1 0164h Port P2 Port P2 selection, P2SEL 02Eh Cap/Com control, CCTL2 0166h Port P2 interrupt enable, P2IE 02Dh Cap/Com control, CCTL3 0168h Port P2 interrupt edge select, P2IES 02Ch Cap/Com control, CCTL4 016Ah Port P2 interrupt flag, P2IFG 02Bh Reserved 016Ch Port P2 direction, P2DIR 02Ah Reserved 016Eh Port P2 output, P2OUT 029h Timer_A register, TAR 0170h Port P2 input, P2IN 028h Cap/Com register, CCR0 0172h Port P1 Port P1 selection, P1SEL 026h Cap/Com register, CCR1 0174h Port P1 interrupt enable, P1IE 025h Cap/Com register, CCR2 0176h Port P1 interrupt edge select, P1IES 024h Cap/Com register, CCR3 0178h Port P1 interrupt flag, P1IFG 023h Cap/Com register, CCR4 017Ah Port P1 direction, P1DIR 022h Reserved 017Ch Port P1 output, P1OUT 021h Reserved 017Eh Port P1 input, P1IN 020h Port P4 Port P4 selection, P4SEL 01Fh Port P4 direction, P4DIR 01Eh Port P4 output, P4OUT 01D Port P4 input, P4IN 01Ch
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS. Figure 2. Supply Voltage Interconnection
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† A serial resistor of 1 kW to the RST/NMI pin is recommended to enhance latch-up immunity.
1.1 MHz at
Figure 3. Processor Frequency vs Supply Voltage
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) supply current (into VCC ) excluding external current (f(system) = 1 MHz) (see Note 6) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT C336/7 TA= –40°C +85°C, VCC = 3 V 400 500 I(AM) Active mode C336/7 TA= –40°C +85°C, VCC = 5 V 800 900 mAI(AM) Active mode P337A TA= –40°C +85°C, VCC = 3 V 570 700 mA P337A TA= –40°C +85°C, VCC = 5 V 1170 1250 C336/7 TA= –40°C +85°C, VCC = 3 V 50 70 I(CPUOff) Low power mode (LPM0 1) C336/7 TA= –40°C +85°C, VCC = 5 V 100 130 mAI(CPUOff) Low pow er mode , (LPM0 ,1) P337A TA= –40°C +85°C, VCC = 3 V 50 70 mA P337A TA= –40°C +85°C, VCC = 5 V 100 130 I(LPM2) Low power mode (LPM2) TA= –40°C +85°C, VCC = 3 V 7 12 mAI(LPM2) Low pow er mode , (LPM2) TA= –40°C +85°C, VCC = 5 V 18 25 mA TA= –40°C 2.0 3.5 TA= 25°C VCC = 3 V 2.0 3.5 I(LPM3) Low power mode (LPM3) TA= 85°C 1.6 3.5 mAI(LPM3) Low pow er mode , (LPM3) TA= –40°C 5.2 10 mA TA= 25°C VCC = 5 V 4.2 10 TA= 85°C 4.0 10 TA= –40°C 0.1 0.8 I(LPM4) Low power mode, (LPM4) TA= 25°C VCC = 3 V/5 V 0.1 0.8 mA() TA= 85°C 0.4 1.5 NOTE 6: All inputs are tied to 0 V or VCC2. Outputs do not source or sink any current. The current consumption in LPM2 and LPM3 are measured with active Basic Timer1 module (ACLK selected), LCD Module (fLCD =1024 Hz, 4MUX) and USART module (UART, ACLK, 2400 Baud selected) Current consumption of active mode versus system frequency, IAM = IAM[1MHz] × fsystem[MHz] Current consumption of active mode versus supply voltage, IAM = IAM[3V] + 200mA/V × (VCC –3) schmitt-trigger inputs Port 0 to P4: P0.x to P4.x, Timer/Port: CIN, TP0.5 PARAMETER TEST CONDITIONS MIN NOM MAX UNIT VIT Positive going input threshold voltage VCC = 3 V 1.2 2.1 VVIT+ Positive-going input threshold voltage VCC = 5 V 2.3 3.4 V VIT Negative going input threshold voltage VCC = 3 V 0.7 1.5 VVIT– Negative-going input threshold voltage VCC = 5 V 1.4 2.3 V Vh Input hysteresis (VIT VIT ) VCC = 3 V 0.3 1 VVhys Input hysteresis (VIT+–VIT–) VCC = 5 V 0.6 1.4 V
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000
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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) outputs Port 0 to P4: P0.x to P4.x, Timer/Port: TP0.0 to TP0.5, LCD: S2/O2 to S29/O29, XBUF: XBUF, JTAG:TDO PARAMETER TEST CONDITIONS MIN NOM MAX UNIT IOH = – 1.2 mA, See Note 7 VCC =3V VCC –0.4 VCC VOH High level output voltage IOH = – 3.5 mA, See Note 8 VCC = 3 V VCC –1.0 VCC VVOH High-level output voltage IOH = – 1.5 mA, See Note 7 VCC =5V VCC –0.4 VCC V IOH = – 4.5 mA, See Note 8 VCC = 5 V VCC –1.0 VCC IOL = 1.2 mA, See Note 7 VCC =3V VSS VSS +0.4 VOL Low level output voltage IOL = 3.5 mA, See Note 8 VCC = 3 V VSS VSS +1 VVOL Low-level output voltage IOL = 1.5 mA, See Note 7 VCC =5V VSS VSS +0.4 V IOL = 4.5 mA, See Note 8 VCC = 5 V VSS VSS +1 NOTES: 7. The maximum total current for all outputs combined should not exceed ±9.6 mA to hold the maximum voltage drop specified. 8. The maximum total current for all outputs combined should not exceed ±28 mA to hold the maximum voltage drop specified. leakage current (see Note 9) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Ilkg(TP) High-impedance leakage current, Timer/PortTimer/Port:VTP0.x, VCC = 3 V/5 V, CIN = VSS , VCC , (see Note 10) ± 50 nA Ilkg(S27) High-impedance leakage current, S27 VS27 = VSS to VCC , VCC = 3 V/5 V ± 50 nA Ilkg(P0x) Leakage current, port 0 Port P0: P0.x, 0 ≤×≤ 7, (see Note 11) VCC = 3 V/5 V, ± 50 nA NOTES: 9. The leakage current is measured with VSS or VCC applied to the corresponding pins(s) – unless otherwise noted. measurement. In the leakage measurement mode, the input CIN is included. The input voltage is VSS or VCC . 11. The leakages of the digital port terminals are measured individually. The port terminal must be selected for input and there must be no optional pullup or pulldown resistor. optional resistors (see Note 12) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT R (opt1) VCC = 3 V/5 V 1.4 4.1 6.8 kW R (opt2) VCC = 3 V/5 V 2.1 6.2 11 kW R (opt3) VCC = 3 V/5 V 4.2 12 20 kW R (opt4) VCC = 3 V/5 V 6.6 19 32 kW R (opt5) Resistors, individually programmable with ROM code, all port pins,VCC = 3 V/5 V 12 37 62 kW R (opt6) values applicable for pulldown and pullup VCC = 3 V/5 V 26 75 124 kW R (opt7) VCC = 3 V/5 V 39 112 185 kW R (opt8) VCC = 3 V/5 V 65 187 309 kW R (opt9) VCC = 3 V/5 V 91 261 431 kW R (opt10) VCC = 3 V/5 V 117 337 557 kW NOTE 12: Optional resistors R(optx) for pulldown or pullup are not programmed in standard OTP/EPROM devices P/E 337.
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) inputs and outputs PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT t(int) External interrupt timing Port P0, P1 to P2: External trigger signal for the interrupt flag (see Notes 13 and 14) 3 V/5 V 1.5 cycle t(cap) Timer_A, capture timing TA0-TA4 External capture signal (see Note 15)3 V/5 V 250 ns f(IN) P0 1 CIN TP 0 5 UCLK SIMO SOMI
3 V/5 V DC f(system) MHz
t(H) or t(L) Input frequency P0.1, CIN, TP 0.5, UCLK, SIMO, SOMI, TACLK TA0 -TA4 3 V 300 f(system) ns t(H) or t(L) TACLK , TA0-TA4
5 V 300 f(system)
f(XBUF) XBUF, C L = 20 pF 3 V/5 V f(system) f(TAx) Output frequency TA0-4, CL = 20 pF 3 V/5 V DC f(system)/2 MHz f(UCLK) UCLK, C L = 20 pF 3 V/5 V DC f(system) t(Xdc) XBUF, C L = 20 pF f(MCLK)= 1.1 MHz f(XBUF) = f(ACLK) f(XBUF) = f(ACLK/n)
3 V/5 V
40% 35% 60% 65% Dt(TA) Duty cycle of output TA0..4, CL = 20 pF t(TAH)= t(TAL) 3 V/5 V 0 ±100 ns Dt(UC) UCLK, C (L) = 15pF t(UCH)= t(UCL) 3 V/5 V 0 ±100 ns t(t) USART: Deglitch time See Note16 3 V 5 V 0.6 0.3 2.6 1.4 ms NOTES: 13. The external signal sets the interrupt flag every time t(int) is met. It may be set even with trigger signals shorter than t(int). The conditions to set the flag must be met independently from this timing constraint. T(int) is defined in MCLK cycles. 14. The external interrupt signal cannot exceed the maximum input frequency (f(in)) 15. The external capture signal triggers the capture event every time t(cap) is met. It may be triggered even with capture signals shorter than t(cap). The conditions to set the flag must be met independently from this timing constraint. 16. The signal applied to the USART receive signal/terminal (URXD) should meet the timing requirements of t(t) to ensure that the URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum timing condition of t(t). The operating conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the URXD line. LCD PARAMETER TEST CONDITIONS MIN NOM MAX UNIT V(33) Voltage at R33 2.5 VCC +0.2 V(23) Analog voltage Voltage at R23 VCC = 3 V/5 V V(13) Analog voltage Voltage at R13 VCC = 3 V/5 V V V(03) Voltage at R03 V(33) – 2.5 VCC +0.2 VO(HLCD) Output 1 I(HLCD )<= 10 nA VCC = 3 V/5 V V(R33) – 0.125 VCC V VO(LLCD) Output 0 I(LLCD) <= 10 nA VCC = 3 V/5 V VSS VSS + 0.125 V I(R03) R03 = VSS No load at all td ±20 I(R13) Input leakage R13 = VCC /3 segment and common lines, ±20 nA I(R23) R23 = 2 × VCC /3 common lines, VCC = 3 V/5 V ±20 V(Sxx1) Segment line I(S )=3 mA VCC = 3 V/5 V V(13) V(13) – 0.1 V V(Sxx2) g voltage I(Sxx)= – 3 mA, VCC = 3 V/5 V V(23) V(23) – 0.1 V
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Figure 4. Power-On Reset (POR) vs Supply Voltage Figure 5. V(POR) vs Temperature
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000 23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) DCO PARAMETER TEST CONDITIONS MIN NOM MAX UNIT f(NOM) DCO N (DCO) = 1 A0h FN_4=FN_3=FN_2 = 0 VCC = 3 V/5 V 1 MHz f(DCO3) N (DCO) = 00 0110 0000 VCC = 3 V 0.15 0.6 MHz f(NOM) f(DCO3) (DCO) FN_4=FN_3=FN_2 = 0 VCC = 5 V 0.18 0.62 MH z f(NOM) f(DCO26) N (DCO) = 11 0100 0000 VCC = 3 V 1.25 4.7 MHzf(DCO26) (DCO) FN_4=FN_3=FN_2 = 0 VCC = 5 V 1.45 5.5 MH z f(DCO3) N (DCO) = 00 0110 0000 VCC = 3 V 0.36 1.05 MHz 2xf(NOM) f(DCO3) (DCO) FN_4=FN_3=0, FN_2 = 1 VCC = 5 V 0.39 1.2 MH z 2xf(NOM) f(DCO26) N (DCO) = 11 0100 0000 VCC = 3 V 2.5 8.1 MHzf(DCO26) (DCO) FN_4=FN_3=0, FN_2 = 1 VCC = 5 V 3 9.9 MH z f(DCO3) N (DCO) = 00 0110 0000 VCC = 3 V 0.5 1.5 MHz 3xf(NOM) f(DCO3) (DCO) FN_4=0, FN_3=1, FN_2=X VCC = 5 V 0.6 1.8 MH z 3xf(NOM) f(DCO26) N (DCO) = 11 0100 0000 VCC = 3 V 3.7 11 MHzf(DCO26) (DCO) FN_4=0,FN_3 =1, FN_2=X VCC = 5 V 4.5 13.8 MH z f(DCO3) N (DCO) = 00 0110 0000 VCC = 3 V 0.7 1.85 MHz 4xf(NOM) f(DCO3) (DCO) FN_4=1, FN_3 = FN_2=X VCC = 5 V 0.8 2.4 MH z 4xf(NOM) f(DCO26) N (DCO) = 11 0100 0000 VCC = 3 V 4.8 13.3 MHzf(DCO26) (DCO) FN_4=1, FN_3 = FN_2=X VCC = 5 V 6 17.7 MH z N (DCO) f(MCLK) = f(NOM) FN_4=FN_3=FN_2 = 0 VCC = 3 V/5 V A0h 1A0h 340h S f(NDCO)+1 = S x f(NDCO) VCC = 3 V/5 V 1.07 1.13 Legend Tolerance at Tap 26 DCO Frequency Adjusted by Bits 2∧9–2∧5 in SCFI1 Tolerance at Tap 3 4xfNOM 3xfNOM 2xfNOM fNOM f(DCO26) f(DCO3) f(DCO26) f(DCO3) f(DCO26) f(DCO3) f(DCO26) f(DCO3) FN_2 = 0 FN_3 = 0 FN_4 = 0 FN_2 = 1 FN_3 = 0 FN_4 = 0 FN_2 = X FN_3 = 1 FN_4 = 0 FN_2 = X FN_3 = X FN_4 = 1
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000
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electrical characteristics over recommended and operating free-air temperature range (unless otherwise noted) (continued) RAM PARAMETER TEST CONDITIONS MIN NOM MAX UNIT V(RAMh) CPU halted (see Note 17) 1.8 V NOTE 17: This parameter defines the minimum supply voltage when the data in the program memory RAM remains unchanged. No program execution should happen during this supply voltage condition. Timer/Port comparator PARAMETER TEST CONDITIONS MIN NOM MAX UNIT I() Com parator (Timer/Port) CPON = 1 VCC = 3 V 175 350 mAI(com) Comparator (Timer/Port) CPON = 1 VCC = 5 V 600 mA Vref(COM) Internal reference voltage at (–) terminal CPON = 1 VCC = 3 V/5 V 0.230 × VCC1 0.260 × VCC1 V Vh( C O M )Input hysteresis (comparator) CPON = 1 VCC = 3 V 5 37 mV Vhys(COM) Input hysteresis (comparator) CPON = 1 VCC = 5 V 10 42 mV JTAG, program memory PARAMETER TEST CONDITIONS MIN NOM MAX UNIT f(TCK) JTAG/test TCK frequency VCC = 3 V DC 5 MHzf(TCK) JTAG/test TCK frequency VCC = 5 V DC 10 MH z R (test) Pullup resistors on TMS, TCK, TDI (see Note 18) VCC = 3 V/5 V 25 60 90 kW V(FB) Fuse blow voltage, C versions (see Note 20)VCC = 3 V/5 V 5.5 6 V(FB) JTAG/fuse Fuse blow voltage, E/P versions (see Note 20)VCC = 3 V/5 V 11 12 I(FB) (see Note 19) Supply current on TDI/VPP to blow fuse 100 mA t(FB) Time to blow the fuse 1 ms V(PP) Programming voltage, applied to TDI/VPP 12.0 12.5 13.0 V I(PP) Current from programming voltage source 70 mA t(pps) EPROM(E) and Programming time, single pulse 5 ms t(ppf) OTP(P) versions only Programming time, fast algorithm 100 ms Pn Number of pulses for successful programming 4 100 Pulse Data retention TJ <55°C 10 Year t(erase) EPROM(E) version only Erase time wave length 2537 Å at
15 Ws/cm2 (UV lamp of 12 mW/ cm2) 30 min
(erase) () y Write/erase cycles 1000 NOTES: 18. The TMS and TCK pullup resistors are implemented in all ROM(C), OTP(P) and EPROM(E) versions. The pullup resistor on TDI is implemented in C versions only. 19. Once the fuse is blown no further access to the MSP430 JTAG/test feature is possible. 20. The voltage supply to blow the fuse is applied to TDI/VPP pin during the fuse blowing procedure.
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 typical input/output schematics CMOS INPUT CMOS 3-STATE OUTPUT VCC (see Note A) (see Note A) GND VCC (see Note A) (see Note A) GND VCC 60 k TYP MSP430C336/337: TMS, TCK, TDI MSP430P/E337A: TMS, TCK NOTES: A. Optional selection of pullup or pulldown resistors available on ROM (masked) versions. B. Fuses for the optional pullup and pulldown resistors can only be programmed at the factory. CMOS SCHMITT-TRIGGER INPUT (see Note B) (see Note B) (see Note B) (see Note B)
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000
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typical input/output schematics (continued) Noninverting COM 0–3 VC VD Control COM0–3 VA VB Segment control VA VB Segment control LCDCTL (LCDM5,6,7) Data (LCD RAM bits 0–3 or bits 4–7) S0, S1 S2/O2–Sn/On LCD OUTPUT (COM0–4, Sn, Sn/On) NOTE A: The signals VA, VB, VC, and VD come from the LCD module analog voltage generator.
source. The TDO/TDI terminal is used to apply the test input data for JTAG circuitry. resistors when switching from P/E337A to C337 devices. Otherwise system power consumption will increase. avoid floating a node, which could increase the current consumption of the device. Figure 6. MSP430P/E337A: TDI/VPP, TDO/TDI
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NOTES: A. Optional selection of pullup or pulldown resistors available on ROM (masked) versions. B. Fuses for the optional pullup and pulldown resistors can only be programmed at the factory. Figure 7. Port P0, P0.0, Input/Output With Schmitt-Trigger NOTES: A. Optional selection of pullup or pulldown resistors available on ROM (masked) versions. B. Fuses for the optional pullup and pulldown resistors can only be programmed at the factory. Figure 8. Port P0, P0.1, Input/Output With Schmitt-Trigger
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NOTES: A. Optional selection of pullup or pulldown resistors available on ROM (masked) versions. B. Fuses for the optional pullup and pulldown resistors can only be programmed at the factory. Figure 11. Port P1, P1.0 to P1.7, Input/Output With Schmitt-Trigger
NOTES: A. Optional selection of pullup or pulldown resistors available on ROM (masked) versions. B. Fuses for the optional pullup and pulldown resistors can only be programmed at the factory. Figure 12. Port P2, P2.0 to P2.7, Input/Output With Schmitt-Trigger
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NOTES: A. Optional selection of pullup or pulldown resistors available on ROM (masked) versions. B. Fuses for the optional pullup and pulldown resistors can only be programmed at the factory. Figure 13. Port P3, P3.0 to P3.7, Input/Output With Schmitt-Trigger
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A. Optional selection of pullup or pulldown resistors available on ROM (masked) versions. B. Fuses for the optional pullup and pulldown resistors can only be programmed at the factory. Figure 16. Port P4, P4.4, Input/Output With Schmitt-Trigger Figure 17. Port P4, P4.5, Input/Output With Schmitt-Trigger NOTES: A. UART mode: The clock can only be input if UART mode and UART function is selected, the direction of P4.5/UCLK is always input. B. SPI, slave mode: The clock to UCLK is used to shift data in and out. D. Optional selection of pullup or pulldown resistors available on ROM (masked) versions. E. Fuses for the optional pullup and pulldown resistors can only be programmed at the factory.
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TF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/VPP pin to ground if the fuse is not burned. fuse check mode has the potential to be activated. type of device is in use and the state of the TMS pin. the TMS pin high (default condition). Figure 20. Fuse Check Mode Current, MSP430C33x at the TMS pin (see Figure 21). Figure 21. Fuse Check Mode Current, MSP430P337A spikes that could cause signal edges on the TMS pin. Configuration of TMS, TCK, TDI/VPP and TDO/TDI pins in applications.
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000 37POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA PJM (R-PQFP-G100) PLASTIC QUAD FLATPACK 4040022/B 03/95 0,16 NOM 14,20 17,45 13,80 16,95 12,35 TYP 1,03 0,73 0,25 Seating Plane 0,25 MIN Gage Plane 0,38 0,22 100 22,95 23,45 20,20 19,80 2,50 2,90 3,40 MAX 18,85 TYP 0°–7° M0,130,65 0,10 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-022
MSP430C33x, MSP430P337A MIXED SIGNAL MICROCONTROLLERS SLAS227A – OCTOBER 1999 – REVISED JUNE 2000
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HFD (S-GQFP-G100) CERAMIC QUAD FLATPACK 0,15 TYP 14,20 17,45 13,80 16,9512,35 TYP 0,60 1,00 Seating Plane 0,10 MIN 3,70 TYP 4081530/A 09/95 18,85 TYP 100 19,20 22,95 23,45 4,25 MAX 20,20 0,30 TYP 0,10 0,65 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.
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