PMS430E112

MSP430X11X_16 TI1 | Alldatasheet

Document overview

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Technical content

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Low Supply Voltage Range 2.5 V to 5.5 V /C0068Ultralow-Power Consumption: − Active Mode: 330 µA at 1 MHz, 3 V − Standby Mode: 1.5 µA − Off Mode (RAM Retention): 0.1 µA /C0068Wake-up From Standby Mode in less than 6 µs /C006816-Bit RISC Architecture, 200 ns Instruction Cycle Time /C0068Basic Clock Module Configurations: − Various Internal Resistors − Single External Resistor − 32 kHz Crystal − High Frequency Crystal − Resonator − External Clock Source /C006816-Bit Timer_A With Three Capture/Compare Registers /C0068Serial Onboard Programming /C0068Program Code Protection by Security Fuse /C0068Family Members Include: MSP430C111: 2k Byte ROM,128 Byte RAM MSP430C112: 4k Byte ROM, 256 Byte RAM MSP430P112: 4k Byte OTP, 256 Byte RAM /C0068EPROM Version Available for Prototyping: − PMS430E112: 4k Byte EPROM, 256 Byte RAM /C0068Available in a 20-Pin Plastic Small-Outline Wide Body (SOWB) Package, 20-Pin Ceramic Dual-In-Line (CDIP) Package (EPROM Only) /C0068For Complete Module Descriptions, Refer to the MSP430x1xx Family User’s Guide, Literature Number SLAU049

description

The T exas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs. The MSP430x11x series is an ultra low-power mixed signal microcontroller with a built in 16-bit timer and fourteen I/O pins. Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data and display them or transmit them to a host system. Stand alone RF sensor front-end is another area of application. TEST/VPP VCC P2.5/ROSC VSS XOUT/TCLK XIN RST /NMI P2.0/ACLK P2.1/INCLK P2.2/TA0 P1.7/TA2/TDO/TDI P1.6/TA1/TDI P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK P2.4/TA2 P2.3/TA1 DW PACKAGE (TOP VIEW) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1998 − 2004, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004

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(DW) CDIP 20-Pin (JL) −40°C to 85°C MSP430C111IDW MSP430C112IDW−40°C to 85°C MSP430C112IDW MSP430P112IDW 25°C — PMS430E112JL25°C — PMS430E112JL functional block diagram Oscillator ACLK SMCLK CPU Incl. 16 Reg. Bus Conv MCB XIN XOUT/TCLK P2 MDB, 16 Bit MAB, 16 Bit MCLK MAB,

4 Bit

Timer_A3

3 CC Reg

8 I/Os, with

6 I/Os, with

MDB, 16-Bit MAB, 16-Bit JTAG TEST/VPP Test JTAG Emulation Module 8 6 MDB, 8 Bit

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINALTERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION P1.0/TACLK 13 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input P1.1/TA0 14 I/O General-purpose digital I/O pin/Timer_A, Capture: CCI0A input, Compare: Out0 output P1.2/TA1 15 I/O General-purpose digital I/O pin/Timer_A, Capture: CCI1A input, Compare: Out1 output P1.3/TA2 16 I/O General-purpose digital I/O pin/Timer_A, Capture: CCI2A input, Compare: Out2 output P1.4/SMCLK/TCK 17 I/O General-purpose digital I/O pin/SMCLK signal output/Test clock, input terminal for device programming and test P1.5/TA0/TMS 18 I/O General-purpose digital I/O pin/Timer_A, Compare: Out0 output/test mode select, input terminal for device programming and test. P1.6/TA1/TDI 19 I/O General-purpose digital I/O pin/Timer_A, Compare: Out1 output/test data input terminal. P1.7/TA2/TDO/TDI 20 I/O General-purpose digital I/O pin/Timer_A, Compare: Out2 output/test data output terminal or data input during programming. P2.0/ACLK 8 I/O General-purpose digital I/O pin/ACLK output P2.1/INCLK 9 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK P2.2/TA0 10 I/O General-purpose digital I/O pin/Timer_A, Capture: CCI0B input, Compare: Out0 output P2.3/TA1 11 I/O General-purpose digital I/O pin/Timer_A, Capture: CCI1B input, Compare: Out1 output P2.4/TA2 12 I/O General-purpose digital I/O pin/Timer_A, Compare: Out2 output P2.5/ROSC 3 I/O General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency RST /NMI 7 I Reset or nonmaskable interrupt input TEST/VPP 1 I Selects test mode for JTAG pins on Port1/programming voltage input during EPROM programming VCC 2 Supply voltage VSS 4 Ground reference XIN 6 I Input terminal of crystal oscillator XOUT/TCLK 5 I/O Output terminal of crystal oscillator or test clock input

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instruction can operate on word and byte data. Table 1. Instruction Word Formats Table 2. Address Mode Descriptions

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: /C0068Active mode AM; − All clocks are active /C0068Low-power mode 0 (LPM0); − CPU is disabled ACLK and SMCLK remain active. MCLK is disabled /C0068Low-power mode 1 (LPM1); − CPU is disabled ACLK and SMCLK remain active. MCLK is disabled DCO’s dc-generator is disabled if DCO not used in active mode /C0068Low-power mode 2 (LPM2); − CPU is disabled MCLK and SMCLK are disabled DCO’s dc-generator remains enabled ACLK remains active /C0068Low-power mode 3 (LPM3); − CPU is disabled MCLK and SMCLK are disabled DCO’s dc-generator is disabled ACLK remains active /C0068Low-power mode 4 (LPM4); − CPU is disabled ACLK is disabled MCLK and SMCLK are disabled DCO’s dc-generator is disabled Crystal oscillator is stopped

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004

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interrupt vector addresses The interrupt vectors and the power-up starting address are located in the ROM with an address range of 0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up, external reset, watchdog WDTIFG (see Note1) Reset 0FFFEh 15, highest NMI, oscillator fault NMIIFG, OFIFG (see Note 1) (non)-maskable, (non)-maskable 0FFFCh 14 0FFFAh 13 0FFF8h 12 0FFF6h 11 Watchdog Timer WDTIFG maskable 0FFF4h 10 Timer_A3 TACCR0 CCIFG (see Note 2) maskable 0FFF2h 9 Timer_A3 TACCR1 and TACCR2 CCIFGs, TAIFG (see Notes 1 and 2) maskable 0FFF0h 8 0FFEEh 7 0FFECh 6 0FFEAh 5 0FFE8h 4 I/O Port P2 (eight flags − see Note 3)P2IFG.0 to P2IFG.7 (see Notes 1 and 2) maskable 0FFE6h 3 I/O Port P1 (eight flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) maskable 0FFE4h 2 0FFE2h 1 0FFE0h 0, lowest NOTES: 1. Multiple source flags 2. Interrupt flags are located in the module 3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0−5) are implemented on the ’11x devices.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable 1 76 54 0 OFIE WDTIE 32 1 rw-0 rw-0 rw-0 Address 0h NMIIE WDTIE: Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode. OFIE: Oscillator fault enable NMIIE: (Non)maskable interrupt enable interrupt flag register 1 76 54 0 OFIFG WDTIFG 32 1 rw-0 rw-1 rw-(0) Address 02h NMIIFG WDTIFG: Set on Watchdog Timer overflow (in watchdog mode) or security key violation. Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode. OFIFG: Flag set on oscillator fault NMIIFG: Set via RST /NMI-pin Legend rw: rw-0,1: Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC SFR bit is not present in device. rw-(0,1): Bit can be read and written. It is Reset or Set by POR

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004

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Int. Vector

2 KB ROM

16b Per. 8b Per. SFR FFFFh FFE0h FFDFh F800h 027Fh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h MSP430C111 Int. Vector 4 KB EPROM 256B RAM 16b Per. 8b Per. SFR FFFFh FFE0h FFDFh 02FFh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h MSP430P112 PMS430E112 Int. Vector

4 KB ROM

16b Per. 8b Per. SFR FFFFh FFE0h FFDFh F000h 02FFh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h MSP430C112 F000h peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to the MSP430x1xx Family User’s Guide, literature number SLAU049. oscillator and system clock The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The basic clock module provides the following clock signals: /C0068Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal. /C0068Main clock (MCLK), the system clock used by the CPU. /C0068Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. digital I/O There are two 8-bit I/O ports implemented—ports P1 and P2 (only six P2 I/O signals are available on external pins): /C0068All individual I/O bits are independently programmable. /C0068Any combination of input, output, and interrupt conditions is possible. /C0068Edge-selectable interrupt input capability for all the eight bits of port P1 and six bits of port P2. /C0068Read/write access to port-control registers is supported by all instructions. NOTE: Six bits of Port P2, P2.0 to P2.5, are available on external pins − but all control and data bits for Port P2 are implemented.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 watchdog timer The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_A3 Signal Connections Input Pin Number Device Input SignalModule Input Name Module Block Module Output Signal Output Pin Number 13 - P1.0 TACLK TACLK ACLK ACLK Timer NASMCLK SMCLK Timer NA 9 - P2.1 INCLK INCLK 14 - P1.1 TA0 CCI0A 14 - P1.1 10 - P2.2 TA0 CCI0B CCR0 TA0 18 - P1.5 DV SS GND CCR0 TA0 10 - P2.2 DV CC VCC 15 - P1.2 TA1 CCI1A 15 - P1.2 11 - P2.3 TA1 CCI1B CCR1 TA1 19 - P1.6 DV SS GND CCR1 TA1 11 - P2.3 DV CC VCC 16 - P1.3 TA2 CCI2A 16 - P1.3 ACLK (internal) CCI2B CCR2 TA2 20 - P1.7 DV SS GND CCR2 TA2 12 - P2.4 DV CC VCC

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004

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PERIPHERALS WITH WORD ACCESS Watchdog Watchdog/Timer Control WDTCTL 0120h Timer_A Timer_A Interrupt Vector Timer_A Control Cap/Com Control Cap/Com Control Cap/Com Control Reserved Reserved Reserved Reserved Timer_A Register Cap/Com Register Cap/Com Register Cap/Com Register Reserved Reserved Reserved Reserved TAIV TACTL TACCTL0 TACCTL1 TACCTL2 TAR TACCR0 TACCR1 TACCR2 012Eh 0160h 0162h 0164h 0166h 0168h 016Ah 016Ch 016Eh 0170h 0172h 0174h 0176h 0178h 017Ah 017Ch 017Eh PERIPHERALS WITH BYTE ACCESS Basic Clock Basic Clock Sys. Control2 Basic Clock Sys. Control1 DCO Clock Freq. Control BCSCTL2 BCSCTL1 DCOCTL 058h 057h 056h EPROM EPROM Control EPCTL 054h Port P2 Port P2 Selection Port P2 Interrupt Enable Port P2 Interrupt Edge Select Port P2 Interrupt Flag Port P2 Direction Port P2 Output Port P2 Input P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h Port P1 Port P1 Selection Port P1 Interrupt Enable Port P1 Interrupt Edge Select Port P1 Interrupt Flag Port P1 Direction Port P1 Output Port P1 Input P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN 026h 025h 024h 023h 022h 021h 020h Special Function SFR Interrupt Flag1 SFR Interrupt Enable1 IFG1 IE1 002h 000h

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. to the TEST pin when blowing the JTAG fuse.

2.2 MHz

5.35 MHz

Figure 1. C Version Frequency vs Supply Voltage NOTE: Minimum processor frequency is defined by system clock.

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1.1 MHz

Figure 2. P/E Version Frequency vs Supply Voltage NOTE: Minimum processor frequency is defined by system clock.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) supply current (into VCC ) excluding external current PARAMETER TEST CONDITIONS MIN NOM MAX UNIT TA = −40°C +85°C, f(MCLK) = f(SMCLK) = 1 MHz,VCC = 3 V 330 400 µA C11x TA = −40C +85 C, f(MCLK) = f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz VCC = 5 V 630 700 µA C11x TA = −40°C +85°C, VCC = 3 V 3.4 4 µA I Active mode TA = −40C +85 C, f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz VCC = 5 V 7.8 10 µA I(AM) Active mode TA = −40°C +85°C, fMCLK = f(SMCLK) = 1 MHz, VCC = 3 V 400 500 µA P112 A fMCLK = f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz VCC = 5 V 730 900 µA P112 TA = −40°C +85°C, VCC = 3 V 3.4 4 µATA = −40C +85 C, f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz VCC = 5 V 7.8 10 µA C11x TA = −40°C +85°C, fMCLK = 0 MHz, VCC = 3 V 51 60 I(CPUOff) Low power mode, C11x TA = −40C +85 C, fMCLK = 0 MHz, f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz VCC = 5 V 120 150 µAI(CPUOff) Low power mode, (LPM0) P112 TA = −40°C +85°C, f(MCLK) = 0 MHz, VCC = 3 V 70 85 µA(LPM0) P112 TA = −40C +85 C, f(MCLK) = 0 MHz, f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz VCC = 5 V 125 170 I(LPM2) Low power mode, (LPM2) TA = −40°C +85°C, f(MCLK) = f(SMCLK) = 0 MHz, VCC = 3 V 8 22 µAI(LPM2) Low power mode, (LPM2) A f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 = 0, Rsel = 3VCC = 5 V 16 35 µA TA = −40°C f(MCLK) = f(SMCLK) = 0 MHz, 2 2.6 TA = 25°C f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 = 1 VCC = 3 V 1.5 2.2 I(LPM3) Low power mode, (LPM3) TA = 85°C f(ACLK) = 32,768 Hz, SCG0 = 1 VCC = 3 V 1.85 2.2 µAI(LPM3) Low power mode, (LPM3) TA = −40°C f(MCLK) = f(SMCLK) = 0 MHz, 6.3 8 µA TA = 25°C f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 = 1VCC = 5 V 5.1 7 TA = 85°C f(ACLK) = 32,768 Hz, SCG0 = 1VCC = 5 V 5.1 7 TA = −40°C f(MCLK) = f(SMCLK) = 0 MHz, VCC = 3 V/ 0.1 0.8 I(LPM4) Low power mode, (LPM4) TA = 25°C f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 0 Hz, SCG0 = 1 VCC = 3 V/ 5 V 0.1 0.8 µAI(LPM4) Low power mode, (LPM4) TA = 85°C f(ACLK) = 0 Hz, SCG0 = 1 5 V 0.4 1 µA NOTE: All inputs are tied to VSS or VCC . Outputs do not source or sink any current. current consumption of active mode versus system frequency IAM = IAM[1 MHz] × fsystem [MHz] current consumption of active mode versus supply voltage IAM = IAM[3 V] + 175 µA/V × (VCC −3 V)

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) Schmitt-trigger inputs Port 1 to Port P2; P1.0 to P1.7, P2.0 to P2.5 PARAMETER TEST CONDITIONS MIN NOM MAX UNIT VIT+ Positive-going input threshold voltage VCC = 3 V 1.2 2.1 VVIT+ Positive-going input threshold voltage VCC = 5 V 2.3 3.4 V VIT− Negative-going input threshold voltage VCC = 3 V 0.7 1.5 VVIT− Negative-going input threshold voltage VCC = 5 V 1.4 2.3 V Vhys Input voltage hysteresis, (VIT+ − VIT−) VCC = 3 V 0.3 1 VVhys Input voltage hysteresis, (VIT+ − VIT−) VCC = 5 V 0.6 1.4 V standard inputs RST/NMI, TCK, TMS, TDI PARAMETER TEST CONDITIONS MIN NOM MAX UNIT VIL Low-level input voltage VCC = 3 V/5 V VSS VSS +0.8 V VIH High-level input voltage VCC = 3 V/5 V 0.7xVCC VCC V inputs Px.x, TAx PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT Port P1, P2: P1.x to P2.x, 3 V/ 5 V 1.5 cycle t(int) External Interrupt timingPort P1, P2: P1.x to P2.x, External trigger signal for the interrupt flag, (see Note 1)3 V 540 ns t(int) External Interrupt timingExternal trigger signal for the interrupt flag, (see Note 1)

5 V 270 ns

3 V/ 5 V 1.5 cycle t(cap) Timer_A, capture timing TA0, TA1, TA2. (see Note 2) 3 V 540 ns t(cap) Timer_A, capture timingTA0, TA1, TA2. (see Note 2) NOTES: 1. The external signal sets the interrupt flag every time the minimum tint cycle and time parameters are met. It may be set even with trigger signals shorter than tint. Both the cycle and timing specifications must be met to ensure the flag is set. 2. The external capture signal triggers the capture event every time when the minimum tcap cycles and time parameters are met. A capture may be triggered with capture signals even shorter than tcap. Both the cycle and timing specifications must be met to ensure a correct capture of the 16-bit timer value and to ensure the flag is set. internal signals TAx, SMCLK at Timer_A PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT f(IN) Input frequency Internal TA0, TA1, TA2, tH = tL

3 V dc 10

MHzf(IN) Input frequency Internal TA0, TA1, TA2, t H = tL 5 V dc 15 MHz f(TAint) Timer_A clock frequency Internally, SMCLK signal applied 3 V/5 V dc fSystem leakage current (see Note 1) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Ilkg(Px.x) High-impendance leakage current Port P1: P1.x, 0 ≤ ×≤ 7 (see Note 2) VCC = 3 V/5 V, ±50 nAIlkg(Px.x) High-impendance leakage current Port P2: P2.x, 0 ≤ ×≤ 5 (see Note 2) VCC = 3 V/5 V, ±50 nA NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional pullup or pulldown resistor.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) outputs P2x, TAx PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT f(P20) Output frequency P2.0/ACLK, C L = 20 pF 3 V/5 V 1.1 MHzf(TAx) Output frequency TA0, TA1, TA2, C L = 20 pF 3 V/5 V dc fSystem MHz fP20 = 1.1 MHz 40% 60% t(Xdc) P2.0/ACLK, CL = 20 pF fP20 = fXTCLK 3 V/ 5 V 35% 65%t(Xdc) Duty cycle of O/P frequency P2.0/ACLK, CL = 20 pF fP20 = fXTCLK/n

3 V/ 5 V

50% t(TAdc) Duty cycle of O/P frequency TA0, TA1, TA2, C L = 20 pF, Duty cycle = 50% 3 V/ 5 V 0 ±50 ns outputs Port 1 to P2; P1.0 to P1.7, P2.0 to P2.5 PARAMETER TEST CONDITIONS MIN NOM MAX UNIT VOH High-level output voltage I(OH) = − 1.5 mA, VCC = 3 V/5 V,See Note 1 VCC −0.4 VCC VVOH High-level output voltage I(OH) = − 4.5 mA, VCC = 3 V/5 V,See Note 2 VCC -0.6 VCC V VOL Low-level output voltage I(OL) = 1.5 mA, VCC = 3 V/5 V,See Note 1 VSS VSS +0.4 VVOL Low-level output voltage I(OL) = 4.5 mA, VCC = 3 V/5 V,See Note 2 VSS VSS +0.6 V NOTES: 1. The maximum total current, IOH and IOL , or all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop specified. 2. The maximum total current, IOH and IOL , or all outputs combined, should not exceed ±36 mA to hold the maximum voltage drop specified. optional resistors, individually programmable with ROM code (see Note 1) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT R (opt1) VCC = 3 V/5 V 2.1 4.1 6.2 kΩ R (opt2) VCC = 3 V/5 V 3.1 6.2 9.3 kΩ R (opt3) VCC = 3 V/5 V 6 12 18 kΩ R (opt4) VCC = 3 V/5 V 10 19 29 kΩ R (opt5) Resistors, individually programmable with ROM code, all port pins,VCC = 3 V/5 V 19 37 56 kΩ R (opt6) Resistors, individually programmable with ROM code, all port pins, values applicable for pulldown and pullup VCC = 3 V/5 V 38 75 113 kΩ R (opt7) values applicable for pulldown and pullup VCC = 3 V/5 V 56 112 168 kΩ R (opt8) VCC = 3 V/5 V 94 187 281 kΩ R (opt9) VCC = 3 V/5 V 131 261 392 kΩ R (opt10) VCC = 3 V/5 V 167 337 506 kΩ NOTE 1: Optional resistors Roptx for pulldown or pullup are not programmed in standard OTP or EPROM devices MSP430P112 or PMS430E112.

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 3. Power-On Reset (POR) vs Supply Voltage Figure 4. VPOR vs Temperature

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) wake-up from lower power modes (LPMx) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT t(LPM0)/ t(LPM2) Delay time VCC = 3 V/5 V 100 ns t(LPM3) Delay time R Sel = 4, DCO = 3, MOD = 0 VCC = 3 V/5 V 2.6 6 µs t(LPM4) R Sel = 4, DCO = 3, MOD = 0 VCC = 3 V/5 V 2.8 6 µs RAM PARAMETER MIN NOM MAX UNIT V(RAMh) CPU halted (see Note 1) 1.8 V NOTE 1: This parameter defines the minimum supply voltage VCC when the data in the program memory RAM remains unchanged. No program execution should happen during this supply voltage condition. DCO (MSP430P112) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT f(DCO03) R sel = 0, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 3 V 0.12 MHzf(DCO03) R sel = 0, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 5 V 0.13 MHz f(DCO13) R sel = 1, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 3 V 0.19 MHzf(DCO13) R sel = 1, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 5 V 0.21 MHz f(DCO23) R sel = 2, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 3 V 0.31 MHzf(DCO23) R sel = 2, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 5 V 0.34 MHz f(DCO33) R sel = 3, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 3 V 0.5 MHzf(DCO33) R sel = 3, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 5 V 0.55 MHz f(DCO43) R sel = 4, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 3 V 0.5 0.8 1.1 MHzf(DCO43) R sel = 4, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 5 V 0.6 0.9 1.2 MHz f(DCO53) R sel = 5, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 3 V 0.9 1.2 1.55 MHzf(DCO53) R sel = 5, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 5 V 1.1 1.4 1.7 MHz f(DCO63) R sel = 6, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 3 V 1.7 2 2.3 MHzf(DCO63) R sel = 6, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 5 V 2.1 2.4 2.7 MHz f(DCO73) R sel = 7, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 3 V 2.8 3.1 3.5 MHzf(DCO73) R sel = 7, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C VCC = 5 V 3.8 4.2 4.5 MHz f(DCO47) R sel = 4, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C VCC = 3 V/5 V FDCO40 FDCO40 FDCO40 MHzf(DCO47) R sel = 4, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C VCC = 3 V/5 V FDCO40 x1.8 FDCO40 x2.2 FDCO40 x2.6 MHz S(Rsel) SR = fRsel+1/fRsel VCC = 3 V/5 V 1.4 1.65 1.9 ratio S(DCO) SDCO = fDCO+1 /fDCO VCC = 3 V/5 V 1.07 1.12 1.16 ratio D t Temperature drift, Rsel = 4, DCO = 3, VCC = 3 V −0.31 −0.36 −0.40 %/°CD t Temperature drift, Rsel = 4, DCO = 3, MOD = 0 (see Note 1) VCC = 5 V −0.33 −0.38 −0.43 %/°C D V Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0 (see Note 1) VCC = 3 V to 5 V 0 5 10 %/V NOTE 1: These parameters are not production tested.

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NOTE 1: These parameters are not production tested. Figure 5. DCO Characteristics

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) main DCO characteristics /C0068Individual devices have a minimum and maximum operation frequency. The specified parameters for f(DCOx0) to f(DCOx7) are valid for all devices. /C0068All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7. /C0068DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter SDCO . /C0068Modulation control bits MOD0 to MOD4 select how often f(DCO+1) is used within the period of 32 DCOCLK cycles. The frequency f(DCO) is used for the remaining cycles. The frequency is an average equal to: /C0102/C0097/C0118/C0101/C0114/C0097/C0103/C0101/C0043 /C0051/C0050/C0032/C0102/C0040/C0068/C0067/C0079/C0041/C0032/C0102/C0040/C0068/C0067/C0079/C0041/C0049/C0041 /C0077/C0079/C0068/C0032/C0102/C0040/C0068/C0067/C0079/C0041/C0041/C0040/C0051/C0050/C0042/C0077/C0079/C0068/C0041/C0032/C0102/C0040/C0068/C0067/C0079/C0041/C0049/C0041 crystal oscillator, XIN, XOUT PARAMETER TEST CONDITIONS MIN NOM MAX UNIT C XIN Capacitance at input VCC = 3 V/5 V 12 pF C XOUT Capacitance at output VCC = 3 V/5 V 12 pF VIL Input levels at XIN VCC = 3 V/5 V (see Note 2) VSS 0.2×VCC V VIH Input levels at XIN VCC = 3 V/5 V (see Note 2) 0.8×VCC VCC V NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer. 2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) EPROM Memory, P- and E- versions only (see Note 1) PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT V(PP) Programming voltage, applied to TEST/VPP 12 12.5 13 V I(PP) Current from programming voltage source 70 mA t(pps) Programming time, single pulse 5 ms t(ppf) Programming time, fast algorithm 100 µs P(n) Number of pulses for successful programming 4 100 Pulse t(erase) Erase time: Wave length 2537 Å at 15 Ws/cm2 (UV lamp of 12 mW/ cm2) 30 min t(erase) Write/erase cycles 1000 cycles Data retention Tj < 55°C 10 Year NOTES: 1. Refer to the Recommended Operating Conditions for the correct VCC during programming. JTAG Interface PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT fTCK TCK input frequency see Note 1

3 V DC 5

MHzfTCK TCK input frequency see Note 1 5 V DC 10 MHz NOTES: 1. f TCK may be restricted to meet the timing requirements of the module selected. JTAG Fuse (see Note 1) PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT VFB Fuse blow voltage, C versions (see Note 2) 3 V/ 5 V 5.5 6 VVFB Fuse blow voltage, E/P versions (see Note 2) 3 V/ 5 V 11 13 V IFB Supply current into TEST/VPP during fuse blow 100 mA tFB Time to blow fuse 1 ms NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to bypass mode. 2. The fuse blow voltage is applied to the TEST/VPP pin.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

Port P1, P1.0 to P1.3, input/output with Schmitt-trigger EN D (See Note 1) (See Note 2) (See Note 2) (See Note 1) GND VCC P1.0 − P1.3 Interrupt Edge Select EN Set Q P1IE.x P1IFG.x P1IRQ.x Interrupt Flag P1IES.x P1SEL.x Module X IN P1IN.x P1OUT.x Module X OUT Direction Control From Module P1DIR.x P1SEL.x Pad Logic NOTE: x = Bit Identifier, 0 to 3 For Port P1 PnSel.x PnDIR.x Dir. Control from module PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x † Signal from or to Timer_A NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions. 2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory. CMOS INPUT (RST /NMI) VCC (see Note 1) (see Note 1) GND (see Note 2) (see Note 2)

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

input/output schematic (continued) Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features EN D See Note 1 See Note 2 See Note 2 See Note 1 GND VCC P1.4−P1.7 Interrupt Edge Select EN Set Q P1IE.x P1IFG.x P1IRQ.x Interrupt Flag P1IES.x P1SEL.x Module X IN P1IN.x P1OUT.x Module X OUT Direction Control From Module P1DIR.x P1SEL.x Pad Logic Bus Keeper TST Fuse 60 kΩ Fuse Blow Control VPP_Internal Control By JTAG TDO Controlled By JTAG P1.x TDI P1.x TST TST TMS TST TCK TST Controlled by JTAG TS T P1.x P1.x P1.7/TDI/TDO P1.6/TDI P1.5/TMS P1.4/TCK Typical TEST/VPP GND N OTES:The test pin should be protected from potential EMI and ESD voltage spikes. This may require a smaller external pulldown resistor in some applications. x = Bit identifier, 4 to 7 for port P1 During programming activity and during blowing the fuse, the pin TDO/TDI is used to apply the test input for JTAG circuitry. PnSel.x PnDIR.x Dir. Control from module PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x † Signal from or to Timer_A NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions. 2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004 23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 input/output schematic (continued) Port P2, P2.0 to P2.4, input/output with Schmitt-trigger EN D See Note 1 See Note 2 See Note 2 See Note 1 GND VCC P2.0 − P2.4 Interrupt Edge Select EN Set Q P2IE.x P2IFG.x P2IRQ.x Interrupt Flag P2IES.x P2SEL.x Module X IN P2IN.x P2OUT.x Module X OUT Direction Control From Module P2DIR.x P2SEL.x Pad Logic NOTE: x = Bit Identifier, 0 to 4 For Port P2 0: Input 1: Output PnSel.x PnDIR.x Dir. Control from module PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x † Signal from or to Timer_A NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions. 2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

input/output schematic (continued) Port P2, P2.5, input/output with Schmitt-trigger and ROSC function for the Basic Clock module EN D See Note 1 See Note 2 See Note 2 See Note 1 GND VCC P2.5 Interrupt Edge Select EN Set Q P2IE.5 P2IFG.5 P2IRQ.5 Interrupt Flag P2IES.5 P2SEL.5 Module X IN P2IN.5 P2OUT.5 Module X OUT Direction Control From Module P2DIR.5 P2SEL.5 Pad Logic NOTE: DCOR: Control bit from basic clock module if it is set, P2.5 is disconnected from P2.5 pad Bus Keeper 0 1 VCC Internal to Basic Clock Module DCOR DC Generator 0: Input 1: Output PnSel.x PnDIR.x Director Control from module PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions. 2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 input/output schematic (continued) Port P2, un-bonded bits P2.6 and P2.7 EN D Interrupt Edge Select EN Set Q P2IE.x P2IFG.x P2IRQ.x Interrupt Flag P2IES.x P2SEL.x Module X IN P2IN.x P2OUT.x Module X OUT Direction Control From Module P2DIR.x P2SEL.x Bus Keeper 0: Input 1: Output Node Is Reset With PUC PUC NOTE: x = Bit identifier, 6 to 7 for Port P2 without external pins P2Sel.x P2DIR.x Dir. Control from module P2OUT.x Module X OUT P2IN.x Module X IN P2IE.x P2IFG.x P2IES.x NOTE: A good use of the unbonded bits 6 and 7 of port P2 is to use the interrupt flags. The interrupt flags can not be influenced from any signal other than from software. They work then as soft interrupt.

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, I TF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. When the TEST pin is taken back low after a test or programming session, the fuse check mode and sense currents are terminated. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see Figure 6). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). Time TMS Goes Low After POR TMS ITF ITEST Figure 6. Fuse Check Mode Current, MSP430x11x

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004 27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

16 PIN SHOWN

0.400 (10,15) 0.419 (10,65) 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) A 0.020 (0,51) 0.014 (0,35) 0.293 (7,45) 0.299 (7,59) 0.010 (0,25) 0.050 (1,27) 0.016 (0,40) (15,24) (15,49) PINS ** 0.010 (0,25) NOM A MAX DIM A MIN Gage Plane 0.500 (12,70) (12,95) 0.510 (10,16) (10,41) 0.400 0.410 0.600 0.610 0.004 (0,10) M0.010 (0,25) 0.050 (1,27) 0°−/C0257 8° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MS-013

/C0077/C0083/C0080/C0052/C0051/C0048/C0120/C0049/C0049/C0120 /C0077/C0073/C0088/C0069/C0068 /C0083/C0073/C0071/C0078/C0065/C0076 /C0077/C0073/C0067/C0082/C0079/C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082/C0083 SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004

28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430C111IDW, MSP430C112IDW, MSP430P112IDW pin out TEST/VPP VCC P2.5/ROSC VSS XOUT/TCLK XIN RST /NMI P2.0/ACLK P2.1/INCLK P2.2/TA0 P1.7/TA2/TDO/TDI P1.6/TA1/TDI P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK P2.4/TA2 P2.3/TA1 DW PACKAGE (TOP VIEW) PMS430E112 pin out TEST/VPP VCC P2.5/ROSC VSS XOUT/TCLK XIN RST /NMI P2.0/ACLK P2.1/INCLK P2.2/TA0 P1.7/TA2/TDO/TDI P1.6/TA1/TDI P1.5/TA0/PMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK P2.4/TA2 P2.3/TA1 JL PACKAGE (TOP VIEW)

www.ti.com 28-Oct-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples MSP-EVK430A110 OBSOLETE 0 TBD Call TI Call TI MSP430C111IDW OBSOLETE SOIC DW 20 TBD Call TI Call TI -40 to 85 MSP430P112AY OBSOLETE DIESALE Y 0 TBD Call TI Call TI -40 to 85 MSP430P112IDW OBSOLETE SOIC DW 20 TBD Call TI Call TI -40 to 85 M430P112 PMS430E112JL OBSOLETE CDIP JL 20 TBD Call TI Call TI P430 E112 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

www.ti.com 28-Oct-2014 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

MCER003A – JANUARY 1997 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 JL (R-GDIP-T20) CERAMIC DUAL-IN-LINE PACKAGE 0.200 (5,08) MAX 0.310 (7,87) 0.290 (7,37) 0.130 (3,30) MIN 0.008 (0,20) 0.014 (0,36) Seating Plane 4040109/C 08/96 0.020 (0,51) MIN Window 0.015 (0,38) 0.050 (1,27) 0.050 (1,27) 0.015 (0,38) 0.975 (24,76) 0.930 (23,62) 0.023 (0,58) 0.015 (0,38) 0.245 (6,22) 0.300 (7,62) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only E. Falls within MIL-STD-1835 GDIP1-T20

www.ti.com PACKAGE OUTLINE C TYP10.63 9.97

2.65 MAX

18X 1.27 20X 0.51 0.31 11.43 TYP0.33 0.10 0 - 8 0.3 0.1 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 13.0 12.6 B 7.6 7.4 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. 1 20

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.200

www.ti.com EXAMPLE BOARD LAYOUT (9.3)

0.07 MAX

0.07 MIN

20X (2) 20X (0.6) 18X (1.27) (R ) TYP 0.05 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC SYMM SYMM LAND PATTERN EXAMPLE SCALE:6X 10 11 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (9.3) 18X (1.27) 20X (0.6) 20X (2) 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 10 11 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X

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