PMB2304R INFINEON | Alldatasheet
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PMB 2304R Version 2.1 Specification June 2002 preliminary
Edition 03.02 Published by Infineon Technologies AG SC, Balanstraße 73,
81541 München
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Product InfoWireless Components Specification, June 2002 Package: PMB 2304R preliminary Productinfo General Description The PMB 2304R PLL is a high speed CMOS IC, especially designed for use in battery powered radio equipment and mobile telephones and serves as a functional replacement of the PMB 2307R. The primary applications are in digital cellular and cordless systems e.g. GSM 900/1800/1900 and DECT systems. The wide range of dividing ratios also allows application in analog systems.
Features
/G01 Low operating current consumption (typically 3.5 mA) /G01 High input sensitivity, high input frequencies (220 MHz) /G01 Extremely fast phase detector without dead zone /G01 Linearization of the phase detector output by current sources /G01 Synchronous programming of the counters (N-, N/A-, R-counters) and system parameters /G01 Fast modulus switchover for 65-MHz operation /G01 Switchable modulus trigger edge /G01 Serial control (3-wire bus: data, clock, enable) for fast programming fmax ~ 10 MHz) /G01 Large dividing ratios for small channel spacing A counter 0 to 127 N counter 3 to 16.383 R counter 3 to 65.535 /G01 Serial control (3-wire bus: data, clock, enable) for fast programming fmax ~ 10 MHz) /G01 Switchable polarity and phase detector current programmable /G01 2 Multifunction outputs frn, fvn outputs of the R- and N/A- counters for test /G01 Output port (e.g. for standby of the prescaler) /G01 External current setting for PD output /G01 Lock detect output with quasidigital lock detect Application /G01 GSM 900 / 1800 / 1900 /G01 DECT /G01 Analog systems
Ordering Information
Type Ordering Code Package PMB 2304R Q67106-H9100 P-TSSOP-16
1 Table of Contents
5.1.3 Typical Supply Current I
2 Product Description
Specification, June 2002
2.1 Overview
The PMB 2304R PLL is a high speed CMOS IC, especially designed for use in battery powered radio equipment and mobile telephones and serves as a func- tional replacement of the PMB 2307R. The primary applications are in digital cellular and cordless systems e.g. GSM 900/1800/1900 and DECT systems. The wide range of dividing ratios also allows application in analog systems.
2.2 Features
/G01 Low operating current consumption (typically 3.5 mA) /G01 High input sensitivity, high input frequencies (220 MHz) /G01 Extremely fast phase detector without dead zone /G01 Linearization of the phase detector output by current sources /G01 Synchronous programming of the counters (N-, N/A-, R-counters) and system parameters /G01 Fast modulus switchover for 65-MHz operation /G01 Switchable modulus trigger edge /G01 Serial control (3-wire bus: data, clock, enable) for fast programming fmax ~ 10 MHz) /G01 Large dividing ratios for small channel spacing A counter 0 to 127 N counter 3 to 16.383 R counter 3 to 65.535 /G01 Serial control (3-wire bus: data, clock, enable) for fast programming fmax ~ 10 MHz) /G01 Switchable polarity and phase detector current programmable /G01 2 Multifunction outputs frn, fvn outputs of the R- and N/A- counters for test /G01 Output port (e.g. for standby of the prescaler) /G01 External current setting for PD output /G01 Lock detect output with quasidigital lock detect
Specification, June 2002
2.3 Application
/G01 GSM 900 / 1800 / 1900 /G01 DECT /G01 Analog systems
2.4 Package Outlines
3 Functional Description
Specification, June 2002
3.1 Pin Configuration
Pin_config.wmf Figure 3-1 Pin Configuration
3.2 Pin Definition and Function
Table 3-1 Pin Definition and Function Pin No. Symbol Equivalent I/O-Schematic Function
1 RI Reference Frequency
Input with highly sensitive preamplifier for 16-bit R-counter. With small input signals AC coupling must be set up, where DC cou- pling can be used for large input signals. VSS Ground for serial control logic. 560 Ω ESD 2pF STDBY STDBY RI 500K Ω Pin1
Specification, June 2002
3 EN 3-Line Bus: Enable
Enable line of the serial control with inter- nal pull-up resistor. When EN = H the input signals CLK and DA are disabled internally. When EN = L the serial control is activated. The received data are trans- ferred into the latches with the positive edge of the EN-signal. DA 3-Line Bus: Data Serial data input with internal pull-up resistor. The last two bits before the EN- signal define the destination address. In a byte-oriented data structure the transmit- ted data have to end with the EN-signal, i.e. bits to be filled in (don’t care) are transmitted first. CLK 3-Line Bus: Clock Clock line with internal pull-up resistor. The serial data are read into the internal shift register with the positive edge (see pulse diagram for serial data control). VDD Positive supply voltage for serial control logic.
7 MOD Modulus Control Output for external
dual modulus prescaler. The modulus output is low at the beginning of the cycle. When the A-counter has reached its set value, MOD switches to high. When the N-counter has reached its set value, MOD switches to low again, and the cycle starts from the top. When the prescaler has the counter factor P or P + 1 (P for MOD = H, P + 1 for MOD = L), the overall divider factor is NP + A. The value of the A-counter must be smaller than that of the N-counter. The trigger edge of the modulus signal to the input signal can be selected (see programming tables and MODA, B) according to the needs of the prescaler. In single modulus operation and for standby operation in dual modu- lus operation, the output is low. Pin 3 EN ESD *2pF 560 Ω 75kΩ Pin 4 DA ESD *2pF 560 Ω 75kΩ Pin 5 CLK ESD *2pF 560 Ω 75kΩ ESD 2pF pin 7 MOD
Specification, June 2002
8 NC not connected
9 NC not connected
10 FI VCO-Frequency
Input with highly sensitive preamplifier for 14-bit N-counter and 7-bit A-counter. With small input signals AC coupling must be set up, where DC coupling can be used for large input signals. VSS1 Ground for the preamplifiers, counters, phase detector and charge pump. (Note: The pins VDD and VDD 1 respec- tively VSS and VSS 1 have to have the same supply voltage.)
12 PD Phase Detector
Tristate charge pump output. The inte- grated, positive and negative current sources can be programmed with respect to their current density by means of the serial control. Activation and deactivation depend on the phase relationship of the scaled-down input signals FI:N, RI:R. (See phase detector output waveforms.) frequency fV < fR or fV lagging:p-channel current source active frequency fV > fR or fR leading:n-channel current source active frequencyfV = fR and PLL locked:current sources are switched off, PD-output is tristate In standby mode the PD-output is set to tristate. The assignment of the current sources to the output signals of the phase detector can be swapped in it’s polarity, i.e. the sign of the phase detector con- stant can be controlled. VDD1 Positive supply voltage for the preamplifi- ers, counters, phase detector and charge pump. 560 Ω ESD 2pF STDBY STDBY FI 500K Ω Pin10 ESD *2pF pin 12 PD * Only this pin has limited build-in ESD protection
Specification, June 2002
14 MFO1 Multifunction Output for the signals fRN ,
Φ V,, Φ VN , and port1. –The signal fRN is the divided signal of the reference frequency. The L-time corresponds to 1/fRI respec- tively –In the port function the port 1 output sig- nal is assigned to the information of the programmed status. The output switches with the rising edge of the EN-signal The standby mode does not affect the port function. MFO2 Multifunction I/O-Pin for the external ref- erence current setting IREF and the signals Φ RN and fVN ( in testmode). –The signal fVN is the divided signal of FI- input. The L-time corresponds to 1/fFI respectively. Output levels are not specified, the signal should only be used for test purpose. –In the internal charge pump mode the reference current IREF at MFO2 deter- mines the value of the PD-output current. 16 LD Lock Detector Output (open drain). Uni- polar output of the phase detector in the form of a pulse-width modulated signal. The LD-pulse width corresponds to the phase difference. In the locked state the LD-signal is at H-level. For standby mode see Standby Table. Only for ABL status 11 no gating of ABL impulse is performed. ESD 2pF pin 14 MFO1 MF02 V REF V REF IREF ESD 2pF 560 Ω Internal Charge Pump Mode & standby Pin15 ESD 2pF pin 16 LD
Specification, June 2002
3.3 Functional Block Diagram
Funct_block.wmf Figure 3-2 Functional Block Diagram 16-Bit R-Counter Data Register Shadow Register Shift Register Phase- Detector and Charge Pump Lock- Detector Modulus Control 14-Bit N-Counter Data Register Shadow Register Shift Register 7-Bit A-Counter Data Register Shadow Register Shift Register Serial Control Logic ƒR /G01 R ƒV /G01 V IREF RI FI CLK DA EN V SS V DD V SS1 V DD1 MOD MFO2 MFO1 PD LD
Specification, June 2002
3.4 General Description
The circuit consists of a reference-, A- and N-counter, a dual modulus control logic, a phase detector with charge pump output and a serial control logic. The setting of the operating mode and the selection of the counter ratios is done serially at the ports CLK, DA and EN. The operating modes allow the selection of single or dual operation, asynchro- nous or synchronous data acquisition, 4 different antibacklash-impulse times, 8 different PD-output current modes, polarity setting of the PD-output signal, adjustment of the trigger-edge of the MOD-output signal, 2 standby modes and the control of the multifunction outputs MFO1 and MFO2. The reference frequency is applied at the RI-input and divided by the R-counter. It’s maximum value is 100 MHz. The VCO-frequency is applied at the FI-input and divided by the N- or N/A-counter according to single or dual mode opera- tion. The maximum value at FI is 220 MHz at single-, and 65 MHz at dual mode operation. The phase and frequency sensitive phase detector produces an output signal with adjustable anti-backlash impulses in order to prevent a dead zone for very small phase deviations. Phase differences of less than 100 ps can be resolved. In general the shortest anti-backlash pulse gives the best system performance.
3.5 Programming
Programming of the IC is done by a serial data control. The contents of the mes- sage are assigned to the functional units according to the address. Single or dual mode operation as well as asynchronous or synchronous data acquisition is set by status 2 and should therefore precede the programming of the counters.
3.6 Data acquisition
The PMB 2304R offers the possibility of synchronous data acquisition to avoid error signals at the phase detector due to non-corresponding dividing factors in the counters produced by asynchronous loading. Synchronous programming guarantees control during changes of frequency or channel. That means that the state of the phase detector or the phase difference is kept maintained, and in case of “lock in”, the control process starts with the phase difference “zero”.
Specification, June 2002 This is done as follows: 1. Setting of synchronous data acquisition by status 2. 2. Programming of the R-counter, status 1 (optional)-data is being loaded into shadow registers. 3. Programming of the N- or N/A-counter-data is being loaded into shadow reg- isters, the EN-signal starts the synchronous loading procedure. 4. Synchronous programming – which means data transfer of all data from the shadow registers to the data registers – takes place at that point in time when the respective counter reaches “zero + 1”, the maximum repetition rate for channel change is therefore fFI:N. 5. Transfer of status 1 information into the corresponding data register is tied to the N-counter loading, but follows the loading of the N-data register in the distance of one N-counter dividing ratio, this guarantees that for example a new PD-current value becomes valid at the same time when the counters are loaded with the new data. Synchronous avoids additional phase error caused by programming. Synchro- nous data acquisition is of especial advantage, when large steps in frequency are to be made in a short time. For this purpose a high reference frequency can be programmed in order to achieve rapid – “rough” – transient response. This method increases the fundamental frequency nearly by the square route of the reference frequency relation. When rough lock is achieved, another synchro- nous data transfer is needed to switch back to the original channel spacing. A “fine” lock in will finish the total step response. It may not be necessary to change reference frequency, but it make sense to perform synchronous data acquisition in any case. Especially for GSM, PCN, PCS, DECT, DAMPS, PHP systems the synchronous mode should be used to get best performance of the PMB 2304R. Standby Condition: The PMB 2304R has two standby modes (standby 1, 2) to reduce the current consumption. Standby 1 switches off the whole circuit, the current consumption is reduced below 1 µA. Standby 2 switches off the counters, the charge pump and the outputs, only the preamplifiers stay active. For the influence on the output signals see standby table (5-10). fRN , fVN , Φ RN , Φ VN are the inverted signals of fR , fV,Φ R , Φ V.
4 Applications
Applications
Specification, July 1999
4.1 PCB Layout
oben.wmf Figure 4-1 Top Side unten.wmf Figure 4-2 Bottom Side
Specification, July 1999
4.2 Application Board
stromlauf.wmf Figure 4-3 Application board
Specification, July 1999
4.3 Bill of material
Nr Reference Symbol name Technology
1 C1 CAP 10p
2 C2 CAPELK 4µ7
3 C3 CAP 10p
4 C4 CAP 10p
5 C5 CAP 10p
6 C6 CAP 220pF
7 C7 CAP 330pF
8 C8 CAP 30pF
9 C9 CAP 100p
10 C10 CAP 100n
11 C11 CAP 100p
12 C12 CAP 100n
13 C13 CAPELK 4µ7
14 C14 CAP 5.6nF
15 C15 CAP 150p
16 C16 CAP 10nF
17 C17 CAP 1nF
18 C18 CAPELK 4µ7
19 IC1 PMB2314T PMB2314T
20 IC2 PMB2305 PMB2304R
21 J1 CON-5 5 Pin
22 J2 JUMP-2SMD0603 JUMPER_2SMD06031
23 J3 JUMP-2SMD0603 JUMPER_2SMD06031
24 N2 VCO2 1500MHz
25 R1 RES 10k
26 R2 RES 10k
27 R3 RES 10k
28 R4 RES 4k7
29 R5 RES 4k7
30 R6 RES 4k7
31 R7 RES 27k
32 R8 RES 124k
Specification, July 1999 33 R9 RES 8.2k
34 R10 RES 18
35 R11 RES 56
36 R12 RES 18
37 R13 RES 18
38 R14 RES 47
39 R15 RES 10
40 R16 RES 10
41 R17 RES 22k
42 SMA SMA_stehend
43 - SMA SMA_stehend
44 X1 SMA SMA_stehend
45 X2 SMA SMA_stehend
5 Reference
Specification, June 2002
5.1 Electrical Data
5.1.1 Absolute Maximum Range
The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result. Table 5-1 Absolute Maximum Range Parameter Symbol Limit Values Unit Remarks min max Supply Voltage VDD -0.3 6 V Input Voltage V1 -0.3 VDD + 0.3 V Output Voltage VQ GND VDD V Power dissipation per output PQ 10 mW Total power dissipation Ptot 300 mW Ambient temperature TA -40 85 °C in operation Storage temperature Tstg -50 125 °C Thermal Resistance R thJA 180 K/W ESD Integrity except @Pin 12 (PD) (according to MIL833 Method 3015.7) VESD 1 KV ESD Integrity except @Pin 12 (PD) (according to MIL833 Method 3015.7) VESD 400 V
Specification, June 2002
5.1.2 Operating Ratings
Within the operating ratings the IC operates as described in the circuit descrip- tion. The AC/DC characteristic limits are not guaranteed.
5.1.3 Typical Supply Current IDD
All pins are protected against ESD. Unused inputs without pullup resistors must be connected to either VDD or VSS . Parameter Symbol Limit Values Unit Test Conditions L Item min max Supply Voltage VDD 2.7 5.5 V Input frequency dual mode ƒFI 0.1 30 MHz VDD = 2.7V Input frequency single HF-modeƒFI 0.1 90 MHz VDD = 2.7V Input frequency single LF-modeƒFI 0.1 35 MHz VDD = 2.7V Input reference frequency ƒRI 20 MHz VDD = 2.7V PD-output current / IPD 4 mA PD-output voltage VPD 0.5 VDD - 0.5 V VDD = 4.5- 5.5V PD-output voltage VPD 0.5 VDD - 0.5 c VDD = 2.7V Ambient temperature TA -40 85 °C Table 5-3 Typical Supply Current IDD Parameter Symbol Limit Values Unit Test Conditions L Item min max Supply voltage VDD 2.7 55 . 5 V Supply current: ƒFI = 50MHz VFI = 150mVrms ƒRI = 10MHz VRI = 150mVrms IPD = 0.25mA Iref = 100 µA single mode HF IDD 1.63 2.6 2.94 mA dual mode IDD 1.76 2.80 3.17 mA standby 2 IDD 0.11 0.62 0.75 mA standby 1 IDD 1 µA
Specification, June 2002
5.1.4 AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified sup- ply voltage and ambient temperature range. Typical characteristics are the median of the production. Symbol Limit Values Unit Test Conditions L Item min typ max Input Signals DA, CLK, EN (with internal pull-up resistors) H-input voltage VIH 0.7- VDD VDD V 1.1 L-input voltage VIL 0.3- VDD V 1.2 Input capacity CI 5 pF H-input current IH 10 µA VI = VDD = 5.5V 1.3 L-input current IL -60 µA VI = GND 1.4 Input Signal RI Input capacity CI 3 pF H-input current IH 30 µA VI = VDD = 5.5V 2.4 L-input current IL -30 µA VI = GND 2.5 Input Signal FI (dual mode) Input capacity CI 3 pF H-input current IH 30 µA VI = VDD = 5.5V 3.4 L-input current IL -30 µA VI = GND 3.5 Input Signal FI (single HF-mode) Input capacity CI 3 pF H-input current IH 30 µA VI = VDD = 5.5V 4.5 L-input current IL -30 µA VI = GND 4.6
Specification, June 2002 Symbol Limit Values Unit Test Conditions L Item min typ max Input Signal FI (single LF-mode) Input capacity CI 3 pF H-input current IH 30 µA VI = VDD = 5.5V 5.4 L-input current IL -30 µA VI = GND 5.5 Output Current /IPD / Current mode: 6.1 "0.175 mA" IPROG -20% 0.175 +20% mA VPD = VDD/2 IREF = 100µΑ VDD = 4.5V 6.2 "0.25 mA" IPROG -20% 0.25 +20% mA 6.3 "0.35 mA" IPROG -20% 0.35 +20% mA 6.4 "0.5 mA" IPROG -20% 0.5 +20% mA 6.5 "0.7 mA" IPROG -20% 0.7 +20% mA 6.6 "1.0 mA" IPROG -15% 1.0 +15% mA 6.7 "1.4 mA" IPROG -15% 1.0 +15% mA 6.8 "2.0 mA" IPROG -10% 2.0 +10% mA 6.9 Standby" /IPD / 0.1 1 nA /G01 6.10 Output Tolerance IPD ∆IPD / IPROG -10% -5% +0% VPD = VDD/2, VDD = 2.7V 7.1 Input Voltage MFO2 (Internal charge pump mode) IREF = 100µA 8.1 Output Signal MFO1 (push pull) H-output voltage VQH VDD - 1 V VDD = 2.7V,IQH=-1.2mA 9.3 L-output voltage VQL 1V VDD = 2.7V,IQL=1.2mA 9.4 Rise time tR 51 2 n s VDD = 2.7V,C I=10pF 9.7 Fall time tF 41 2 n s VDD = 2.7V,C I=10pF 9.8
Specification, June 2002 Symbol Limit Values Unit Test Conditions L Item min typ max Output Signal MFO2 (push pull) H-output voltage VQH VDD - 1 V VDD = 2.7V,IQH= 1.2mA 10.3 L-output voltage VQL 1V VDD = 2.7V,IQL= 1.2mA 10.4 Rise time tR 31 0 n s VDD = 2.7V,C I=10pF 10.7 Fall time tF 31 0 n s VDD = 2.7V,C I=10pF 10.8 Output Signal LD (n-channel open drain) IQL = 0.3mA 11.1 Fall time tF 51 2 n s VDD = 2.7V,CI=10pF 11.4 Output Signal MOD (push pull) IQH = -0.5mA 12.1 IQL = 0.5mA 12.2 H-output voltage VQH VDD -0.4 V VDD = 2.7V, IQH = - 0.3mA 12.3 L-output voltage VQL 0.4 V VDD = 2.7V, IQL= 0.3mA 12.4 Propagation delay time H-L to FI Propagation delay time L-H to FI Rise time tR 3.2 5 ns VDD = 2.7V, CI = 5pF 12.9 Fall time tF 25 n s VDD = 2.7V, CI = 5pF 12.10 Propagation delay time H-L to FI tDQHL 15 ns VDD = 2.7V, CI = 5pF 12.11 Propagation delay time L-H to FI tDQHL 15 ns VDD = 2.7V, CI = 5pF 12.12 /G01 /G02 This value is only guaranteed in lab.
Specification, June 2002
5.2 Phase detector outputs
Figure 5-1 Phase detector output signals P-Channel Tri-State. P-Channel Tri-State. RI PD PD LD (RI:R) (FI:N) Polarity pos. Polarity neg. N-Channel Frequency fV > fR or fV leading Frequency fV = fRFrequency fV < fR or fV lagging fR fV MOD A MOD B FI Φ V Polarity pos. (internal Signal) N-Channel Φ R Polarity pos. (internal Signal)
Specification, June 2002
5.3 Serial Control Data Format
Table 5-5 Serial Control Data Format (status 1,2) Status 1 Status 2 0 1 Data acquisition mode 1 asynchronous synchronous Mode 1 2 see table Mode 2 3 see table PD-polarity 4 negative positive Standby 1 5 standby active Standby 2 6 standby active Anti-backlash pulse width 1 7 see table Anti-backlash pulse width 2 8 see table Preamplifier select 9 see table Single / dual mode 10 single dual
1 Port 1 11 low high
2 PD-current 1 12 see table
3 PD-current 2 13 see table
4 PD-current 3 14 see table
Specification, June 2002 Table 5-6 Serial Control Data Format (N-, N/A-counter) Table 5-7 Serial Control Data Format (R-counter) Dual Mode Single Mode
1 MSB
Specification, June 2002
5.4 Programming Tables
- No ABL gating performed * In general the shortest anti-backlash pulse gives the best system performance Table 5-8 Status Bits Anti- Backlash Pulse Width 2 Anti- Backlash Pulse Width 1 tW (typ.) [ns] 0 01 . 3 VDD = 5V 0 15 1 01 0 not recommended 1 11 3 * any application where continuous lock detect is required Table 5-9 Status Bits Preamplifier Function Mode Single/Dual Mode Preamplifier Select 0 0 FI-input frequency,single HF-mode 0 1 FI-input frequency,single LF-mode 1 0 FI-input frequency, dual-mode, FI- trigger edge LH, MOD A 1 1 FI-input frequency, dual-mode, FI- trigger edge HL, MOD B Table 5-10 Standby Table Output Pins Status MFO1 MFO2 LD PD MOD Φ V Φ VN Standby 1 low high high resistive tristate low Standby 2 low high high resistive tristate low
Specification, June 2002
5.5 Pulse Diagram
Status Bits PD-Current Mode PD-Current 3 PD-Current 2 PD-Current 1 Ipd/mA 0 00 0.175 0 01 0.25 0 10 0.35 0 11 0.5 1 00 0.7 1 01 1 1 10 1.4 1 11 2 Table 5-12 Status Bits Multifunction Output Mode 2 Mode 1 MFO 1 MFO 2 Remarks 0 0f RN fVN test mode 0 1 Φ V Φ RN external charge pump mode 1 1 0 Φ VN Φ RN external charge pump mode 2 1 1P o r t 1 Iref internal charge pump mode 50% 50% 50% 50% 50%50% VQH VQL VQH VQL FI MOD A MOD B tDQLH tDQLH tDQLH tDQLH tR tF tFtR
Specification, June 2002
5.6 Serial Control Data Input Timing
Figure 5-3 Serial Control Data Input Timing Table 5-13 Parameter Symbol Limit Values Unit min max Clock frequency ƒCL 12 MHz H-pulsewidth (CL) tWHCL 40 ns Data setup tDS 20 ns Setup time-clock enable tCLE 20 ns Setup time enable-clock tECL 20 ns H-pulsewidth (enable) tWHEN 40 ns Rise, fall time tR, tF 10 µs Propagation delay time EN-PORTtDEP 1 µs VIL VIH VIH VIL VIH VIL VIH VIL tWHCL tWHEN tECLtCLE tDS tDEP CLK DA EN MFO1 tFtR MFO3
Specification, June 2002
5.7 Diagram Input Sensitivity FI
Figure 5-4 Input sensitivity FI (single HF-mode)