PM8803TR STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 34
Technical content
Datasheet sections
- 1 Typical application circuits and block diagrams
- 1.1 Application circuits
- 1.2 Block diagrams
- 2 Pin descriptions and connection diagrams
- 3 Electrical specifications
- 3.1 Absolute maximum ratings
- 3.2 Thermal data
- 3.3 Electrical characteristics
- 4 PD interface
- 4.1 Detection
- 4.2 Classification
- 4.3 Indication of successful 2-event classification
- 4.4 Undervoltage lockout
- 4.5 Inrush and DC current limiting
- 4.6 High-voltage startup regulator
- 5 PWM controller
- 5.1 Oscillator
- 5.2 Delay time control
- 5.3 Soft-start
- 5.4 PWM comparator / slope compensation
- 5.5 Current limit
- 5.6 Thermal protection
- 6 Auxiliary sources
- 7 Package mechanical data
- 8 Revision history
Features
■ IEEE 802.3at compliant PD interface ■ Works with power supplied from Ethernet LAN cables or from local auxiliary sources ■ Successful IEEE802.3at Layer1 classification indicator ■ Integrated 100 V, 0. 45 Ω, 1 A hot-swap MOSFET ■ Accurate 140 mA typ. inrush current level ■ Programmable classification current ■ Programmable DC current limit up to 1 A ■ Integrated high-voltage startup bias regulator ■ Thermal shutdown protection ■ Current mode pulse width modulator ■ Programmable oscillator frequency ■ 80% maximum duty cycle with internal slope compensation ■ Support for flyback, forward, forward active clamp, flyback with synchronous rectification
Applications
■ VoIP phones, WLAN AP ■ WiMAX CPEs ■ Security cameras ■ PoE/PoE+ Powered Device appliances
Description
The PM8803 integrates a standard compliant Power over Ethernet (PoE) interface and a current mode PWM controller to simplify the design of the power supply sections of all powered devices. The PoE/PoE+ interface incorporates all the functions required by the IEEE 802.3at including detection, classification, undervoltage lockout (UVLO) and in-rush current limitation. The PM8803 specifically performs IEEE802.3at Layer1 hardware classification, providing an indication of Type 2 PSE successful detection to the rest of the system. The PM8803 has been designed to work with power either from the Ethernet cable or from an external power source such as a wall adapter, ensuring prevalence of the auxiliary source with respect to the PoE. The DC/DC section of the PM8803 features a programmable oscillator frequency, an adjustable slope compensation, dual complementary low-side drivers, programmable dead time and an internal temperature sensor. The PM8803 targets high-efficiency conversion at all load conditions supporting flyback, forward, forward with active clamp converters and synchronous rectification. HTSSOP20 Table 1. Device summary
1 Typical application circuits and block diagrams
1.1 Application circuits
Figure 1. Simplified application schematic for po wered devices using PM8803 in forward active
Figure 2. Simplified application schematic for powered devices using PM8803 in synchronous
1.2 Block diagrams
Figure 3. PM8803 internal block diagram
Figure 4. Block diagram of the DC/DC section of the PM8803
2 Pin descriptions and connection diagrams
Figure 5. Pin connections (top view) Table 2. Pin descriptions Input of the Pulse Width Modulator. bias an opto-coupler transistor. 2V B 5 V , up to 10 mA Bias Rail. This reference voltage can be used to bias an opto-coupler transistor. Current sense input for current mode control and overcurrent protection. GAT1 switches high to blank leading edge current spikes. 4R T N 1 Power ground for the GAT1 driver. This pin must be connected to RTN2 and ARTN. Main gate driver output of the PWM controller. capability. (5 ohm typ MOSFETs). Output of the internal high-voltage regulator. Secondary gate driver output. designs. 1 A peak sink-source current capability (5 ohm typ. MOSFETs). 8A R T N Analog PWM supply ground. RTN for sensitive analog circuitry including the SMPS current limit amplifier.
10 VDD
Power ground for the secondary gate driver. MOSFET which closes VSS to the return path of the DC-DC converter.
10 VSS
11 VDD
System high potential input.
12 VDD
System high potential input.
13 DET
will flow through the resistor only during the detection phase. Front auxiliary startup pin. rating pin. Connect this pin to VSS if not used. 15 CLS Classification resistor pin. Connect the classification programming resistor from this pin to VSS.
16 DCCL
section of PM8803. It can be set to exceed the IEEE802.3at current limit. Leave the pin open for standard IEEE 802.3at applications. age to ARTN to connect this low voltage rating pin. Connect this pin to ARTN if not used. GAT1 and GAT2. This pin cannot be left open.
19 FRS
Table 2. Pin descriptions (continued)
20 T2P
Successful 2-event classification indicator. performing a 2-event classification. T2P is an active-low signal. electrically connected to VSS.
3 Electrical specifications
3.1 Absolute maximum ratings
Table 3. Absolute maximum ratings Note: Absolute maximum ratings are limits beyond which damage to the device may occur.
3.2 Thermal data
Table 4. Thermal data
3.3 Electrical characteristics
GAT1 and GAT2 = not loaded, TA = 25 °C unless otherwise specified. Values in Bolded type apply over the full operating ambient temperature range.
- Internally limited to 160 °C typ with inte rnal overtemperature protection circuit.
- Package mounted on a 4-layer board ( 2 signals + 2 power s ), CU thickness 35 micron, with 6-8 vias on the
Table 5. Electrical characteristics - interface section
Table 5. Electrical characteristics - interface section (continued)
Table 6. Electrical characteristics - SMPS section
Table 6. Electrical characteristics - SMPS section (continued)
represent the most likely parametric norm at TA = 25 °C, and are provided for reference only. 2 Device thermal limitations could limit useful operating range. be limited within the specified max current limit.
4 PD interface
4.1 Detection
In Power over Ethernet systems, the Power Sourcing Equipment (PSE) senses the Ethernet connection to detect whether the Powered Device (PD) is plugged into the cable termination by applying a small voltage (2.7 V to 10 V) on the Ethernet cable and measuring the equivalent resistance in at least two consecutive steps. During this phase, the PD must present a resistance between 23.75 kΩ and 26.25 kΩ. The signature resistor must be connected between the DET and VDD pins. This resistor is in-series to a pass transistor (see Figure 3) enabled only during the detection phase. No current is flowing through the signature resistor for the rest of the operative phases (classification and turn-on). The value of the detection resistance has to be selected also taking into account the typical drop in voltage of the diode bridges. The typical value that can be used in most case is 24.9 kΩ. During detection, most of the circuits inside the PM8803 are disabled to minimize the offset current.
4.2 Classification
The classification phase in a PoE network is the feature that allows PSE to plan and allocate the available power to the appliances connected to various Ethernet ports. The PM8803 complies with both IEEE802.3at 1-event and 2-event classification schemes. 1-event classification in IEEE802.3at is the same as specified in the IEEE 802.3af standard, which divides the power levels below 12.95 W into 5 classes (Class 0 to Class 4). While Class 4 was reserved in IEEE802.3af, in IEEE802.3at Class 4 identifies Type2 PDs requiring up to 25.5 W. A Type2 PD is a PD that provides a Class 4 signature during Physical Layer Classification, understands 2-event classification and is capable of Data Link Layer classification. Figure 8 represent the voltage at the input of the PD when connected to a PSE performing 2-event classification. A Type2 PD will present in both classification events a Class 4 current while during the so called “mark-event”, between the 2 classification fingers, the PD will present an invalid signature resistance. To support the classification function, an equivalent programmable constant current generator has been implemented. Figure 6 depicts a primary schematic of the classification circuit. Following the successful completion of the detection phase, the voltage of the CLS pin is set to the 1.4 V voltage reference and a pass transistor connects the VIN pin to the CLS pin.
Figure 6. PM8803: reference schematic of the PoE classification logic
4.3 Indication of successful 2-event classification
or 2-event physical layer classification by asserting the T2P signal. classification event is completed. PD is connected to a Type1 PSE, and only 13 W input power will be available. Table 7. Value of the external classification resistor for the different PD classes of
4.4 Undervoltage lockout
UVLO is released and the hot-swap MOSFET is activated, initiating the inrush sequence. from normal operating conditions.
4.5 Inrush and DC current limiting
and the DC/DC input capacitance is charged in a controlled manner. During the inrush phase, the current is limited to 140 mA. to activate the DC/DC section. Figure 9. Line transient response
This limitation is active after the in-rush phase is completed. The useful programming range for the current limitation is between 140 mA and 1 A. The practical resistor value range is between 22 kΩ and 150 kΩ.
4.6 High-voltage startup regulator
The PM8803 embeds a high-voltage startup regulator to provide a controlled reference voltage of 8.0 V to the internal current mode PWM controller during its startup phase. The regulator output is connected to the VC pin as well as to the DC/DC section In normal isolated topology, the VC pin is diode-connected to the auxiliary winding of the transformer used for the flyback or forward configuration. When the voltage from the transformer exceeds the regulated voltage, the high-voltage regulator is shut off, reducing the amount of power dissipated inside the PM8803. In more detail, when the voltage from the auxiliary winding exceeds 8.0 V, the regulator resets its intervention threshold to 7 V. In this way, a loosely regulated voltage from the auxiliary winding is allowed without current-sharing with the internal regulator. In the meantime, if the auxiliary voltage fails, the internal regulator takes over without losing DC/DC control. The UVLO threshold on VC is 6.0 V typically: at this voltage the DC/DC controller operations are stopped and the outputs frozen in low state. While the external auxiliary voltage has to be chosen higher than 8.0 V to take advantage of the auxiliary winding, it must be also lower than 16 V for all operating conditions, to avoid the intervention of the internal protection clamp. A capacitor in the range of 220 nF-10 uF must be connected to DC/DC ground for stability. For applications with high current drawn from VC, large capacitance should be used (e.g. 10 µF) in order to avoid converter switch-off during the startup phase. A VC UVLO mechanism monitors the level of voltage on the VC pin. When VC voltage exceeds the VC UVLO_R, the PWM controller is enabled and it remains enabled until the VC voltage drops below its VCUVLO_F value. When an auxiliary winding is not used, the internal HV regulator UVLO threshold is set at 6.6 V and the current limit is set at 20 mA typ. This value includes the current internally drawn to bias the DC/DC controller, the gate drivers, the VB bias regulator and the external components that may be connected to the VC and VB pins. Notice that using the HV regulator without the auxiliary winding increases the internal power dissipation, and, when operating at high ambient temperature, may lead the device to go into thermal shutdown.
4.7 5 V bias regulator The PM8803 features an accurate 5 V output regulator, which can be used to bias the DC/DC feedback network and the optocoupler connected to the microcontroller. A capacitor in the range of 100 nF - 2.2 µF must be connected to ARTN for stability. The regulator current is supplied from the VC pin, to take advantage of the more efficient bias from the auxiliary winding. This means that the current drawn from the VB pin must be taken into account to evaluate the maximum current drawn from the VC pin The current drawn from the VB pin must be limited to 10 mA maximum. The VB regulator is also able to accept injected current up to 1 mA without losing voltage regulation.
5 PWM controller
5.1 Oscillator
The PWM switching frequency is equal to the programmed oscillator frequency. Figure 11. PWM frequency vs. R T
5.2 Delay time control
5.3 Soft-start
The DC/DC section of the PM8803 features an internal, digitally controlled, soft-start to make sure that output voltage ramps up in a safe and controlled manner. At the startup of the converter, the input voltage of the PWM comparator (CTL pin) is clamped to a value which is increased cycle by cycle until it reaches the regulation voltage. This results in a converter duty-cycle increasing from zero to the operative value in 4096 switching periods maximum. Taking into account that the output voltage will start to increase only when the CTL pin is higher than 1 V, effective duration of the output voltage soft-start ramp can be estimated with the following formula:
5.4 PWM comparator / slope compensation
In typical isolated operations, current is sensed on a sense resistor Rs put between the source of the primary side MOS and the RTN pin. The PWM comparator produces the PWM duty cycle by comparing the Rs ramp signal on CS with an error voltage derived from the error amplifier output. The error amplifier output voltage at the CTL pin is attenuated by a 4:1 resistor divider before it is presented to the PWM comparator input. The PWM duty cycle increases with the voltage at the CTL pin. The controller output duty cycle reduces to zero when the CTL pin voltage drops below approximately 1 V. For duty cycles greater than 50%, current mode control loops are subject to sub-harmonic oscillation. The PM8803 fixes the maximum duty cycle at 80% and implements a slope compensation technique consisting of adding an additional fixed slope voltage ramp to the signal at the CS pin. This is achieved by injecting a 45 µA sawtooth current into the current sense signal path on an integrated 2 kΩ resistor. Additional slope compensation may be added by increasing the source impedance of the current sense signal with an external resistor between the CS pin and the source of the current sense signal. The net effect in this case is to increase the slope of the voltage ramp at the PWM comparator terminals.
5.5 Current limit
The current sensed through the CS pin is compared to two fixed levels of 0.5 V and 0.7 V. The lower level is used to perform a cycle-by-cycle current limit, terminating the PWM pulse. If the overload persists for a duration longer than 4096 switching periods, the PWM is shut down for the same duration before beginning a new soft-start. At 250 kHz the allowed overcurrent duration is about 16 ms. TSS ms[] 4096
0.7 V level is reached on CS, the gate driver is instantaneously shut down and a new soft-
start is performed after 4096 switching periods. completely shutting down the PWM controller. Figure 14. Overload (left) and short-circuit (right) behavior
5.6 Thermal protection
PWM controller is switched off. automatically, without recycling the input voltage.
6 Auxiliary sources
The majority of Powered Devices is designed to work with power from either a PoE network or auxiliary sources. Even though having both sources simultaneously connected is not the normal operating case, the presence of an auxiliary supply allows PDs to be used also when the PoE is not available or not sufficient. Different alternatives are available for connecting auxiliary sources to the PoE section of a PD device. Auxiliary sources can be connected prior to the hot-swap MOSFET, after the hot- swap MOSFET or even at the output of the DC/DC converter. All the above-mentioned methods are available with the PM8803. Both Figure 1 and Figure 2 show simplified application schematics where auxiliary sources can be connected either Prior (Front) or After (Rear) the internal hot-swap MOSFET (VDD and RTN) making use of a resistor divider between the external source and respectively SP or SA pins. Connection of the wall adapter prior to the internal hot-swap MOSFET has a limitation on the voltage of the adapter itself, since it is seen as an alternative of the PoE line and the embedded DC/DC section would be activated only when its value is above the UVLO_R threshold. If the voltage on the SP pin is above 1.1 V, the internal UVLO threshold is bypassed and the PM8803 operates with voltage as low as 15 V typical. The current flowing into the hot-swap MOSFET will be limited by a dual threshold: typically140 mA during the inrush phase, and a user programmable value (DCCL pin) for the rest of the phases. Priority of one source over another cannot be guaranteed by design, since it depends on timings of insertion and the value of the PoE line with respect to the auxiliary. If, for example, the PoE connection is already established, the auxiliary source cannot prevail unless its value is higher than that of the PoE after the diode bridge. Please note that with the use of a low-voltage adapter applied before the hot swap frontal connection, the max power drawn could be evaluated as ( Vin - Vd ) x Imax; in case of a 15 V adapter the input power will be limited to about (15 - 0.5) x 1 A = 14.5 W, much lower than the available power from the PoE connection. High-power systems must use high-voltage power adapters, with voltage at 48 V, and rear connections, not to be limited by the internal DC current limitation. Both Figure 1 and Figure 2 show simplified application schematics where auxiliary sources are also connected after the internal hot-swap MOSFET (VDD and RTN). This connection, together with the resistor divider on the SA pin, allows priority of the external source with respect to the PoE. Indeed, if the voltage of this pin is above the value of 1.20 V, the PM8803 will disable its PD interface section and enable the DC/DC section only. The internal hot- swap MOSFET will be opened. Depending on the value of the auxiliary source, the resistor divider must be dimensioned in order to have voltage on the SA and SP pins above their thresholds but still below their maximum operative value of 3.3 V specified in Table 3. Figure 15 depicts a smooth transition between a PoE and a wall adapter whose voltage is 5 V higher than the PoE voltage.
Figure 15. Smooth transition from POE to auxiliary source only if the input voltage is over the signature threshold (10.8 V typ, 10.3 V -11.3 V range). Note that inrush current in this case is not limited and an external solution must be found. The T2P signal will remain high (de-asserted) if a rear auxiliary source is connected. system reboot because the PSE needs some time to re-detect the PD.
7 Package mechanical data
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 8. HTSSOP20 mechanical data
Figure 16. HTSSOP20 mechanical drawing
8 Revision history
Table 9. Document revision history 10-Mar-2011 1 Initial release. 07-Nov-2012 2 Document status promoted from preliminary data to production data.