PM7628FP AD | Alldatasheet
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FEATURES input data is directed into one of the DAC data latches deter- @ On-Chip Latches for Both DACs mined by the DAC selection control line DAC A/DAC B. @ +5V to +15V Single Supply Operation Operating from a single +5V to +15V power supply, the PM-7628 @ DACs Matched to 1% dissipates only 12mW of power in a space saving 20-pin 0.3" ¢ Four-Quadrant Multiplication DIP, and 20-terminal surface mount packages. The PM-7628 TTLICMOS Compatible from +5V To +15V features circuitry designed to protect against damage from elec- ® Full Temperature Operation tostatic discharges. e Ful @ Low Power Consumption e Microprocessor Compatible (60ns Write Time) CROSSREFERENCE @ Improved ESD and Latch-Up Resistance eae Automatically Insertable CerDIP and Plastic Packages ———Pm ADE RANGE Available in Surface Mount SO, PLCC, and LCC Packages PM7628AR anrezaTa MIL PM7628ARC/863 AD7628TE @ Improved AD7628 Tewreesc———SCSC~CTaeSSCSCN e Available in Die Form —pwresrp SCD TODBKN Gg PM7628FPC AD7628KP
APPLICATIONS
@ Disk Drives e Digital Gain/Attenuation Control PIN CONNECTIONS @ Digitally-Controlled Filter Parameters | @ Digitally-Controlled Audio Circuits acno [3] [20] ours | e X-Y Graphics oura [3] [75] Reg® Sue DIP @ Digital/Synchro Conversion Fred [3] [18] Vaer® (P-Suftix) e Robotics VaerA [a] [37] Voo 20-PIN HERMETIC DIP @ Ideal for Battery-Operated Equipment __ 9ann [3] [is] wa (R-Suffix) pacamac 8 Le} pal <= 20-PIN SOL ORDERING INFORMATION ' (use) Der 2! 280 se) (S-Sutfix) | PACKAGE: 20-Pin DIP. pee [el per | EXTENDED oes [a f2! 982 <o8 GAIN MILITARY INDUSTRIAL 284 [rol pe] 28s 555% RELATIVE ERROR TEMPERATURE TEMPERATURE TelaTelat ACCURACY Ty = +25°C 55°C TO +125°C 40°C TO +85°C nee [2] Tal Vaee® | 21/2LSB 22LSB PM7628AR_ PM7628ER PLCC PACKAGE con ‘a tal veo | sy2ise 2188 PMTB2BARG/96 CN noepctt (PC-Suftix) ‘DAC AOAC B is | wa | ___ 21/2188 22LSB - pare2ers't LCC PACKAGE aed a seas * Fordevices processedin total compliance to MIL-STD-883, add /883 after part (RC-Suffix) elo atcl number. Consult factory for 883 data sheet. eeeca ‘Burn-in is available on commercial and industrial temperature range parts in eos 8 CerDIP, plastic DIP, and TO-can packages. ‘For availability and burn-in information on SO and PLCC packages, contact your local sales office. FUNCTIONAL DIAGRAM Vngr GENERAL DESCRIPTION id The PM-7628 is an improved version of the AD7628 offering Vop0 4 Ree TTL compatibility from +5 to +15 volts and faster AC timing. It 60 Cc] outa contains two 8-bit multiplying CMOS digital-to-analog convert- ste, YP) Eee: z ers that are fabricated ina single chip. This monolithic construc- oar 4 tion offers excellent DAC-to-DAC matching and tracking over Agno temperature. oR Co | [| Pea The PM-7628 consists of two thin-film R-2R resistor-ladder net- Bo P| Toure works, two tracking span resistors, two data latches, one input Ee | oI buffer, and control logic circuitry. Dono The PM-7628's digital inputs are bus compatible with most 8-bit T microprocessors, including the 6800, 8080, 8085, and Z80. Vee? Data loading is similar to that of a RAM's write cycle. Digital REV. A DIGITAL-TO-ANALOG CONVERTERS 2-665
(T, = +25°C, unless otherwise noted.) CAUTION: Voto AGND eceececseee . wee OV, #17V 1. Donot apply voltages higher than V,,, of less than GND potential on any ter- oto DGND eee eee OV to H17V minal except Vac. D0 joo cereenencneeennnenanennananaannanaanananananeatensaae 2, The digital control inputs are zener-protected; however, permanent damag- AGND to DGND wn nenseennenteneinnnenntnn OV, Voy + 0.3V may occur on unprotected units from high-energy electrostatic fields, Keep DD Voinar Vpin2o 10 AGND vsvsssessessenssensensensernerneens —O.3V, Voy 3. Donotinsert this device into powered sockets; remove power before insertion VigegAs VgepB tO AGND o.ecscecssssssnseeseetnseesstisssenssens £25V Cr removal. ath eee yee FB to AGND 225V 4. Use proper antistatic handling procedures. are’ Vere Tevvererereeeeeernnecenennrenenenecnnnennnnennennns 5. Stresses above those listed under "Absolute Maximum Ratings" may cause Operating Temperature Range permanent damage to the device. PACKAGE TYPE jg (Note 1) % UNITS 20-Pin Hermetic DIP (R) 80 15 CW 20-Pin Plastic DIP (P) 74 32 CW 20-Contact LCC (RC) 89 27 CW 20-Contact PLCC (PC) 76 36 CW NOTE: 1. @,, 8 specified for worst case mounting conditions, i.e., @,, is specified for device in socket for CerDIP, P-DIP, and LCC packages; ©,, is specified for device soldered to printed circuit board for PLCC packages. ELECTRICAL CHARACTERISTICS: at V,, = +5V + 5%; Vac eA = Vac B = +10V; lou A = oy 7B = OV; T, = Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted. ee PM-7628 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY (Note 1) Resolution N 8 - - Bits Relative Accuracy (Note 2) INL - - 21/2 .sB Differential Nonlinearity . _ . (Note 3) DNL 1 .sB Full-Scale Gain Error c Ty = 425°C - 20.5 22 isp (Note 4) FSE T, = Full Temp, Range - 24.0 23 Gain Temperature Coefficient (A Gain / A Temperature) TCG eg - - 30.007 %PC (Notes 4, 10) Output Leakage Current Ty = 425°C - 35 +250 it iN lourA (Pin 2) Igy 7B (Pin 20) hg , = Full Temp. Range - - +2200 nA (Note 5) Input Resistance (Wage: Vacr8) Riu 8 - 15 ka (Note 6) Input Resistance Match AR y - 20.1 st % WaerAVaer®) Fin 2-666 DIGITAL-TO-ANALOG CONVERTERS REV. A
ELECTRICAL CHARACTERISTICS: at V,, = +5V + 5%; Vac cA = Vac -B = +10V; Igy yA = loy;B = OV; T, = Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted. Continued . PM-7628 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (Note 9) Digital Input High - _ (Note 8) Minn 24 v Digital Input Low (Note 8) Vine - - 08 v Input Current \\ Ty = +25°C - 4001 Fs] A (Note 7) WN T, =Full Temp. Range - - +10 ” Input Capacitance c DB0-DB7 - - 10 7 (Note 10) N WR, CS, DACA/DACB - - 15 e SWITCHING CHARACTERISITCS (Notes 10, 11) Chip Select to Write Set-Up Time ‘es 00 ns Chip Select to Write Hold Time ton "0 - - ns DAC Select to Write Set-Up Time tas 100 ~ ~ ns DAC Select to Write Hold Time tan ‘0 - - ns Data Valid to 7 a a 7 Write Set-Up Time ‘os 00 - - ne Data Valid to Write Hold Time fon ‘0 ~ ~ ns Write Puise Width wa 90 - - ns POWER SUPPLY Al Digital Input = Vjyyjy OF Viggy - - 1 mA Supply Current oo All Digital Input = OV oF V5 Ty = 425°C - - 05 mA T, = Full Temp. Range - - 1.0 REV. A DIGITAL-TO-ANALOG CONVERTERS 2-667
ELECTRICAL CHARACTERISTICS: at V,, = +5V + 5%; V,--A = Ve B = +10V; loys = loysB = OV; T, = Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted. Continued . PM-7628 PARAMETER ‘SYMBOL CONDITIONS MIN TYP MAX UNITS AC PERFORMANCE CHARACTERISTIC (Note 12) DC Supply Rejection Ratio , _ _ (AGain/ A Vp9) PSRR a = gee Range > - foe %i% (Note 13) i, = Full Temp. Rangs ’ Gurrent Setting Time ts T, = Full Temp. Range - - 300 ns Digital Charge Injection 7 _ _ (Note 17) Q Ty= 425°C 100 nVs CoyA DAC Latches Loaded - - 25 Coy 8 with 0000 0000 - - 25 Output Capacitance Courh DAC Latches Loaded rr PF CoyB with 111101411 - - 60 _ Vee t0 loyrA: AC Feodthrough T,, = Full Temp. Range - - 65 ‘e (Note 18) — vr — VperB 10 Igy 18: _ _ 70 Fly Th = +25°C - > “65 T, = Full Temp. Range VperA 0 boy 8! CCly a, VperA= 20V, . Sinewave @ f= 10kHz - 80 - Channel-to-Channel VperB = 0Vi Ty = +25°C 0B Isolation I (Note 19) VaerB 10 loyrAs CClgp VaerB = 20V,, , Sinewave @ f = 10kHz - -80 - VaepA = OViT, = +25°C Digal Crosstak ae For Code Transition rom 0000 000010 1111 1111 - 20 _ nVs Ty= 425°C Harmonic Distortion THD Viy= 6VIms @ f= 1hHz - 85 - 3B Ty= 425°C 2-668 DIGITAL-TO-ANALOG CONVERTERS REV. A
ELECTRICAL CHARACTERISTICS: at V,, = +10.8V and +15.75V; Vac = VageB = +10V; loys = loyrB = OV; T, = Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted. PM-7628 PARAMETER ‘SYMBOL CONDITIONS . MIN TYP MAX UNITS STATIC ACCURACY (Note 1) Resolution N sO - Bits Relative Accuracy _ . (Note 2) INL 2 usB Differential Nonlinearity Nowe 8) DNL - - Fs) usB Full Scale Gain Error 6 Ty = 425°C - 40.5 #2 ise (Note 4) FSE T, = Full Temp. Range - H 43 Gain Temperature Coefficient (AGain / 4 Temperature) TCG. 5 - = 40,0035 PC (Notes 4, 10) Output Leakage Current Ty = 425°C - 35 +50
1 A A
ourA (Pin2) loyr8(Pin20) ke T, = Full Temp. Range - - 4200 " (Note 5) Input Resistance (per: Veer) Rwy 8 - 15 kQ (Note 6) Input Resistance Match AR in “ Bin - 40.1 Fa) % Wace Vaer®) Rin DIGITAL INPUTS (Note 9) Digital Input High oe _ (Note 8) Vine 24 v Digital Input Low (Note 8) Vine - - 08 v Input Current \\ Ty = #25°C - +.001 4 A (Note 7) iN T,, =Full Temp. Range - - +0 bs Input Capacitance c DBO-DB7 - - 10 a (Note 10) IN ‘WR, CS, DAC A/DACB - - 15 e REV. A DIGITAL-TO-ANALOG CONVERTERS 2-669
. . ELECTRICAL CHARACTERISTICS: at V,, = +10.8V and +15.75V; VaecA = VpceB = +10V; Ioy7A = loyrB = OV; T, = Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted. Continued PM-7628 PARAMETER ‘SYMBOL CONDITIONS . Min P max UNITS SWITCHING CHARACTERISITCS (Notes 10, 11) Chip Select to Write Set-Up Time tos 60 - - ns Chip Select to Write Hold Time ‘on % - - ns DAC Select to Write Set-Up Time tas 60 ~ ~ ns DAC Select to Write Hold Time tan "0 ~ ~ ns Data Valid to ~~ - - . Write Set-Up Time tos 70 - - ns Datavaidto a a Write Hold Time ‘on - ~ ns Write Pulse Width twa 60 - - ns POWER SUPPLY All Digital Input = Viyy, OF Vip Ty = #25°C - - 2 mA T, = Full Temp. Range - - 25 Supply Current 'oo Al Digital Input = OV or +5V to Vp Ty = 425°C - - 0s mA 1, = Full Temp. Range - - 10 AC PERFORMANCE CHARACTERISTIC (Note 12) _ DC Supply Rejection Ratio 7 _ . (Note 13) am ip. Rang " Current Settling Time (Notes 10,15, 16,20) ts T, = Full Temp. Range - 200 ns Digital Charge Injection = 425° - 160 - Vs (Note 17) Q T,= 425°C n Courk DAC Latches Loaded - - 25 Cou8 with 0000 0000 - - 25 Output Capacitance CourA DAC Latches Loaded = - 60 pF Coy 8 with 1191 1911 - - 60 2-670 DIGITAL-TO-ANALOG CONVERTERS REV. A
ELECTRICAL CHARACTERISTICS: at V,, = +10.8V and +15.75V; VaccA = VazeB = +10V5 loys = loyrB = OV; Th = Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted. Continued PM-7628 PARAMETER SYMBOL CONDITIONS . MIN TYP MAX UNITS Viner A' lout: AC Foeathrough J, = Full Temp. Range - - 65 ® (Note 18) . Vag FB '0 lour8: - - 70 FTg Ty = 425°C > > 78 T,, = Full Temp. Range Veer tO loyxB: Clg, VaepA = 20V,,, Sinewave @f = 10kHz - -80 - Channel-to-Channel Vaer® = 0Vi Ta = +25°C 8 Isolation - (Note 19) WrerB 0 lous’: CClag VaerB=20V,,., Sinewave @ f = 10kHz - -80 - Vper = OV:T, = 425°C Digtal Crosatak e For Code Transition from 0000 0000101111 1111 - 50 _ ns Ty= 425°C Harmonic Distortion THD Nin= 6¥ems @ f= tkHz - -85 - B T y= 425°C NOTES: 1. Specifications apply to both DAC A and DAC B 11. See timing diagram, 2, This is an endpoint linearity specification. 12. These characteristics are for design guidance only and are not subject to 3. _All,grades guaranteed to be monotonic over the full operating temperature test. range. 18. AV, y= 15%. 4, Measured using internal Re gA and R, 8. Both DAC latches loaded with 14. From digital input to 90% of final analog-output current. 19111111, 15. VagpA= Vag gB = +10V; loyAs Igy 7B load = 1000, Cy, = 13pF. - VacrA= Vaer! our’ lout! »Cexr é PAC loaded a anrree ro. 16. WR, CS = OV, DBO-DB7 = OV 10 V;3, oF Vp t0 OV. ; jverv.. = 800 penne 17. For code transition 0000 000010 1111 1111 ~ Vin= oo _ 18. VacpA, Vag B= 20V,, , Sinewave @f = 10kHz, 1 ner: Vrer' bp . ies aca bits loos wr oS pac ‘ Dace 95°C) is less th 19. Both DAC latches loaded with 1111 1111, . tea puts are MOS gates. Typical input current (+25°C) is less than 20. Extrapolated: t, (1/2 LSB) = tp, +6.2t, where t = the measured first time 10. Guaranteed and not tested, Constant ofthe final RC decay WRITE CYCLE TIMING DIAGRAM a |= ton-+| “sv CHIPSELECT [4 tpg ota av DACTA/DAC B — ° f-—— wa + “sv WaITE ° Notes: 1. ALLINPUT SIGNAL RISE AND FALL [0s +/+ 10H TIMES MEASURED FROM 10% TO 90% 7 “sv ARE, =t=20ns. DATAIN (080-067) Cm oatamsrane 2. mans eASURewenT RerEnENCe iu Ya ° veveris Yet REV. A DIGITAL-TO-ANALOG CONVERTERS 2-671
DA 1. ANALOG GROUND (AGND) 11. DIGITAL INPUT DB, A IE} apme 2 OUTPUTA(OUTA) 12.,DIGITAL INPUT DB, Fr Hee res 3. DAC AFEEDBACK RESISTOR (R,,A) 13, DIGITAL INPUT DB, Cote a Wee 4. DACAREFEREMCEINPUT (Vpe-A) 14, DIGITAL INPUT DB, (LSB) cad Ee ikl g 5. DIGITAL GROUND (DGND) 15. CHIP SELECT (CS) ep! We 6. DIGITAL SELECTION (DAC A/DAC B) 16. WRITE (WR) 6 [emt 1% 7. DIGITAL INPUT DB, (MSB) 17. POSITIVE POWER SUPPLY (V,,,) a I HF 8. DIGITAL INPUT DB, 18. DAC B REFERENCE INPUT (VB) Po ee 9, DIGITAL INPUT DB, 19. DAC B FEEDBACK RESISTOR (R,,B) pi NICH ANNAN TE 10. DIGITAL INPUT DB, 20. OUTPUT B (OUT B) Oe ry a Bes F's hl onl ell Substrate (die Backside) is internally Bao dD 2 os connected to Vpn DIE SIZE 0.082 x 0.078 inch, 6,396 sq. mils (2.08 x 1.98 mm, 4.126 sq. mm) WAFER TEST LIMITS at V,,,, = +5V, +10.8V or +15.75V, Vac A = VaggB = +10V, OUT A = OUT B = OV; T, = 25°C, unless otherwise noted. PM-7628G PARAMETER SYMBOL CONDITIONS Limit UNITS Relative Accuracy INL Endpoint Linearity Error 21/2 LSB MAX Differential Nonlinearity ONL Ea] LSB MAX Gain Error Grse DAC Latches Loaded with 1111 1114 +2 LSB MAX DAC Latches Loaded with 0000 0000 Output Leakage lee Pad 2 and 20 30 nA MAX ka MIN’ Input Resistance Rw Pad 4 and 18 and KO MAX VaerAVaerB Input ner Vac + ¥ Resistance Match ace’ 8 * MAX Digital Input High Vin 24 VMIN Digital Input Low Vic 08 VMAX Input Current Iw Vy = OV OF Von, 4 HAMAX All Digital Inputs Vig, OF Vin, 2 nm Supply Current ‘oo All Digital Inputs OV or +5V to Vp 0s mA MAX DC Supply Rejection ‘ (aGain/ aV,) PSRR Vpp = 25% 0.01 %% MAX NOTE: Electrical tests are performed at wafer probe to the limits shown, Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. 2-672 DIGITAL-TO-ANALOG CONVERTERS REV.A
TYPICAL PERFORMANCE CHARACTERISTICS TOTAL UNADJUSTED ERROR RELATIVE ACCURACY FULL-SCALE GAIN ERROR vs DIGITAL INPUT vs REFERENCE VOLTAGE vs TEMPERATURE a are ess} TLL Pew [TT | 4 aI MELA. wranrcsrcmon| | BER pop tee PCO ic: ee a ee See 3 0280 2 FI 2 : | EPEER CSE Baaeenen io a] def | ws cal inane LO C1 CEP ed A ve OO sweLT TTT TT DIGITAL CODE REFERENCE VOLTAGE (VOLTS) ‘TEMPERATURE (°C) OUTPUT LEAKAGE CURRENT POWER SUPPLY REJECTION AC FEEDTHROUGH so vs TEMPERATURE core vs TEMPERATURE 5 vs FREQUENCY Poo Se eae g0 [TTT wos 4 of ratte ero) gee yr | AEE EECA |-Ai
3 Z [ 8 Patt
i a_i titty 3: ieee > A ce} LMI Til [ee |b o| PT | Beer PCP) bee ®t Lt Ty pt yt sont || | ttt tT | PT TT Ty se ELT TTT os LT TT veo LT TTI TTT 75 50 -2 0 2 80 75 100 125 75 50-25 0) 25 SD 7S 100125, 1k 10k 100k ™ TOTAL HARMONIC DISTORTION ANALOG CROSSTALK vs FREQUENCY vs FREQUENCY (= Th ‘AMAT @ -20|- Vrer= 6¥eus 20 Pe Is JETTIE PCM tT ih | | \\ 3° 3° [acre y a za A ! ee nN i i LUTTE TPs REV. A DIGITAL-TO-ANALOG CONVERTERS 2-673
TYPICAL PERFORMANCE CHARACTERISTICS Continued GAIN AND PHASE SHIFT SUPPLY CURRENT (Ipp) vs FREQUENCY WITH vs TEMPERATURE OP-42 OUTPUT AMPLIPHIER Poo J HOT FCC PCT a os a= oo IT TTT UT saptiti tt wa LIE TIE NUT be : 2 ; EER Lion a ri UTE UN GAIN (Vout/Vrer) TEST CIRCUIT juvenson 0 vs FREQUENCY 5 FOR GAIN vs FREQUENCY rasan aot ar asase SAU ee NT | [SEAN | 982 TS Bg. a 0 A ——? ane. ae COT em TiriN* ¢ st E> a a i oro i A | ec bo cate eg i UY a Com VOLTAGE SWITCHING MODE CHARACTERISTICS GAIN AND PHASE vs FREQUENCY RELATIVE ACCURACY VOLTAGE SWITCHING (VOLTAGE MODE) 3 vs REFERENCE VOLTAGE MODE TEST CIRCUIT P-CoICneTIC Ty 4 “| See. ~ TX | SCEPUPGTT 7 obeleded | | GH | g MAXIMUM PosiTive ERROR| \\” | IU CREAR Ow = | SEU a Lips | tk 10K 100K 1M 10M i o 2 4 6 8 10 2-674 DIGITAL-TO-ANALOG CONVERTERS REV. A
PARAMETER DEFINITIONS CIRCUIT INFORMATION RELATIVE ACCURACY ORINTEGRAL NONLINEARITY (INL) D/A SECTION This is the single most important DAC specification. PMI meas- There is a normally closed switch in series with the internal ures INL as the maximum deviation of the analog output (from feedback resistor (R,,) as shown in Figure 1. This switch im- the ideal) from a straight line drawn between the end points. Itis proves linearity performance over temperature and power sup- expressed as a percent of full-scale range or in terms of LSBs. ply rejection; however, when the circuit is not powered up, the Refer to PMI 1988 Data Book, Section 11, for additional digital- switch assumes an open state. to-analog converter definitions. See the PM-7528 data sheet for additional circuit information and applications. INTERFACE LOGIC INFORMATION DAC SELECTION Both DAC latches share a common 8-bit input port. The control a a fe | input DAC A/DAC B selects which DAC can accept data from the nero ! input port. aR aR R of, MODE SELECTION _ bs bo dss dh. bf . The inputs CS and WR control the operating mode of the se- ' j lected DAC. See Mode Selection Table below. 919 919 919 919 $ ) oour WRITE MODE __ ‘Lag 1] it oacno When CS and WR are both low, the selected DAC is in the write ! i H v mode. The input data latches of the selected DAC are transpar- ent and its analog output responds to the data on the data bit line DBO-DB7. — me HOLD MODE FIGURE 1: Simplified Functional Circuit for DAC A or DAC B The selected DAC latch retains the data which was present on the data lines just prior to CS or WR assuming a high state. Both DIGITAL SECTION analog outputs remain at the values corresponding to the data in The digital inputs are CMOS inverters. They were designed their respective latches. such that TTL input levels are converted into internal CMOS logic levels; they are used todrive the internal circuitry. Asimple 5V regulator is used to ensure TTL compatibility at V,,, = 12V to MODESELECTIONTABLE Sg ee Figure) DAGAIDACB CS WR DACA DAC ADAC B cs wR DACA DAC B The PM-7628’s digital inputs are TTL compatible between the L L L WRITE HOLD Vpp range of +5V to +16.5V. The digital inputs affect the amount i of quiescent supply current as shown in Figure 3. Peak supply H L L HOLD WRITE current occurs as the digital input (V,,) passes through the tran- sition region. Maintaining the digital input voltages as close as — xX HX HOLD HOLD possible to the supplies (V_,, and DGND) minimizes supply x x H HOLD HOLD current consumption. L = Low State H = High State X = Don't Care Yoo Zz GND FIGURE 2: Simplified Schematic of Digital Inputs REV. A DIGITAL-TO-ANALOG CONVERTERS 2-675
APPLICATIONS INFORMATION DC or AC signals. The circuit in Figure 7 performs two- The most common application of the PM-7628 is in the voltage quadrant multiplication. Table 1 provides example analog output mode. Unipolar output operation provides ato 10 volt —-utPuts for the given digital input codes. output swing when connected, as shown in Figure 7. The For bipolar output operation, connect the PM-7628 as shown in maximum output voltage polarity is the inverse of the input Figure 8. This circuit configuration provides an offset current, reference voltage, since the op amp inverts the input currents. derived from the reference, to enable the output op amp to The transfer equation for unipolar operation is Vout = —Vin X swing in both polarities. The digital input coding becomes D/256, where D is the decimal value of the data bit inputs DB offset binary. Table 2 provides some example analog outputs thru DB7 and Vy is the reference input voltage. The transfer for various digital inputs (D). The transfer equation for bipolar equation highlights another popular application of CMOS __ operationis Vout = Vin X (D/128 ~ 1), where D is the decimal DAC’s, multiplication. The output voltage is the product ofthe _ value of the data bit inputs DBg thru DB; This circuit provides reference voltage and the digital input code. The reference full four-quadrant multiplication, able to accept + polarities on input voltage can be any value in the range of +25 volts for both both inputs as well as the circuit output. Viv 6 (stow) RY Vop od am © VourA Dac Boe | AGNO AGNO <s 018] _>| contron 19, Boref— >| tosie ‘, SEEK | ours LatcH = is DGNo + $F. ‘GND Vi 8 = sme RECOMMENDED TRIM RESISTOR bs :D TAIN Fi éabineD, SEETABLE FOR RECOMMENDED VALUES, VALUES 8 GRADE__ MAKE GAIN ADJUSTMENT WITH DIGITAL INPUT OF 255, SRMIRSSISTOR, =—-_HP/ENVAR_
2 C,,C, PHASE COMPENSATION (10pF-15pF) IS RR 2008
REQUIRED WHEN USING HIGH SPEED AMPLIFIERS TO RR, 820 PREVENT RINGING OR OSCILLATION. tS FIGURE 7: Dual DAC Unipolar Binary Operation (2 Quadrant Multiplication). See Table 1. TABLE 1: Unipolar Binary Code Table. See Figure 7. TABLE 2: Bipolar (Offset Binary) Code Table. See Figure 8. DAC LATCH CONTENTS ANALOG OUTPUT DAC LATCH CONTENTS ANALOG OUTPUT MSB LSB (DAC A or DAC B) MSB LsB (DAC A or DAC B) vata ttn Vyy (388 ) ti4a 4404 +Vyy (435) a a ee — io 1000 0001 Vy (438) 1000 0001 +Vy (728)
128 Vin
1000 0000 Vy (358 ) =- 1000 0000 o ont 4ttt Vp (338) ott 4444 Vy (728 ) 0000 0001 Vy (33) 0000 0001 Vp, (433) 0 12 0000 0000 Vy (a58) =0 0000 0000 —Vyy (738) NOTE: 1 LSB = (2) (Vy) = z5%n) NOTE: 1 LSB = (277) (Viy) = wm (Vin) REV.A DIGITAL-TO-ANALOG CONVERTERS 2-677
(#10V)' R, Re 5 20k Vpp 0 — DB, 14 \\ | FAL gs roxst y © VourA De, , Ry 4 5kQ ORR g — | id = one og contaon AGN AGN AGND aber) Tose ro, Re fo | EE: = LateH paca = ie Re Ww oe = ND Ya) = ae NOTES: A "RR, AND R,, R, USED ONLY IF GAIN ADJUSTMENTIS REQUIRED.SEE 20K8t TABLE IN FIGURE 7 FOR RECOMMENDED VALUES. Vin8 © Your 8 ADJUST R, FOR Vou, A= OV WITH CODE 1000 0000 IN DACA LATCH. (e10v) Ry ‘ADJUST R, FOR Vo" B = 0V WITH CODE 1000 0000 INDAC B LATCH. es
2 MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R,, Like
°C), C, PHASE COMPENSATION (10pF-15pF)IS REQUIRED TO MINIBIZE AGND RINGING, FIGURE 8: Dual DAC Bipolar Operation (4 Quadrant Multiplication). See Table 2. APPLICATION HINTS 3. HIGH-FREQUENCY CONSIDERATIONS: The output To ensure system performance consistent with PM-7628 specifi- capacitance of a CMOS DAC works in conjunction with the cations, careful attention must be given to the following points: amplifier feedback resistance to add a pole to the open-loop 1. GENERAL GROUND MANAGEMENT: AC or transient response: this can cause ringing or oscillation. Stability can voltages between the PM-7628 AGND and DGND can e restored by adding a small phase-compensation capaci- fan ini i" ‘ tor in parallel with the feedback resistor. cause noise injection into the analog output. The simplest ; method of ensuring that voltages at AGND and DGND are = 4. DYNAMIC PERFORMANCE: The dynamic performance of equal, is to tie AGND and DGND together at the PM-7628. the two DACs in the PM-7628 will depend upon the gain and In more complex systems where the AGND-DGND con- phase characteristics of the output amplifiers, together nection is on the back-plane, it is recommended that with the optimum choice of the PC board layout and Schottky diodes (HP5082-2835 or equivalent) be connected decoupling components. in inverse parallel between the PM-7628 AGND and DGND 5. CIRCUIT LAYOUT SUGGESTIONS: Analog and digital pins. ground traces should be routed between package pins to 2. OUTPUT AMPLIFIER OFFSET: CMOS DACs exhibit a isolate the digital inputs from the analog circuitry. Analog code-dependent output resistance which in turn causes a ground traces should also be placed between pins 17-18, code-dependent amplifier noise gain. The effect is a code- 18-19, 3-4, 4-5 to minimize reference feedthrough to the dependent differential nonlinearity term at the amplifier output in multiplying applications. A power supply bypass output with a maximum magnitude of 0.67 Vog (Vos is capacitor (0.14F in parallel with a 1uF or 104F) is recom- amplifier input-offset voltage). This differential nonlinearity mended across Vpp to DGND. term adds to the R/2R differential nonlinearity. To maintain monotonic operation, it is recommended that amplifier Vos be no greater than 10% of 1 LSB over the temperature range of interest. 2-678 DIGITAL-TO-ANALOG CONVERTERS REV. A
2-680 DIGITAL-TO-ANALOG CONVERTERS