PM7545HPZ

PM7545HPZ ETC2 | Alldatasheet

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MULTIPLYING CMOS D/A CONVERTERS FEATURES The PM-7545 operates from 5 to 15 volt power supplies, offering © Preadjusted Full Scale .... +1 LSB Maximum Gain Error —‘T TL logic compatibility at Vop of 5V and CMOS logic compat- © Small 20-Pin 0.3" Wide DIP Vpp Of 15V, offering TTL logic input compatibility. © PM-7545 TTL Compatible for Vpp = 5V ¢ PM-7645 TTL and 5V CMOS Compatible for Vpp = 15V PIN CONNECTIONS ¢ High ESD Resistance ORDERING INFORMATION} on OY [2] *rs psec th ii hh) er acno FY [5 Veer PACKAGE: 20-PIN ono iB = Yoo 20-PIN EPOXY DIP 2) ae (mst 1 wr m MILITARY? INDUSTRIAL COMMERCIAL "eet ape (P-Suttix) al MAXIMUM TEMPERATURE TEMPERATURE TEMPERATURE 20-PIN HERMETIC DIP_ | { GAINERROR -55°C to -25°C to 0°C to ovo [ey f=) oeotsay (R-Suffix) Has] T= +25°C +125°C +85°C +70°C pes 4 ES pet > pe eee os? ose +1LSB PM7545AR PM7545ER — PM7545GP es Fe Fi}. o02 6 +3LSB PM7545BR PM7545FR — PM7545HP. a FA ves oO +3LSB - - PM7545HPCff +1LSB PM7645AR PM7645ER PM7645GP oo 1) +3LSB PM7645BR PM7645FR — PM7645HP. sebe8 9 pci pe ALM dh Ah 8e3e3 * For devices processed in total compliance to MIL-STD-883, add /883 after BIE TeIrs] xg part number. Consult factory for 883 data sheet. pm7sasHpc |S") 28"" fs] La] Yoo Zz + Burn-inis available on commercial and industrial temperature range parts in os fs] [a] wa < cerdip, plastic dip, and TO-can packages. For ordering information, see 1988 20-PIN PLCC peo fe] fie] cs D Data Book, Section 2 (PC-Sutfix) ee |] fs] sous) | O tt For availability and burn-in information on SO and PLCC packages, ver fa] fa] be: ial contact your local sales office. ola ol 4 BEER & CROSS REFERENCE (oe) pl shade hth i TEMPERATURE fa) F PMI ADI RANGE PM7545AR ‘AD7545GUD FUNCTIONAL DIAGRAM PM7545BR AD7545UD PM7545BR AD7545TD MILITARY 1] PM7545BR AD7545SD ee PM7545ER ‘AD7545GCQ PM7545FR ‘AD7545CQ PM7545FR ‘AD75458Q INDUSTRIAL = | PM7545FR AD7545AQ © our PM7545GP ‘AD7545GLN Vaer 0 MULTIPLYING DAC >| PM7545HP AD7545LN o Aco PM7545HP AD7545KN COMEEEOIN PM7545HP AD7545JN ai Who Von GENERAL DESCRIPTION aol) >» The PM-7545/PM-7645 are 12-bit CMOS multiplying DACs with peene internal data latches. Digital data is input in a 12-bit wide data lormat, while CS and WR control inputs are active low. During is time the latches are transparent allowing digital inputs direct roy ‘Onnection to the DAC. When WR is returned to logic high, the ‘urrent data word in the latch is saved.

PM-7545/PM-7645 12-BIT BUFFERED MULTIPLYING CMUS D/A CUNVENI ENS ; q ABSOLUTE MAXIMUM RATINGS 4EC (Ta = 25°C unless otherwise noted.) iia ted. Vere Veer to DGND . 05 ‘operation at or above this specification is not implied. Exposure to above ARAM nrB: Vrer tO sitieiemeneneeseesient ed MeNeR SIRS A a maximum rating conditions for extended periods may affect device reliability. een i occur on unprotected units from high-energy electrostatic fields. Keep units Oper etn Jemperature Range ° o, in conductive foam at all times until ready to use. Use proper anti-static NALC ‘aput ELECTRICAL CHARACTERISTICS at Vop=+5V, Vrer=+10V, Vour=0V, AGND = DGND =0V; Ta=-55°C to +125°C apply for ay PM-7545AR/BR, Ta=~—25°C to +85°C apply for PM-7545ER/FR, Ta=0°C to +70°C apply for PM-7545GP/HP/HPC, unless otherwise __ noted. 15V operating characteristics are shown on the following pages. ‘np ee EEE==FaE==F=r=ar=lty EEE DE PM-7545A/E/G PM-7545B/F/H — PARAMETER SYMBOL —_ CONDITIONS. MIN TYP MAX MIN TYP MAX UNITS SWI STATIC ACCURACY ie STATIC ACCURACY Resolution N 12 - - 12 = - Bits aN Hewotmtiy a a Relative _ x _ _ = Accurecy INL Ta= Full Temp. Range - +12 +12 LsB i i Differential oni Ta= Full Temp. Range _ _ “| _ _ a em Nonlinearity (Note 1) ‘ Gain Error Ta= 425°C - - H - - +3 i (Notes 2, 3) Gese T, = Full Temp. Range - - 42 - - +4 = = ailNeteeresSh AUN Te TO i Gain Temperature % Coefficient TCG¢s, (Note 4) = +2 +5 - #2 +5 ppm/*C S AGain/ATemperature » soy DC Supply Rejection Ta= 425°C _ - — 0.002 - — 0.002 AGain/AVpp HSS. Tq = Full Temp. Range (4Voo=25%) - 0.004 - — 0,004 we AGabn AN, TRU Te mF a eG Ta = +28°C, WR = CS = OV, _ _ on _ Py Output Leakage \\ All Digital Inputs = OV ~ PA Currenvat Our ue T,= Full Temp. Range AB Versions - - 200 - - 200 E/F/G/H Versions - - 50 = - 50 a rrr EY = SONNE ee DYNAMIC PERFORMANCE a re toe Propagation Delay i Ta= +25°C - = 300 = = 300 ns (Notes 4, 5, 6, 7) tei (QUT Load = 1002, Ceyr = 13pF) - - = - = = (Notes 4.5.6.7) POUT Load ='1009 Cexr= 19PF) Se Ta= Full Temp. Range Current Settling Time ts (To 1/2 LSB) (Note 4) - - 1 - - 1 ro a lour Load = 10022 Ta=+25°C Digital Chi 4 - - - = Hee ° T,= Full Temp. Range ~ oo es nvs : Ver = AGND (Note 4) - - a aaa ieee ee ee = AC Feedthrough Ta= Full Temp. Range ne FT Vaee = 210V, f = 10kHz - 5 - - 5 = mp9 out All Digital Inputs = OV sc See 11-294 8/87, Rev. B1

[PMI PM-7545/PM-7645 12-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTERS ELECTRICAL CHARACTERISTICS at Vop=+5V, Vrer=+10V, Vour=0V, AGND = DGND = OV; Ta=~55°C to +125°C apply for PM-7545AR/BR, Ta=~25°C to +85°C apply for PM-7545ER/FR, Ta = 0°C to +70°C apply for PM-7545GP/HPHPC, unless otherwise noted. 15V operating characteristics are shown on the following pages. (Continued) ———— PM-7545A/E/G PM-7545B/F/H PARAMETER SYMBOL —_ CONDITIONS MIN TYP MAX MIN TYP MAX UNITS REFERENCE INPUT Input Resistance T,= Full Temp. Range A, 7 " 18 7 " 18 (Pin 19 to GND) sad Input Resistance we ANALOG OUTPUTS Se Output Capacitance T,= Full Temp. Range (Note 4) Cour DBO-DB11 = OV, WR = CS = OV - - 70 - - 70 pF Cour DBO-DB11 = Vpp, WR = CS = OV - - 150 - - 150 DIGITAL INPUTS ea igs 2 Input High Voltage Vint - - 24 = - heh Input Low Voltage Vint a> Full Temp; henge as = 08 ~ — 08 ¥ BE Input Current 1 dA eo ~ ~ 4 ~ ~ ' » & parent " T,= Full Temp. Range = = 10 = = 10 ” g Input Capacitance a T,= Full Temp. Range _ _ 5 _ _ ¥ = Zz DB0-DB11, WR, CS IN Vin =0 (Note 4) is oO SWITCHING CHARACTERISTICS See Timing Diagram Oo (Notes 4, 8, 9) ie) Chip Select to t Ta= 425°C 280 200 - 280 200 - 9 Write Setup Time cs Ta= Full Temp. Range 380 270 - 380 270 - ad Spam Sane A EES Chip Select to a _ _ Vite Flokd time ten T, = Full Temp. Range 0 0 = ns < Write Pulse A Ta= 425°C 250 175 - 250 175 = 7 Width = Ta = Full Temp. Range 380 270 zs 380 270 — bi ; Data Setup T= #25°C 140 100 - 140 100 = 2 Time os T,= Full Temp. Range 210 150 - 210 150 = = Data Hold Time ton T,= Full Temp. Range 10 - - 10 = - rn O POWER SUPPLY [ay Sih a ee Ta = Full Temp. Range ‘oo {All Digital Inputs Vig. OF Vins) 2 ~ 2 me Supply Current 2s SSS ] | Tas 425° abt ~ 2 100 = 2 100 loo Ta Full Temp. Range i: 5 00 : pet BA (All Digital Inputs OV oF Vop) Os NOTES: 1. 12-bit monotonic over full temperature range. 6. All digital inputs = OV to Vop; or Vpp to OV. 3. Using internal rg. DAC register loaded with 1111 1111 1111. Gain error is 1nA. adjustable using the circuits of Figures 4 and 5, 8. Sample tested at +25°C to ensure compliance. 4. GUARANTEED and NOT TESTED. 9. Chip select CS must be coincident or present before and/or after write WR; _ | 5. From digital input change to 90% of final analog output that is, tos > twa ton = 0.

[PMI PM-7545/PM-7645 12-BIT BUFFERED MULTIPLYING CMOS D/A CONVEHIEHKS: ELECTRICAL CHARACTERISTICS at Vpp = + 15V, Vaer=+10V, Vour=0V, AGND = DGND = OV; Ta=~55°C to +125°C apply for PM-7545/PM-7645AR/BR, Ta = 25°C to +85°C apply for PM-7545/PM-7645ER/FR, Ta = 0°C to +70°C apply for PM-7545/ PM-7645GP/HP and PM-7545HPC, unless otherwise noted. eee PM-7545A/E/G PM-7545B/F/H PM-7645A/E/G PM-7645B/F/H PARAMETER SYMBOL —_ CONDITIONS MIN TYP MAX MIN TYP MAX UNITS STATIC ACCURACY Resolution N 12 - = 12 - - Bits Relative INL Tq = Full Temp. Range - - +12 - — v2 LsB Accuracy a Differential Ni: Ta= Full Temp. Range _ _ ej _ _ 4 Lse Nonlinearity (Note 1) Gain Error a Ta= 425°C - - 4 - - +3 ies (Notes 2, 3) PSE T,= Full Temp. Range - - +2 - - +4 Gain Temperature Coefficient TCGrs (Note 4) - +2 +5 - #2 +5 ppm/*c AGain/ATemperature DC Supply Rejection Ta=+25°C ¥ - — 0.002 - — 0.002 = % AGAIN/AVoD pss T,= Full Temp. Range (2Vo0=#5%) = 0.004 - - 0.004 bs Output Leakage ; All Digital inputs = OV Pf Current at OUT xe) Ta= Full Temp. Range A/B Versions - ~ 200 ~ - 200 E/F/G/H Versions - - 50 ~ - 50 DYNAMIC PERFORMANCE Propagation Delay Ta= +25°C _ = (Notes 4, 5, 6, 7) too (OUT Load = 1000, Cexr = 13pF) aed = . T,= Full Temp. Range Current Settling Time t, (To 72 LSB) (Note 4) - - 1 - - 1 Hs lour Load = 10022 Ta= 425°C Var = AGND (Note 4) T,= Full Temp. Range aie (lial FT Vper = + 10V, f= 10kHz = 5 = = 5 = mp9 08%; All Digital Inputs = OV REFERENCE INPUT Input Resistance T,= Full Temp. Range Ko (Pin 19 to GND) Rrer Input Resistance 7 " 6 7 i) be ANALOG OUTPUTS Output Capacitance Ta= Full Temp. Range (Note 4) Cour DB0-DB11 = OV, WR = CS =0V - - 60 - - 60 pF Court DBO-DB11 = Vpp, WR = CS = OV - - 120 - - 120 DIGITAL INPUTS | Input High Voltage Vow _ 13.5 - - 13.5 - - 7 fnpub ow Voltage. Vie T,= Full Temp. Range, PM-7545 - - rr ° ~ i Input High Voltage Vine 24 - - 24 = - = : v Input Low Voltage Vine TAS Bullitemip Range PM-TEAS - ~ 08 - - 08 Ta= +25°C i aa 1 = - ; Input t ‘ A iaaial tw T, = Full Temp. Range - - 10 - - 10 “ Input Capacitance T, = Full Temp. Range F DB0—pB11,WA,cS ON Vin = 0 (Note 4) ~ ~ 8 ~ ~ 8 ° a 11-296 8/87, Rev. B1

[PMD PM-7545/PM-7645 12-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTERS ELECTRICAL CHARACTERISTICS at Vop= + 15V, Vrer= +10V, Vout = OV, AGND = DGND = OV; Ta=-55°C to +125°C apply for PM-7545/PM-7645AR/BR, Ta = -25°C to +85°C apply for PM-7545/PM-7645ER/FR, Ta = 0°C to +70°C apply for PM-7545/ pM-7645GP/HP and PM-7545HPC, unless otherwise noted. (Continued) PM-7545A/E/G PM-7545B/F/H PM-7645A/E/G PM-7645B/F/H PARAMETER SYMBOL CONDITIONS. Min TYP MAX MIN TYP) MAX UNITS (PARAMETER Swe, - oro POWER SUPPLY (POWER SUPPER T,= Full Temp. Range = = 2 os at 'oo (All Digital Inputs Vive OF Vin) 2 mt eee in cc Supply Current Th=+25°C - 2 100 = 2 100 loo T,= Full Temp. Range - 5 100 - 5 100 bA {All Digital Inputs OV oF Vpp) a SWITCHING CHARACTERISTICS See Timing Diagram es manaeen (Notes 4, 8, 9) __ [Notes 48 8) n Chip Select to t Ta=+25°C 180 120 = 180 120 - ai iA Write Setup Time cs Ta = Full Temp. Range 200 150 - 200 150 = a _Write Setup Time Cee Chip Select to _ _ _ _ Z 4 <amna te Ta = Full Temp. Range 0 0 ns 3] __ Write Fro Tne Write Pulse t Ta=+25°C 160 100 - 160 100 - 5 Width 7s Ta = Full Temp. Range 240 170 - 240 170 = “ oO _Wieth ee Data Setup f Ta= 425°C 90 60 = 90 60 - 1S) Time os Ta = Full Temp. Range 120 80 i 420 80 = s U0 cc Data Hold Time ton Ta = Full Temp. Range 10 - ~ 10 - - ns ie} itch iad ns edi al nc Ti sg SWITCHING CHARACTERISTICS See Timing Diagram a es (Notes 4, 8, 9) note a Chip Select to j Ta=+25°C 150 - - 150 — = o Write Setup Time cs T= Full Temp. Range 210 = — 210 = = as = Pe cat) Chip Select to Z _ _ _ . Write Hold Time tow Tar Full Temp. Range ° ° = jie q ee Write Pulse A Ta= 425°C 150 - - 150 - = EB Width ba T= Full Temp. Range 210 - — 210 — a se i Data Setup f Ta= 425°C 225 - - 225 - - [a Time ii T, = Full Temp. Range 300 = - 300 = a me NN a a ar Data Hold Time ton Ta = Full Temp. Range 10 - = 10 - one ns te a he a NOTES: ] ] 1. 12-bit monotonic over full temperature range. 6. All digital inputs = OV to Vpp; oF Vpp to OV. 3. Using internal Reg. DAC register loaded with 1111 11111111. Gain error is Ana. adjustable using the circuits of Figures 4 and 5. 8. Sample tested at +25°C to ensure compliance. 4, GUARANTEED and NOT TESTED. 9. Chip select CS must be coincident or present before and/or after write WR; 5. From digital input change to 90% of final analog output. that is, tos = twr, ton O. me o1e7 Aw. Ba

PMD PM-7545/PM-7645 12-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTERS DICE CHARACTERISTICS BO == rs] Oe line ===—Enml Sh) era eS | ee ee ee 4. OUT 11. DB4 SST 2. AGND 12. DB3 [ap em eK | oa 3. DGND 13. DB2 | ita | Tecan leavin | -al | 4. DB11 (MSB) 14. DBI a. [ or 5. DB10 15. DBO (LSB) =| secre escc7|| a 6. DBS 16. CS | = (he a 7. DBB 17. WR | = ots [es a 8. DB7 18. Vop ee =| 9. DBS 19. Vrer i i= = 0 Fre | a _ Lh] | a [ee et For additional DICE ordering information, refer | pot Yi a] ——) to 1988 Data Book, Section 2. po MC ee oe 1 , DIE SIZE 0.102 x 0.100 inch, 10,200 sq. mils (2.59 x 2.54mm, 6.58 sq. mm) WAFER TEST LIMITS at Ta = 25°C, Vpp = +5 or +15V, Ver = +10V, Vout = OV, AGND = DGND = OV. en eee PM-7545G/PM-7645G PARAMETER SYMBOL CONDITIONS uMIT ‘UNITS Relative Accuracy INL Endpoint Linearity Error 22 LSB MAX Differential Nonlinearity DNL 22 LSB MAX Gain Error Grse DAC Latches Loaded with 111111111111 +5 LSB MAX Output Leakage hike a Loaded with 0000 0000 0000 +10 nA MAX Input Resistance Rrer Pad 19 — 75 kQ MIN/kQ. MAX Digital Input Vop=5V ayy. 24 in High Vint Voo = 15V PM-7545 only as vi Digital Input Voo=5V ay, 08 x tow Vin. Voo = 15V PM-7545 only 15 VMA\\ ; Digital input High Vine Vpp = 15V PM-7645 only 24 Vv MIN Digital | it — a “ Vint Vpp = 15V PM-7645 only 08 VMAX Input Current hin Vin = OV oF Vpp +1 uA MAX All Digital Inputs Vin. OF Vine 2 Si ly Ci x pels Givrent ‘oo All Digital Inputs OV or Vop 04 MAMA - DC Supply Rejection (AGain/AVpp) PSS AVpp = 5% 0.002 %/% MA\\ NOTE: oe a ee Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. 11-298 8/87, Rev. B1

{PMI PM-7545/PM-7645 12-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTERS. TYPICAL ELECTRICAL CHARACTERISTICS at Vpp = + 5V or +15V, AGND = DGND = OV, Vper = + 10V, OUT = OV; Ta= 25°C, unless otherwise noted. (Note 1) ponleneiindiaaeeletede il rrr PM-7545G/PM-7645G PARAMETER SYMBOL CONDITIONS TYPICAL UNITS Digital Input Capacitance Cw - ee _ i pF DAC Latches Loaded with 0000 0000 0000 50 Output Capacitance Cour’ Pista occ latte pF DAC Latches Loaded with 111111111111 110 Propagation Delay t Vpo = 15V 140 (Notes 2, 3, 4) po Vpp = 5V_ PM-7545 only 230 ne NOTES: 4. These characteristics are for design guidance only and are not subject to test. 2. From digital input change to 90% of final analog output. 3. OUT load = 1002, Cex = 13pF. 4. CS = WR = 0, DBO to DB11 = OV to Vp oF Vop to OV. n eZ TYPICAL PERFORMANCE CHARACTERISTICS = w FULL-SCALE GAIN ERROR LOGIC THRESHOLD VOLTAGE OUTPUT LEAKAGE CURRENT 5 vs TEMPERATURE vs SUPPLY VOLTAGE vs TEMPERATURE fo) spoon [TT TT] * rl TEL Sr = ————— Bo) SSS] 3 os 3 seoittttittt| 3 Pee COC) SSE zo LA 5 es PA PCr) | EEEEEEEa ¢ Se ee 8 4 2 = = — — —> ee === === rt at SS att | | a ee A aL ETT TTT | j Eras | | Eee EYTI§ TEMPERATURE (°C) Voo SUPPLY VOLTAGE TEMPERATURE (°C) Q SUPPLY CURRENT SUPPLY CURRENT vs TEMPERATURE vs TEMPERATURE 1] PM-7545 PM-7645 === == —— ne ee Fa 7 LEE TE | (oo) «| SSS=Ss== 2. — — a d 3 eee eee 5 — i i eee ee tL YT ‘ STP TT | cot 11 | 4 reneesaruneray rere rey

PM-7545/PM-7645 12-BIT BUFFERED MULTIPLYING CMOS D/A CONVERTERS PARAMETER DEFINITIONS LOGIC INFORMATION RELATIVE ACCURACY WRITE CYCLE TIMING DIAGRAM. Sometimes referred to as endpoint nonlinearity, and is a measure of the maximum deviation from a straight line passing —T= through the endpoints of the DAC transfer function. Relative Yoo Accuracy is measured after the zero and full-scale points have ore been adjusted, and is normally expressed in LSB or as a ty ° percentage of full scale. —_ ke Yoo Warre DIFFERENTIAL NONLINEARITY “9 This is the difference between the measured change and the ‘os ‘OH ideal change between any two adjacent codes. A differential DATAIN (iit oaravauio Yoo nonlinearity of +1 LSB maximum over the full operating tem- Wpe-pett Miu a perature range will ensure that a device is monotonic (the output will increase for an increase in digital code applied). mene eens WRITE MoDE: HOLD MODE CS AND WR LOW, DAC RESPONDS _—EITHER CS OR WR HIGH, DATA BUS GAIN ERROR TO DATA BUS (DB0-DB11) INPUTS. (0B0-0811) IS LOCKED OUT; DAC . HOLDS LAST DATA PRESENT WHEN Gain or full scale error is the amount of output error between the WR OR CS ASSUMED HIGH STATE. ideal output and the actual output. The ideal output is Vaer NOTER ey cots minus 1 LSB. The gain error is adjustable to zero using external Oe Stave = y= 4One résistance: ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF Vpp, wy, TIMING MEASUREMENT REFERENCE Level ts YIM* Vib OUTPUT CAPACITANCE THE PM-7645 USES AN INPUT LOGIC HIGH OF 5 VOLTS. The capacitance from OUT to AGND. PROPAGATION DELAY This is measured from the digital input change to the analog D/A CONVERTER SECTION output current reaching 90% of its final value. FIGURE 1: Simplified D/A Circuit of PM-7545 DIGITAL CHARGE INJECTION “ 7 . e This is a measure of the amount of charge injected to the analog Vaer © output from the digital inputs, when the digital inputs change Py en states. It is the area of the glitch and is specified in nVsec; it is OFrs measured with Vper = AGND. \\ 9 Ry 3Y QiPPiPei? gre gre oF Le eS BURN-IN CIRCUIT di ogto ogo oho (mise) se) +10 pm reeerm.res weer it a Figure 1 shows a simplified circuit of the D/A Converter section ee and Figure 2 gives an approximate equivalent switch circuit. Ris i eres a typically 11kQ. [| Kate: See lo] 3%, The binary-weighted currents are switched between OUT al Lal sono ne and AGND by N-channel switches, thus maintaining a constant pian wat ns current in each ladder leg independent of the switch state. om, ~ ws The capacitance at the OUT terminal, Cour, is code dependent a ee 4 and varies from 70pF (all switches to AGND) to 150pF (all lie | Ro switches to OUT). One of the current switches is shown in Tl io * lis] pbs Figure 2. [| - The input resistance at Ver (Figure 1) is always equal to Rion ir ioe in | WoueAe (RL opis the R/2R ladder characteristics resistance and is equal [| 8 oe Y] Cis Cre te to value “R”). Since the input resistance at the Vper pin § constant, the reference terminal can be driven by a reference voltage or a reference current, ac or dc, of positive or negative polarity. (If a current source is used, a low-temperature coefficient external Reg is recommended to define scale facto") a a eee 11-300 8/87, Rev. B1