PM7226ER

PM7226A AD | Alldatasheet

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FEATURES 300 mil DIP. All digital inputs are TTL/CMOS (5V) compatible. © No Adjustments Required, Total Error +1/2 LSB Max Also, each DAC’s input latch is addressable for easy micro- Over Temperature , processor interface. The on-board output amplifier can each drive Four Voltage Output DACs ona Single Chip up to 5mA from either a single or dual supply. Continued @ Single (+5V to +15V) or Dual Supply © Improved PM-7226A Version Provides ORDERING INFORMATION ' ~ Faster 50ns Write Time, All Temperatures TOTAL EXTENDED - Tested 5V Specifications UNADJUSTED MILITARY INDUSTRIAL = COMMERCIAL ip — Reduced Reference Input Transition Current ——ERROR TEMPERATURE TEMPERATURE TEMPERATURE _ —Epi-CMOS Processing for Improved Latch-up 412LSB = PM7226AR PM7226ER PM7226GP Resistance +1LSB PM7226BR PM7226FR - 41LSB PM7226BRC/883_ PM7226FPC - #1LSB _ PM7226FS - APPLICATIONS 41 LSB - PM7226FP_ =

41 LSB - PM7226AFR -

e@ Automatic Test Equipment +1LSB _ PM7226AFP - ¢ Process and Industrial Control + For dovieosprocossod in wil complet MI-STO-6G3 0aa/B80aerpar e Scientific Instrumentation number. Consult factory for 883 data sheet, e Medical Instrumentation t Burn-in is available on commercial and industrial temperature range parts in e Multichannel Microprocessor Controlled CerDIP and plastic DIP packages. ~ System Calibration tt For availability and burn-in information on SO packages, contact your local — Op Amp Offset and Gain Adjust Sales office — Level and Threshold Setting CROSS REFERENCE GENERAL DESCRIPTION PMI ADI TEMPERATURE RANGE. The PM-7226 contains four 8-bit voltage output CMOS digital- PM7226AR — MIL to-analog converters ina single chip. Also incorporated into this —PM7226BR AD T226TQ chip are four input latches and interface control logic. PM7226ER _ IND . PM7226FR ‘AD72268Q The four latches are under control of one write and two address raat signals and are fed f it data bus. It allows th paveser re 30 ignals and are fed from a common 8-bit data bus. It allows the PM7226FPC AD7228KP COM PM-7226 to be packaged into a narrow space-saving 20-pin, PM7226FP ‘AD7226KN FUNCTIONAL DIAGRAM ga er 91a" peer te [ wc [Yeo | S oven? Fe —=—7 | 7 g G b\\ss Saco d'vano REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its which may result from ts use, No license fs granted by Implication or Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6677 otherwise under any patent or patent rights of Analog Devices. Telex: 924491 Cable: ANALOG NORWOODMASS

PIN CONNECTIONS GENERAL DESCRIPTION Continued The PM-7226’s compact size, low power, and economical cost perchannel, make it attractive for applications requiring multiple Vour® Gy [20] Vour® D/A converters without sacrificing circuit board space. System VourA I 173] VourD reliability is also increased due to reduced part count. For higher 20-PIN iritalta DIP Vss G3] {78} Voo channel output systems the PM-7226A can be connected with (R-Suffix) Vrer Ko the DAC-8426 to provide a complete eight or higher channel 20-PIN EPOXY DIP AGND [5] AL output D/A system with an internal +10V reference in only two IC (P-Suffix) ano [ef wR packages. DB, (MSB) [7] [fa] OB (LSB) 20-PIN SOL DB, [2] fia] OB, PMI's advanced oxide-isolated, silicon-gate, CMOS process (S-Suffix) 08s [iz] DB. allows the PM-7226’s analog and digital circuitry to be DB, [io [7] DBs manufactured on the same chip. This, coupled with PMI’s highly stable thin-film R-2R resistor ladder, aids in matching and 2 5 % Se temperature tracking between DACs. ialeeleted PM-7226FPC The PM-7226 and the PM-7226A are improved replacements for Veer (4 (sieI edb y 20-CONTACT PLCC. the AD7226. sano ae (PC-Suffix) Formilitary temperature range PM-7226A, contact factory for 883 Dano [6] fre] Ay PM-7226BRC/883C data sheet. DB; (MSB) bs] WA 20-CONTACT LCC DB [2] [i] D8 (188) (RC-Suffix) fo} Folfr} 2} 53) deeded Specifications apply for DUAL or SINGLE SUPPLY, unless otherwise specified. ELECTRICAL CHARACTERISTICS: DUAL SUPPLY: Vip = +11.4V10+16.5V; Veg =-5V 410%; AGND = DGND =0V; Vag, =+2V t0 (Vpp -4V). SINGLE SUPPLY: V,, = +15V +5%; Vg = AGND = DGND = OV; V,,-, = +10V; unless otherwise specified. T, = 55°C to+125°C apply for PM-7226AR/BR; T, =—40°C to +85°C apply for PM-7226ER/ERV/EP/EPC/FS/AFR/AFP; T, = 0°C to +70°C apply for PM-7226GP. All specifications apply for DACs A, B, C, and D. PM-7226A/PM-7226 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY Resolution N 8 - - Bits Total Unadjusted Error PM-7226A/E/G - - #12 (Note 1) TUE pm-7226B/F/H/AF ‘NOte7) - - Py tsB Relative Accuracy INL COC EUAR : > “ LsB Differential Nonlinearity PM-7226N/E/G - - 412 (Note 2) ONL PM-7226B/F/H/AF - - 4 ise Full-Scale Error Grice vcestshe em = = e LsB Full-Scale T Coefficient ule ae emperature Coefficient oq _ 1 420 ppmec DUAL SUPPLY PM-7226N/E/G - - Py PM-7226B/F/H/AF - - 420 Zero Code Error Vase TT oe mv SINGLE SUPPLY PM-7226A/E/G - - 410 PM-7226B/F/H/AF - - #20 Zero Code Error ‘Temperature Coefficient TCV, DUAL SUPPLY ONLY - 410 - ed (Note 4) _ REV. D

Specifications apply for DUAL or SINGLE SUPPLY, unless otherwise specified. ELECTRICAL CHARACTERISTICS: DUAL SUPPLY: Vpp=+11.4V to +16.5V; V., =-5V +10%; AGND = DGND = OV; Vac, =+2V 10 (Vpp -4V). SINGLE SUPPLY: Vp, = +15V 5%; Va. = AGND = DGND = OV; Var, = +10V; unless otherwise specified. T, = 55°C to +125°C apply for PM-7226AR/BR; T,=—40°C to +85°C apply for PM-7226ER/ER/FP/FPC/FS/AFR/AFP; T, = 0°C to +70°C apply for PM-7226GP. All specifications apply for DACs A, B, C, and D. Continued : PM-7226A/PM-7226 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFERENCE INPUT Tnput Resistance Pace 2 4 = 1a Input Capacitance ©. Digital inputs =allOs 65 = = oF (Note 4) eal Digital Inputs = all 1s - - 300 DIGITAL INPUTS Digital Inputs High Vow 24 = = v Digital Inputs Low Vin = = 08 v PowensupuesOCOC“—SCSCSC“‘(SSNSNSCNSCNSCSCSCS Poste Supp Current lop - 5 2 7A eons) ey Current leg DUAL SUPPLY ONLY, Ve, =-5V - 4 10 mA Power Dissipation Poiss Vop = +12V, Veg = OV - 72 144 mw “Power Supply Sensitviy =Pggsssti«C me OSSSSOSC~—<CS~si‘“‘“SCSCSSSC SC Vour Slew Rate (Note 4) SR 25 4 = Vins “Bite or Negasve 4 - 3 5 us (Notes 4, 5) Digital Crosstalk (Note 4) Q = 10 = nvs “Minimum LoadResistanco Ry Ve OVO”S™*~<“—~sSOSstSSSCSCi<— ‘SWITCHING CHARACTERISTICS (Note 4) ‘Address to Write Set-Up Time hs 0 2 = ne ‘Address to Write Hold Time tw ° = = ns Data Valid to Write Set-Up Time os acon ° > - ns Data Valid to Write Hold Time tow 10 - - ns Write Pulse Width twa Peeyeee n 8 - : ns NOTES: 2 Altdeviees guaranteed manotonicoverthe filperang temperature ange. © Vner= +10V:towhere ouput sets to 12 LSB 3. Vg ~4V is the maximum reference voltage for the above specifications. Sm Reed Outputs unloaded, 4, Guaranteed by design and not subject to production test. ‘oo REV. D 3

ELECTRICAL CHARACTERISTICS : +5V Supply Operation at Vp, = +5V 25%, Veg = 0 0r-5V, AGND = DGND = OV, Vage = +1.25V, unless otherwise noted. T, =—40°C to +85°C applies for PM-7226AFR/FP. All specifications apply for DACs A, B, C, and D. PM-7226A ONLY PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Resolution N 8 - = Bits Differential Nonlinearity DNL ‘Applies to Codes 2 through 255 = - Ht LsB Full-Scale Error Grse - - 4 LsB ee rVolons Rene Vacr Vour< pp -3-5¥) 12 1.25 13 v Reference Input Resistance Race Digital Inputs all 1s 2 - - ka Reference Input Capacitance Caer Digital Inputs all 18 = = 300 pF DIGITAL INPUTS (All specifications the same as for V,, = +12V supplies) DYNAMIC PERFORMANCE (All specifications are the same as for V,. = +12V supplies.) Positive Supply Current loo - 35 12 mA Negative Supply Current Is Vag =~5V only = 35 10 mA Power Dissipation Poiss Vgg=0V - 175 60 mw SWITCHING CHARACTERISTICS Address-to-Write Setup Time as ° - - ns Address-to-Write Hold Time tan 20 - = ns Data Valid-to-Write Setup Time bs 180 - = ns Data Valid-to-Write Hold Time bs 20 - = ns Write Pulse Width twa 120 - - ns 4 REV. D

(Mae ae Serr ‘ Fe . i eS ELS SSS] are ic SRA r VourB 1. DB. of 1 11. = ol 3 se a os 3. Veg 13. DB, aya im. SSSS ES is 4. Vers 14. DB, (LSB) = =e 5. AGND 15. WR Ir i Te 6. DGND 16 A 5a i leo 7. DB, (MSB) 47. A 6 ‘i pS ee 8. DB, 18. V, =a els Ele. 9. DB, 19. Vou, le Fl = i P ieyess 10, DB, 20. Voyre ecueottey | tela ta? (MEd ‘CU cNTR an Substrate (die backside) is internally connected to V,,. pADPR | Pier oie sap DIE SIZE 0.129 x 0.152 inch, 19,608 sq. mils (3.28 x 3.86 mm, 12.65 sq. mm) Specifications apply for DUAL or SINGLE SUPPLY, unless otherwise specified. WAFER TEST LIMITS: DUAL SUPPLY: Vop =+11.4V to +16.5V; Veg =-5V +10%; AGND = DGND = OV; V.-, = +2V to (Vp, —4V). SINGLE SUPPLY: V, p = +15V +5%; V., = AGND = DGND = OV; Vag = +10V; unless otherwise specified. T, = +25°C. All specifi- cations apply for DAGs A, B, C, D. PM-7226BGC PARAMETER SYMBOL CONDITIONS LIMITS UNITS Total Unadjusted Error TUE Voy = +15V # LSB MAX Relative Accuracy INL a LSB MAX Differential Nonlinearity DNL FS) LSB MAX Full-Scale Error Gece “ LSB MAX Zero Code Error Vase +420 mv MSX Reference Input Voltage Range Veer 2.10 (Vp9 ~4V) v Reference Input Resistance Bw 2 KOMIN Digital inputs High Von 24 VMIN Digital Inputs Low Vine 08 VMAX Digital input Current hy Vyy=0V OF Voy, a HAMAX Positive Supply Current lop Vin = Vane OF Vang 12 mAMAX Negative Supply Current Is Vin=Viue OF lau: Veg <5 10 mAMAX NOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. REV. D 5

ABSOLUTE MAXIMUM RATINGS (T, = +25°C, unless Packace TRE ~—~*~« Nowe) SCC otherwise noted) a ee ee Vpp to AGND of DGND ...ssssesssssesseessnsesnseesseeees O.3V, +17V 20-Pin Hermetic DIP (R) 76 "1 SC Ves to AGND of DGND.vnsccncnnnsnnssnniiune TV, Vp _20-Pin Paste DIP (P) oa a “cw Vo t0 Vig ssssssssossssersescensnsnssosensssnsesesssssssnnsessssssess “OSV, +24V 20-Contact LCC (RC, TC) 88 33 sc AGND Of DGND wsccsvercsnnrccinrnensnsee —0.3V, Vo 20-Pin SOL (S) 88 25 °C Veer tO AGND u..sssssssseusnntisiatisnusisnsnn 0.3V,Vpp --NOTESS =SS*=C<CS~S~C<St Voy to AGND (Note 1) 1. Outputs may be shortened to any terminal provided the package power dissi- Operating Temperature pation is not exceeded. Typical output short-circuit current to AGND is SOmA. 4 550 0 2, The digitalinputs are diode-protected; however, permanent damage may occur ARIBR Versions JAE RIA Versions. Seo Mee ‘on unconnected inputs from high-energy electrostatic fields. Keep device in Junction Temperature ..r.scsccsssessssccesessnnnseeceesnnnneesesesees $150°C 4. Stresses above those listed under “Absolute Maximum Ratings” may cause ps Storage Temperature “65°C to +150°C permanent damage to the device. This is a stress rating only and functional Lead T ture (Soldering 10 000) y300°¢ operation at or above this specification is not implied. Exposure to above 5. @,,isspecified orworstcase mounting conditions, ,¢.,0,,is specified for device in’socket for CerDIP, P-DIP, and LCC packages; @,, |S specified for device soldered to printed circuit board for SOL and PLCC packages. BURN-IN CIRCUIT +15V ? Dy q 0.01pF 10a 11 Vour8 Voure | 20 4.7uF x 4 = oor —24 Yourk Vour |19 ta a Vo AN 3] Vss Voo | 18 © +10V ss0v0 4] Veer ty [a7 La | AGN os ne. a | «| ocx aA a B,s8) DBs) Rp eH |e | 05, os, | 13] [ o| DBs DB, | 12 {10 | va, os, [1] -6- REV. D

TYPICAL PERFORMANCE CHARACTERISTICS TOTAL UNADJUSTED ERROR CHANNEL-TO-CHANNEL vs DIGITAL INPUT MATCHING (DACs A, B, C, D Ta = 55°C, 425°C, +125°C SUPERIMPOSED) (ALL SUPERIMPOSED) RELATIVE ACCURACY Vs Vper 1.0 pfs y-fee ty , ese etl te | Ea 88 “oo e-Lt TTT TTT @ “ht 3 “eee Taree voo-ev | | | 3 fve--av [| | [it a a a 28 Mega SM Maer t250 Tg St waliapac! © ot N Lwin NI | «HINA ogi ogg Es ° Han Ag Fi 04 ae I = z 06 - PEEEEEEEH F-EE-EHHH “se © 32 64 96 128 160 192 224 256 O© 32 64 96 128 160 192 224 256 ar) 2 4 6 8 10 12 #14 DIGITALINPUT CODE (DECIMAL) DIGITAL INPUT CODE (DECIMAL) Ver (VOLTS) DIFFERENTIAL NONLINEARITY ZERO CODE ERROR SUPPLY CURRENT \\ VS VaeF vs TEMPERATURE vs TEMPERATURE ° soe EE "Ty a eee] eo eo ee + > 25 i = «pee eee og SENEEEERE SL NAfeserer a ee ae a ce Zo tt Tt WN 8 oe Sor 8 LT TT TT i eS Coo B oe Vas sev ys a a a 4 = ae ESSSS=2c5 [EEF etc 9) 89 2 4 6 8 10 12 14 "075750 25 02550 75 100 125 150 “875-50 25025 5075 100 125 Vrer (VOLTS) TEMPERATURE (°C) TEMPERATURE (°C) REFERENCE INPUT CURRENT Vout NOISE DENSITY BROADBAND NOISE AND CAPACITANCE vs CODE 100 vs FREQUENCY (DC TO 200kHz) © ooo: LLU EET Tn Til O 32 64 96 128 160 192 224 256 q 10 400 1k 40k 100k CODE FREQUENCY (Hz) REV. D -7-

The amplifier's output stage uses an intrinsic NPN bipolar tran- With a dual supply, the current source is still in its high imped- sistor. This transistor provides a low impedance, high output ance (saturation) state when the output is at OV. Therefore, the current capability using a small part of the chip area. The tran- current source has 5V of bias in dual supply operation. When sistor is derived from the P-well and the substrate. The emitter Vgg = OV, however, the current sink capability is reduced as the of this NPN transistor is loaded with a 450nA NMOS current output voltage approaches OV; the current source is coming out source referenced to Vg. This allows 450A to be sunk to the . of its saturation region and starts appearing resistive. negative supply allowing the amplifiers output to go directly to The amplifier's current limiting and butfering abilities are achieved ground. by using an NMOS transistor and a series resistor. The transis- A simplified circuit of the output amplifier is shown in Figure 3. tor is configured as a source follower and is driving the resistor Note how the current source is connected between the parasitic and NPN output transistor. This is also shown in Figure 3. NPN output transistors emitter and Vag, Figure 4 shows atypi- Figure § displays the combined amplifier source and sink capa- cal plot o he Rint coven sink capabllity versus output volt- bility to the point of current limiting. This plot was made with the age; note that @ is for a dual and single supply operation. Let s digital inputs set at zero code. Note that the maximum source id acloser look at what happens to its behavior by referring to current available is dependent on the V,,, supply voltage. ‘igure 4. 200 _ Yoo 2 wl al _| Z 150 SOURCE Se E |_| CURRENT a gm) Sear an 5 ° 7 TI coun INPUT Ke eo | oe ese HA Vg =-5V ourpur 5 -02 | DIGITALIN=0 a d ss aoe, |_| a a a So 1 } | 450pA SOURCE Y ey ae a | 2 4 ° 1 2 Vour - OUTPUT VOLTAGE (VOLTS) Vss FIGURE 5: ink-' . FIGURE 3: Amplifier Output Stage IE 5: Output Sink-Source Current vs. Voltage The amplifier's internal gain stages were designed so that they maintain good gain over its common-mode range; the objective 700 was to maintain good offset performance over the specified volt- = 600 Bo iey LITT] age range. The amplifier's offset voltage is laser-trimmed during zg I | ILE E Ee the manufacturing process; this eliminates offset trimming by the ¥ 800} ve,--sv| ETE user in most applications. The effect of amplifier offset is included a in the data sheet under "total unadjusted error” specification. © soolfvss-ov—+}+ 1 1 TT | o | PEELE DIGITAL SECTION g The digital inputs are CMOS inverters. They were designed such 300

3 HET PEELE that TTL and CMOS (5V) input levels are converted into internal

2 200 CMOS logic levels; they are used to drive the internal circuitry. A te) EET ELLE simple 5V regulator is used to ensure the high-speed timing. “LETT TT o123 45 67 8 9 10 Vour (VOLTS) FIGURE 4: DAC Output Current Sink REV. D 3

APPLICATIONS INFORMATION Although the PM-7226 can operate with either a single or dual POWER SUPPLY power supply, improved zero-code error can be obtained by using The PM-7226 data sheet is specified with dual and single power dual supplies. supply conditions. The dual supply specifications are specified DYNAMIC PERFORMANCE with a positive supply (V_p) range of +11.4V to +16.5V, and a The PM-7226's settling time is limited by the internal amplifier's negative supply (Vgg) Of -5V. The specified reference voltage + slew rate as shown in Figure 10. Depicted is the dynamic re- (Vac) under these conditions range from +2V to V.. —4V. For sponse for a positive full-scale output voltage swing. Figure 10c those applications requiring +10V at the output (V_-,=+10V), shows the expanded view with no evidence of signal overshoot Vpp must be +14V minimum to meet data sheet limits. or ringing; note that the typical settling time is 1.85ys. An ex- The specified V,_, for the single supply specifications is +10V. panded vrigt of re negative full-scale oun vonage swing J The Vier Voltage range for both dual and single power supply thety ical cottlin time is 26 aa overshoot ata minimum, an applications must be observed if the PM-7226's multiplying ca- typ 9 “OHS. pabilities are to be preserved. a) LARGE SIGNAL 2. feet 2, Cae 5 to A] 52 az E 3g | i | | Vag 3§ Pad TIME (2us/D1V) TIME (2us/DIV) Ves =-5V Vos = 0V b) SETTLING TIME RESPONSE (NEGATIVE TRANSITION) 5 ——— 7 5 v Hl 5 vy g i > i > | 3s | 3s SE : | Se | i i

8 BE d | ut 8 BE i cc

TIME (1ys/DIV) TIME (1ps/DIV) Veg =-SV Vos = OV c) SETTLING TIME RESPONSE (POSITIVE TRANSITION) 5 - 2$ ‘TEST CONDITIONS, ALL PHOTOS: 3° Vop = +18V a Veer = +10V R, =2kO > DIGITAL INPUT SEQUENCE 0,255, 0 sé TIME (1ps/DIV) Vos = 0V FIGURE 10: Dynamic Response REV. D -11-

AGND BIASING MULTIPLYING OPERATION Some applications may require the DAC's output voltage level Good multiplying capabilities are realized with the PM-7226 if to be offset above ground. This is easily accomplished with the the reference signal level is kept within +2V and V_, —4V. The PM-7226; the desired DC offset voltage can be applied to the maximum input signal level is +12.5V for a Vp, supply voltage of AGND pin. Raising AGND above DGND affects all four DACs +16.5V; however, it is recommended that V,,, = +15V +5% and because AGND is common to them. The digital input voltage _the AC voltage swing vary from +2V to +11V. Phe signal must be levels are not affected. Figure 11 shows the circuit configuration AC coupled and biased up with a voltage divider as shown in and Figure 12 shows the relative accuracy with AGND biased at Figure 13. A buffer amplifier should be used to ensure that the OV, +2V, and+5V. Thegraph shows both a dual and single supply DAC's V,,-- impedance (the R-2R ladder input resistance varies operation with V_) at+15V. Itis important to remember that other trom 2kQ to infinity) does not load the resistor divider. parameters degrade more pronouncedly than relative accuracy. The V... small-signal fr IB bandwidth) f REF ig) fequency response (3d! indwidth) for Note, Vpp and Vg must be referenced to DGND. the PN7226 is typically 1.5MHz. Its small-signal harmonic The DAC's output voltage expression under this condition is: distortion is less than -57dB at 1kHz and -55dB at 100kHz. Voyr = AGND bias + Vj, x D/256 where AGND bias is the voltage level above DGND and D is the digital input code integer number that is between 0 and 255. 415V Ry

9 Dac 0 Vour Ac 4 > oVour

‘SIGNAL Ss 6 Gg é— Re 2" i 4 t FIGURE 11: AGND Biasing Scheme FIGURE 13: AC Signal Input Scheme 0.40 | 1.0 w= fees SEE otras DEEL = oo = +" _ O75 F Vpp = 45V cy ae A A a 0 Vagr = +1V" Fa oo 5 [| tye] oa Fr 2 0.25 gon Shee aE | Vsg=-8V-T tJ ia Piscensscoo ACCEL ee ae 5 sof tment?” | | | Bo ee el

004 EE ee WP avd 275

Aa oo ao Lt] | TT T | o 123 45 6 7 8 9 10 0 32 64 96 128 160 192 224 256 Veer (VOLTS) DIGITAL INPUT CODE (DECIMAL) FIGURE 12: Relative Accuracy vs. Vig-(AGND=OV, +2V,+5V) FIGURE 14: Relative Accuracy with Single +5V Operation -12- REV. D

+5V SINGLE SUPPLY OPERATION BASIC APPLICATIONS Operation of the improved PM-7226A at a +5V V,,, is guaran- UNIPOLAR OPERATION teed in the separate specification table. Linearity performance Figure 15 shows the PM-7226 configured in the unipolar mode specified by DNLis still maintained within+1 LSB maximum. DNL of operation; the analog output voltage is of a single positive and offset performance isimproved with a-SV supply, seegraph ——_pojarity only. Table 2 shows the code for this mode of operation. in Typical Performance Characteristics section. Input reference voltages must be limited to 1.3V maximum with V,,, = 5V. Micro- processor interface timing is slower, but guaranteed to the values provided. Vrer Voo GENERAL GROUND MANAGEMENT 4 18 Ground management implies the placement of a system's ana- log and digital ground currents. Analog and digital ground returns are a source of system errors and must be addressed. Re- Ne member, the analog signal is only as good as the integrity of its > 2g VourA analog ground. Different ground management techniques are used depending i us) on the size and type of the overall system. Proper grounding t) DB) techniques require tying the analog and digital grounds together 14] (LSB) UN | 1 at the DAC's socket, and each ground return line be brought out 0 Vour8 separately to their respective power supply grounds. Tying the grounds together at the device socket and at the power supplies, or at more than one location, can create ground loops. This causes noisy digital ground currents to flow through the analog UN | 20 ground paths destroying the analog's ground integrity. Voltage Ea © Youre differences of millivolts (and hundreds of millivolts in some sys- tems) can be found in these ground paths. Other sources of system errors can be introduced by the prod- | WA UN uctof ground noise currents and ground bus impedances. Using 18] ay Ea 19 5 Vourd large conductors or ground planes between the converter and O77] Ay power supplies will minimize the ground impedances and thus, Vss AGND GND reduce system errors. 3 c | 5 If system requirements dictate the use of common return lines to ° the power supplies for both the analog and digital grounds, the = converter should then be placed as close to the power supplies as possible. FIGURE 15: Unipolar Operation POWER SUPPLY DECOUPLING Power supply decoupling capacitors are important to suppress TABLE 2: Unipolar Code Table (Refer to Figure 15) oscillations and noise transients from entering the system. Noise DAC DATAINPUT ~~ANALOGOUTPUT. transients are generated from digital switching or switching power MSB LSB (DAC A, B, C, or D) supplies; and oscillations on the power supply lines are caused ee by lead inductances combined with stray capacitance. These vy 255, transients and oscillations can also cause system errors. rrrrr pigs + NREF Fl Bypassing the PM-7226 at the socket with only high frequency decoupling capacitors may not remove these oscillations. AnLC 10000001 +VREF (2) tank circuit can be formed by the stray power lead inductance 256 and capacitance. These reactive components can allow oscilla- 128) +Vrer tions to occur during a digital current step. It is necessary, then, 10000000 +VREF (2) => to remove or lower the tank's resonant frequency. The easiest a methodis to parallel the high frequency decoupling capacitor with 127 a low frequency capacitor. o114%44141441 +VREF (2) The high frequency decoupling capacitors should be ceramic and ——---!————————————- in the range of 0.01,1F; the low frequency decoupling capacitors 00000001 +VREF (5) should be tantalum and between 1 to 10uF as close as possible 256 to the device socket. 00000000 ov REV. D -13-

The table shows that there is no signal inversion between +Vpre TABLE 3: Bipolar Code Table (Refer to Figure 16) and Voy7- Note that the analog output voltage is equal toV, DAC DATA INP IALOG OUTPUT multiphed by the digital input code (hence, multiplying DAC). MSB Yon (ack, B,C er) The expression for 1 LSB and Voy); is: ay eo

1 LSB = Voge X 2°, Of Vege x 1/256 11449994 +Veer (127)

Vour= Vper * D258, 10000001 +VRer () where Dis the digital input integer between 0 and 255. SSS 10000000 ov o11t4444 Ver (35) Vaer Yoo 128 4 Pn. 00000001 128 ne 00000000 “Veer (128) « Veer IN | Vou 128 © Vour i SSSSSSSSSseeeeFeFeFeS An BIPOLAR OPERATION 7] a Figure 16 illustrates the PM-7226 in the bipolar mode of opera- v) OI ng tion. This mode allows the output voltage to swing plus or minus tal te UN | © Vour8 and is determined by the digital input code; this can be seen in > Table 3. This configuration requires an external amplifier andtwo A resistors for each channel requiring bipolar operation. ai The output voltage expression is given by: I] ng Vour = ((1 + Ry/R,) x D/256 x Vac) —(RY/R, X Vee) moe © Voure where Dis the digital input code integer between 0 and 255. IfR, =R,, then V,,,, becomes: Ry 2! ‘ouT Ne Voyr = (2X D/256 ~ 1) X Vee o| wa LN] To keep gain and offset errors at a minimum, R, and R, should 318 a, Ne © Vout be matched to +0.1% and track over the operating temperature ot ho [oe | range of interest. Vss AGND__DGNO 3 [sé FIGURE 16: Bipolar Operation 14 REV. D

+10V +15V 4 18 R Var Vop PM-7226 . R vwo ial

2 Po | © Yours

[oe | ? 0 -15V 7| pay I R (MSB) R mh ob fT 14] (LSB) + Pe Ry © Vour2 i a 1 o -15V R W I epi © -15V 15} A ° WR R 017 ho 10 Fe RY 0 Vours = eee Vss AGND__DGNO. © -15V 3 6

0 Ef “Ry = 500KQ; Re = 1kO; Rg = 330k0; R4 = 1MO

FIGURE 19: Alternate Offset Adjust (See Text) In order to have a plus or minus (+) offset adjust control, the cur- Some op amps are not provided with offset adjustment pins, rentthrough R, must equal the current through R, when the PM- in these cases, the circuit configuration of Figure 19 can be 7226 is at half scale, binary code = 1000 0000. used. Again, the current through resistor R, must equal the The resistor values (R,, R,) should be chosen to give the re- current through R, with the PM-7226 at half scale, digital code = quired offset adjustment range desired. Lower values provide a 1000 0000. larger range; however, resolution will be sacrificed. Reversing With the circuit components shown, the maximum adjustment connections at pins 1 and 5 (of the op amp) will reverse the off- range is t5mV. Incremental adjustment resolution is 391V per set adjustment direction. bit. -16- REV. D

“ST | ompaoe | I Hs IE — Veer Yoo ° I P=] tet DACA > Hea o wNoow 2 ; | es) | | cy anaes DACB > <r -_ > | moo WN . | cit> ovmaoows 15] <r o18] A, | 017] Ay ——-—-! UN [wecwp.aos | [oe | | DACD > > © WINDOW 5 Ves AGND __DGND ° 3 5 6 > I V = V Led) FIGURE 20: Non-Overlapping Window Comparator STAIRCASE WINDOW COMPARATOR upper limit of window 2, the lower limit being Voy;B, etc. These Many applications need to determine whether voltage levels limits (window size) can be microprocessor controlled. The rela- are within predetermined limits. Some requirements are for non- tionship Vice > Vregr > AGND apply. overlapping windows and others for overlapping windows. More versatility can be obtained by connecting the output of DAC reapoctvely configurations are shown in Figures 20 and 21, B WoynD) te Vege this allows Var (which i common to allfour . ‘S) to be under microprocessor control (see Programmable The non-overlapping circuit uses one PM-7226 and ten com- DAC Reference Voltage section). This, however, reduces the parators; this allows for five voltage windows. These windows windows to four. Overlapping windows (Figure 21) will reduce range between V,-, and analog ground. Figure 20 shows that the windows to three. the first window is between Vier aNd Voy7A. Voy7A is also the REV. D -17-

? Ro fo 4 a 1 | Nox, ! Vow 7a ne In| Ea | $R : ART — ca a4 o 5] WA —-—-4 off} a, Tow F Se [se] Dols RSF gy 7 > voo= Vv ie__l FIGURE 21: Overlapping Window Comparator PROGRAMMABLE DAC REFERENCE VOLTAGE With the PM-7226's flexibility, one of the internal DACs can be > used to control Vpe- for all of the DACs, and under micropro- cessor control. od Yoo PM-7226 The circuit configuration is shown in Figure 22. The relationship Ne Of Vag to V,,, is dependent upon the digital code and the ratio of Ea R, and R,, and is given by: Hos, mo > Veer = [(1 + R)AR x D/256)] x Viy o) where R = R,/R, (Figure 22) 14] (188) ne 1 D = Digital Input Code | ee | Table 4 shows V,.-, for various ratios of R, and R,. [ oe | in 26 | sooner TABLE 4: Vice VS. R,, R, (see Figure 22) COMPONENTS R,,R, DIGITAL INPUT CODE Vaer ota IN ° 36 R,=R, 0000 0000 (0/256) Vin ola | o> | te R,=R, 1000 0000 (128/256) 1.3Viy Vss AGND __DGNO rs EJ G R, =R, 11111111 (255/256) Vin 8 E R,=3R, 0000 0000 (0/256) 4Viy R, =3R, 1000 0000 (128/256) 1.6V,y FIGURE 22: Programmable DAC Reference R,=3R, 1111 1111 (255/256) Vin -18- REV. D

Ais Ass| ‘ADDRESS BUS "ADDRESS BUS “L_| . “" = * LOGIC | 6502 A eros ty P7228 cane " pM-7226 = ADDRESS a a

8212 DB; 087

PG = o ° D7/AD7 DI DATA BUS/ADDRESS Bo Do/ADg | — FIGURE 28: PM-7226 to 6502 INTERFACE (Simplified FIGURE 25: PM-7226 to 8085A INTERFACE (Simplified circuit, only lines of interest are shown.) circuit, only lines of interest are shown.) As As ADDRESS BUS ADDRESS BUS A “ Po eam) * ADDRESS At pM.7006 (Sarre) 8 “ puereas Wa ADDRESS Wa —— Wa DECODE P wR Rw 17 Wa

087 DTACK

D DATABUS DBs]

2 DATABUS

FIGURE 26: PM-7226 to Z-80 INTERFACE (Simplified circuit, only lines of interest are shown.) FIGURE 29: PM-7226 to 68000 INTERFACE (Simplified circuit, only lines of interest are shown.) As ADDRESS BUS . Any combination of wave shapes may be simultaneously gener- ho ated. It only requires the functions to be programmed into the PROMonan interlace basis. The output amplitudes can also be — fo microprocessor controlled; see previous section on Program- Rw ADDRESS |, Ay mable DAC Reference Voltage.

6809 DECODE tT»

(@-BITpP) PM-7226 MICROPROCESSOR INTERFACING c BD; WR Interfacing the PM-7226 to a microprocessor is simplified by virtue of its loading structure simplicity. Data is loaded into the DAC by 087 use of only three control lines, the write strobe (WR) and two DAC < Bp selection control signals (A), A,). 8 0B; Figures 25 through 29 show various popular microprocessor z DB DATABUS interface configurations. a Ea FIGURE 27: PM-7226 to 6809 INTERFACE (Simplified circuit, only lines of interest are shown.) -20- REV. D