PM7080A STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 23
Technical content
Datasheet sections
- 1 Typical application and efficiency
- 2 Pins description
- 3 Absolute maximum ratings
- 3.1 Recommended operating conditions
- 4 Electrical characteristics
- 5 Functional block and PWM timing diagrams
- 6 Detailed operational description
- 6.1 PWM input and tri-state function
- 6.2 Temperature sensing and fault reporting (TMON/FAULT)
- 6.3 Voltage input (VIN)
- 6.4 Switch node (sw and phase)
- 6.5 Ground connections (AGND and PGND)
- 6.6 Control and drive supply voltage input (VDRV, VCC)
- 6.7 Bootstrap circuit (BOOT)
- 6.8 Current sensing and report IMON
- 6.9 IMON_REF
- 6.10 Shoot through protection and adaptive dead time
- 6.11 Under voltage lockout (UVLO)
- 6.12 Advanced fault report
- 7 PM7080A electrical curves
- 8 PCB layout recommendations
- 9 Package information
- 9.1 QFN 5x6 41L package information
Features
- Optimized MOSFET switching performance with integrated Schottky diode in LS MOSFET
- 110 A peak and 60 A continuous current capability
- High frequency operation up to 1.5 MHz
- 3.3 V PWM logic with tri-state and hold-off
- PWM minimum controllable on-time of 30 ns
- Low PWM propagation delay (< 20 ns)
- Current sense monitor output 5mV/A (I MON) and 2% accuracy
- Temperature monitor output 8mV/C (T MON) and 2% accuracy
- Fault reporting and mapping through both I MON and TMON – High Side MOSFET Short – Accurate over-current protection – Over-temperature protection – Under-voltage lockout for V IN/VCC/VDRV/BOOT
- Thermally enhanced QFN 5x6 41L package Application
- High performance synchronous buck converter – Intel, AMD CPU power supply – GPU, ASIC and AI chip power supply – Cloud computing and AI
- DC/DC converters
- Telecom and networking
Description
The PM7080A is an integrated power stage solution optimized for synchronous buck applications to offer high current, high efficiency, and high power density solution. to deliver above 110 A per phase peak current. The internal power MOSFETs utilize state-of-the-art technology that delivers industry benchmark performance to significantly reduce switching and conduction losses. The PM7080A incorporates an advanced MOSFET gate driver IC that features high current diving capability, adaptive dead-time control and integrated bootstrap switch to enable high frequency switching up to 1.5MHz. The device incorporates an innovative inductor current emulation algorithm with thermal compensation to achieve best-in-class reporting accuracy. It also includes a temperature monitor function with 2% accuracy. The PM7080A provides comprehensive protection features, including cycle-by-cycle over-current protection, over-temperature protection, high-side MOSFET short protection, VIN/VCC/VDRV/ BOOT UVLO protection. In addition to their analog reporting capability, the combined logic outputs of IMON and TMON provide fault mapping to the PWM controller for specific fault condition deciphering. The PM7080A is compatible with industry-standard footprint. Product status link PM7080A Product summary Order code PM7080A Temperature range -40 to +125 Package QFN 5x6 41L Packing Tape & reel Smart power stage with current sensing, temperature monitor and fault reporting PM7080A Datasheet DS13910 - Rev 1 - April 2022 For further information contact your local STMicroelectronics sales office. Prerelease product(s)
1 Typical application and efficiency
Figure 1. Typical application circuit Figure 2. Efficiency vs. output current (VIN = 12 V, L = 150 nH, VCC = VDRV = 5 V)
2 Pins description
Figure 3. Pinout (Top transparent view) Table 1. Pin description
2 AGND Ground for internal circuitry (not a ground for the drivers)
3 VCC Supply voltage for internal circuitry (does not power the drivers)
4 VDRV Supply voltage for internal gate drive
40 PGND
32 PHASE
35 EN Enables the driver
36 TMON/FAULT
38 IMON Output voltage representative of the inductor current with a ratio of 5 mV/A
39 REFIN Internal reference voltage for IOUT, but can be overdriven externally if desired
3 Absolute maximum ratings
Table 2. Absolute maximum ratings (TA = 25 °C, unless otherwise noted)
- The specification values indicated “AC” is V SW to PGND - 8 V (< 20 nSec, 10 μJ), min. and 30 V (< 50 nSec), max.
3.1 Recommended operating conditions
Table 3. Recommended operating conditions
4 Electrical characteristics
Table 4. Electrical specifications
Electrical characteristics
Prerelease product(s)
Parameter Symbol Test conditions Min. Typ. Max. Unit Current sense accuracy IMON_ACC IOUT > 20 A -2 - 2 %
10 A < IOUT < 20 A -3 - 3 %
5 A < IOUT < 10 A -4 - 4 %
IOUT < 5 A -8 - 8 % Current sense negative range - -50 - A Current sense positive range - 130 - A REFIN voltage range REFIN 1 - 2 V Temperature reporting Temperature reporting gain TMON_GAIN - 8 - mV/C Temperature reporting offset TMON_OS Junct. temperature = 0 C - 0.6 - V Temperature reporting accuracy TMON_ACC -3 - 3 % TMON source current ITMON 5 - - mA TMON_FAULT level VTMON_FLT 2.6 - 3.6 V Over-current protection Accurate positive OCP IOCP_A_P 120 130 140 A Accurate negative OCP IOCP_A_N -50 -60 -70 A Crude positive OCP IOCP_C_P - 150 - A Crude negative OCP IOCP_C_N - -100 - A OCP mask time TMASK_OCP - 100 - nSec Over temperature protection OTP rising threshold TOTP_R - 150 - C OTP hysteresis TOTP_HYS - 10 - C MOSFET driver HS GATE pull down resistor RHG_PH - 20 - kΩ LS GATE pull down resistor RGL_PGND - 20 - kΩ Bootstrap forward voltage VBOOT_F - 0.4 - V PM7080A Prerelease product(s)
5 Functional block and PWM timing diagrams
Figure 4. Functional block diagram Figure 5. PWM timing diagram
6 Detailed operational description
6.1 PWM input and tri-state function
The PWM input receives the PWM control signal from the VR controller IC. The PWM input is designed to be compatible with standard controllers using two state logic (H and L) and advanced controllers that incorporate tri-state logic (H, L,and tri-state) on the PWM output. For two state logic, the PWM input operates as follows. When PWM is high, the low side is turned OFF and the high side is turned ON. When PWM input is driven low, the high side turns off and the low side turns on. For tri-state logic, the PWM input operates as above for driving the MOSFETs. However, there is a third state that is entered into as the PWM output of the tri-state compatible controller enters its high impedance state during shut-down. The high impedance state of the controller's PWM output allows the device to pull the PWM input into the tri-state region (see the tri-state voltage threshold diagram below). If the PWM input stays in this region for the tri-state hold-off period, tTSHO, both high side and low side MOSFETs are turned off. This function allows the VR phase to be disabled without negative output voltage swing caused by inductor ringing and saves a Schottky diode clamp. The PWM and tri-state regions are separated by hysteresis to prevent false triggering. The PM7080A incorporates PWM voltage thresholds that are compatible with 3.3 V logic.
6.2 Temperature sensing and fault reporting (TMON/FAULT)
The TMON/ FAULT signal is a dual function pin: 1. It is a voltage signal proportional to the internal temperature of the power stage device with a conversion factor of 8 mV/°C. In a multi-phase solution, all TMON/FAULT signals are “wired-or” connected to the PWM controller and will indicate the temperature of the highest device 2. It indicates a catastrophic fault condition in the powerstage by pulling the signal to logic high (3.3 V logic compatible). The catastrophic fault conditions are: a. HS FET over-current for 10 consecutive cycles b. OT trip for the device maximum junction temperature c. High side MOSFET drain to source short d. High side BOOT UVLO 3. It indicates other UVLO fault condition in the powerstage by pulling the signal to logic low (0 V). The UVLOfault conditions are: a. V CC/VDRV UVLO b. V IN VULO
6.3 Voltage input (VIN)
This is the power input to the drain of the high side power MOSFET. This pin is connected to the high power intermediate BUS rail.
6.4 Switch node (sw and phase)
The switch node (SW) is the circuit PWM regulated output. This is the output applied to the filter circuit to deliver the regulated high output for the buck converter. The PHASE pin is internally connected to the switch node (SW). This pin (PHASE) is to be used exclusively as the return pin for the BOOT capacitor. A 20.2 kΩ resistor is connected between GH and PHASE to provide a discharge path for the HS MOSFET in the event that VDRV goes to zero while VIN is still applied. PM7080A Detailed operational description DS13910 - Rev 1 page 8/23 Prerelease product(s)
6.5 Ground connections (AGND and PGND)
Internal to the PM7080A, the AGND is shorted to the PGND through the lead frame. To avoid parasitic ground loops, the AGND for each individual instantiation of the device on the PCB should be derived from the PGND of the same device. It is not advised to connect all of the AGND connections at the system level together. If decoupling capacitance to AGND is used for each device IMON_REF pin, it should be tied to the local AGND. Further, if possible, it is recommended to use the provided IMON_REF signal from each device to accompany the IMON signal to provide a true differential output and avoid ground coupled cross-talk between IMON channels. AGND decoupling capacitance to VCC should be kept as close as possible to the device. Typically, a 1 Ω/1 μF capacitor decoupling capacitor network on VCC to AGND should be used. The 1 Ω resistor feeding VCC is connected to VDRV for its unfiltered voltage. VDRV should have its own 1 μF capacitor to PGND.
6.6 Control and drive supply voltage input (VDRV, VCC)
VCC is the bias supply for the gate drive control IC. VDRV is the bias supply for the gate drivers. It is recommended to separate these pins through a 1 Ω resistor with 1 μF//10 nF decoupling capacitance. This creates a low pass filtering effect to avoid coupling of high frequency gate drive noise into the IC’s sensitive analog circuits.
6.7 Bootstrap circuit (BOOT)
The internal bootstrap switch and an external bootstrap capacitor form a charge pump that supplies voltage to the BOOT pin. An integrated bootstrap diode is incorporated so that only an external capacitor is necessary to complete the bootstrap circuit. Connect a bootstrap capacitor with one leg tied to BOOT pin and the other tied to PHASE pin.
6.8 Current sensing and report IMON
A current sense circuit monitors the low side MOSFET and reproduces a real-time representative signal for the entire switching period. The IMON pin is a voltage source output signal that duplicates the real-time waveform of inductor current proportional to the load current by a ratio of 5 uA/A and is differentially referenced to IMON_REF voltage which is provided internally (1.5 V), but can be driven externally.
6.9 IMON_REF
IMON_REF should be terminated to an external voltagereference from 1.2V to 1.8V to provide a return path for IMON current source.
6.10 Shoot through protection and adaptive dead time
The PM7080A has an internal adaptive logic to avoid shoot through and optimize dead time. The shoot through protection ensures that both high side and low side MOSFET are not turned on the same time. The adaptive dead time control operates as follows. The HS and LS gate voltages are monitored to prevent the one turning on until the other's gate voltage is sufficiently low (1 V), that and built in delays ensure each power MOS is turned off before the other turns on. This feature helps to adjust dead time as gate transitions change with respect to output current and temperature.
6.11 Under voltage lockout (UVLO)
During the start up cycle, the UVLO disables the gate drive holding high side and low side MOSFET gate low until the input voltage rail has reached a point at which the logic circuitry can be safely activated. The PM7080A also incorporates logic to clamp the gate drive signals to zero when the UVLO falling edge triggers the shutdown of the device. As an added precaution, a 20.2 kΩ resistor is connected between GH and PHASE to provide a discharge path for the HS MOSFET. Additionally, there is a UVLO that monitors the BOOT voltage. If the BOOT voltage droops low, the low side drive will be momentarily activated to recharge the BOOT capacitor. PM7080A Ground connections (AGND and PGND) DS13910 - Rev 1 page 9/23 Prerelease product(s)
6.12 Advanced fault report
summarizes the fault types in relationship with IMON and TMON/FLT levels. Table 5. Avanced fault report
7 PM7080A electrical curves
(VIN = 12 V, VDRV = VCC = 5 V, LOUT = 150 nH. Power loss includes inductor loss, driver and controller loss unless otherwise stated) Figure 6. Driver current vs. driver voltage Figure 7. Driver current vs. switching frequency Figure 8. Threshold voltage vs. temperature Figure 9. Quiescent current vs. temperature
8 PCB layout recommendations
Figure 15. VIN/PGND planes and decoupling Figure 16. VSWH plane
- Layout V IN and PGND planes as shown above.
- Ceramic capacitors should be placed right between V IN and
ripple induced by the MOSFET switching operation.
- Difference values / packages of ceramic capacitors should be
- Smaller capacitance value, closer to device V IN pin (s)
- Connect output inductor to DrMOS with large plane to lower the
to shield the switching noise.
- If any snubber network is required, place the components as
shown above and the network can be placed at bottom. Figure 17. VCIN/VDRV input filter Figure 18. BOOT resistor and capacitor placement
- The V CIN/VDRV input filter ceramic cap should be placed
separately with one resistor in between.
- C VCIN cap should be placed between pin 3 and pin 2 (AGND of
driver IC) to achieve best noise filtering.
- C VDRV cap should be placed between pin 5 (PGND of driver IC)
low side MOSFET during switching cycle.
- For connecting C VCIN analog ground, it is recommended to use
large plane to reduce parasitic inductance.
- These components need to be placed very close to DrMOS,
right between PHASE (pin 32) and BOOT (pin 33).
- To reduce parasitic inductance, chip size 0402 can be used.
9 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
9.1 QFN 5x6 41L package information
Figure 22. QFN 5x6 41L package outline
0.1 C B
0.1 C A
0.1 M C A B
Table 6. QFN 5x6 41L mechanical data
Package information
DS13910 - Rev 1 page 16/23 Prerelease product(s)
Dimensions (mm) Min. Nom. Max. E2-2 1.90 1.95 2.00 E2-3 2.05 2.10 2.15 E2-4 1.35 1.40 1.45 E2-5 0.25 0.30 0.35 L 0.35 0.40 0.45 L1 0.225 0.275 0.325 F1 0.125 BSC F2 0.275 BSC K1 0.35 ref. K2 0.40 ref. K3 0.35 ref. K4 0.40 ref. K5 0.40 ref. K6 0.40 ref. K7 0.40 ref. N (3) 39 Nd (3) 10 Ne (3) 10 1. Applied only for terminals 2. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip 3. N is the number of terminals, Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction PM7080A QFN 5x6 41L package information DS13910 - Rev 1 page 17/23 Prerelease product(s)
Figure 23. QFN 5x6 41L footprint
Revision history
Table 7. Document revision history 19-Apr-2022 1 Initial release.
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