PM5180NGUT

LM5180 TI1 | Alldatasheet

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Technical content

ADVANCE□INFORMATION Output Current (A) Efficiency (%) VIN = 12V VIN = 24V VIN = 36V VIN = 48V VIN = 70V VOUT = 5 V SW FB VIN EN/UVLO TC GND SS/BIAS RSET LM5180 C OUT C IN 100 F 2.2 F VIN = 4.5 V...70 V 3 : 1 D FLY R SET 12.1 k: R FB 158 k: D 2 D 1 R TC 130 k: C SS 47 nF Copyright © 2018, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. LM5180 SNVSB06 –JULY 2018 LM5180PSRFlybackConverterWith100-V,1.5-AIntegratedPowerMOSFET

1 Features

1• Designed for Reliable and Rugged Applications – Wide Input Voltage Range of 4.5 V to 70 V – Robust Solution with Only One Component Crossing the Isolation Barrier – ±1% Total Output Regulation Accuracy – Optional VOUT Temperature Compensation – 6-ms Internal or Programmable Soft Start – Input UVLO and Thermal Shutdown Protection – Hiccup-Mode Overcurrent Fault Protection – –40°C to 150°C Junction Temperature Range

• Integration Reduces Solution Size and Cost – Integrated 100-V, 0.35-Ω Power MOSFET – No Opto-coupler or Transformer Auxiliary Winding Required for VOUT Regulation – Internal Loop Compensation – Low EMI Operation to Meet CISPR 32 – 8-Pin, 4-mm × 4-mm WSON Package
• High Efficiency PSR Flyback Operation – Quasi-resonant Switching in Boundary Conduction Mode (BCM) at Heavy Load – Low Input Quiescent Current – External Bias Option for Improved Efficiency – Minimum Load Less Than 0.5% of Full Load
• Create a Custom Regulator Design Using WEBENCH® Power Designer

2 Applications

• Isolated Power Rails for PLC Systems
• Motor Drive: IGBT Gate Drive Supplies
• Building Automation HVAC Systems

3 Description

The LM5180 is a primary-side regulated (PSR) flyback converter with high efficiency over a wide input voltage range of 4.5 V to 70 V. The isolated output voltage is sampled from the primary-side flyback voltage, eliminating the need for an optocoupler, voltage reference, or third winding from the transformer for output voltage regulation. The high level of integration results is a simple, reliable and high-density design with only one component crossing the isolation barrier. Boundary conduction mode (BCM) switching enables a compact magnetic solution and better than ±1% load and line regulation performance. An integrated 100-V power MOSFET provides output power up to 7 W with enhanced headroom for line transients. The LM5180 converter simplifies implementation of isolated DC/DC supplies with optional features to optimize performance for the target end equipment. The output voltage is set by one resistor, while an optional resistor improves output voltage accuracy by negating the thermal coefficient of the flyback diode voltage drop. Additional features include an internally- fixed or externally-programmable soft start, optional bias supply connection for higher efficiency, precision enable input with hysteresis for adjustable line UVLO, hiccup-mode overload protection, and thermal shutdown protection with automatic recovery. The LM5180 flyback converter is available in a 8-pin, 4-mm × 4-mm, thermally-enhanced WSON package with 0.8-mm pin pitch. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LM5180 WSON (8) 4.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Typical Efficiency, VOUT = 5 V

ADVANCE□INFORMATION LM5180 SNVSB06 –JULY 2018 www.ti.com Product Folder Links: LM5180 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Table of Contents

11.3 Receiving Notification of Documentation Updates 32

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES July 2018 * Initial release

ADVANCE□INFORMATION EN/UVLO VIN FB GND RSET SS/BIAS TC SW LM5180 www.ti.com SNVSB06 –JULY 2018 Product Folder Links: LM5180 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (1) P = Power, G = Ground, I = Input, O = Output.

5 Pin Configuration and Functions

8-Pin WSON With Wettable Flanks Top View Pin Functions PIN I/O(1) DESCRIPTION NO. NAME 1 SW P Switch node that is internally connected to the drain of the N-channel power MOSFET. Connect to the primary-side switching terminal of the flyback transformer. 2 FB I Primary side feedback pin. Connect a resistor from FB to SW. The ratio of the FB resistor to the resistor at the RSET pin sets the output voltage. 3 VIN P/I Input supply connection. Source for internal bias regulators and input voltage sensing pin. Connect directly to the input supply of the converter with short, low impedance paths.

4 EN/UVLO I

Enable input and undervoltage lockout (UVLO) programming pin. If the EN/UVLO voltage is below 1.1 V, the converter is in shutdown mode with all functions disabled. If the EN/UVLO voltage is greater than 1.1 V and below 1.5 V, the converter is in standby mode with the internal regulator operational and no switching. If the EN/UVLO voltage is above 1.5 V, the start-up sequence begins.

5 SS/BIAS I

Soft-start or bias input. Connect a capacitor from SS/BIAS to GND to adjust the output start-up time and input inrush current. If SS/BIAS is left open, the internal 6-ms soft-start timer is activated. Connect an auxiliary winding through a low leakage diode to SS/BIAS to supply bias to the internal voltage regulator and enable internal soft start.

6 TC I

Temperature compensation pin. Tie a resistor from TC to RSET to compensate for the temperature coefficient of the forward voltage drop of the secondary diode, thus improving regulation at the secondary-side output. 7 RSET I Reference resistor tied to GND to set the reference current for FB. Connect a 12.1-kΩ resistor from RSET to GND. 8 GND G Analog and power ground. Ground connection of internal control circuits and power MOSFET.

ADVANCE□INFORMATION LM5180 SNVSB06 –JULY 2018 www.ti.com Product Folder Links: LM5180 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)(1) MIN MAX UNIT Input voltage VIN to GND –0.3 75 V EN/UVLO to GND 0 75 TC to GND –0.3 6 SS to GND –0.3 14 FB to GND –0.3 75.3 FB to VIN –0.3 0.3 RSET to GND –0.3 3 Output voltage SW to GND –1.5 100 V SW to GND (20-ns transient) –3 Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS- 001, all pins(1) HBM ESD Classification Level 2 ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) CDM ESD Classification Level C4B ±500

6.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage 4.5 70 V VSW SW voltage 100 V VEN/UVLO EN/UVLO voltage 70 V VBIAS SS/BIAS voltage 13 V TJ Operating junction temperature –40 150 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) LM5180 UNITNGU (WSON)

8 PINS

RΘJA Junction-to-ambient thermal resistance 41.3 °C/W RΘJC(top) Junction-to-case (top) thermal resistance 34.7 °C/W RΘJB Junction-to-board thermal resistance 19.1 °C/W ΨJT Junction-to-top characterization parameter 0.3 °C/W ΨJB Junction-to-board characterization parameter 19.2 °C/W RΘJC(bot) Junction-to-case (bottom) thermal resistance 3.2 °C/W

ADVANCE□INFORMATION LM5180 www.ti.com SNVSB06 –JULY 2018 Product Folder Links: LM5180 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

6.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits aaply over the full –40°C to 150°C junction temperature range unless otherwise indicated. VIN = 24 V and VEN/UVLO = 2 V unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ISHUTDOWN VIN shutdown current VEN/UVLO = 0 V 3 µA IACTIVE VIN active current VEN/UVLO = 2.5 V, VRSET = 1.8 V 290 µA IACTIVE_BIAS VIN current with BIAS connected VSS/BIAS = 6 V 25 µA ENABLE AND INPUT UVLO VSD-RISING Standby threshold VEN/UVLO rising 0.65 1.1 V VSD-FALLING Shutdown threshold VEN/UVLO falling 0.3 V VEN-RISING Enable threshold VEN/UVLO rising 1.47 1.5 1.53 V IEN-HYST Enable current hysteresis VEN/UVLO = 1.6 V 5 µA VEN-HYST Enable voltage hysteresis VEN/UVLO falling 0.05 V FEEDBACK IRSET RSET current RRSET = 12.1 kΩ 100 µA VRSET RSET regulation voltage RRSET = 12.1 kΩ 1.198 1.21 1.222 V VFB-VIN1 FB to VIN voltage IFB = 80 µA –40 mV VFB-VIN2 FB to VIN voltage IFB = 120 µA 40 mV SWITCHING FREQUENCY FSW-MIN Minimum switching frequency 10 kHz FSW-MAX Maximum switching frequency 350 kHz tON-MIN Minimum switch on-time 150 ns DIODE THERMAL COMPENSATION VTC TC voltage ITC = ±10 µA, TJ = 25°C 1.2 V POWER SWITCHES RDS(on) MOSFET on-state resistance ISW = 100 mA 0.35 Ω SOFT-START AND BIAS ISS SS ext capacitor charging current 5 µA tSS Internal SS time 6 ms VBIAS-UVLO- RISE BIAS enable voltage VSS/BIAS rising 5.68 5.9 V VBIAS-UVLO- HYST BIAS UVLO hysteresis VSS/BIAS falling 180 mV CURRENT LIMIT IPEAK Peak current limit threshold 1.35 1.5 1.65 A THERMAL SHUTDOWN TSD Thermal shutdown threshold TJ rising 180 °C TSD-HYS Thermal shutdown hysteresis 20 °C

ADVANCE□INFORMATION LM5180C IN C SS VIN N P : NS EN/UVLO VIN SW FB SS/BIASGND TC RSET R FB VREF COMP Internal SS SAMPLED FEEDBACK FB 100-V Power MOSFET Standby Shutdown 1.1 V VDD VDD UVLO BIAS REGULATOR THERMAL SHUTDOWN SS/BIAS VDD VDD VIN 1.5 A ILIM TRIMMED REFERENCE R SET TC REGULATION R TC VOUT C OUT D FLY CONTROL LOGIC 1.5 V 1.45 V gm 5 PA C S R S LM5180 SNVSB06 –JULY 2018 www.ti.com Product Folder Links: LM5180 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The LM5180 primary-side regulated (PSR) flyback converter is a high-density, cost-effective solution for industrial systems requiring less than 7 W of isolated DC/DC power. This compact, easy-to-use flyback converter with low IQ and high efficiency can be applied over a wide input voltage range from 4.5 V to 70 V. Primary-side regulation of the isolated output voltage using sampled values of the primary winding voltage eliminates the need for an auxiliary transformer winding or an opto-coupler for feedback. Regulation performance that rivals that of traditional opto-coupler solutions is achieved without the associated cost, solution size and reliability concerns. The LM5180 converter services a wide range of applications including IGBT-based motor drives, factory automation, and medical equipment.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Integrated Power MOSFET

The LM5180 is a flyback dc/dc converter with integrated 100-V, 1.5-A N-channel power MOSFET. During the MOSFET on-time, the transformer primary current increases from zero with slope VIN / LMAG (where LMAG is the transformer primary-referred magnetizing inductance) while the output capacitor supplies the load current. When the high-side MOSFET is turned off by the control logic, the SW voltage VSW swings up to approximately VIN + (NPS × VOUT), where NPS = NP/NS is the primary-to-secondary turns ratio of the transformer. The magnetizing current flows in the secondary side through the flyback diode, charging the output capacitor and supplying current to the load. Duty cycle D is defined as tON / tSW, where tON is the MOSFET conduction time and tSW is the switching period. Figure 1 shows a typical schematic of the LM5180 PSR flyback circuit. Components denoted in red are optional depending on the application requirements.

Figure 1. LM5180 Flyback Converter Schematic (Optional Components in Red)

7.3.2 PSR Flyback Modes of Operation

modes of operation as illustrated in Figure 2. Figure 2. Three Modes of Operation Illustrated by Variation of Switching Frequency With Load

ADVANCE□INFORMATION SET FB OUT D PS REF RR V V N V ˜ ˜ MAG PRI-PK(DCM) SW(DCM) DCM IN L I F D V ˜ ˜ OUT OUT D PRI-PK(DCM) MAG SW(DCM)

2 I V VI L F

˜ ˜ ˜ MAG PRI-PK(DCM) OUT(DCM) SW(DCM) L I P F 2 OUT D OUT PRI-PK(BCM) IN

2 V V II V D

˜ ˜ ˜ SW(BCM) MAG MAG PRI-PK(BCM) IN PS OUT D L L I V N V V § · ˜ ¨ ¸ ¨ ¸ ˜ © ¹ MAG PRI-PK(BCM) OUT(BCM) SW(BCM) L I P F 2 OUT D PS BCM IN OUT D PS V V ND V V V N ˜ ˜ LM5180 SNVSB06 –JULY 2018 www.ti.com Product Folder Links: LM5180 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Feature Description (continued) The LM5180 operates in boundary conduction mode (BCM) at heavy loads. The power MOSFET turns on when the current in the secondary winding reaches zero, and the MOSFET turns off when the peak primary current reaches the level dictated by the output of the internal error amplifier. As the load is decreased, the frequency increases in order to maintain BCM operation. The duty cycle of the flyback converter is given Equation 1, where VD is the forward voltage drop of the flyback diode as its current approaches zero. (1) The output power in BCM is given by Equation 2, where the applicable switching frequency and peak primary current in BCM are specified by Equation 3 and Equation 4, respectively. (2) (3) (4) As the load decreases, the LM5180 clamps the maximum switching frequency to 350 kHz, and the converter enters discontinuous conduction mode (DCM). The power delivered to the output in DCM is proportional to the peak primary current squared as given by Equation 5 and Equation 6. Thus, as the load decreases, the peak current reduces to maintain regulation at 350-kHz switching frequency. (5) (6) (7) At even lighter loads, the primary-side peak current set by the internal error amplifier decreases to a minimum level of 0.3 A, or 20% of its 1.5-A peak value, and the MOSFET off-time extends to maintain the output load requirement. The system operates in frequency foldback mode (FFM), and the switching frequency decreases as the load current is reduced. Other than a fault condition, the lowest frequency of operation of the LM5180 is 12 kHz, which sets a minimum load requirement of approximately 0.5% full load.

7.3.3 Setting the Output Voltage

To minimize output voltage regulation error, the LM5180 senses the reflected secondary voltage when the secondary current reaches zero. The feedback (FB) resistor, which is connected between SW and FB as shown in Figure 1, is determined using Equation 8, where RSET is nominally 12.1 kΩ. (8)

7.3.3.1 Diode Thermal Compensation

diode. Select the thermal compensation resistor using Equation 9.

7.3.4 Control Loop Error Amplifier

when the output voltage is in regulation, an on-time interval is initiated when the secondary current reaches zero.

7.3.5 Precision Enable

connect EN/UVLO directly to VIN. This allows the LM5180 to start up when VIN is within its valid operating range. Figure 3. Programmable Input Voltage UVLO With Hysteresis respectively, where VUVLO1 and VUVLO2 are the UVLO comparator thresholds and IUVLO is the hysteresis current.

hard shutdown and precision-enable thresholds.

7.3.6 Configurable Soft Start

options include a 6-ms internally-fixed soft start and an externally-programmable soft start. control ramp and starts up to the regulated output voltage in 6 ms. internal current source ISS of 5 µA charges CSS and generates a ramp to control the primary current amplitude. Calculate the soft-start capacitance for a desired soft-start time, TSS, using Equation 12. CSS is discharged by an internal FET when switching is disabled by EN/UVLO or thermal shutdown.

7.3.7 External Bias Supply

The LM5180 has an external bias supply feature that reduces input quiescent current and increases efficiency. Figure 4. External Bias Supply Using Transformer Auxiliary Winding

ADVANCE□INFORMATION LM5180 www.ti.com SNVSB06 –JULY 2018 Product Folder Links: LM5180 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Feature Description (continued) When using a transformer auxiliary winding for bias power, the total leakage current related to DBIAS1 and DBIAS2 should be less than 1 µA across the full operating temperature range.

7.3.8 Minimum On-Time and Off-Time

When the internal power MOSFET is turned off, the leakage inductance of the transformer resonates with the SW node parasitic capacitance. The resultant ringing behavior can be excessive with large transformer leakage inductance and may corrupt the secondary zero-current detection. In order to prevent such a situation, a minimum switch off-time, designated as tOFF-MIN, of maximum 500 ns is set internally to ensure proper functionality. This sets a lower limit for the transformer magnetizing inductance as discussed in Detailed Design Procedure. Furthermore, noise effects as a result of power MOSFET turn-on can impact the internal current sense circuit measurement. To mitigate this effect, the LM5180 provides a blanking time after the MOSFET turns on. This blanking time forces a minimum on-time, tON-MIN, of 150 ns.

7.3.9 Overcurrent Protection

In case of an overcurrent condition on the isolated output(s), the output voltage drops lower than the regulation level since the maximum power delivered is limited by the peak current capability on the primary side. The peak primary current is maintained at 1.5 A until the output decreases to the secondary diode voltage drop to impact the reflected signal on the primary side. At this point, the LM5180 assumes the output cannot be recovered and re-calibrates its switching frequency to 9 kHz until the overload condition is removed. The LM5180 responds with similar behavior to an output short circuit condition.

7.3.10 Thermal Shutdown

Thermal shutdown is an integrated self-protection to limit junction temperature and prevent damage related to overheating. Thermal shutdown turns off the device when the junction temperature exceeds 180°C to prevent further power dissipation and temperature rise. Junction temperature decreases after shutdown, and the LM5180 restarts when the junction temperature falls to 160°C.

7.4 Device Functional Modes

7.4.1 Shutdown Mode

EN/UVLO facilitates ON and OFF control for the LM5180. When VEN/UVLO is below approximately 0.6 V, the device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in shutdown mode drops to 3 μA at VIN = 24 V. The LM5180 also employs internal bias rail undervoltage protection. If the internal bias supply voltage is below its UV threshold, the converter remains off.

7.4.2 Standby Mode

The internal bias rail LDO regulator has a lower enable threshold than the converter itself. When VEN/UVLO is above 0.6 V and below the precision-enable threshold (1.5 V typically), the internal LDO is on and regulating. The precision enable circuitry is turned on once the internal VCC is above its UV threshold. The switching action and voltage regulation are not enabled until VEN/UVLO rises above the precision enable threshold.

7.4.3 Active Mode

The LM5180 is in active mode when VEN/UVLO is above the precision-enable threshold and the internal bias rail is above its UV threshold. The LM5180 operates in one of three modes depending on the load current requirement: 1. Boundary conduction mode (BCM) at heavy loads. 2. Discontinuous conduction mode (DCM) at medium loads. 3. Frequency foldback mode (FFM) at light loads. Refer to PSR Flyback Modes of Operation for more detail.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.2 Typical Applications

refer to the TI Designs reference design library.

8.2.1 Design 1: Wide VIN, Low IQ PSR Flyback Converter Rated at 5 V, 1 A

The schematic diagram of a 5-V, 1-A PSR flyback converter is given in Figure 5. Figure 5. Schematic for Design 1 With VIN(nom) = 24 V, VOUT = 5 V, IOUT = 1 A

8.2.1.1 Design Requirements

The required input, output, and performance parameters for this application example are shown in Table 1. Table 1. Design Parameters components are listed in Table 2. Table 2. List of Components for Design 1 DCLAMP 1 Zener, 24 V, 1 W, PowerDI-123, AEC-Q101 DFLZ24-7 Diodes Inc.

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5180 device with WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.

ADVANCE□INFORMATION IN(max) D-REV OUT PS V 70 VV V 5 V 28 VN 3 t | MAG PRI-PK PRI-PK OUT(max) SW(BCM) IN PS OUT L I IP F 2 1 1 2 V N V ˜ ˜ OUT PRI-PK PS SEC-RMS

2 I I NI 3

˜ ˜ ˜ PRI-RMS PRI-PK DI I 3 ˜ OUT D PS OFF-MIN MAG PRI-PK(FFM) V V N t 5V + 0.3V 3 500nsL 26.5 +I 0.3A ˜ ˜ ˜ ˜t IN(min)MAX PS MAX OUT D VD 0.6 10 VN 31 D V V 1 0.6 5 V + 0.3V ˜ ˜ LM5180 SNVSB06 –JULY 2018 www.ti.com Product Folder Links: LM5180 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.1.2.2 Custom Design With Excel Quickstart Tool

Select components based on the converter specifications using the LM5180 quick-start calculator available for download from the LM5180 product folder.

8.2.1.2.3 Flyback Transformer – T1

Choose a turns ratio based on an approximate 60% max duty cycle at minimum input voltage using Equation 13, rounding up or down as needed. (13) Select a magnetizing inductance based on the minimum off-time constraint using Equation 14. Choose a value of 30 µH with a saturation current of 2 A for this application. (14) Note that a higher magnetizing inductance provides a larger operating range for BCM and FFM, but the leakage inductance may increase based on the increase number of primary turns, NP. The primary and secondary winding RMS currents are given by Equation 15 and Equation 16, respectively. (15) (16) Find the maximum output power for a given turns ratio using Equation 17, where the typical value for IPRI-PK(max) from Electrical Characteristics is 1.5 A. Iterate by increasing the turns ratio if the output power is too low at minimum input voltage. (17)

8.2.1.2.4 Flyback Diode – DFLY

The flyback diode reverse voltage is given by Equation 18. (18) Choose a 40-V, 3-A Schottky diode for this application to account for diode voltage overshoot and ringing related to transformer leakage inductance and diode parasitic capacitance. Connect an appropriate RC snubber circuit (for example, 100 Ω and 22 pF) across the diode if needed.

ADVANCE□INFORMATION PRI-PK CIN-RMS D I 4I 1 2 3 D ˜ ˜ ˜ PRI-PK IN SW IN DI D 1 2C 2 F V © ¹ t ˜ ˜ ' PS PRI-PK COUT-RMS OUT OUT

2 N II I 1 3 I

˜ ˜ ˜ ˜ OUT OUT PRI-PK PS OUT 2 PRI-PK SW OUT II I NC I F V © ¹ t ˜ ˜ ' DZ(clamp) PS OUT DV 1.5 N V V 1.5 3 5V 0.3V 24V ˜ ˜ ˜ ˜ | DZ(clamp) SW(max) IN(max)V V V LM5180 www.ti.com SNVSB06 –JULY 2018 Product Folder Links: LM5180 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

8.2.1.2.5 Clamp Circuit – DF, DCLAMP

Connect a diode-Zener clamp circuit across the primary winding to limit the peak SW node voltage after MOSFET turn-off below the maximum level of 100 V, as given by Equation 19. (19) Choosing the zener, DCLAMP, with clamp voltage of approximately 1.5 times the reflected output voltage, as specified by Equation 20, provides a balance between the maximum SW voltage excursion and the leakage inductance demagnetization time. (20) Select an ultra-fast switching diode or Schottky diode for DF with rated voltage greater than the maximum input voltage and with low forward recovery voltage drop.

8.2.1.2.6 Output Capacitor – COUT

The output capacitor determines the voltage ripple at the converter output, limits the voltage excursion during a load transient, and sets the dominant pole of the converter's small-signal response. For a flyback converter specifically, the output capacitor supplies the load current when the main switch is on, and therefore the output voltage ripple is a function of load current and duty cycle. Select an output capacitance using Equation 21 to limit the ripple voltage amplitude to less than 1% of the output voltage at minimum input voltage. (21) Substituting the full load current, switching frequency, peak primary current and peak-to-peak voltage ripple specification gives COUT greater than 30 μF. Mindful of the voltage coefficient of ceramic capacitors, select a 100- µF, 6.3-V capacitor in 1210 case size with X5R or better dielectric. The output capacitor RMS ripple current is given by Equation 22. (22)

8.2.1.2.7 Input Capacitor – CIN

Select an input capacitance using Equation 23 to limit the ripple voltage amplitude to less than 5% of the input voltage when operating at nominal input voltage. (23) Substituting the input current at full load, switching frequency, peak primary current and peak-to-peak ripple specification gives CIN greater than 2 μF. Mindful of the voltage coefficient of ceramic capacitors, select a 4.7-µF, 100-V capacitor with X7S or X7R dielectric in 1210 case size. The input capacitor RMS ripple current is given by Equation 24. (24)

8.2.1.2.8 Feedback Resistor – RFB

8.2.1.2.9 Thermal Compensation Resistor – RTC

Select a resistor for output voltage thermal compensation, designated RTC, based on Equation 26.

8.2.1.2.10 UVLO Resistors – RUV1, RUV2

8.2.1.3 Application Curves

Unless otherwise stated, application performance curves were taken at TA = 25°C. Figure 6. Efficiency (Linear Scale) Figure 7. Efficiency (Log Scale)

400 Ps/DIV

Figure 8. Load Regulation (Linear Scale) Figure 9. Load Regulation (Log Scale) Figure 10. Switching Frequency Over Load and Line Figure 11. Start-up Characteristic Figure 12. Enable ON Characteristic Figure 13. Short Circuit Recovery

1 Ps/DIV

Figure 14. SW Node Voltage Figure 15. SW Node Voltage Figure 16. Flyback Diode Voltage Figure 17. Flyback Diode Voltage

8.2.2 Design 2: PSR Flyback Converter With Dual Outputs of 15 V and –8V at 200 mA

Figure 18. Schematic for Design 2 With VIN(nom) = 48 V, VOUT1 = 15 V, VOUT2 = –8 V, IOUT = 200 mA

8.2.2.1 Design Requirements

The required input, output, and performance parameters for this application example are shown in Table 3. Table 3. Design Parameters

Table 4. List of Components for Design 2 DFLY1 1 Switching diode, fast recovery, 200 V, 1 A, SOD-123 DFLU1200-7 Diodes Inc. DCLAMP 1 Zener, 24 V, 1 W, PowerDI-123 DFLZ24-7 Diodes Inc. DF 1 Switching diode, 75 V, 0.3 A, SOD323 1N4148WS Diodes Inc.

8.2.2.2 Detailed Design Procedure

Using the LM5180 quick-start calculator, components are selected based on the flyback converter specifications.

8.2.2.2.1 Flyback Transformer – T1

of secondary turns for the respective outputs. 30 µH with a saturation current of 2 A for this application.

8.2.2.2.2 Flyback Diodes – DFLY1 and DFLY2

ADVANCE□INFORMATION UVLO1 UV2 UV1 IN(on) UVLO1 V 1.5 VR R 340 k 68 kV V 9 V 1.5 V ˜ :˜ : UVLO2 IN(on) IN(off) UVLO1 UV1 UVLO V 1.45 VV V 9 V 7 VV 1.5 VR 340kI 5 ˜ ˜ OUT D PS FB V V N 15 V 0.3 V 1R 154 k0.1mA 0.1mA ˜ ˜ : IN(max) D2-REV OUT2 PS V V V 70 V 0.55 8 V 46.5 VNt ˜ IN(max) D1-REV OUT1 PS V 70 VV V 15 V 85 VN 1 t LM5180 www.ti.com SNVSB06 –JULY 2018 Product Folder Links: LM5180 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (32) (33) Choose a 200-V, 1-A ultra-fast switching diode and a 100-V, 1-A Schottky diode for the positive and negative outputs, respectively, to allow some margin for inevitable voltage overshoot and ringing related to leakage inductance and diode capacitance. If needed, use a diode RC snubber circuit, for example 100 Ω and 22 pF, to mitigate such overshoot and ringing.

8.2.2.2.3 Input Capacitor – CIN

The input capacitor, CIN, filters the primary-side triangular current waveform. To prevent large ripple voltage, use a low-ESR ceramic input capacitor sized according to Equation 23 for the RMS ripple current given by Equation 24. In this design example, choose a 4.7-µF, 100-V ceramic input capacitor with X7S dielectric and 1210 footprint.

8.2.2.2.4 Feedback Resistor – RFB

Install a 154-kΩ resistor from SW to FB based on an output voltage setpoint of 15 V (plus a flyback diode voltage drop) reflected to the primary by a transformer turns ratio of unity. (34)

8.2.2.2.5 UVLO Resistors – RUV1, RUV2

Given VIN(on) and VIN(off) as the input voltage turn-on and turn-off thresholds of 9 V and 7 V, respectively, select the upper and lower UVLO resistors using Equation 35 and Equation 36. (35) (36)

8.2.2.3 Application Curves

Figure 19. Efficiency (Linear Scale) Figure 20. Efficiency (Log Scale) Figure 21. Load Regulation (Linear Scale) Figure 22. Load Regulation (Log Scale) Figure 23. Start-Up Characteristic Figure 24. ENABLE ON Characteristic

200 Ps/DIV

Figure 25. SW Node Voltage, Full Load Figure 26. SW Node Voltage, Full Load Figure 27. Flyback Diode Voltages, Full Load Figure 28. Flyback Diode Voltages, Full Load Figure 29. Output 1 Load Transient, 50 mA to 200 mA Figure 30. Output 2 Load Transient, 50 mA to 200 mA

8.2.3 Design 3: PSR Flyback Converter With Stacked Dual Outputs of 24 V and 5 V

Figure 31. Schematic for Design 3 With VIN(nom) = 24 V, VOUT1 = 24 V, VOUT2 = 5 V

8.2.3.1 Design Requirements

The required input, output, and performance parameters for this application example are shown in Table 5. Table 5. Design Parameters including multi-winding flyback transformer, input and output capacitors, rectifying diodes, and converter IC.

Table 6. List of Components for Design 3 DFLY1 1 Switching diode, fast recovery, 200 V, 1 A, SOD-123 DFLU1200 Diodes Inc. DFLY2 1 Schottky diode, 40 V, 1 A, SOD-123 B140HW Diodes Inc. DCLAMP 1 Zener, 22 V, 1 W, PowerDI-123 DFLZ22-7 Diodes Inc.

8.2.3.2 Detailed Design Procedure

design procedure is similar to that outlined for Designs 1 and 2 previously.

8.2.3.2.1 Flyback Transformer – T1

approximate 60% max duty cycle at minimum input voltage using Equation 37. outputs is thus specified as 1 : 1.5 : 0.4. saturation current of 2 A to handle the peak primary current.

8.2.3.2.2 Feedback Resistor – RFB

8.2.3.2.3 UVLO Resistors – RUV1, RUV2

8.2.3.3 Application Curves

Figure 32. Efficiency Figure 33. Start-Up Characteristic Figure 34. ENABLE ON Characteristic Figure 35. Recovery From Short Circuit

400 Ps/DIVVOUT2 100mV/DIV

Figure 36. SW Node Voltage, Full Load Figure 37. SW Node Voltage, Full Load Figure 38. Flyback Diode Voltages, Full Load Figure 39. Flyback Diode Voltages, Full Load Figure 40. Output 1 Load Transient, 50 mA to 100 mA Figure 41. Output 2 Load Transient, 100 mA to 200 mA

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9 Power Supply Recommendations

The LM5180 flyback converter is designed to operate from a wide input voltage range from 4.5 V to 70 V. The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended Operating Conditions. In addition, the input supply must be capable of delivering the required input current to the fully-loaded regulator. Estimate the average input current with Equation 42. where

• η is the efficiency (42) If the converter is connected to an input supply through long wires or PCB traces with a large impedance, special care is required to achieve stable performance. The parasitic inductance and resistance of the input cables may have an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients at VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip during a load transient. If the regulator is operating close to the minimum input voltage, this dip can cause false UVLO fault triggering and a system reset. The best way to solve such issues is to reduce the distance from the input supply to the regulator and use an aluminum electrolytic input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitors helps to damp the input resonant circuit and reduce any voltage overshoots. A capacitance in the range of 10 µF to 47 µF is usually sufficient to provide input damping and helps to hold the input voltage steady during large load transients. A typical ESR of 0.25 Ω provides enough damping for most input circuit configurations. An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as well as some of the effects mentioned above. The application report Simple Success with Conducted EMI for DC-DC Converters provides helpful suggestions when designing an input filter for any switching regulator.

ADVANCE□INFORMATION LM5180 www.ti.com SNVSB06 –JULY 2018 Product Folder Links: LM5180 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

10 Layout

The performance of any switching converter depends as much upon PCB layout as it does the component selection. The following guidelines are provided to assist with designing a PCB with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI. Figure 42 and Figure 43 provide layout examples for single-output and dual-output designs, respectively.

10.1 Layout Guidelines

PCB layout is a critical for good power supply design. There are several paths that conduct high slew-rate currents or voltages that can interact with transformer leakage inductance or parasitic capacitance to generate noise and EMI or degrade the power supply's performance. 1. Bypass the VIN pin to GND with a low-ESR ceramic capacitor, preferably of X7R or X7S dielectric. Place CIN as close as possible to the LM5180 VIN and GND pins. Ground return paths for the input capacitor(s) must consist of localized top-side planes that connect to the GND pin and exposed PAD. 2. Minimize the loop area formed by the input capacitor connections and the VIN and GND pins. 3. Locate the transformer close to the SW pin. Minimize the area of the SW trace or plane to prevent excessive e-field or capacitive coupling. 4. Minimize the loop area formed by the diode-Zener clamp circuit connections and the primary winding terminals of the transformer. 5. Minimize the loop area formed by the flyback rectifying diode, output capacitor and the secondary winding terminals of the transformer. 6. Tie the GND pin directly to the power pad under the device and to a heat-sinking PCB ground plane. 7. Use a ground plane in one of the middle layers as a noise shielding and heat dissipation path. 8. Have a single-point ground connection to the plane. Route the return connections for the reference resistor, soft-start, and enable components directly to the GND pin. This prevents any switched or load currents from flowing in analog ground traces. If not properly handled, poor grounding results in degraded load regulation or erratic output voltage ripple behavior. 9. Make VIN+, VOUT+ and ground bus connections short and wide. This reduces any voltage drops on the input or output paths of the converter and maximizes efficiency. 10. Minimize trace length to the FB pin. Locate the feedback resistor close to the FB pin. 11. Locate components RSET, RTC and CSS as close as possible to their respective pins. Route with minimal trace lengths. 12. Place a capacitor between input and output return connections to route common-mode noise currents directly back to their source. 13. Provide adequate heatsinking for the LM5180 to keep the junction temperature below 150°C. For operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat- sinking vias to connect the exposed PAD to the PCB ground plane. If the PCB has multiple copper layers, connect these thermal vias to inner-layer ground planes. The connection to VOUT+ provides heatsinking for the flyback diode.

10.2 Layout Examples

Figure 42. LM5180 Single-Output PCB Layout Figure 43. LM5180 Dual-Output PCB Layout

ADVANCE□INFORMATION LM5180 www.ti.com SNVSB06 –JULY 2018 Product Folder Links: LM5180 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 Development Support

For development support, see the following:

• LM5180 Quick-start Calculator
• LM5180 Simulation Models
• For TI's reference design library, visit TIDesigns
• For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center

11.1.3 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5180 device with WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

• LM5180EVM-S05 EVM User's Guide (SNVU592)
• Under the Hood of Flyback SMPS Designs (SLUP261)
• Flyback Transformer Design Considerations for Efficiency and EMI (SLUP338)
• White Papers: – Valuing Wide VIN, Low EMI Synchronous Buck Circuits for Cost-driven, Demanding Applications (SLYY104) – An Overview of Conducted EMI Specifications for Power Supplies (SLYY136) – An Overview of Radiated EMI Specifications for Power Supplies (SLYY142)
• TI Designs: – Snubberless Non-Isolated AC/DC Flyback Converter Reference Design with Simplified Transformer (TIDUAN6)
• TI Blogs: – Flyback Converters: Two Outputs are Better Than One – Common Challenges When Choosing the Auxiliary Power Supply for Your Server PSU – Maximizing PoE PD Efficiency on a Budget

ADVANCE□INFORMATION LM5180 SNVSB06 –JULY 2018 www.ti.com Product Folder Links: LM5180 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Documentation Support (continued)

• AN-2162: Simple Success with Conducted EMI from DC-DC Converters (SNVA489)
• Automotive Cranking Simulator User's Guide (SLVU984)
• Using New Thermal Metrics (SBVA025)
• Semiconductor and IC Package Thermal Metrics (SPRA953)

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, go to the device product folder on ti.com. In the upper right corner, click on Alert me to register for a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.5 Trademarks

E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.7 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages have mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com PACKAGE OUTLINE C 8X 0.35 0.25 3 0.05 2.4 1.98 0.05 6X 0.8

0.8 MAX

8X 0.5 0.3 0.05 0.00 A 4.1 3.9 B 4.1 3.9 (0.2) TYP

0.1 MIN

(0.05) WSON - 0.8 mm max heightNGU0008C PLASTIC SMALL OUTLINE - NO LEAD 4224001/A 11/2017 PIN 1 INDEX AREA SEATING PLANE 0.08 C 4 5 PIN 1 ID

0.1 C A B

0.05 C THERMAL PAD EXPOSED SYMM SYMM9 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.000 A-A 30.000 SECTION A-A TYPICAL ADVANCE□INFORMATION LM5180 www.ti.com SNVSB06 –JULY 2018 Product Folder Links: LM5180 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

8X (0.3) (3) (3.8) 6X (0.8) (1.98) ( 0.2) VIA TYP (0.74) (1.25) 8X (0.6) (R0.05) TYP WSON - 0.8 mm max heightNGU0008C PLASTIC SMALL OUTLINE - NO LEAD 4224001/A 11/2017 SYMM 4 5 EXPOSED METAL SHOWN LAND PATTERN EXAMPLE SCALE:15X SYMM 9 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DETAILS DEFINED (PREFERRED) EXPOSED METAL ADVANCE□INFORMATION LM5180 SNVSB06 –JULY 2018 www.ti.com Product Folder Links: LM5180 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP 8X (0.3) 8X (0.6) (1.75) (1.31) (3.8) (0.755) 6X (0.8) WSON - 0.8 mm max heightNGU0008C PLASTIC SMALL OUTLINE - NO LEAD 4224001/A 11/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 9: 77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X SYMM 4 5 METAL TYP SYMM ADVANCE□INFORMATION LM5180 www.ti.com SNVSB06 –JULY 2018 Product Folder Links: LM5180 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

www.ti.com 1-Aug-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PM5180NGUT PREVIEW WSON NGU 8 250 TBD Call TI Call TI -40 to 150 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LM5180 :

www.ti.com 1-Aug-2018 Addendum-Page 2

• Automotive: LM5180-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

www.ti.com SDC08B (Rev A)

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