Power Management

PM5143QRWGTQ1

Texas Instruments

3.5-V to 65-V Low IQ, Dual Synchronous Buck DC/DC Controller

Manufacturer: Texas Instruments

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ADVANCE□INFORMATION VOUT2 = 5 V IOUT2 = 10 A VIN = 3.5 V...65 V SS2RES DEMB AGND SS1 COMP2 PGND2 VOUT2 CS2 LO2 SW2 HO2 HB2 VIN COMP1 PGND1 VOUT1 CS1 LO1 SW1 HO1 HB1 VCC PG1 HOL1 LOL1 HOL2 LOL2 EN1 EN2 VCCX RT VDDA PG2 SYNCOUT VIN VIN VOUT1 = 3.3 V IOUT1 = 10 A LM5143-Q1 * VOUT1 tracks VIN if VIN < 3.7 V VOUT2 tracks VIN if VIN < 5.4 V LO1 C O2 C IN LO2 C O1 R S2R S1 Q L1 Q H1 Q L2 Q H2 DITH Copyright © 2018, Texas Instruments Incorporated FB2FB1 MODE VDDA Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. LM5143-Q1 SNVSB29 –OCTOBER 2018 LM5143-Q13.5-Vto65-VLowIQ,DualSynchronousBuckDC/DCController

1 Features

1• AEC-Q100 Qualified for Automotive Applications: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature

Versatile Synchronous Buck DC/DC Controller – Wide Input Voltage Range of 3.5 V to 65 V – 1% Accurate, Fixed 3.3-V, 5-V or Adjustable Outputs from 0.6 V to 55 V – Shutdown Mode Current: 4 µA Typical – No-Load Standby Current: 15 µA Typical
Two Interleaved Synchronous Buck Channels – Dual-Channel or Single-Output Multi-Phase – 65-ns tON(min) for High VIN / VOUT Ratio – 60-ns tOFF(min) for Low Dropout
Switching Frequency From 100 kHz to 2.2 MHz – SYNC In and SYNC Out Capability – Optional Spread-Spectrum Modulation – Meets CISPR 25 EMI Requirements
Inherent Protection Features for Robust Design – Hiccup-Mode Overcurrent Protection – Independent ENABLE and PGOOD Functions – VCC, VDDA, and Gate-Drive UVLO Protection – Thermal Shutdown Protection With Hysteresis
Slew-Rate-Controlled Adaptive Gate Drivers
Selectable Diode Emulation or FPWM
VQFN-40 Package With Wettable Flanks
Create a Custom Design Using the LM5143-Q1 With WEBENCH® Power Designer

2 Applications

Automotive Electronic Systems
Infotainment Systems, Instrument Clusters, ADAS
High-Voltage Battery-Operated Systems

3 Description

The LM5143-Q1 is a 65-V synchronous buck DC/DC controller for high-current single or dual outputs. The device uses an interleaved, stackable, current-mode control architecture for easy loop compensation, fast transient response, excellent load and line regulation, and accurate current sharing with paralleled phases for higher output current. A high-side switch minimum on-time of 65 ns gives large step-down ratios, enabling the direct conversion from 12-V, 24-V, or 48-V automotive inputs to low-voltage rails for reduced system complexity and solution cost. The LM5143-Q1 continues to operate during input voltage dips as low as 3.5 V, at nearly 100% duty cycle if needed. Current is sensed using the inductor DCR for highest efficiency or an optional shunt resistor for high accuracy. The 15-μA no-load quiescent current with the output voltage in regulation extends operating run-time in battery-powered systems. Power the LM5143-Q1 from the output of the switching regulator or another available source for even lower input quiescent current and power loss. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LM5143-Q1 VQFN (40) 6.00 mm × 6.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. High-Efficiency Dual Step-Down Regulator

12.3 Receiving Notification of Documentation Updates 52

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES October 2018 * Initial release

5 Description (continued)

Several features are included to simplify compliance with CISPR 25 and automotive EMI requirements. Adaptively timed, high-current MOSFET gate drivers with adjustable slew rate control minimize body diode conduction during switching transitions, reducing switching losses and improving thermal and EMI performance at high input voltage and high switching frequency. To reduce input capacitor ripple current and EMI filter size, 180° interleaved operation is provided for two outputs. A 90° out-of-phase clock output works well for cascaded, multi-channel, or multi-phase power stages. Resistor-adjustable switching frequency as high as 2.2 MHz can be synchronized to an external clock source to eliminate beat frequencies in noise-sensitive applications. Optional spread spectrum modulation further improves the EMI signature. Additional features of the LM5143-Q1 include user-selectable diode emulation for lower current consumption at light-load conditions, configurable soft-start functions, open-drain Power-Good flags for fault reporting and output monitoring, independent enable inputs, monotonic start-up into prebiased loads, integrated VCC bias supply regulator, programmable hiccup-mode overload protection, and thermal shutdown protection with automatic recovery. The LM5143-Q1 controller comes in a 6-mm × 6-mm thermally-enhanced, 40-pin VQFN package with wettable flanks to facilitate optical inspection during manufacturing.

ADVANCE□INFORMATION Exposed Pad (EP) on Bottom Connect to Ground SS2 COMP1 SS1 FB1 PG1 HOL1 VIN COMP2 FB2 CS2 VOUT2 VCCX PG2 CS1 VOUT1 HOL2 HO2 SW2 HO1 SW1 HB1 LO2 LOL1 VCC PGND2 VCC LO1 PGND1 LOL2 HB2 RES EN1 DEMB RT DITH VDDA MODE AGND SYNCOUT EN2 LM5143-Q1 SNVSB29 –OCTOBER 2018 www.ti.com Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

6 Pin Configuration and Functions

40-Pin VQFN with Wettable Flanks Top View Connect Exposed Pad on bottom to AGND and PGND on the PCB.

ADVANCE□INFORMATION LM5143-Q1 www.ti.com SNVSB29 –OCTOBER 2018 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (1) P = Power, G = Ground, I = Input, O = Output. Pin Functions PIN I/O(1) DESCRIPTION NO. NAME

1 SS2 I

Channel 2 soft-start programming pin. An external ceramic capacitor and an internal 20-μA current source set the ramp rate of the internal error amplifier reference during soft-start. Pulling SS2 below 150 mV turns off the channel 2 gate driver outputs, but all the other functions remain active. 2 COMP2 O Output of the channel 2 transconductance error amplifier. COMP2 is high impedance in interleave or slave mode.

3 FB2 I

Feedback input of channel 2. Connect FB2 to VDDA for a 3.3-V output or connect FB2 to AGND for a fixed 5-V output. A resistive divider from VOUT2 to FB2 sets the output voltage level between 0.6 V and 55 V. The regulation threshold at FB2 is 0.6 V.

4 CS2 I

Channel 2 current sense amplifier input. Connect CS2 to the inductor side of the external current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used) using a low- current Kelvin connection.

5 VOUT2 I

Output voltage sense and the current sense amplifier input of channel 2. Connect VOUT2 to the output side of the channel 2 current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used). 6 VCCX P Optional input for an external bias supply. If VVCCX > 4.3 V, VCCX is internally connected to VCC and the internal VCC regulator is disabled. Connect a ceramic capacitor between VCCX and PGND. 7 PG2 O An open-collector output which goes low if VOUT2 is outside a specified regulation window. 8 HOL2 O Channel 2 high-side gate driver turnoff output. 9 HO2 O Channel 2 high-side gate driver turn-on output. 10 SW2 P Switching node of the channel 2 buck regulator. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET and the drain terminal of the low-side MOSFET. 11 HB2 P Channel 2 high-side driver supply for bootstrap gate drive. 12 LOL2 O Channel 2 low-side gate driver turnoff output. 13 LO2 O Channel 2 low-side gate driver turn-on output. 14 PGND2 G Power ground connection pin for low-side NMOS gate driver. 15, 16 VCC P VCC bias supply pin. Pins 15 and 16 must to be connected together on the PCB. Connect ceramic capacitors between VCC and PGND1 and between VCC and PGND2. 17 PGND1 G Power ground connection pin for low-side NMOS gate driver. 18 LO1 O Channel 1 low-side gate driver turnon output. 19 LOL1 O Channel 1 low-side gate driver turnoff output. 20 HB1 P Channel 1 high-side driver supply for bootstrap gate drive. 21 SW1 P Switching node of the channel 1 buck regulator. Connect to the channel 1 bootstrap capacitor, the source terminal of the high-side MOSFET and the drain terminal of the low-side MOSFET.

22 HO1 O Channel 1 high-side gate driver turnon output

23 HOL1 O Channel 1 high-side gate driver turnoff output. 24 PG1 O An open-collector output that goes low if VOUT1 is outside a specified regulation window. 25 VIN P Supply voltage input source for the VCC regulators.

26 VOUT1 I

Output voltage sense and the current sense amplifier input of channel 1. Connect VOUT1 to the output side of the channel 1 current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used).

27 CS1 I

Channel 1 current sense amplifier input. Connect CS1 to the inductor side of the external current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used) using a low- current Kelvin connection.

28 FB1 I

Feedback input of channel 1. Connect the FB1 pin to VDDA for a 3.3-V output or connect FB1 to AGND for a 5-V output. A resistive divider from VOUT1 to FB1 sets the output voltage level between 0.6 V and 55 V. The regulation threshold at FB1 is 0.6 V. 29 COMP1 O Output of the channel 1 transconductance error amplifier (EA).

30 SS1 I

Channel 1 soft-start programming pin. An external capacitor and an internal 20-μA current source set the ramp rate of the internal error amplifier reference during soft-start. Pulling the SS1 voltage below 150 mV turns off the channel 1 gate driver outputs, but the all the other functions remain active. 31 EN1 I An active high input (VOH > 2 V) enables Output 1. If Outputs 1 and 2 are disabled, the LM5143-Q1 is in shutdown mode unless a SYNC signal is present at DEMB. EN1 should never be floating.

32 RES O

Restart timer pin. An external capacitor configures the hiccup-mode current limiting. A capacitor at the RES pin determines the time the controller remains off before automatically restarting in hiccup mode. The two regulator channels operate independently. One channel may operate in normal mode while the other is in hiccup-mode overload protection. The hiccup mode commences when either channel experiences 512 consecutive PWM cycles with cycle-by-cycle current limiting. Connect RES to VDDA during power-up to disable hiccup-mode protection.

33 DEMB I

Diode Emulation pin. Connect DEMB to AGND to enable diode emulation mode. Connect DEMB to VDDA to operate the LM5143-Q1 in forced PWM (FPWM) mode with continuous conduction at light loads. DEMB can also be used as a synchronization input to synchronize the internal oscillator to an external clock.

34 MODE I

Connect MODE to AGND or VDDA for dual-output or interleaved single-output operation, respectively. This also configures the LM5143-Q1 with an EA transconductance of 1200 µS. Connecting a 10-kΩ resistor between MODE and AGND sets the LM5143-Q1 for dual-output operation with an ultra-low IQ mode and an EA transconductance of 60 µS. 35 AGND G Analog ground connection. Ground return for the internal voltage reference and analog circuits. 36 VDDA O Internal analog bias regulator output. Connect a ceramic decoupling capacitor from VDDA to AGND. 37 RT I Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 100 kHz and 2.2 MHz.

38 DITH I

A capacitor connected between the DITH pin and AGND is charged and discharged with a 20-µA current source. If dithering is enabled, the voltage on the DITH pin ramps up and down modulating the oscillator frequency between –5% and +5% of the internal oscillator. Connecting DITH to VDDA during power-up disables the dither feature. DITH is ignored if an external synchronization clock is used.

39 SYNCOUT O

SYNCOUT is a logic level signal with a rising edge approximately 90º lagging HO2 (or 90º leading HO1). When the SYNCOUT signal is used to synchronize a second LM5143-Q1 controller, all phases are 90º out of phase. 40 EN2 I An active high input (VOH > 2 V) enables Output 2. If Outputs 1 and 2 are disabled, the LM5143-Q1 is in shutdown mode unless a SYNC signal is present on DEMB. EN2 should never be floating.

6.1 Wettable Flanks

100% automated visual inspection (AVI) post-assembly is typically required to meet requirements for high reliability and robustness. Standard quad-flat no-lead (VQFN) packages do not have solderable or exposed pins and terminals that are easily viewed. It is therefore difficult to visually determine whether or not the package is successfully soldered onto the printed-circuit board (PCB). The wettable-flank process was developed to resolve the issue of side-lead wetting of leadless packaging. The LM5143-Q1 is assembled using a 40-pin VQFN package with wettable flanks to provide a visual indicator of solderability, which reduces the inspection time and manufacturing costs.

ADVANCE□INFORMATION LM5143-Q1 www.ti.com SNVSB29 –OCTOBER 2018 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)(1) MIN MAX UNIT Input voltage VIN to PGND –0.3 70 V SW1, SW2 to PGND –0.3 70 SW1, SW2 to PGND (20-ns transient) –5 HB1 to SW1, HB2 to SW1 –0.3 6.5 HB1 to SW1, HB2 to SW1 (20-ns transient) –5 HO1 to SW1, HOL1 to SW1, HO2 to SW2, HOL2 to SW2 –0.3 VHB + 0.3 HO1 to SW1, HOL1 to SW1, HO2 to SW2, HOL2 to SW2 (20-ns transient) –5 LO1, LOL1, LO2, LOL2 to PGND –0.3 VVCC + 0.3 LO1, LOL1, LO2, LOL2 to PGND (20-ns transient) –1.5 VVCC + 0.3 SS1, SS2, COMP1, COMP2, RES, RT, DITH to AGND –0.3 VVDDA + 0.3 EN1, EN2 to PGND –0.3 70 VCC, VCCX, VDDA, PG1, PG2, DEMB, FB1, FB2 to AGND –0.3 6.5 VOUT1, VOUT2, CS1, CS2 –0.3 60 VOUT1 to CS1, VOUT2 to CS2 –0.3 0.3 PGND to AGND –0.3 0.3 V Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –40 150 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC-Q100-002 (1) HBM ESD Classification Level 2 ±2000 V Charge device model (CDM), per AEC-Q100-011, CDM ESD Classification Level C4B Corner pins ±750 V Other pins ±500 V

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted). MIN NOM MAX UNIT VIN Input voltage range VIN to PGND –0.3 65 V SW1, SW2 to PGND –0.3 65 HB1 to SW1, HB2 to SW1 –0.3 5 5.25 HO1 to SW1, HOL1 to SW1, HO2 to SW2, HOL2 to SW2 –0.3 VHB + 0.3 LO1, LOL1, LO2, LOL2 to PGND –0.3 5 5.25 FB1, FB2, SS1, SS2, COMP1, COMP2, RES, DEMB, RT, DITH to AGND –0.3 5.25 EN1, EN2 to PGND –0.3 65 VCC, VDDA to PGND –0.3 5 5.25 VOUT1, VOUT2, CS1, CS2 to PGND –0.3 55 PGND to AGND –0.3 0.3 TJ Operating junction temperature –40 150 °C

ADVANCE□INFORMATION LM5143-Q1 SNVSB29 –OCTOBER 2018 www.ti.com Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.4 Thermal Information

THERMAL METRIC(1) LM5143-Q1 UNITRWG (VQFN)

40 PINS

RΘJA Junction-to-ambient thermal resistance 34.8 °C/W RΘJC(top) Junction-to-case (top) thermal resistance 22.8 °C/W RΘJB Junction-to-board thermal resistance 9.5 °C/W RΘJC(bot) Junction-to-case (bottom) thermal resistance 1.3 °C/W ΨJB Junction-to-board characterization parameter 9.4 °C/W ΨJT Junction-to-top characterization parameter 0.3 °C/W

7.5 Electrical Characteristics

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted), Typical values correspond to TJ = 25℃, VVIN = 12 V, VVCCX = 5 V, VVOUT1 = 3.3 V, VVOUT2 = 5 V, VEN1 = VEN2 = 5 V, RRT = 10 kΩ, FSW = 2.2 MHz, no-load on the drive outputs (HO1, HOL1, LO1, LOL1, HO2, HOL2, LO2, and LOL2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT VOLTAGE (VIN) ISHUTDOWN Shutdown mode current VIN = 12 V, VEN1 = VEN2 = 0 V 4 7 µA ISTANDBY1 Standby current, channel 1 VIN = 12 V, VEN1 = 5 V, VEN2 = 0V, VVOUT1 =

3.3 V, in regulation, no-load, not switching,

DEMB = MODE = GND 25 31 µA ISTANDBY2 Standby current, channel 2 VIN = 12 V, VEN1 = 0V, VEN2 = 5V, VVOUT2 = 5 V, in regulation, no-load, not switching, DEMB = MODE = AGND 35 43 µA ISTANDBY3 Standby current, channel 1, ultra-low IQ mode VIN = 12 V, VEN1 = 5 V, VEN2 = 0 V, VVOUT1 = DEMB = GND, RMODE = 10 kΩ to GND 15 21 µA ISTANDBY4 Standby current, channel 2, ultra-low IQ mode VIN = 12 V, VEN1 = 0 V, VEN2 = 5 V, VVOUT2 =

5 V, in regulation, no-load, not switching,

DEMB = GND, RMODE = 10 kΩ to AGND 25 33 µA BIAS REGULATOR (VCC) VVCC-REG VCC regulation voltage VVIN = 6 V to 18 V, IVCC = 0 to 170 mA, VVCCX = 0 V 4.75 5 5.25 V VCC-UVLO VCC UVLO rising threshold VVCC rising 3.2 3.3 3.4 V VVCC-HYST VCC UVLO hysteresis 90 mV IVCC-LIM VCC sourcing current limit 170 250 mA ANALOG BIAS (VDDA) VVDDA-REG VDDA regulation voltage 4.75 5 5.25 V VVDDA-UVLO VDDA UVLO rising threshold VVCC rising, VVCCX = 0 V 3.1 3.2 3.3 V VVDDA-HYST VDDA UVLO hysteresis VVCCX = 0 V 90 mV RVDDA VDDA resistance VVCCX = 0 V 50 Ω EXTERNAL BIAS (VCCX) VVCCX-ON VCCX(ON) rising threshold 4.1 4.3 4.4 V RVCCX VCCX resistance VVCCX = 5 V 1 Ω VVCCX-HYST VCCX hysteresis voltage 200 mV CURRENT LIMIT (CS1, CS2) VCS1 Current limit threshold 1 Measured from CS1 to VOUT1 66 73 80 mV VCS2 Current limit threshold 2 Measured from CS2 to VOUT2 66 73 80 mV TCS-DELAY CS delay to output 40 ns GCS CS amplifier gain 11.4 12 12.6 V/V ICS-BIAS CS amplifier input bias current 0 10 nA

ADVANCE□INFORMATION LM5143-Q1 www.ti.com SNVSB29 –OCTOBER 2018 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted), Typical values correspond to TJ = 25℃, VVIN = 12 V, VVCCX = 5 V, VVOUT1 = 3.3 V, VVOUT2 = 5 V, VEN1 = VEN2 = 5 V, RRT = 10 kΩ, FSW = 2.2 MHz, no-load on the drive outputs (HO1, HOL1, LO1, LOL1, HO2, HOL2, LO2, and LOL2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER GOOD (PG1, PG2) PG1UV PG1 UV trip level Falling with respect to the regulation voltage 90% 92% 94% PG2UV PG2 UV trip level Falling with respect to the regulation voltage 90% 92% 94% PG1OV PG1 OV trip level Rising with respect to the regulation voltage 108% 110% 112% PG2OV PG2 OV trip level Rising with respect to the regulation voltage 108% 110% 112% PG1UV-HYST PG1 UV hysteresis Rising with respect to the regulation voltage 3.4% PG1OV-HYST PG1 OV hysteresis Rising with respect to the regulation voltage 3.4% PG2UV-HYST PG2 UV hysteresis Rising with respect to the regulation voltage 3.4% PG2OV-HYST PG2 OV hysteresis Rising with respect to the regulation voltage 3.4% VOL-PG1 PG1 voltage Open collector, IPG1 = 2 mA 0.4 V VOL-PG2 PG2 voltage Open collector, IPG2 = 2 mA 0.4 V tPG-RISE-DLY OV filter time VOUT rising 25 µs tPG-FALL-DLY UV filter time VOUT falling 25 µs HIGH-SIDE GATE DRIVER (HO1, HO2, HOL1, HOL2) VHO-LOW HO low-state output voltage IHO = 100 mA 0.05 V VHO-HIGH HO high-state output voltage IHO = –100 mA, VHO-HIGH = VHB – VHO 0.07 V tHO-RISE HO rise time (10% to 90%) CLOAD = 2700 pF 4 ns tHO-FALL HO fall time (90% to 10%) CLOAD = 2700 pF 3 ns IHO-SRC HO peak source current VHO = VSW = 0 V, VHB = 5 V, VVCCX = 5 V 3.25 A IHO-SINK HO peak sink current VVCCX = 5 V 4.25 A VBT-UV BOOT UVLO VVCC falling 2.5 V VBT-UV-HYS BOOT UVLO hysteresis 110 mV IBOOT BOOT quiescent current 3 µA LOW-SIDE GATE DRIVER (LO1, LO2, LOL1, LOL2) VLO-LOW LO low-state output voltage IHO = 100 mA 0.05 V VLO-HIGH LO high-state output voltage IHO = –100 mA 0.07 V tLO-RISE LO rise time (10% to 90%) CLOAD = 2.7 nF 4 ns tLO-FALL LO fall time (90% to 10%) CLOAD = 2.7 nF 3 ns ILO-SOURCE LO peak source current VHO = VSW = 0 V, VHB = 5 V, VVCCX = 5 V 3.25 A ILO-SINK LO peak sink current VVCCX = 5 V 4.25 A RESTART (RES) IRES-SRC RES current source 20 µA VRES-TH RES threshold 1.2 V HICCYCLES HICCUP mode fault 512 cycles RRES-PD RES pull-down resistance 5 Ω OUTPUT VOLTAGE SETPOINT (VOUT1, VOUT2) VOUT50 5 V output voltage setpoint VFB = 5 V, VIN = 5.2 V to 65 V 4.95 5 5.05 V

ADVANCE□INFORMATION LM5143-Q1 SNVSB29 –OCTOBER 2018 www.ti.com Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted), Typical values correspond to TJ = 25℃, VVIN = 12 V, VVCCX = 5 V, VVOUT1 = 3.3 V, VVOUT2 = 5 V, VEN1 = VEN2 = 5 V, RRT = 10 kΩ, FSW = 2.2 MHz, no-load on the drive outputs (HO1, HOL1, LO1, LOL1, HO2, HOL2, LO2, and LOL2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FEEDBACK (FB1, FB2) VFB-3V3-SEL VOUT select threshold 3.3-V output VVDDA – 0.3 V RFB-5V Resistance FB to AGND for 5-V output VMODE = 0 V or RMODE = 10 kΩ 500 Ω RFB-EXTRES Thevenin equivelent resistance VMODE = 0 V or RMODE = 10 kΩ, VFB < 2 V 5 10 kΩ VFB2-LOW Master mode select logic level low MODE = VDDA 0 0.8 V VFB2-HIGH Master mode select logic level high MODE = VDDA 2 V VFB1-LOW Diode emulation logic level low in slave mode MODE = FB2 = VDDA 0 0.8 V VFB1-HIGH Diode emulation logic level high in slave mode MODE = FB2 = VDDA 2 V VFB-REG Regulated feedback voltage TJ = –40°C to 125°C 0.594 0.6 0.606 V ERROR AMPLIFIER (COMP1, COMP2) gm1 EA transconductance FB to COMP, RMODE < 5 kΩ to AGND 1020 1200 µS gm2 EA transconductance, ultra-low IQ mode MODE = GND, RMODE = 10 kΩ 60 µS IFB Error amplifier input bias current 15 nA VCOMP-CLMP COMP clamp voltage VFB = 0 V 2 V ICOMP-SLAVE COMP leakage, slave mode VCOMP = 1 V, MODE = FB2 = VCC 10 nA ICOMP-INTLV COMP2 leakage, Imode VCOMP = 1 V, MODE = VCC, VFB2 = 0 V 10 nA ICOMP-SRC1 EA source current VCOMP = 1 V, VFB = 0.4 V, VMODE = 0 V 100 µA ICOMP-SINK1 EA sink current VCOMP = 1 V, VFB = 0.8 V, VMODE = 0 V 100 µA ICOMP-SRC2 EA source current, ultra-low IQ mode VCOMP = 1 V, VFB = 0.4 V, RMODE = 10 kΩ to AGND 10 µA ICOMP-SINK2 EA sink current, ultra-low IQ mode VCOMP = 1 V, VFB = 0.8 V, RMODE = 10 kΩ to AGND 10 µA VSS-OFFSET EA SS offset with VFB = 0 V Raise VSS until VCOMP > 300 mV 35 mV ADAPTIVE DEADTIME CONTROL VGS-DET VGS detection threshold VGS falling, no-load 2.5 V tDEAD1 HO off to LO on deadtime 20 ns tDEAD2 LO off to HO on deadtime 15 ns DIODE EMULATION (DEMB) VDEMB-LOW DEMB input low threshold 0.8 V VDEMB_HIGH DEMB input high threshold 2 V VZC-SW Zero-cross threshold VDEMB = 0 V –5 mV VZC-SS Zero-cross threshold soft-start DEMB = VCC,

50 SW cycles after first HO pulse –5 mV

VZC-DIS Zero-cross threshold disabled DEMB = VCC,

1000 SW cycles after first HO pulse 200 mV

ENABLE (EN1, EN2) VEN-LOW EN1/2 low threshold VVCCX = 0 V 0.8 V VEN-HIGH-TH EN1/2 high threshold VVCCX = 0 V 2 V IEN-LEAK EN1/2 leakage currernt EN1, EN2 logic inputs only 1 µA

ADVANCE□INFORMATION LM5143-Q1 www.ti.com SNVSB29 –OCTOBER 2018 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted), Typical values correspond to TJ = 25℃, VVIN = 12 V, VVCCX = 5 V, VVOUT1 = 3.3 V, VVOUT2 = 5 V, VEN1 = VEN2 = 5 V, RRT = 10 kΩ, FSW = 2.2 MHz, no-load on the drive outputs (HO1, HOL1, LO1, LOL1, HO2, HOL2, LO2, and LOL2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SWITCHING FREQUENCY (RT) VRT RT regulation voltage 10 kΩ < RRT < 220 kΩ 0.8 V MODE RMODE-HIGH Resistance to AGND for ultra-low IQ 5 kΩ RMODE-LOW Resistance to AGND for normal IQ 0 500 Ω VMODE-LOW Non-interleaved mode input low threshold 0 0.8 V VMODE-HIGH Interleaved mode input high threshold 2 V SYNCHRONIZATION INPUT (SYNCIN) VDEMB-LOW DEMB input low threshold 0 0.8 V VDEMB-HIGH DEMB input high threshold 2 V tSYNC-MIN DEMB minimum pulse width VMODE = 0 V or RMODE = 10 kΩ 50 250 ns FSYNCIN External SYNC frequency range VIN = 8 V to 18 V, % of the nominal frequency set by RRT –20% 20% tSYNCIN-HO1 Delay from DEMB rising to HO1 rising edge 100 ns tSYNCIN- SLAVE Delay from DEMB falling edge to HO2 rising edge Slave mode, MODE = FB2 = VCC 100 ns tDEMB-FILTER Delay from DEMB low to diode emulation enable VMODE = 0 V or RMODE = 10 kΩ 15 50 µs tAWAKE- FILTER Maximum SYNC period to maintain standby state VEN1 = VEN2 = 0 V 40 µs SYNCHRONIZATION OUTPUT (SYNCOUT) VSYNCOUT-HI SYNCOUT high-state voltage ISYNCOUT = –16 mA, VVCC = 5 V 2 V VSYNCOUT- LO SYNCOUT low-state voltage ISYNCOUT = 16 mA 0.8 V FSYNCOUT SYNCOUT frequency MODE = FB2 = VDDA 0 Hz tSYNCOUT1 Delay from HO2 rising edge to SYNCOUT rising edge VDEMB = 0 V, TS = 1/FSW, FSW set by RRT TS/4 – 100 ns tSYNCOUT2 Delay from HO2 rising edge to SYNCOUT falling edge VDEMB = 0 V, TS = 1/FSW, FSW set by RRT 3TS/4 – 100 ns DITHER (DITH) IDITH Dither source/sink current 20 µA VDITH-HIGH Dither high-level threshold 1.26 V Dither low-level threshold 1.14 V SOFT START (SS1, SS2) ISS Soft-start current VMODE = 0 V 14 20 26 µA RSS-PD Soft-start pull-down resistance VMODE = 0 V 3 Ω VSS-FB SS to FB clamp voltage VCS – VOUT > 73 mV 125 mV ISS-SLAVE SS leakage, slave mode VSS = 0.8 V, MODE = FB2 = VDDA 10 nA ISS-INTLV SS2 leakage, interleaved mode VSS = 0.8 V, MODE = VDDA, VFB2 = 0 V 10 nA THERMAL SHUTDOWN TSHD Thermal shutdown 175 °C TSHD-HYS Thermal shutdown hysteresis 15 °C

7.6 Switching Characteristics

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted). Typical values correspond to TJ = 25℃, VVIN = 12 V, VVCCX = 5 V, VVOUT1 = 3.3 V, VVOUT2 = 5 V, VEN1 = VEN2 = 5 V, RRT = 10 kΩ, FSW = 2.2 MHz, no-load on the gate driver outputs (HO1, HOL1, LO1, LOL1, HO2, HOL2, LO2, and LOL2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FSW1 Switching frequency 1 RRT = 100 kΩ 218 220 242 kHz FSW2 Switching frequency 2 RRT = 10 kΩ 2.2 MHz FSW3 Switching frequency 3 RRT = 220 kΩ 100 kHz SLOPE1 Internal slope compensation 1 FSW = 220 kHz 64 mV/µs SLOPE2 Internal slope compensation 2 FSW = 2.2 MHz 557 mV/µs tON(min) Minimum on-time 65 80 ns tOFF(min) Minimum off-time 60 100 ns PHHO1-HO2 Phase between HO1 and HO2 DEMB = MODE = AGND 180 °

8 Detailed Description

8.1 Overview

The LM5143-Q1 is a dual-phase or dual-channel switching controller that features all of the functions necessary to implement a high-efficiency synchronous buck power supply operating over a wide input voltage range from 3.5 V to 65 V. The LM5143-Q1 is configured to provide a fixed 3.3-V or 5-V output, or an adjustable output between 0.6 V to 55 V. This easy-to-use controller integrates high-side and low-side MOSFET drivers capable of sourcing 3.25-A and sinking 4.25-A peak current. Adaptive dead-time control is designed to minimize body diode conduction during switching transitions. Current-mode control using a shunt resistor or inductor DCR current sensing provides inherent line feedforward, cycle-by-cycle peak current limiting, and easy loop compensation. It also supports a wide duty cycle range for high input voltage and low dropout applications as well as when a high voltage conversion ratio (for example, 10- to-1) is required. The oscillator frequency is user-programmable between 100 kHz to 2.2 MHz, and the frequency can be synchronized as high as 2.5 MHz by applying an external clock to DEMB. An external bias supply can be connected to VCCX to maximize efficiency in high input voltage applications. A user-selectable diode emulation feature enables discontinuous conduction mode (DCM) operation to further improve efficiency and reduce power dissipation during light-load conditions. Fault protection features include current limiting, thermal shutdown, UVLO and remote shutdown capability. The LM5143-Q1 incorporates features to simplify the compliance with automotive EMI requirements (CISPR 25). An optional spread spectrum frequency modulation (SSFM) technique reduces the peak EMI signature, while the adaptive gate drivers with slew rate control minimize high-frequency emissions. Finally, 180° out-of-phase interleaved operation of the two controller channels reduces input filtering and capacitor requirements. The LM5143-Q1 is provided in a 40-pin VQFN package with wettable flank pinout and an exposed pad to aid in thermal dissipation.

ADVANCE□INFORMATION 800mV RT amp BIAS PLL & OSCILLATORS CLK1 CLK2 VDDA CONTROL HICCUP FAULT TIMER

512 CYCLES

VREF 0.6V VREF 20PA GAIN = 12 SLOPE COMP RAMP PWM1/2 STANDBY LEVEL SHIFT ADAPTIVE DEADTIME CLK1/2 DEM/FPWM CURRENT LIMIT HB1/2 UVLO PG DELAY 25Ps PGUV PGOV ILIM1/2 ILIM1/2 COMMON CHANNEL 1/2 0.660V 0.552V 75mV FB DECODER /MUX 3.3V SS1/2 SS1/2 ERROR AMPLIFER HICCUP1/2 FB1/2 150mV Q Q R S DECODER INTERLEAVE HB1 Copyright © 2018, Texas Instruments Incorporated MODE DITH SYNCOUT DEMB/ SYNCIN RT HO1/2 HOL1/2 SW1/2 LO1/2 LOL1/2 PGND1/2 VCC PG1/2 COMP1/2 SS1/2 FB1/2 VOUT1/2 CS1/2 EN1/2 AGND RES VDDA VCC VCCX VIN 20PA ULIQ DEM/FPWM INTERLEAVE COMP1/2 ENABLE GM 125mV ILIM1/2 20PA 20PA VOUT1 ULIQ LM5143-Q1 SNVSB29 –OCTOBER 2018 www.ti.com Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Input Voltage Range (VIN)

Figure 1. Dual-Output Regulator Schematic Diagram With Input Voltage Operating Range of 3.5 V to 65 V input bypass capacitors to minimize voltage overshoot and ringing. V/s ramp rate. VCC does not come up in this condition.

8.3.2 High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA)

voltage tracks VIN minus a small voltage drop. recommended range for each VCC capacitor is from 2.2 µF to 10 µF.

ADVANCE□INFORMATION SW IN(min) OUT SW OFF(min) tV V t t RT SW 22R k F MHz: ª º ¬ ¼ ª º ¬ ¼ LM5143-Q1 SNVSB29 –OCTOBER 2018 www.ti.com Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Feature Description (continued) An internal 5-V linear regulator generates the VDDA bias supply. Bypass VDDA with a 470-nF or greater ceramic capacitor to make sure a low-noise internal bias rail. Normally VDDA is 5 V, but there are two operating conditions where it regulates at 3.3 V. The first is in skip cycle mode with VOUT1 set to 3.3 V and VOUT2 disabled. The second is in a cold-crank start-up where VIN is 3.8 V and VOUT1 is 3.3 V. Internal power dissipation of the VCC regulator can be minimized by connecting VCCX to a 5-V output at VOUT1 or VOUT2 or to an external 5-V supply. If the VCCX voltage is above 4.3 V, VCCX is internally connected to VCC and the internal VCC regulator is disabled. Tie VCCX to AGND if it is unused. Never connect VCCX to a voltage greater than 6.5 V or less than –0.3 V. If an external supply is connected to VCCX to power the LM5143- Q1, VIN must be greater than the external bias voltage to avoid damage to the controller.

8.3.3 Enable (EN1, EN2)

The LM5143-Q1 contains two enable inputs. EN1 and EN2 facilitate independent start-up and shutdown control of VOUT1 and VOUT2. The enable pins can be connected to a voltage as high as 70 V. If an enable input is greater than 2 V, its respective output is enabled. If an enable pin is pulled below 0.4 V, the output is shutdown. If both outputs are disabled, the LM5143-Q1 is in a low-IQ shutdown mode with a 4-µA typical current drawn from VIN. TI does not recommend leaving EN1 or EN2 floating.

8.3.4 Power Good Monitor (PG1, PG2)

The LM5143-Q1 includes output voltage monitoring signals for VOUT1 and VOUT2 to simplify sequencing and supervision. The power-good function can be used to enable circuits that are supplied by the corresponding voltage rail or to turn on sequenced supplies. Each power-good output (PG1 and PG2) switches to a high impedance open-drain state when the corresponding output voltage is in regulation. Each output switches low when the corresponding output voltage drops below the lower power-good threshold (92% typical) or rises above the upper power-good threshold (110% typical). A 25-µs deglitch filter prevents false tripping of the power-good signals due to transients. TI recommends pullup resistors of 10 kΩ (typical) from PG1 and PG2 to the relevant logic rail. PG1 and PG2 are asserted low during soft start and when the corresponding buck converter is disabled by EN1 or EN2.

8.3.5 Switching Frequency (RT)

The LM5143-Q1 oscillator is programmed by a resistor between RT and AGND to set an oscillator frequency between 100 kHz to 2.2 MHz. CLK1 is the clock for channel 1 and CLK2 is for channel 2. CLK1 and CLK2 are 180º out of phase. Calculate the RT resistance for a given switching frequency using Equation 1. (1) Under low VIN conditions when either of the high-side MOSFET's on-time exceeds the programmed oscillator period, the LM5143-Q1 extends the switching period of that channel until the PWM latch is reset by the current sense ramp exceeding the controller compensation voltage. In such an event, the oscillators (CLK1 and CLK2) operate independently and asynchronously until both channels can maintain output regulation at the programmed frequency. The approximate input voltage level where this occurs is given by Equation 2, where tSW is the switching period and tOFF(min) is the minimum off-time of 60 ns. (2)

8.3.6 Clock Synchronization (DEMB)

To synchronize the LM5143-Q1 to an external source, apply a logic-level clock signal (greater than 2 V) to DEMB. The LM5143-Q1 can be synchronized to ±20% of the programmed frequency up to a maximum of 2.5 MHz. If there is an RT resistor and a synchronization signal, the LM5143-Q1 ignores the RT resistor and synchronizes to the external clock. Under low VIN conditions when the minimum off-time is reached, the synchronization signal is ignored, allowing the switching frequency to reduce to maintain output voltage regulation.

1.26 V (+5%)

1.14 V (±5%)

8.3.7 Synchronization Out (SYNCOUT)

8.3.8 Spread Spectrum Frequency Modulation (DITH)

Figure 2. Switching Frequency Dithering

8.3.9 Configurable Soft-Start (SS1, SS2)

supply rail is also reduced. The LM5143-Q1 regulates the FB voltage to the SS voltage or the internal 600-mV reference, whichever is lower. tSS is the required soft-start time. LO gate driver is disabled when the LM5143-Q1 pulls SS low internally due to a fault condition.

8.3.10 Output Voltage Setpoint (FB1, FB2)

connecting FB to AGND. The FB1 and FB2 connections (either VDDA or GND) are detected during power up. VCC voltage decreasing below its falling UVLO threshold) and then powered up again. The recommended starting value for RFB2 is between 10 kΩ and 20 kΩ. Figure 3. Control Loop Error Amplifier for the LM5143-Q1 to detect the divider and set the channel to the adjustable output mode.

ADVANCE□INFORMATION OUT S O-IDEAL SW V (V) R (m )L (

24 F (MHz)

: 5 V 65ns 2.1MHz24 V 0.208 0.137 ! OUT ON(min) SW IN V t F V ! LM5143-Q1 www.ti.com SNVSB29 –OCTOBER 2018 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Feature Description (continued) If one output is enabled and the other disabled, the VCC output is in regulation. The HB voltage of the disabled channel charges to VCC through the bootstrap diode. As a result, the HO driver bias current (approximately 1.5 µA) can charge the disabled channel output to approximately 2.2 V. If this is not desired, add a load resistor (100 kΩ) to the output that is disabled to maintain a low-voltage OFF-state.

8.3.11 Minimum Controllable On-Time

There are two limitations to the minimum output voltage adjustment range: the LM5143-Q1 voltage reference of 0.6 V and the minimum controllable switch-node pulse width, tON(min). tON(min) effectively limits the voltage step-down conversion ratio VOUT/VIN at a given switching frequency. For fixed-frequency PWM operation, the voltage conversion ratio must satisfy Equation 8. where

tON(min) is 65 ns (typical);
FSW is the switching frequency. (8) If the desired voltage conversion ratio does not meet the above condition, the LM5143-Q1 transitions from fixed switching frequency operation to a pulse-skipping mode in order to maintain output voltage regulation. For example, if the desired output voltage is 5 V with an input voltage is 24 V and switching frequency of 2.1 MHz, the voltage conversion ratio test in Equation 9 is satisfied. (9) For wide VIN applications and low output voltages, an alternative is to reduce the LM5143-Q1 switching frequency to meet the requirement of Equation 8.

8.3.12 Error Amplifier and PWM Comparator (FB1, FB2, COMP1, COMP2)

Each channel of the LM5143-Q1 has an independent high-gain transconductance amplifier that generates an error current proportional to the difference between the feedback voltage and an internal precision reference (0.6 V). The output of the transconductance amplifier is connected to the COMP pin, allowing the user to provide external control loop compensation. A type-II compensation network is generally recommended for peak current- mode control. The amplifier has two gain settings, one is for normal operation with a gm of 1200 µS and the other is for ultra- low IQ with a gm of 60 µS. For normal operation connect MODE to AGND. For ultra-low IQ connect MODE to AGND through a 10 kΩ resistor.

8.3.13 Slope Compensation

The LM5143-Q1 provides internal slope compensation for stable operation with peak current-mode control and a duty cycle greater than 50%. Calculate the buck inductance to provide a slope compensation contribution equal to one times the inductor downslope using Equation 10. (10)

A lower inductance value generally increases the peak-to-peak inductor current, which minimizes size and cost, and improves transient response at the cost of reduced light-load efficiency due to higher cores losses and peak currents.
A higher inductance value generally decreases the peak-to-peak inductor current, which increases the full- load efficiency by reducing switch peak and RMS currents at the cost of requiring larger output capacitors to meet load-transient specifications.

8.3.14 Inductor Current Sense (CS1, VOUT1, CS2, VOUT2)

inductor (DCR current sensing).

8.3.14.1 Shunt Current Sensing

the inductor and the output, with a Kelvin connection to the LM5143-Q1 current sense amplifier. current limit comparator immediately terminates the applicable HO output for cycle-by-cycle current limiting. Calculate the shunt resistance using Equation 11.

VCS is current sense threshold of 73 mV;
IOUT(CL) is the overcurrent setpoint that is set higher than the maximum load current to avoid tripping the overcurrent comparator during load transients;
ΔIL is the peak-peak inductor ripple current. (11)

Figure 4. Shunt Current Sensing Implementation The respective SS voltage is clamped 150 mV above FB during an overcurrent condition for each channel. low during brief overcurrent events, preventing output voltage overshoot during recovery.

8.3.14.2 Inductor DCR Current Sensing

Figure 5. Inductor DCR Current Sensing Implementation

RCSCCS > LO/RDCR → the DC level is correct, but the AC amplitude is attenuated.
RCSCCS < LO/RDCR → the DC level is correct, but the AC amplitude is amplified. (12) Choose the CCS capacitance greater than or equal to 0.1 μF to maintain a low-impedance sensing network, thus reducing the susceptibility of noise pickup from the switch node. Carefully observe the Layout Guidelines to make sure that noise and DC errors do not corrupt the differential current sense signals applied between the CS and VOUT pins.

8.3.15 Hiccup Mode Current Limiting (RES)

1.2 V RES Threshold

Figure 6. Hiccup Mode Timing Diagram Calculate the RES capacitance using Equation 13, where tRES is the specified hiccup delay as shown in Figure 6.

8.3.16 High-Side and Low-Side Gate Drivers (HO1/2, LO1/2, HOL1/2, LOL1/2)

ceramic capacitor connected with short traces between the applicable HB and SW pins. CBST in Figure 7 according to Equation 14.

QG is the total gate charge of the high-side MOSFET at the applicable gate drive voltage;
ΔVBST is the voltage variation of the high-side MOSFET driver after turnon. (14) To determine CBST, choose ΔVBST so that the available gate drive voltage is not significantly impacted. An acceptable range of ΔVBST is 100 mV to 300 mV. The bootstrap capacitor must be a low-ESR ceramic capacitor, typically 0.1 µF. Use high-side and low-side MOSFETs with logic level gate threshold voltages.

Figure 7. Integrated MOSFET Gate Drivers

8.3.17 Output Configurations (MODE, FB2)

8.3.17.1 Independent Dual-Output Operation

AGND for independent outputs. Table 1. Output Voltage Settings Figure 8. Regulator Schematic Configured for Independent Dual Outputs

8.3.17.2 Single-Output Interleaved Operation

0.6 V to 55 V. See Table 2 and Figure 9. Table 2. Single-Output Interleaved Operation Figure 9. Two-Phase Regulator Schematic Configured for Single-Output Interleaved Operation

8.3.17.3 Single-Output Multiphase Operation

To configure the LM5143-Q1 for multiphase operation (3 or 4 phases), two LM5143-Q1 controllers are required. disable a phase and then try to re-enable the phase, it will not start-up. Table 3. Single-Output Multiphase Operation

Figure 10. Multiphase Regulator Schematic Configured for Single-Output Interleaved Operation

8.4 Device Functional Modes

8.4.1 Standby Modes

programmed for diode emulation (VDEMB < 0.4 V). channel 1 set to 3.3 V and the second channel disabled.

8.4.2 Diode Emulation Mode

disadvantage being slower light-load transient response. DCM to CCM operation provides monotonic start-up performance. Table 4. DEMB Settings

8.4.3 Thermal Shutdown

Turns off the high-side and low-side MOSFETs.
Pulls SS1/2 and PG1/2 low.
Turns off the VCC regulator.
Initiates a soft-start sequence when the die temperature decreases by the thermal shutdown hysteresis of

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LM5143-Q1 is a synchronous buck controller used to convert a higher input voltage to two lower output voltages. The following sections discuss the design procedure for a dual-output implementation using a specific circuit design example. To expedite and streamline the process of designing of a LM5143-Q1-based regulator, a comprehensive LM5143-Q1 Quickstart Calculator is available for download to assist the designer with component selection for a given application.

9.1.1 Power Train Components

A comprehensive understanding of the buck regulator power train components is critical to successfully completing a synchronous buck regulator design. The following section discuss the output inductor, input and output capacitors, power MOSFETs, and EMI input filter.

9.1.1.1 Buck Inductor

For most applications, choose a buck inductance such that the inductor ripple current, ΔIL, is between 30% to 50% of the maximum DC output current at nominal input voltage. Choose the inductance using Equation 15 based on a peak inductor current given by Equation 16. (15) (16) Check the inductor data sheet to make sure that the saturation current of the inductor is well above the peak inductor current of a particular design. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can then concentrate on copper loss and preventing saturation. Low inductor core loss is evidenced by reduced no-load input current and higher light-load efficiency. However, ferrite core materials exhibit a hard saturation characteristic and the inductance collapses abruptly when the saturation current is exceeded. This results in an abrupt increase in inductor ripple current, higher output voltage ripple, not to mention reduced efficiency and compromised reliability. Note that the saturation current of an inductor generally decreases as its core temperature increases. Of course, accurate overcurrent protection is key to avoiding inductor saturation.

9.1.1.2 Output Capacitors

Ordinarily, the output capacitor energy store of the regulator combined with the control loop response are prescribed to maintain the integrity of the output voltage within the dynamic (transient) tolerance specifications. The usual boundaries restricting the output capacitor in power management applications are driven by finite available PCB area, component footprint and profile, and cost. The capacitor parasitics— equivalent series resistance (ESR) and equivalent series inductance (ESL)— take greater precedence in shaping the load transient response of the regulator as the load step amplitude and slew rate increase. The output capacitor, COUT, filters the inductor ripple current and provides a reservoir of charge for step-load transient events. Typically, ceramic capacitors provide extremely low ESR to reduce the output voltage ripple and noise spikes, while tantalum and electrolytic capacitors provide a large bulk capacitance in a relatively compact footprint for transient loading events. Based on the static specification of peak-to-peak output voltage ripple denoted by ΔVOUT, choose an output capacitance that is larger than that given by Equation 17.

8 F V R I

adds to the surplus of charge in the output capacitor that must be depleted as quickly as possible. Figure 11. Load Transient Response Representation Showing COUT Charge Surplus or Deficit capacitance can be advantageously employed to absorb the excess charge and minimize the voltage overshoot. significantly with applied DC voltage and operating temperature.

ADVANCE□INFORMATION OUT IN SW IN ESR OUT D 1 D IC F V R I t ' OUT IN OUT ESR SW IN I D 1 DV I R F C ' 2 L CIN,rms OUT II D I 1 D 12 © ¹ LM5143-Q1 www.ti.com SNVSB29 –OCTOBER 2018 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Application Information (continued) Ignoring the ESR term in Equation 17 gives a quick estimation of the minimum ceramic capacitance necessary to meet the output ripple specification. Two to four 47-µF, 10-V, X7R capacitors in 1206 or 1210 footprint is a common choice for a 5-V output. Use Equation 18 to determine if additional capacitance is necessary to meet the load-off transient overshoot specification. A composite implementation of ceramic and electrolytic capacitors highlights the rationale for paralleling capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range. While the ceramic provides excellent mid- and high-frequency decoupling characteristics with its low ESR and ESL to minimize the switching frequency output ripple, the electrolytic device with its large bulk capacitance provides low-frequency energy storage to cope with load transient demands.

9.1.1.3 Input Capacitors

Input capacitors are necessary to limit the input ripple voltage to the buck power stage due to switching- frequency AC currents. TI recommends using X7S or X7R dielectric ceramic capacitors to provide low impedance and high RMS current rating over a wide temperature range. To minimize the parasitic inductance in the switching loop, position the input capacitors as close as possible to the drain of the high-side MOSFET and the source of the low-side MOSFET. The input capacitor RMS current for a single-channel buck regulator is given by Equation 19. (19) The highest input capacitor RMS current occurs at D = 0.5, at which point the RMS current rating of the input capacitors should be greater than half the output current. Ideally, the DC component of input current is provided by the input voltage source and the AC component by the input filter capacitors. Neglecting inductor ripple current, the input capacitors source current of amplitude (IOUT − IIN) during the D interval and sinks IIN during the 1−D interval. Thus, the input capacitors conduct a square-wave current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive component of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, the peak-to-peak ripple voltage amplitude is given by Equation 20. (20) The input capacitance required for a particular load current, based on an input voltage ripple specification of ΔVIN, is given by Equation 21. (21) Low-ESR ceramic capacitors can be placed in parallel with higher valued bulk capacitance to provide optimized input filtering for the regulator and damping to mitigate the effects of input parasitic inductance resonating with high-Q ceramics. One bulk capacitor of sufficiently high current rating and four 10-μF 50-V X7R ceramic decoupling capacitors are usually sufficient for 12-V battery automotive applications. Select the input bulk capacitor based on its ripple current rating and operating temperature range. Of course, a two-channel buck regulator with 180° out-of-phase interleaved switching provides input ripple current cancellation and reduced input capacitor current stress. The above equations represent valid calculations when one output is disabled and the other output is fully loaded.

9.1.1.4 Power MOSFETs

The choice of power MOSFETs has significant impact on DC/DC regulator performance. A MOSFET with low on- state resistance, RDS(on), reduces conduction loss, whereas low parasitic capacitances enable faster transition times and reduced switching loss. Normally, the lower the RDS(on) of a MOSFET, the higher the gate charge and output charge (QG and QOSS respectively), and vice versa. As a result, the product of RDS(on) and QG is commonly specified as a MOSFET figure-of-merit. Low thermal resistance makes sure that the MOSFET power dissipation does not result in excessive MOSFET die temperature.

near minimum input voltage, make sure that the MOSFET RDS(on) is rated for the available gate drive voltage. (2) D' = 1–D is the duty cycle complement. relevant driver resistance of the LM5143-Q1. the low-side MOSFET. Eoss1, the energy of Coss1, is dissipated at turnon, but this is offset by the stored energy Eoss2 on Coss2.

RDS(on) at VGS = 5 V.
Drain-source voltage rating, BVDSS, typically 40 V, 60 V or 80 V, depending on the maximum input voltage.
Gate charge parameters at VGS = 4.5 V.
Output charge, QOSS, at the relevant input voltage.
Body diode reverse recovery charge, QRR.
Gate threshold voltage, VGS(th), derived from the Miller plateau evident in the QG vs VGS plot in the MOSFET data sheet. With a Miller plateau voltage typically in the range of 2 V to 3 V, the 5-V gate drive amplitude of the LM5143-Q1 provides an adequately-enhanced MOSFET when on and a margin against Cdv/dt shoot- through when off. The MOSFET-related power losses are summarized by the equations presented in Table 5, where suffixes 1 and 2 represent high-side and low-side MOSFET parameters, respectively. While the influence of inductor ripple current is considered, second-order loss modes, such as those related to parasitic inductances and SW node ringing, are not included. Consult the LM5143-Q1 Quickstart Calculator, available for download from the LM5143- Q1 product folder, to assist with power loss calculations.

Table 5. Buck Regulator MOSFET Power Losses net loss attributed to body diode reverse recovery. losses scale directly with switching frequency.

9 VLQ ' 9

reverse recovery. The LM5143-Q1 is well suited to drive TI's portfolio of NexFET™ power MOSFETs.

9.1.1.5 EMI Filter

filter output impedance must be less than the absolute value of the converter input impedance.

Calculate the required attenuation of the EMI filter at the switching frequency, where CIN represents the existing capacitance at the input of the switching converter.
Input filter inductor LIN is usually selected between 1 μH and 10 μH, but it can be lower to reduce losses in a high-current design.
Calculate input filter capacitor CF.

Figure 12. Buck Regulator With π-Stage EMI Filter obtain the required attenuation as shown by Equation 23.

VMAX is the allowed dBμV noise level for the applicable conducted EMI specification, for example CISPR 25 Class 5.
CIN is the existing input capacitance of the buck regulator.
DMAX is the maximum duty cycle.
IPEAK is the peak inductor current. (23) For filter design purposes, the current at the input can be modeled as a square-wave. Determine the EMI filter capacitance CF from Equation 24.

ADVANCE□INFORMATION O-EA COMP HF BW O-EA COMP 1 1 R C C C R CZ # COMP COMP R C Z m O-EA 1c REF c out OUT p1 p2 sg R 1Öv (s) VG (s) Öv (s) V s s 1 1 Z Z Z © ¹ § · § · ¨ ¸ ¨ ¸ © ¹ © ¹ z O-EA EA(openloop) O-EA BW g R G (s) 1 s R C m IN D IN LR C D INC 4 Ct res IN F

2 L CS

2Attn F IN SW 1 10C L 2 FS § · ¨ ¸ ¨ ¸ © ¹ LM5143-Q1 SNVSB29 –OCTOBER 2018 www.ti.com Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (24) Adding an input filter to a switching regulator modifies the control-to-output transfer function. The output impedance of the filter must be sufficiently small such that the input filter does not significantly affect the loop gain of the buck converter. The impedance peaks at the filter resonant frequency. The resonant frequency of the filter is given by Equation 25. (25) The purpose of RD is to reduce the peak output impedance of the filter at the resonant frequency. Capacitor CD blocks the DC component of the input voltage to avoid excessive power dissipation in RD. Capacitor CD should have lower impedance than RD at the resonant frequency with a capacitance value greater than that of the input capacitor CIN. This prevents CIN from interfering with the cutoff frequency of the main filter. Added damping is needed when the output impedance of the filter is high at the resonant frequency (Q of filter formed by LIN and CIN is too high). An electrolytic capacitor CD can be used for damping with a value given by Equation 26. (26) Select the damping resistor RD using Equation 27. (27)

9.1.2 Error Amplifier and Compensation

A Type-ll compensator using a transconductance error amplifier (EA) is shown in Figure 13. The dominant pole of the EA open-loop gain is set by the EA output resistance, RO-EA, and effective bandwidth-limiting capacitance, CBW as shown by Equation 28. (28) The EA high-frequency pole is neglected in the above expression. The compensator transfer function from output voltage to COMP node, including the gain contribution from the (internal or external) feedback resistor network, is calculated in Equation 29. where

VREF is the feedback voltage reference of 0.6 V
gm is the EA gain transconductance of 1200 µS
RO-EA is the error amplifier output impedance of 64 MΩ (29) (30) (31)

RCOMP << RO-EA and CCOMP >> CBW and CHF, so the approximations are valid. Figure 13. Error Amplifier and Compensation Network

9.2 Typical Applications

an LM5143-Q1-powered implementation, see TI Designs reference design library.

9.2.1 Design 1 – High Efficiency, Dual-Output Buck Regulator for Automotive Body Applications

to reduce IC bias power dissipation and improve efficiency. Figure 14. Application Circuit 1 With LM5143-Q1 Buck Regulator at 2.1 MHz Supply Recommendations for more detail.

9.2.1.1 Design Requirements

Table 6. Design Parameters at 2 ms by 68-nF soft-start capacitors. inductor, and ceramic output capacitor implementation. Table 7. List of Materials for Application Circuit 1

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5143-Q1 device with the WEBENCH® Power Designer.

Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
Compare the generated design with other possible solutions from Texas Instruments.

pricing and component availability.

Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues

ADVANCE□INFORMATION CS(th) LO1(PK) CS(th) LO2(PK) V 73mVR 7.66m1.2 I 1.2 7.94 A V 73mVR 7.36m1.2 I 1.2 8.27 A : : OUT S O1(sc) SW OUT S O2(sc) SW V (V) R (m ) 3.3 V 7mL 0.46 +24 F (MHz) 24 2.1MHz V (V) R (m ) 5 V 7mL 0.69 +24 F (MHz) 24 2.1MHz : : : : LO1 OUT1 OUT1 LO1(PK) OUT1 OUT1 O1 SW IN(max) LO2 OUT2 OUT2 LO2(PK) OUT2 OUT2 O2 SW IN(max) I V V 3.3 V 3.3 VI I I 1 7 A 1 7.94 A2 2 L F V 2 0.68 + 0+] 9 I V V 5 V I I I 1 7 A 1 2 2 L F V 2 0.68 + 0+] 5 V 8.27 A18 V § · ¨ ¸ © ¹ IN(nom) OUT1OUT1 IN(nom) L SW IN(nom) OUT2OUT2 IN(nom) L SW V V V 3.3 V 12V 3.3 VL 0.54 +V I F 12V 2.1A 2.1MHz V V V 5 V 12V 5 VL 0.66 +V I F 12V 2.1A 2.1MHz LM5143-Q1 SNVSB29 –OCTOBER 2018 www.ti.com Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.1.2.2 Custom Design With Excel Quickstart Tool

Select components based on the regulator specifications using the LM5143-Q1 Quickstart Calculator available for download from the LM5143-Q1 product folder.

9.2.1.2.3 Inductor Calculation

Calculate the required buck inductance for each channel based on a 30% inductor ripple current at nominal input voltages using Equation 33. (33) Select a standard inductor value of 0.68 µH for both channels. The peak inductor currents at maximum steady- state input voltage are given by Equation 34. (34) Sub-harmonic oscillation occurs with a duty cycle greater than 50% for peak current-mode control. For design simplification, the LM5143-Q1 has an internal slope compensation ramp proportional to switching frequency that is added to the current sense signal to damp any tendency toward sub-harmonic oscillation. Based on Equation 10, cross-check the inductance to set a slope compensation equal to the ideal one times the inductor current downslope using Equation 35. (35)

9.2.1.2.4 Current-Sense Resistance

Calculate the current-sense resistance based on a maximum peak current capability of at least 20% higher than the peak inductor current at full load to provide sufficient margin during start-up and load-on transients. Calculate the current sense resistances using Equation 36. where

VCS(th) is the 73 mV current limit threshold. (36)

ADVANCE□INFORMATION LO1 CO1(RMS) LO2 CO2(RMS) I 1.89 AI 0.55 A 12 12 I 2.53 AI 0.73 A 12 12 2 2 2 2LO1 OUT1 ESR LO1 SW OUT1 I 1.89AV R I 1m 1.89 A 2mV8 F C 8 2.1MHz 130 O1 OUT1 OUT1 2 2 22 OUT1 OVERSHOOT1 OUT1 O2 OUT2 OUT2 2 2 2 2 OUT2 OVERSHOOT2 OUT2 0.68 + $L I C 100.2 V V V 3.3 V 50mV 3.3 V 0.68 + $L I C 44.1 V V V 5 V 75mV 5 V 't 't CS(th) IN(max) CS-DELAY LO1(PK-SC) LO2(PK-SC) S1 O1 V V T 73mV 18 V 40nsI I 11.49 AR L 7m 0.68 : LM5143-Q1 www.ti.com SNVSB29 –OCTOBER 2018 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Select a standard resistance value of 7 mΩ for both shunts. An 0508 footprint component with wide aspect ratio termination design provides 1-W power rating, low parasitic series inductance, and compact PCB layout. Carefully observe the Layout Guidelines to make sure that noise and DC errors do not corrupt the differential current-sense voltages measured at [CS1, VOUT1] and [CS2, VOUT2]. Place the shunt resistor close to the inductor, use Kelvin-sense connections, and route the sense lines differentially from the shunt to the LM5143-Q1. The CS-to-output propagation delay (related to the current limit comparator, internal logic and power MOSFET gate drivers) causes the peak current to increase above the calculated current limit threshold. For a total propagation delay of TCS-DELAY of 40 ns, calculate the worst-case peak inductor current with the output shorted using Equation 37. (37) Based on this result, select an inductor for each channel with saturation current greater than 12 A across the full operating temperature range.

9.2.1.2.5 Output Capacitors

Estimate the output capacitance required to manage the output voltage overshoot during a load-off transient (from full load to no load) using Equation 38, assuming a load transient deviation specification of 1.5% (50mV for a 3.3-V output). (38) Noting the voltage coefficient of ceramic capacitors where the effective capacitance decreases significantly with applied voltage, select four 47-µF, 6.3-V, X7R, 1210 ceramic output capacitors for each channel. Generally, when sufficient capacitance is used to satisfy the load-off transient response requirement, the voltage undershoot during a no-load to full-load transient will also be satisfactory. Estimate the peak-peak output voltage ripple of channel 1 at nominal input voltage using Equation 39. where

RESR is the effective equivalent series resistance (ESR) of the output capacitors.
130 µF is the total effective (derated) ceramic output capacitance at 3.3 V. (39) Calculate the output capacitor RMS ripple current using Equation 40 and verify that the ripple current is within the capacitor ripple current rating. (40)

9.2.1.2.6 Input Capacitors

A power supply input typically has a relatively high source impedance at the switching frequency. Good-quality input capacitors are necessary to limit the input ripple voltage. As mentioned earlier, dual-channel interleaved operation significantly reduces the input ripple amplitude. in general, the ripple current splits between the input capacitors based on the relative impedance of the capacitors at the switching frequency. Select the input capacitors with sufficient voltage and RMS ripple current ratings.

ADVANCE□INFORMATION HF1 ESR COMP1 1 1 C 15.9pF2 f R 2 500kHz 20 kS S : COMP1 C COMP1 10 10C 1.3nF2 f R 2 60kHz 20 kS S : OUT S CS COMP1 C OUT REF m V R G 3.3V 7m 12R 2 f C 2 60kHz 130 NV g 0.6V 1200 OUT1 IN SW IN ESR OUT1 D 1 D I 0.5 1 0.5 7AC 7.8 )F V R I 2.1MHz 120mV 2m 7A CIN(RMS) OUT1I I D 1 D 7 A 0.5 1 0.5 3.5 A LM5143-Q1 SNVSB29 –OCTOBER 2018 www.ti.com Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Worst case input ripple for a two-channel buck regulator typically corresponds to when one channel operates at full load and the other channel is disabled or operates at no load. Calculate the input capacitor RMS ripple current using Equation 41, assuming a worst-case duty-cycle operating point of 50%. (41) Find the required input capacitance using Equation 42. where

ΔVIN is the input peak-to-peak ripple voltage specification.
RESR is the input capacitor ESR. (42) Recognizing the voltage coefficient of ceramic capacitors, select two 10-µF, 50-V, X7R, 1210 ceramic input capacitors for each channel. Place these capacitors adjacent to the relevant power MOSFETs. In addition, use four 10-nF, 50-V, X7R, 0603 ceramic capacitors near each high-side MOSFET to supply the high di/dt current during MOSFET switching transitions. Such capacitors offer high self-resonant frequency (SRF) and low effective impedance above 100 MHz. The result is lower power loop parasitic inductance, thus minimizing switch-node voltage overshoot and ringing for lower EMI signature. Refer to Figure 32 in Layout Guidelines for more detail.

9.2.1.2.7 Compensation Components

Choose compensation components for a stable control loop using the procedure outlined as follows.

Based on a specified open-loop gain crossover frequency, fC, of 60 kHz, calculate RCOMP1 using Equation 43, assuming an effective output capacitance of 130 µF. Select RCOMP1 of 20 kΩ. (43)
Calculate CCOMP1 to create a zero at the higher of (1) one tenth of the crossover frequency, or (2) the load pole. Select a CCOMP1 capacitor of 1 nF. (44)
Calculate CHF1 to create a pole at the ESR zero and to attenuate high-frequency noise at COMP. Select a CHF1 capacitor of 15 pF. (45) For technical solutions, industry trends, and insights for designing and managing power supplies, please refer to TI's Power House blog series.

(1) The curves with higher efficiency at light load correspond to when diode emulation is enabled (DEMB tied to AGND).

9.2.1.3 Application Curves

Figure 15. Efficiency vs IOUT Figure 16. Efficiency vs IOUT Figure 17. Efficiency vs IOUT, Log Scale Figure 18. Efficiency vs IOUT Figure 19. Efficiency vs IOUT, Log Scale Figure 20. Cold-Crank Response to VIN = 3.8 V

9.2.2 Design 2 – Two-Phase, Single-Output Buck Regulator for Automotive ADAS Applications

Figure 29. Application Circuit 2 With LM5143-Q1 Buck Regulator at 2.1 MHz

9.2.2.1 Design Requirements

Table 8. Design Parameters

ms by a 68-nF soft-start capacitor. inductor, and ceramic output capacitor implementation. Table 9. List of Materials for Application Circuit 2 (1) Configure the regulator as a 3.3-V output by tying FB1 to VDDA.

9.2.2.2 Detailed Design Procedures

9.2.2.3 Application Curves

Figure 30. Efficiency vs IOUT, 5-V Output Figure 31. Efficiency vs IOUT, 3.3-V Output (1)

10 Power Supply Recommendations

The LM5143-Q1 buck controller is designed to operate from a wide input voltage range of 3.5 V to 65 V. The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended Operating Conditions tables. In addition, the input supply must be capable of delivering the required input current to the fully-loaded regulator. Estimate the average input current with Equation 46. where

η is the efficiency (46) If the regulator is connected to an input supply through long wires or PCB traces with a large impedance, take special care to achieve stable performance. The parasitic inductance and resistance of the input cables may have an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients at VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip during a load transient. The best way to solve such issues is to reduce the distance from the input supply to the regulator and use an aluminum or tantalum input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitors helps to damp the input resonant circuit and reduce any voltage overshoots. A capacitance in the range of 10 µF to 47 µF is usually sufficient to provide parallel input damping and helps to hold the input voltage steady during large load transients. An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as well as some of the effects mentioned above. The application report Simple Success with Conducted EMI for DC-DC Converters (SNVA489) provides helpful suggestions when designing an input filter for any switching regulator.

11 Layout

11.1 Layout Guidelines

the low-side and high-side MOSFETs, denoted by 2 and 3, respectively, in Figure 32. Figure 32. DC/DC Regulator Ground System With Power Stage and Gate Drive Circuit Switching Loops

11.1.1 Power Stage Layout

Input capacitors, output capacitors, and MOSFETs are the constituent components of the power stage of a

plane, connected to ground, to shield and isolate the small-signal traces from noisy power traces and lines.

The DC/DC regulator has several high-current loops. Minimize the area of these loops in order to suppress

generated switching noise and optimize switching performance. the low-side MOSFET and negative terminal of the output capacitor(s) at ground as close as possible.

The PCB trace defined as SW node, which connects to the source of the high-side (control) MOSFET, the

wide. However, the SW connection is a source of injected EMI and thus must not be too large.

ADVANCE□INFORMATION LM5143-Q1 SNVSB29 –OCTOBER 2018 www.ti.com Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Layout Guidelines (continued) 4. Follow any layout considerations of the MOSFETs as recommended by the MOSFET manufacturer, including pad geometry and solder paste stencil design. 5. The SW pin connects to the switch node of the power conversion stage and acts as the return path for the high-side gate driver. The parasitic inductance inherent to loop 1 in Figure 32 and the output capacitance (COSS) of both power MOSFETs form a resonant circuit that induces high frequency (greater than 50 MHz) ringing at the SW node. The voltage peak of this ringing, if not controlled, can be significantly higher than the input voltage. Make sure that the peak ringing amplitude does not exceed the absolute maximum rating limit for the SW pin. In many cases, a series resistor and capacitor snubber network connected from the SW node to GND damps the ringing and decreases the peak amplitude. Provide provisions for snubber network components in the PCB layout. If testing reveals that the ringing amplitude at the SW pin is excessive, then include snubber components as needed.

11.1.2 Gate-Drive Layout

The LM5143-Q1 high-side and low-side gate drivers incorporate short propagation delays, adaptive dead-time control and low-impedance output stages capable of delivering large peak currents with very fast rise and fall times to facilitate rapid turnon and turnoff transitions of the power MOSFETs. Very high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. Minimization of stray or parasitic gate loop inductance is key to optimizing gate drive switching performance, whether it be series gate inductance that resonates with MOSFET gate capacitance or common source inductance (common to gate and power loops) that provides a negative feedback component opposing the gate drive command, thereby increasing MOSFET switching times. The following loops are important:

Loop 2: high-side MOSFET, Q1. During the high-side MOSFET turnon, high current flows from the bootstrap (boot) capacitor through the gate driver and high-side MOSFET, and back to the negative terminal of the boot capacitor through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from the gate of the high-side MOSFET through the gate driver and SW, and back to the source of the high-side MOSFET through the SW trace. Refer to loop 2 of Figure 32.
Loop 3: low-side MOSFET, Q2. During the low-side MOSFET turnon, high current flows from the VCC decoupling capacitor through the gate driver and low-side MOSFET, and back to the negative terminal of the capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from the gate of the low-side MOSFET through the gate driver and GND, and back to the source of the low-side MOSFET through ground. Refer to loop 3 of Figure 32. TI strongly recommends following circuit layout guidelines when designing with high-speed MOSFET gate drive circuits. 1. Connections from gate driver outputs, HO1/2, HOL1/2, LO1/2 and LOL1/2 to the respective gates of the high- side or low-side MOSFETs must be as short as possible to reduce series parasitic inductance. Be aware that peak gate drive currents can be as high as 4.25 A. Use 0.65 mm (25 mils) or wider traces. Use via(s), if necessary, of at least 0.5 mm (20 mils) diameter along these traces. Route HO and SW gate traces as a differential pair from the LM5143-Q1 to the high-side MOSFET, taking advantage of flux cancellation. 2. Minimize the current loop path from the VCC and HB pins through their respective capacitors as these provide the high instantaneous current, up to 4.25 A, to charge the MOSFET gate capacitances. Specifically, locate the bootstrap capacitor, CBST, close to the HB and SW pins of the LM5143-Q1 to minimize the area of loop 2 associated with the high-side driver. Similarly, locate the VCC capacitor, CVCC, close to the VCC and PGND pins of the LM5143-Q1 to minimize the area of loop 3 associated with the low-side driver.

11.1.3 PWM Controller Layout

With the proviso to locate the controller as close as possible to the power MOSFETs to minimize gate driver trace runs, the components related to the analog and feedback signals as well as current sensing are considered in the following: 1. Separate power and signal traces, and use a ground plane to provide noise shielding. 2. Place all sensitive analog traces and components related to COMP1/2, FB1/2, CS1/2, SS1/2, RES and RT away from high-voltage switching nodes such as SW1/2, HO1/2, LO1/2 or HB1/2 to avoid mutual coupling. Use internal layer(s) as ground plane(s). Pay particular attention to shielding the feedback (FB) trace from power traces and components. 3. Locate the upper and lower feedback resistors (if required) close to the respective FB pins, keeping the FB

ADVANCE□INFORMATION LM5143-Q1 www.ti.com SNVSB29 –OCTOBER 2018 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Layout Guidelines (continued) traces as short as possible. Route the trace from the upper feedback resistor(s) to the required output voltage sense point(s) at the load(s). 4. Route the CS1/2 and VOUT1/2 traces as differential pairs to minimize noise pickup and use Kelvin connections to the applicable shunt resistor (if shunt current sensing is used) or to the sense capacitor (if inductor DCR current sensing is used). 5. Minimize the loop area from the VCC1/2 and VIN pins through their respective decoupling capacitors to the relevant PGND pins. Locate these capacitors as close as possible to the LM5143-Q1.

11.1.4 Thermal Design and Layout

The useful operating temperature range of a PWM controller with integrated gate drivers and bias supply LDO regulator is greatly affected by:

average gate drive current requirements of the power MOSFETs;
switching frequency;
operating input voltage (affecting bias regulator LDO voltage drop and hence its power dissipation);
thermal characteristics of the package and operating environment. For a PWM controller to be useful over a particular temperature range, the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The LM5143-Q1 controller is available in a small 6-mm × 6-mm 20-pin VQFN (RGW) PowerPAD™ package to cover a range of application requirements. The thermal metrics of this package are summarized in Thermal Information. The application report Semiconductor and IC Package Thermal Metrics provides detailed information regarding the thermal information table. The 40-pin VQFN package offers a means of removing heat from the semiconductor die through the exposed thermal pad at the base of the package. While the exposed pad of the package is not directly connected to any leads of the package, it is thermally connected to the substrate of the LM5143-Q1 device (ground). This allows a significant improvement in heat sinking, and it becomes imperative that the PCB is designed with thermal lands, thermal vias, and a ground plane to complete the heat removal subsystem. The exposed pad of the LM5143-Q1 is soldered to the ground-connected copper land on the PCB directly underneath the device package, reducing the thermal resistance to a very low value. Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal and solder-side ground plane(s) are vital to help dissipation. In a multi-layer PCB design, a solid ground plane is typically placed on the PCB layer below the power components. Not only does this provide a plane for the power stage currents to flow but it also represents a thermally conductive path away from the heat generating devices. The thermal characteristics of the MOSFETs also are significant. The drain pads of the high-side MOSFETs are normally connected to a VIN plane for heat sinking. The drain pads of the low-side MOSFETs are tied to the respective SW planes, but the SW plane area is purposely kept as small as possible to mitigate EMI concerns.

11.1.5 Ground Plane Design

As mentioned previously, using one or more of the inner PCB layers as a solid ground plane is recommended. A ground plane offers shielding for sensitive circuits and traces and also provides a quiet reference potential for the control circuitry. Connect the PGND1 and PGND2 pins to the system ground plane using an array of vias under the exposed pad. Also connect the PGND1 and PGND2 pins directly to the return terminals of the input and output capacitors. The PGND nets contain noise at the switching frequency and can bounce because of load current variations. The power traces for PGND1/2, VIN and SW1/2 can be restricted to one side of the ground plane. The other side of the ground plane contains much less noise and is ideal for sensitive analog trace routes.

11.2 Layout Example

Make the ground connections to the LM5143-Q1 controller as shown in Figure 33. Create a power ground directly connected to all high-power components and an analog ground plane for sensitive analog components. The analog ground plane for AGND and power ground planes for PGND1 and PGND2 must be connected at a single point directly under the IC – at the die attach pad (DAP).
Figure 34 shows the schematic of the high-frequency loops of one synchronous buck channel. The high- frequency power loop current flows through MOSFETs Q2 and Q4, through the power ground plane on layer 2, and back to VIN through the 0603 ceramic capacitors C16 through C19. This loop must be as small as

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.1.2 Development Support

For development support see the following:

LM5143-Q1 Quickstart Calculator
LM5143-Q1 Simulation Models
For TI's reference design library, visit TI Designs
For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center

12.1.3 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5143-Q1 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer gives a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

LM5143-Q1 Synchronous Buck Controller EVM
LM5140-Q1 Synchronous Buck Controller High Density EVM
Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics
AN-2162 Simple Success with Conducted EMI from DC-DC Converters
White Papers: – Valuing Wide VIN, Low EMI Synchronous Buck Circuits for Cost-driven, Demanding Applications – An Overview of Conducted EMI Specifications for Power Supplies – An Overview of Radiated EMI Specifications for Power Supplies
Application Reports: – Maintaining Output Voltage Regulation During Automotive Cold-Crank with LM5140-Q1 Dual Synchronous Buck Controller
Power House Blogs: – How to Use Slew Rate for EMI Control – Synchronous Buck Controller Solutions Support Wide VIN Performance and Flexibility

12.2.1.1 PCB Layout Resources

AN-1149 Layout Guidelines for Switching Power Supplies
AN-1229 Simple Switcher PCB Layout Guidelines
Constructing Your Power Supply – Layout Considerations
Low Radiated EMI Layout Made SIMPLE with LM4360x and LM4600x
Power House Blogs: – High-Density PCB Layout of DC/DC Converters

12.2.1.2 Thermal Design Resources

AN-2020 Thermal Design by Insight, Not Hindsight
AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
Semiconductor and IC Package Thermal Metrics
Thermal Design Made Simple with LM43603 and LM43602
PowerPAD™ Thermally Enhanced Package
PowerPAD Made Easy
Using New Thermal Metrics

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, find the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, see the revision history included in any revised document.

12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.5 Trademarks

NexFET, PowerPAD, E2E are trademarks of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.7 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages show mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 8-Nov-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM5143QRWGRQ1 PREVIEW VQFNP RWG 40 2500 TBD Call TI Call TI -40 to 150 LM5143QRWGTQ1 PREVIEW VQFNP RWG 40 250 TBD Call TI Call TI -40 to 150 PM5143QRWGTQ1 ACTIVE VQFNP RWG 40 250 TBD Call TI Call TI -40 to 150 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com PACKAGE OUTLINE C PIN 1 ID 3.3 0.1

0.9 MAX

4.5 40X 0.3 0.236X 0.5 X 0.6 MAX 40X 0.5 0.3 0.05 0.00 5.75) (0.15) (0.09) B 6.1 5.9 A 6.1 5.9 (0.2) (0.15) 4221568/A 07/2014 VQFN - 0.9 mm max heightRWG0040A PLASTIC QUAD FLATPACK - NO LEAD NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 2011 40 31

0.1 C B A

0.05 C PIN 1 ID (R0.2) SYMM SYMM SEE DETAIL B

0.05 C SEATING PLANE

SCALE 2.200 DETAIL A SCALE 20.000 DETAIL A TYPICAL DETAIL B SCALE 20.000 DETAIL B TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT ( 3.3) (5.8)

0.07 MAX

ALL AROUND 0.07 MIN ALL AROUND ( ) TYP VIA 0.2 (5.8) (1.4) 36X (0.5) 40X (0.6) 40X (0.25) 4221568/A 07/2014 VQFN - 0.9 mm max heightRWG0040A PLASTIC QUAD FLATPACK - NO LEAD SYMM SYMM LAND PATTERN EXAMPLE SCALE:12X 11 20 3140 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). METAL SOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.8) 40X (0.6) 40X (0.25) 36X (0.5) ( 1.43) 2X (1.63) (1.63) (5.8) 4221568/A 07/2014 VQFN - 0.9 mm max heightRWG0040A PLASTIC QUAD FLATPACK - NO LEAD NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11 20 3140 SYMM SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 75% PRINTED SOLDER COVERAGE BY AREA SCALE:12X

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Product Information

PM5143QRWGTQ1 specifications and overview.

Summary

3.5-V to 65-V Low IQ, Dual Synchronous Buck DC/DC Controller

Description

3.5-V to 65-V Low IQ, Dual Synchronous Buck DC/DC Controller

Source title PM5143QRWGTQ1 Datasheet(PDF) - Texas Instruments

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