PM25LV020 ETC1 | Alldatasheet
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512 Kbit /1 Mbit / 2 Mbit / 4 Mbit 3.0 Volt-only, Serial Flash Memory With 100 MHz SPI Bus Interface FEA TURES
- Single Power Supply Operation - Low voltage range: 2.7 V - 3.6 V
- Memory Organization - Pm25LV512A: 64K x 8 (512 Kbit) - Pm25LV010A: 128K x 8 (1 Mbit) - Pm25LV020: 256K x 8 (2 Mbit) - Pm25LV040: 512K x 8 (4 Mbit)
- Cost Effective Sector/Block Architecture - 512Kb : Uniform 4Kbyte sectors / Two uniform 32Kbyte blocks - 1Mb : Uniform 4Kbyte sectors / Four uniform 32Kbyte blocks - 2Mb : Uniform 4Kbyte sectors / Four uniform 64Kbyte blocks - 4Mb : Uniform 4Kbyte sectors / Eight uniform 64Kbyte blocks - Bottom sector is configurable as one 4Kbyte sector or four 1Kbyte sectors (except Pm25LV512A)
- Serial Peripheral Interface (SPI) Compatible - Supports SPI Modes 0 (0,0) and 3 (1,1) - Maximum 33 MHz clock rate for normal read - Maximum 100 MHz clock rate for fast read
- Page Program (up to 256 Bytes) Operation - Typical 2 ms per page program
- Sector, Block or Chip Erase Operation - Typical 60 ms sector, block or chip erase
- Software Write Protection - The Block Protect (BP2, BP1, BP0) bits allow partial or entire memory to be configured as read-only
- Hardware Write Protection - Protect and unprotect the device from write operation by Write Protect (WP#) Pin
- Low Power Consumption - Typical 10 mA active read current - Typical 15 mA program/erase current
- High Product Endurance - Guarantee 200,000 program/erase cycles per single sector - Minimum 20 years data retention
- Industrial Standard Pin-out and Package - 8-pin 150mil SOIC - 8-pin 208mil SOIC for Pm25LV040 - 8-pin 300mil PDIP for Pm25LV040 - 8-contact WSON - 8-pin TSSOP for Pm25LV512A GENERAL DESCRIPTION The Pm25LV512A/010A/020/040 are 512Kbit/1 Mbit/2 Mbit/4 Mbit 3.0 Volt-only Serial Peripheral Interface (SPI) Flash memories. The devices are designed to support 33 MHz fastest clock rate in the industry in normal read mode, 100 MHz in fast read mode and the bottom 4 Kbyte sector into four smaller 1 Kbyte sectors features(except Pm25LV512A). The devices use a single low voltage, ranging from 2.7 Volt to 3.6 Volt, power supply to perform read, erase and program operations. The devices can be programmed in standard EPROM programmers as well. The Pm25LV512A/010A is backward compatible to their predecessors Pm25LV512/010. The Pm25LV512A/010A/020/040 are accessed through a 4-wire SPI Interface consists of Serial Data Input (Sl), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. The devices support page program mode, 1 to 256 bytes data can be programmed into the memory in one program operation. The memory of Pm25LV512A/010A is divided into uniform 4 Kbyte sectors or uniform 32 Kbyte blocks (sector group - consists of eight adjacent sectors) for data or code storage. The memory of Pm25LV020/040 are divided into uniform 4 Kbyte sectors or uniform 64 Kbyte blocks (sector group - consists of sixteen adjacent sectors). The devices have an innovative feature to configure the bottom 4 Kbyte sector into four smaller 1 Kbyte sectors for eliminating additional serial EEPROM needed for storing data. This is a further cost reduction for overall system. The Pm25LV512A/010A/020/040 are manufactured on pFLASH™’s advanced nonvolatile technology. The devices are offered in 8-pin SOIC, 8-contact WSON and 8-pin PDIP (Pm25LV040) packages with operation frequency up to 100 MHz in fast read and 33 MHz in normal read mode. Chingis Technology Corporation 1 Issue Date: Feb., 2009, Rev: 3.5 Pm25LV512A / 010A / 020 / 040
2Chingis Technology Corporation Issue Date: Feb., 2009, Rev: 3.5 Pm25LV512A/010A/020/040 PIN DESCRIPTIONS SYMBOL TYPE DESCRIPTION CE# INPUT Chip Enable: CE# goes low activates the devices internal circuitries for device operation. CE# goes high deselects the devices and switches into standby mode to reduce the power consumption. When the devices are not selected, data will not be accepted via the serial input pin (Sl), and the serial output pin (SO) will remain in a high impedance state. SCK INPUT Serial Data Clock SI INPUT Serial Data Input SO OUTPUT Serial Data Output GND Ground Vcc Device Power Supply WP# INPUT Write Protect: A hardware program/erase protection for all or partial of memory array. When the WP# pin is pulled to low, whole or partial of memory array is write protected depends on the setting of BP2, BP1 and BP0 bits in the Status Register. When the WP# is pulled high, the devices are not write protected. HOLD# INPUT Hold: Pause serial communication with the master device without resetting the serial sequence. CONNECTION DIAGRAMS 8-Pin SOIC Vcc HOLD# SCK SI SO GND WP# CE# Vcc HOLD# SCK SI SO GND WP# CE# 8-Contact WSON Vcc HOLD# SCK SI SO GND WP# CE# 8-Pin PDIP Vcc HOLD# SCK SI SO GND WP# CE# 8-Pin TSSOP
3Chingis Technology Corporation Issue Date: Feb., 2009, Rev: 3.5 Pm25LV512A/010A/020/040 PRODUCT ORDERING INFORMA TION Pm25LVxxxA -100 S C E R Temperature Range C = Commercial (-40°C to +105°C) Package Type S = 8-pin SOIC 150 mil (8S) B = 8-pin SOIC 208 mil (8B) K = 8-contact WSON (8K) P = 8-pin PDIP 300 mil (8P) D = TSSOP (8D) Operating Frequency -100 : 33MHz normal read, 100MHz fast read Device Number Pm25LV512A/010A/020/040 Environmental Attribute E = Lead-free/RoHS compliance package Blank = Standard package Packing Type R = Tape & Reel Blank = Tube Part Number Pm25LV512A-100SCE Pm25LV010A-100SCE Pm25LV020-100SCE Pm25LV040-100SCE Operating Frequency (MHz) Package 8S 150mil SOIC 100 8Q WSON Pm25LV512A-100KCE Pm25LV010A-100KCE Pm25LV020-100KCE Pm25LV040-100KCE 100 Pm25LV040-100BCE Pm25LV040-100PCE Pm25LV512A-100DCE 100 100 100 8B 208mil SOIC 8P 300mil PDIP 8D TSSOP Commercial (-40oC to +105oC) Temperature Range Pm25LV512A-100WC Commercial (-40oC to 105oC) KGD 100 100 100 Pm25LV010A-100WC Pm25LV020-100WC
4Chingis Technology Corporation Issue Date: Feb., 2009, Rev: 3.5 Pm25LV512A/010A/020/040 BLOCK DIAGRAM High Voltage GeneratorControl Logic I/O Buffers and Data Latches Address Latch & Counter
256 B ytes
Serial Peripheral Interface CE# WP# SCK SI SO HOLD#
- Configurable sector size: The memory array of
group - consists of sixteen adjacent sectors). Table 1. Configuration Register Format - Pm25LV010A/020/040 Table 2. Configuration Register Bit Definition register were enabled to "1" which is in protection mode.
1 Kbyte Sector 0_0 Protection:
1 Kbyte Sector 0_1Protection:
1 Kbyte Sector 0_2 Protection:
1 Kbyte Sector 0_3 Protection:
- The Pm25LV010A/020/040 have an option to config-
need of addtional serial EEPROM. for Configuration Register Bit Definition.
7Chingis Technology Corporation Issue Date: Feb., 2009, Rev: 3.5 Pm25LV512A/010A/020/040 REGISTERS (CONTINUED) CONFIGURATION REGISTER (Pm25LV010A/020/ 040) The Configuration Register is built by latchs need to be set each time after power-up before enabling the 1 Kbyte smaller sector size and 1 Kbyte sector write protection. The Bit 0 - Bit 7 of Configuration Register are set as “0”s after power-up reset. Therefore, the devices will be al- ways set as normal mode - the bottom sector set as 4 Kbyte by default after power-up to maintain the back- ward-compatibility. The function of Configuration Register is described as following: SCFG bit: The 1 Kbyte smaller sector mode is enabled by writing “1” to SCFG bit, then Sector 0 is configured as Sector 0_0, Sector 0_1, Sector 0_2 and Sector 0_3. A Sector Erase (SECTOR_ER) instruction can be used to erase any one of those four 1 Kbyte sectors. The SCFG bit will be reset “0” state automatically at power on stage. Thus, the 1 Kbyte smaller sector mode is disabled at power on till SCFG bit was set. The SCFG bit only can be enabled to “1” when BP0, BP1&BP2 of status register were “1” state which in pro- tection mode. On the other word, SCFG bit will be cleared to “0” state when BPx were “0” to disable the protection mode. SP0_x bits: The write protection to those four 1 Kbyte sectors can be activated by writing “1”s to the SP0_0, SP0_1, SP0_2 and SP0_3 bits. The 1 Kbyte sector write protection function can only be enabled when the SCFG is also enabled. The Write Configuration Register (WRCR) instruction can be used to write “0”s or “1”s into Configuration Register. And the Read Configuration Register (RDCR) instruc- tion can be used to read the setting of Configuration Register. Refer to Table 8 for Instruction Set. STATUS REGISTER The Status Register contains WIP and WEL status bits to indicate the status of the devices, the Block Protec- tion Bits (BP0, BP1 and BP2 (Pm25LV040 only)) to define the portion of memory blocks to be write protected, The BP0, BP1, BP2, and SRWD are non-volatile memory cells that can be written by Write Status Register (WRSR) instruction. The default value of BP0, BP1, BP2, and SRWD bits were set as “0” at factory. Once those bits are written as “0” or “1”, it will not be changed by devices power-up or power-down until next WRSR instruction al- ters its value. The Status Register can be read by Read Status Register (RDSR) instruction for its value and sta- tus. Refer to Table 8 for Instruction Set. The function of Status Register is described as following: WIP bit: The Write In Progress (WIP) bit can be used to detact the progress or completion of program or erase operation. When WIP bit is “0”, the devices are ready for write status register, program or erase operation. When WIP bit is “1”, the devices are busy. WEL bit: The Write Enable Latch (WEL) bit indicates the status of internal write enable latch. When WEL bit is “0”, the write enable latch is disabled, all write opera- tions include write status register, write configuration reg- ister, page program, sector erase, block and chip erase operations are inhibited. When WEL bit is “1”, the write enable latch is enabled. Then write operations are allowed. The WEL bit is enabled by Write Enable (WREN) instruc- tion. All write register, program and erase instructions must be preceded by a WREN instruction every time. The WEL bit can be disabled by Write Disable (WRDI) instruction or automatically return to reset state after the completion of a write instruction. BP2, BP1, BP0 bits: The Block Protection (BP2 (Pm25LV040 only), BP1, BP0) bits are used to define the portion of memory area to be protected. Refer to Table 5 and Table 6 Block Write Protection Bits Setting for Pm25LV512A/010A/020 and Pm25LV040. When one of the combination of BP2, BP1 and BP0 bits were set as “1”, the relevant memory area is protected. Any program or erase operation to that area will be prohibited. Especially, the Chip Erase (CHIP_ER) instruction is ex- ecuted only if all the Block Protection Bits are set as “0”s. If SCFG bit was enabled to support 1KB x4 sectores on Sector 0, Sector 0’s protection status will respect SP0_x in Configuration Register and ignore BPx bits status whatever protection status. and SRWD control bits to be set for status register write protection. Refer to Table 3 and Table 4 for Status Reg- ister Format and Status Register Bit Definition.
Table 4. Status Register Bit Definition Table 3. Status Register Format Table 5. Block Write Protect Bits for Pm25LV512A/010A/020 (WP#) signal to provide a Hardware Protection Mode. Register is still changeable by WRSR instruction.
11 All Blocks
000 N o n e
Table 6. Block Write Protect Bits for Pm25LV040 sible noisy environment and protect the data integrity. nored when Vcc drop to 2.1V and lower. BP1,BP0 abd SRWD in the Status Register. or whole memory area to be write protected.
0 Low Writable
1 Low Protected
Table 7. Hardware Write Protection on Status
Table 8. Instruction Set
3 Dummy Bytes
Figure 3. Read Product Identification Sequence Table 9. Product IdentificationREAD PRODUCT IDENTIFICATION OPERATION bit being latched-in on SI during the rising edge of SCK.
out during the falling edge of SCK. ing until the pulled high of CE# signal. Figure 4. Read Product Identification by JEDEC ID READ Sequence
Figure 11. Read Data Sequence Table 10. Address Key in one continuous READ instruction.
rate where the FAST_READ instruction proceeding. Figure 12. Fast Read Data Sequence
abled through a Write Enable (WREN) instruction. bit = “0”, the program operation has completed. consecutive bytes within a page if it is not write protected. bytes data are kept to be programmed into the page. The starting byte can be anywhere within the same page. whole sector or block first. Figure 13. Page Program Sequence
19Chingis Technology Corporation Issue Date: Feb., 2009, Rev: 3.5 Pm25LV512A/010A/020/040 ERASE OPERATION The memory array of Pm25LV512A/010A is organized into uniform 4 Kbyte sectors or 32 Kbyte uniform blocks (sector group - consists of eight adjacent sectors). The memory array of Pm25LV020/040 are organized into uniform 4 Kbyte sectors or 64 Kbyte uniform blocks (sec- tor group - consists of sixteen adjacent sectors). The Pm25LV010A/020/040 of bottom sector (Sector 0) of the devices can be configured into four 1 Kbyte smaller sectors. Before a byte can be reprogrammed, the sector or block which contains this byte must be erased first. In order to erase the devices, there are three erase instructions in- clude Sector Erase (SECTOR_ER), Block Erase (BLOCK_ER) and Chip Erase (CHIP_ER) instructions can be used. A sector erase operation allows to erase any individual sector without affecting the data in others. A block erase operation allows to erase any individual block. And a chip erase operation allows to erase the whole memory array of the devices. Pre-programs the devices are not required prior to a sector erase, block erase or chip erase operation. SECTOR ERASE OPERATION A SECTOR_ER instruction erases a 4 Kbyte sector or a
1 Kbyte smaller sector (Sector 0_3, Sector 0_2, Sector
0_1, Sector 0_0) if the bottom Sector 0 has been config- ured as four smaller sectors. Before the execution of SECTOR_ER instruction, the Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruc- tion. The WEL will be reset automatically after the completion of sector erase operation. The SECTOR_ER instruction is entered, after the CE# is pulled low to select the device and staying low during the entire instruction sequence, by shifting in the SECTOR_ER instruction code and three address bytes via the SI. Erase operation will start immediately after the CE# is pulled high, otherwise the SECTOR_ER in- struction will not be executed. The internal control logic automatically handles the erase voltage and timing. Re- fer to Figure 13 for Sector Erase Sequence. During a erase operation, all instruction will be ignored except the Read Status Register (RDSR) instruction. The progress or completion of the erase opertion can be determined by reading the WIP bit in Status Register through a RDSR instruction. If WIP bit = “1”, the erase operation is still in progress. If WIP bit = “0”, the erase operation has been completed. DEVICE OPERATION (CONTINUED) BLOCK ERASE OPERATION A Block Erase (BLOCK_ER) instruction erases a 32 Kbyte block for the Pm25LV512A/010A or a 64 Kbyte block for the Pm25LV020/040. Before the execution of BLOCK_ER instruction, the Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruc- tion. The WEL will be reset automatically after the completion of block erase operation. The BLOCK_ER instruction is entered, after the CE# is pulled low to select the device and staying low during the entire instruction sequence, by shifting in the BLOCK_ER instruction code and three address bytes via the SI. Erase operation will start immediately after the CE# is pulled high, otherwise the BLOCK_ER in- struction will not be executed. The internal control logic automatically handles the erase voltage and timing. Re- fer to Figure 14 for Block Erase Sequence. CHIP ERASE OPERATION A Chip Erase (CHIP_ER) instruction erases the whole memory array of Pm25LV512A/010A/020/040. Before the execution of CHIP_ER instruction, the Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruction. The WEL will be reset automatically after the completion of chip erase operation. The CHIP_ER instruction is entered, after the CE# is pulled low to select the device and staying low during the entire instruction sequence, by shifting in the CHIP_ER instruction code via the SI. Erase operation will start immediately after the CE# is pulled high, other- wise the CHIP_ER instruction will not be executed. The internal control logic automatically handles the erase voltage and timing. Refer to Figure 15 for Chip Erase Sequence.
Table 11. Block/Sector Addresses of Pm25LV512A/010A
1 Mbit
512 Kbit
Table 12. Block/Sector Addresses of Pm25LV020/040
2 Mbit
4 Mbit
23Chingis Technology Corporation Issue Date: Feb., 2009, Rev: 3.5 Pm25LV512A/010A/020/040 DC AND AC OPERA TING RANGE ABSOLUTE MAXIMUM RA TINGS (1) Notes: 1. Stresses under those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. The functional operation of the device or any other conditions under those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condition for extended periods may affected device reliability. 2. Maximum DC voltage on input or I/O pins are V CC + 0.5 V. During voltage transitioning period, input or I/O pins may overshoot to VCC + 2.0 V for a period of time up to 20 ns. Minimum DC voltage on input or I/O pins are -0.5 V. During voltage transitioning period, input or I/O pins may undershoot GND to -2.0 V for a period of time up to 20 ns. T emperature Under Bias -65 oC to +125oC Storage T emperature -65 oC to +125oC Surface Mount Lead Soldering T emperature Standard Package 240 oC 3 Seconds Lead-free Package 260 oC 3 Seconds Input Voltage with Respect to Ground on All Pins (2) -0.5 V to VCC + 0.5 V All Output Voltage with Respect to Ground -0.5 V to V CC + 0.5 V V CC (2) -0.5 V to +6.0 V Part Number Pm25LV512A/010A/020/040 Operating T emperature -40 oC to +105oC Vcc Power Supply 2.7 V - 3.6 V
24Chingis Technology Corporation Issue Date: Feb., 2009, Rev: 3.5 Pm25LV512A/010A/020/040 DC CHARACTERISTICS Applicable over recommended operating range from: TAC = -40°C to +105°C, VCC = 2.7 V to 3.6 V (unless otherwise noted). Symbol Parameter Min Typ Max Units ICC1 Vcc Active Read Current 10 15 mA ICC2 Vcc Program/Erase Current 15 30 mA ISB1 Vcc Standby Current CMOS 10 20 uA ISB2 Vcc Standby Current TTL 3 mA ILI Input Leakage Current 1 uA ILO Output Leakage Current 1 uA VIL Input Low Voltage- 0 . 5 0 . 8 V VIH Input HIgh Voltage0 . 7 V CC VCC + 0.3 V VOL Output Low Voltage I OL = 2.1 mA 0.45 V VOH Output High Voltage I OH = -100 uA VCC - 0.2 V 2.7V < VCC < 3.6V VCC = 3.6V, CE# = VIH to VCC VIN = 0V to VCC VIN = 0V to VCC , TAC = 0oC to 105oC Condition VCC = 3.6V at 33 MHz, SO = Open VCC = 3.6V at 33 MHz, SO = Open VCC = 3.6V, CE# = VCC
25Chingis Technology Corporation Issue Date: Feb., 2009, Rev: 3.5 Pm25LV512A/010A/020/040 AC CHARACTERISTICS Applicable over recommended operating range from TA = -40°C to +105°C, VCC = 2.7 V to 3.6 V C L = 1TTL Gate and 10 pF (unless otherwise noted). Symbol Parameter Min Typ Max Units fCT Clock Frequency for fast read mode 0 100 MHz fC Clock Frequency for read mode 0 33 MHz tRI Input Rise Time 8 ns tFI Input Fall Time 8 ns tCKH SCK High Time 4 ns tCKL SCK Low Time 4 ns tCEH CE# High Time 25 ns tCS CE# Setup Time 10 ns tCH CE# Hold Time 5 ns tDS Data In Setup Time 2 ns tDH Data in Hold Time 2 ns tHS Hold Setup Time 15 ns tHD Hold Time 15 ns tV Output Valid 8 ns tOH Output Hold Time Normal Mode 0 ns tLZ Hold to Output Low Z 200 ns tHZ Hold to Output High Z 200 ns tDIS Output Disable Time 100 ns tEC Secter/Block/Chip Erase Time 60 100 ms tPP Page Program Time 25 ms tW Write Status Register Time 60 100 ms tVCS VCC Set-up Time 50 µs
26Chingis Technology Corporation Issue Date: Feb., 2009, Rev: 3.5 Pm25LV512A/010A/020/040 AC CHARACTERISTICS (CONTINUED) SERIAL INPUT/OUTPUT TIMING (1) Note: 1. For SPI Mode 0 (0,0) VALID IN CE# VIL VIH SCK VIH VIH VOH VIL VIL VOL SI SO tCS tCKH tCKL tCEH tDHtDS tV tDIStOH HI-ZHI-Z tCH
27Chingis Technology Corporation Issue Date: Feb., 2009, Rev: 3.5 Pm25LV512A/010A/020/040 AC CHARACTERISTICS (CONTINUED) tHD tHD tHS tHS tHZ tLZ CE# SCK HOLD# SO HOLD TIMING Typ Max Units Conditions C IN 46 p F V IN = 0 V C OUT 81 2 p F V OUT = 0 V PIN CAPACITANCE ( f = 1 MHz, T = 25°C ) Note: These parameters are characterized but not 100% tested. OUTPUT TEST LOAD INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Vcc 1.8 K 1.3 K OUTPUT PIN 10 pF 0.8Vcc 0.2Vcc
0.5 Vcc
Note: 1. Input Pulse Voltage : 0.2Vcc to 0.8Vcc. 2. Input Timing Reference Voltages : 0.3Vcc to 0.7Vcc. 3. Output Timing Reference Voltage : Vcc/2.
28Chingis Technology Corporation Issue Date: Feb., 2009, Rev: 3.5 Pm25LV512A/010A/020/040 POWER-UP AND POWER-DOWN At Power-up and Power-down, the device must not be selected (CE# must follow the voltage applied on Vcc) until Vcc reaches the correct value: - Vcc(min) at Power-up, and then for a further delay of tVCE - Vss at Power-down Usually a simple pull-up resistor on CE# can be used to insure safe and proper Power-up and Power-down. To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while Vcc is less than the POR threshold value (Vwi) during power up, the device does not respond to any instruction until a time delay of tPUW has elapsed after the moment that Vcc rised above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, Vcc is still below Vcc(min). No Write Status Chip Selection Not Allowed All Write Commands are Rejected tVCE Read Access Allowed Device fully accessible tPUW Vcc Vcc(max) Vcc(min) Reset State V (write inhibit) Time Symbol Parameter Min. Max. Unit tVCE *1 Vcc(min) to CE# Low 10 us tPUW *1 Power-Up time delay to Write instruction 1 10 ms V WI *1 Write Inhibit Voltage 2.1 2.3 V Note : *1. These parameters are characterized only. Power-up Timing Register, Program or Erase instructions should be sent until the later of: - tPUW after Vcc passed the VWI threshold - tVCE after Vcc passed the Vcc(min) level At Power-up, the device is in the following state: - The device is in the Standby mode - The Write Enable Latch (WEL) bit is reset At Power-down, when Vcc drops from the operating voltage, to below the Vwi, all write operations are dis- abled and the device does not respond to any write instruction.
29Chingis Technology Corporation Issue Date: Feb., 2009, Rev: 3.5 Pm25LV512A/010A/020/040 PROGRAM/ERASE PERFORMANCE Parameter Unit Typ Max Remarks Sector Erase Time ms 60 100 From writing erase command to erase completion Block Erase Time ms 60 100 From writing erase command to erase completion Chip Erase Time ms 60 100 From writing erase command to erase completion Page Programming Time ms 2 5 From writing program command to program completion Parameter Min Typ Unit Test Method Endurance 200,000 Cycles JEDEC Standard A117 Data Retention 20 Y ears JEDEC Standard A103 ESD - Human Body Model 2,000 Volts JEDEC Standard A114 ESD - Machine Model 200 Volts JEDEC Standard A115 ESD - Charged Device Model 1,000 Volts JEDEC Standard C101-A Latch-Up 100 + I CC1 mA JEDEC Standard 78 Note: These parameters are characterized and are not 100% tested. Note: These parameters are characterized and are not 100% tested. RELIABILITY CHARACTERISTICS
30Chingis Technology Corporation Issue Date: Feb., 2009, Rev: 3.5 Pm25LV512A/010A/020/040 PACKAGE TYPE INFORMA TION End View 5.00 4.80 Top View Side View 4.00 3.80 6.20 5.80 1.75 1.35 0.25 0.10 0.51 0.33
1.27 BSC
0.25 0.19 1.27 0.40 45º 0.595 0.495 8-Pin JEDEC 150mil Small Outline Integrated Circuit (SOIC) Package (measure in millimeters)
31Chingis Technology Corporation Issue Date: Feb., 2009, Rev: 3.5 Pm25LV512A/010A/020/040 PACKAGE TYPE INFORMA TION End View 5.38 5.18 Top View Side View 5.38 5.18 8.10 7.70 2.16 1.75 0.25 0.05 0.48 0.35 0.25 0.19 0.80 0.50 5.38 5.18 5.33 5.13 8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit (SOIC) Package (measure in millimeters)
32Chingis Technology Corporation Issue Date: Feb., 2009, Rev: 3.5 Pm25LV512A/010A/020/040 PACKAGE TYPE INFORMA TION (CONTINUED) 8-Contact Ulta-Thin Small Outline No-Lead (WSON) Package (measure in millimeters) 5.00 BSC Top View Side View 0.48 0.35 6.00 BSC 0.80 0.70 0.25 0.19 1.27 BSC Bottom View Pin 1 0.75 0.50 4.00 3.40
33Chingis Technology Corporation Issue Date: Feb., 2009, Rev: 3.5 Pm25LV512A/010A/020/040 PACKAGE TYPE INFORMA TION (CONTINUED) 8-pin 300mil wide body, Plastic Dual In-Line Package PDIP (measure in millimeters) 9.53 9.12 6.60 6.20 9.40 8.38 15o 3.45 3.25 0.38(min) 2.54 (typ) 8.26 7.62 4.20 3.60 3.18(min) 1.65 1.40 0.56 0.36
34Chingis Technology Corporation Issue Date: Feb., 2009, Rev: 3.5 Pm25LV512A/010A/020/040 PACKAGE TYPE INFORMA TION (CONTINUED) 8-pin TSSOP Package (measure in millimeters) Pin1 4.5 0.65 4.3 6.6 6.2 3.1 2.9 0.30 0.25 1.05 1.00 1.05 1.20 0.15 0.05 0.7 0.5 0.25 GAGE PLANE Detail A Detail A 0.127 Unit : m illim eters
35Chingis Technology Corporation Issue Date: Feb., 2009, Rev: 3.5 Pm25LV512A/010A/020/040 REVISION HISTOR Y Date Revision No. Description of Changes Page No. January , 2004 0.3 Advanced Product Specification All March, 2004 0.4 Extend The Range of Operation T emperature All August, 2004 0.5 Correct part no for WSON package Register status setting 6,7,8 October , 2004 0.6 Correct part no Register setting for small sector feathure Al l page 7 January , 2005 0.7 Preliminary version release January , 2005 0.8 1. Support 208mil SOI C package 2. Correct read timing for D0 latch by HOST 3. Remove T urbo mode Al l February , 2005 0.9 Support 33MHz Removed bask side metal of WSON Standby current 1,3,15,23,24, May , 2005 1.0 JEDEC I D READ instruction Correct the smaller sector (1KB) feature 6,7,10,12 June, 2005 1.1 Description update for the operation of Configuration Register 8,9,15,16 July , 2005 2.0 Support 75MHz for Fast Read Mode All July , 2005 2.1 1. Update fast read speed to 100MHz. 2. Sectore/Block archeticture description. 3. Ordering information - remove non-pbfree parts. 4. Highligh no require WREN before WRCR command. 5. AC measurement conditions. 1,3,16,28 November , 2005 2.3 1. Change AC paramaters for 100MHz spec. Tv 8ns with 10pF Loading, Data I n Hold/Setup tiime 2ns(min), Clock high/low time 4ns(min) TRI, TFI, 8ns(max), TDIS 10ns(max) 2. Support Commercial Grade to -40~+85degreeC 3. Partno chage for Pm25LV010 to Pm25LV010A. 3, 24,25 February , 2006 2.4 1. Update endurance to 200K cycle. 2. Update write inhibit spec. to 2.1V . 3. Update ESD CDM spec 1000V. 1,9,28 March, 2006 2.5 1.Change Logo and company name 2.Modified test condition for DC Al l March, 2006 2.6 Extend the operated temperature to +105degreeC 3,23,24,25 April, 2006 2.7 1. Update Pm25LV512A in the datasheet 2. Correct tCH definition 3. Power-up timing difinition Al l 25,26 May , 2006 2.8 Correct the statement of hardware write protection 9 June, 2006 2.9 Support 8-pin PDI P package for 4Mb SPI 1,2,3,33 May , 2007 3.0 Support sector lock/unlock features Update erase and WRSR time 1,10,11 1,26,30 Jan. 2008 3.1 Support TSSOP package for Pm25LV512A. Support Sector Lock/Unlock for Pm25LV020. 1, 3,35 10,11 Feb. 2008 3.2 Support WSON with back side metal 3, 34
36Chingis Technology Corporation Issue Date: Feb., 2009, Rev: 3.5 Pm25LV512A/010A/020/040 Dat e R e vision N o . Descri pt i o n o f Changes Page N o. Ju n, 20 08 3. 3 Add t h e TSSO P p a r t n umbe r 3 Ju l y , 20 08 3. 4 Re mo ve 8 Q pa c k a ge 3 F eb, 20 09 3 . 5 M od i fy D C C H Z table 24