PM25LQ020 ETC | Alldatasheet

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Technical content

Chingis Technology Corp. 1 DRAFT Date February. 2012, Rev: 05

FEATURES

  • Single Power Supply Operation - Low voltage range: 2.3 V - 3.6 V
  • Memory Organization - Pm25LQ020: 256K x 8 (2 Mbit) - Pm25LQ040: 512K x 8 (4 Mbit)
  • Cost Effective Sector/Block Architecture - 2Mb / 4Mb : Uniform 4KByte sectors / sixteen uniform 64KByte blocks
  • Serial Peripheral Interface (SPI) Compatible - Supports single-, dual- or quad-output - Supports SPI Modes 0 and 3 - Maximum 33 MHz clock rate for normal read - Maximum 104 MHz clock rate for fast read - Maximum 208MHz clock rate - Maximum 400MHz clock rate equivalent Quad SPI
  • Byte Program Operation - Typical 10 us/Byte
  • Page Program (up to 256 Bytes) Operation - Maximum 0.7ms per page program
  • Sector, Block or Chip Erase Operation - Sector Erase (4KB)150ms (Typ) - Block Erase (64KB)500ms (Typ) - Chip Erase 0.5s (2Mb) - Chip Erase  1s (4Mb)

2 Mbit / 4 Mbit Single Operating

Voltage Serial Flash Memory With 104 MHz Dual- or 100MHz Quad-Output SPI Bus Interface

  • Low Power Consumption - Max 12 mA active read current - Max 20 mA program/erase current - Max 50 uA standby current
  • Hardware Write Protection - Protect and unprotect the device from write operation by Write Protect (WP#) Pin
  • Software Write Protection - The Block Protect (BP3, BP2, BP1, BP0) bits allow partial or entire memory to be configured as read-only
  • High Product Endurance - Guaranteed 100,000 program/erase cycles per single sector - Minimum 20 years data retention
  • Industrial Standard Pin-out and Package - 8-pin 208mil SOIC - 8-pin 150mil SOIC - 8-pin 150mil VVSOP - 8-contact WSON - 8-contact USON - PDIP - Lead-free (Pb-free), halogen-free package
  • Additional 256-byte Security information one-time programmable (OTP) area
  • Special protect function - Safe guard function (Appendix 1) - Sector unlock function (Appendix 2) GENERAL DESCRIPTION The Pm25LQ020/040 is 2 Mbit / 4 Mbit Serial Peripheral Interface (SPI) Flash memories, providing single-, dual or quad-output. The devices are designed to support a 33 MHz fclock rate in normal read mode, and 104 MHz in fast read (Quad output is 100MHz), the fastest in the industry. The devices use a single low voltage power supply, ranging from 2.3 Volt to 3.6 Volt, to perform read, erase and program operations. The devices can be programmed in standard EPROM programmers. The Pm25LQ020/040 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output (Sl), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. The devices support p age program mode, where 1 to 256 bytes data can be programmed into the memory in one program operation. These devices are divided into uniform 4 KByte sectors or uniform 64 KByte blocks. The Pm25LQ020/040 are offered in 8-pin SOIC 208mil, 8-pin PDIP, 8-pin VVSOP, 8-contact WSON and 8- contact USON.

Chingis Technology Corp. 2 DRAFT Date February. 2012, Rev: 05 PRODUCT ORDERING INFORMATION Pm25LQxxx - B W E Environmental Attribute E = Lead-free (Pb-free) package Temperature Range W =-40°C to +125°C Package Type B = 8-pin SOIC 208 mil (8B) S = 8-pin SOIC 150 min (8S) K = 8-contact WSON (8K) P = 8-pin PDIP (8P) E = 8-pin VVSOP 150mil K = 8-contact USON (8Z) pFlash Device Number Pm25LQ020 Pm25LQ040 Part Number Operating Frequency (MHz) Package Temperature Range Pm25LQ020-BWE 104 8B 208mil SOIC (-40oC to +125oC) Pm25LQ040-BWE Pm25LQ020-SWE 104 8S 150min SOIC Pm25LQ040-SWE Pm25LQ020-KWE 104 8K WSON Pm25LQ040-KWE Pm25LQ020-PWE 104 8P 300mil PDIP Pm25LQ040-PWE Pm25LQ020-EWE 104 8E 150mil VVSOP Pm25LQ040-EWE Pm25LQ020-ZWE 104 8Z USON

Chingis Technology Corp. 3 DRAFT Date February. 2012, Rev: 05 CONNECTION DIAGRAMS Vcc NC(IO3) SCK SI(IO0) SO(IO1) GND WP#(IO2) CE# CE# CE# GND Vcc HOLD# (IO3) SCK SI (IO0) SI (IO0) SCK HOLD#(IO3) Vcc SO (IO1) WP# (IO2) GND 8-Pin SOIC/VVSOP 8-Contact WSON WP# (IO2) SO (IO1) HOLD#(IO3) 8-Pin PDIP 8-Contact USON

Chingis Technology Corp. 4 DRAFT Date February. 2012, Rev: 05 PIN DESCRIPTIONS SYMBOL TYPE DESCRIPTION CE# INPUT Chip Enable: CE# low activates the devices internal circuitries for device operation. CE# high deselects the devices and switches into standby mode to reduce the power consumption. When a device is not selected, data will not be accepted via the serial input pin (Sl), and the serial output pin (SO) will remain in a high impedance state. SCK INPUT Serial Data Clock SI (IO0) INPUT/OUTPUT Serial Data Input/Output SO (IO1) INPUT/OUTPUT Serial Data Input/Output GND Ground Vcc Device Power Supply WP# (IO2) INPUT/OUTPUT Write Protect/Serial Data Output: A hardware program/erase protection for all or part of a memory array. When the WP# pin is low, memory array write-protection depends on the setting of BP3, BP2, BP1 and BP0 bits in the Status Register. When the WP# is high, the status register are not write-protected. HOLD# (IO3) INPUT/OUTPUT Hold: Pause serial communication by the master device without resetting the serial sequence. Serial Data Input & Output (for 4xI/O read mode)

Chingis Technology Corp. 5 DRAFT Date February. 2012, Rev: 05 BLOCK DIAGRAM SI (IO0) WP# (IO2) HOLD# (IO3) SO (IO1)

Chingis Technology Corp. 7 DRAFT Date February. 2012, Rev: 05 SYSTEM CONFIGURATION The Pm25LQ020/040 devices are designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of the Motorola MC68HCxx series of microcontrollers or any SPI interface -equipped system controllers. The devices have two superset features that can be enabled through specific software instructions and the Configuration Register: 1. Configurable sector size: The memory array of Pm25LQ020/040 is divided into uniform 4 KByte sectors or uniform 64 KByte blocks (a block consists of sixteen adjacent sectors). Table 1 illustrates the memory map of the devices.

Table 1. Block/Sector Addresses of Pm25LQ020 Table 2. Block/Sector Addresses of Pm25LQ040

Status Register Bit Definitions. WEL bit is set by a Write Enable (WREN) instruction. 8 and 9 for the Block Write Protection bit settings. (WP#) signal to provide a Hardware Protection Mode. can be changed by a WRSR instruction. Table 5. Status Register Format

  • The default value of the BP3, BP2, BP1, BP0, and SRWD bits were set to “0” at factory.

Table 6. Status Register Bit Definition Table 9. Block Write Protect Bits for Pm25LQ020/040

protection mechanisms: hardware and software. instruction command sequence will be ignored. ignored when Vcc drop to 2.0V and lower. to the STATUS REGISTER description. register instruction will be ignored. Table 10. Hardware Write Protection on Status

0 Low Writable

1 Low Protected

0 High Writable

1 High Writable

sequence has been shifted in. following operational descriptions. Table 11. Instruction Set

Chingis Technology Corp. 12 DRAFT Date February. 2012, Rev: 05 FAST_READ 0Bh Read Data Bytes from Memory at Fast Read Mode 5 Bytes 104 MHz FRDO 3Bh Fast Read Dual Output 5 Bytes 104 MHz FRDIO BBh Fast Read Dual I/O 3 Bytes 104MHz FRQO 6Bh Fast Read Quad Output 5 Bytes 100 MHz FRQIO EBh Fast Read Quad I/O 2 Bytes 100MHz MR FFh Mode Reset 2 Byte 104MHz PAGE_ PROG 02h Page Program Data Bytes Into Memory 4 Bytes + 256B

104 MHz

SECTOR_ER D7h/ 20h Sector Erase 4 Bytes 104 MHz BLOCK_ER (64KB) D8h Block Erase 64K byte 4 Bytes 104 MHz CHIP_ER C7h/ 60h Chip Erase 1 Byte 104 MHz Quad page program 32h Page Program Data Bytes Into Memory with Quad interface 4 Bytes + 256B Program/Erase suspend 75h /B0h Suspend during the program/erase 104MHz Program/Erase resume 7Ah /30h Resume program/erase 104MHz Program information Raw B1h Program 256 bytes of Security area 4 Bytes 104 MHz Read information Raw 4Bh Read 256 bytes of Security area 4 Bytes 33 MHz HOLD OPERATION HOLD# is used in conjunction with CE# to select the Pm25LQ020/040. When the devices are selected and a serial sequence is underway, HOLD# can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, HOLD# is brought low while the SCK signal is low. To resume serial communication, HOLD# is brought high while the SCK signal is low (SCK may still toggle during HOLD). Inputs to Sl will be ignored while SO is in the high impedance state.

Table 12. Product Identification Figure 3. Read Product Identification Sequence

3 Dummy Bytes

Figure 4. Read Product Identification by JEDEC ID READ Sequence

bit being latched-in on SI during the rising edge of SCK. Figure 5. Read Product Identification by RDMDID READ Sequence

Chingis Technology Corp. 16 DRAFT Date February. 2012, Rev: 05 48 49 50 51 52 53 54 55 56 SCK SIO SO 6 5 4 3 2 17 0 Data Out3 CE# Note : (1) ADDRESS A0 = 0, will output the 1st manufacture ID (9Dh) first -> device ID1 -> 2nd manufacture ID (7Fh) ADDRESS A0 = 1, will output the device ID1 -> 1st manufacture ID (9D) -> 2nd manufacture ID (7Fh)

Table 13. Address Key Figure 12. Read Data Sequence

data at up to a 104 MHz clock. Figure 13. Fast Read Data Sequence

two output pins each at up to a 104 MHz clock. second bit is output on SIO. Figure 14. Fast Read Dual-Output Sequence

directly from the SPI in some applications. 15 illustrates the timing sequence. instruction is terminated by driving CE# high (VIH). Figure 15. Fast Read Dual I/O Sequence (with command decode cycles)

Figure 16. Fast Read Dual I/O Sequence (without command decode cycles) four output pins each at up to a 100 MHz clock. third bit is output on IO1, etc.

Figure 17. Fast Read Quad-Output Sequence

Chingis Technology Corp. 25 DRAFT Date February. 2012, Rev: 05 DEVICE OPERATION (CONTINUED) FRQIO COMMAND (FAST READ QUAD I/O) OPERATION The FRQIO instruction is similar to the FRQO instruction, but allows the address bits to be input four bits at a time. This may allow for code to be executed directly from the SPI in some applications. The FRQIO instruction code is followed by three address bytes (A23 – A0) and a mode byte, transmitted via the IO3, IO2, IO0 and IO1 lines, with each group of four bits latched-in during the rising edge of SCK. The address MSb is input on IO3, the next bit on IO2, the next bit on IO1, the next bit on IO0, and continue to shift in alternating on the four. The mode byte contains the value Ax, where x is a “don’t care” value. After four dummy clocks, the first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group of four bits shifted out at a maximum frequency fCT, during the falling edge of SCK. The first bit (MSb) is output on IO3, while simultaneously the second bit is output on IO2, the third bit is output on IO1, etc. Figure 18 illustrates the timing sequence. The first byte addressed can be at any memory location. The address is automatically incremented after each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single FRQIO instruction. FRQIO instruction is terminated by driving CE# high (VIH). The device expects the next operation will be another FRQIO. It remains in this mode until it receives a Mode Reset (FFh) command. In subsequent FRDIO execution, the command code is not input, saving cycles as described in Figure 19. If a FRQIO instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle

Figure 18. Fast Read Quad I/O Sequence (with command decode cycles)

area set by the Block Protection (BP2, BP1, BP0) bits. into a page that is write-protected will be ignored. Write Enable (WREN) instruction. bytes data are kept to be programmed into the page. The starting byte can be anywhere within the page. erasing the whole sector or block. Figure 21. Page Program Sequence

Chingis Technology Corp. 29 DRAFT Date February. 2012, Rev: 05 DEVICE OPERATION (CONTINUED) The Quad Input Page Program instruction allows up to 256 bytes data to be programmed into memory in a single operation with four pins (IO0, IO1, IO2 and IO3). The destination of the memory to be programmed must be outside the protected memory area set by the Block Protection (BP3, BP2, BP1, BP0) bits. A Quad Input Page Program instruction which attempts to program into a page that is write- protected will be ignored. Before the execution of Quad Input Page Program instruction, the QE bit in the status register must be set to “1” and the Write Enable Latch (WEL) must be enabled through a Write Enable (WREN) instruction. The Quad Input Page Program instruction code, three address bytes and program data (1 to 256 bytes) are input via the four pins (IO0, IO1, IO2 and IO3). Program operation will start immediately after the CE# is brought high, otherwise the Quad Input Page Program instruction will not be executed. The internal control logic automatically handles the programming voltages and timing. During a program operation, all instructions will be ignored except the RDSR instruction. The progress or completion of the program operation can be determined by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program operation is still in progress. If WIP bit is “0”, the program operation has completed. If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page. The starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap around to the beginning of the same page. If the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s. A byte cannot be reprogrammed without first erasing the whole sector or block.

Chingis Technology Corp. 30 DRAFT Date February. 2012, Rev: 05 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 ... INSTRUCTION = 0101 0010b ...23 22 21 3 2 1 0 3 - BYTE ADDRESS CE# SCK IO0 IO1 32 33 34 35 36 37 38 39 CE# SCK IO0 IO1 DATA IN 1 DATA IN 2 6IO2 IO3 DATA IN n. . . IO2 IO3 00110010b

Chingis Technology Corp. 31 DRAFT Date February. 2012, Rev: 05 DEVICE OPERATION (CONTINUED) ERASE OPERATION The memory array of the Pm25LQ020/040 is organized into uniform 4 Kbyte sectors or 64 Kbyte uniform blocks (a block consists of sixteen adjacent sectors). Before a byte can be reprogrammed, the sector or block that contains the byte must be erased (erasing sets bits to “1”). In order to erase the devices, there are three erase instructions available: Sector Erase (SECTOR_ER), Block Erase (BLOCK_ER) and Chip Erase (CHIP_ER). A sector erase operation allows any individual sector to be erased without affecting the data in other sectors. A block erase operation erases any individual block. A chip erase operation erases the whole memory array of a device. A sector erase, block erase or chip erase operation can be executed prior to any programming operation. SECTOR_ER COMMAND (SECTOR ERASE) OPERATION A SECTOR_ER instruction erases a 4 Kbyte sector Before the execution of a SECTOR_ER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is reset automatically after the completion of sector an erase operation. A SECTOR_ER instruction is entered, after CE# is pulled low to select the device and stays low during the entire instruction sequence The SECTOR_ER instruction code, and three address bytes are input via SI. Erase operation will start immediately after CE# is pulled high. The internal control logic automatically handles the erase voltage and timing. Refer to Figure 22 for Sector Erase Sequence. During an erase operation, all instruction will be ignored except the Read Status Register (RDSR) instruction. The progress or completion of the erase operation can be determined by reading the WIP bit in the Status Register using a RDSR instruction. If the WIP bit is “1”, the erase operation is still in progress. If the WIP bit is “0”, the erase operation has been completed. BLOCK_ER COMMAND (BLOCK ERASE) OPERATION A Block Erase (BLOCK_ER) instruction erases a 64 Kbyte block of the Pm25LQ016. Before the execution of a BLOCK_ER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically after the completion of a block erase operation. The BLOCK_ER instruction code and three address bytes are input via SI. Erase operation will start immediately after the CE# is pulled high, otherwise the BLOCK_ER instruction will not be executed. The internal control logic automatically handles the erase voltage and timing. Refer to Figure 23 for Block Erase Sequence. CHIP_ER COMMAND (CHIP ERASE) OPERATION A Chip Erase (CHIP_ER) instruction erases the entire memory array of a Pm25LQ016. Before the execution of CHIP_ER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically after completion of a chip erase operation. The CHIP_ER instruction code is input via the SI. Erase operation will start immediately after CE# is pulled high, otherwise the CHIP_ER instruction will not be executed. The internal control logic automatically handles the erase voltage and timing. Refer to Figure 24 for Chip Erase Sequence.

completed. At some unspecified time before the cycle is complete, the write enable latch (WEL) bit is reset. Figure 30. Program information Raw Sequence Note: 1. The SIR address is from 000000h to 0000FFh.

  1. The SIR protection bit is in the address 000100h.

Chingis Technology Corp. 34 DRAFT Date February. 2012, Rev: 05 DEVICE OPERATION (CONTINUED) To lock the OTP memory: Bit 0 of the OTP control byte, that is byte 256, is used to permanently lock the OTP memory array. When bit 0 of byte 256 = ’1’, the 256 bytes of the OTP memory array can be programmed. When bit 0 of byte 256 = ‘0’, the 256 bytes of the OTP memory array are read-only and cannot be programmed anymore. Once a bit of the OTP memory has been programmed to ‘0’, it can no longer be set to ‘1’. Therefore, as soon as bit 0 of byte 256 (control byte) is set to ‘0’, the 256 bytes of the OTP memory array become read-only in a permanent way. Any program OTP (POTP) instruction issued while an erase, program or write cycle is in progress is rejected without having any effect on the cycle that is in progress Byte1 Byte2 Byte256Byte255 OTP control byte Bit 0X X X X X X X Bit 1~bit 7 do not care When bit 0 = 0 the 256 OTP bytes become read only

Chingis Technology Corp. 35 DRAFT Date February. 2012, Rev: 05 DEVICE OPERATION (CONTINUED) Read Security Information Row (RSIR) The RSIR instruction read the security information Row. There is no rollover mechanism with the read OTP (ROTP) instruction. This means that the read OTP (ROTP) instruction must be sent with a maximum of 256 bytes to read, since once the 256th byte has been read, the same (256th) byte keeps being read on the SO pin. Fig 33. Read Security information Row instruction 0 1 2 3 4 5 6 7 ... INSTRUCTION = 0100 1011b ... CE# SCK SI 40 41 42 43 44 45 46 47 ... ... CE# SCK SO 8 9 10 11 28 29 30 31 24-bit address 2223 21 2 1 0 MSB MSB 6 5 4 3 2 1 0 Data outpur 1 7 6 5 Data output 2 Data output N SO 7 0 33 34 36 37 38 3932 35 SI 6 5 4 3 2 1 Data Out0

Chingis Technology Corp. 36 DRAFT Date February. 2012, Rev: 05 DEVICE OPERATION (CONTINUED) The device allow the interruption of Sector -Erase, Block-Erase or Page -Program operations and conduct other operations. To enter the suspend/ resume mode: issuing 75h/B0h for suspend; 7Ah/30h for resume Suspend to suspend ready timing: 20us. Resume to another suspend timing: 1ms. *Note: It needs 500ns delay time from write command to suspend command After erase suspend, WEL bit will be clear, only read related and resume command can be accepted. (03h, 0Bh, BBh, EBh, 05h, ABh, 9Fh, 90h, 4Bh) To execute a Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend command cycle (75H/B0h), then drives CE# high. The device will not accept another command until it is ready. To determine when the device will accept a new command, poll the WIP bit in the Status register or wait TWS. Program suspend allows the interruption of all program operations. After program suspend, WEL bit will be cleared, only read related and resume command can be accepted. (03h, 0Bh, BBh, EBh, 05h, ABh, 9Fh, 90h, 4Bh) To execute a Program/Erase Suspend operation, the host drives CE# low, sends the Program/Erase Suspend command cycle (75H/B0h), then drives CE# high. The device will not accept another command until it is ready. To determine when the device will accept a new command, poll the WIP bit in the Status register or wait TWS. Program/Erase Resume restarts a Program/Erase command that was suspended. To execute a Program/Erase Resume operation, the host drives CE# low, sends the Program/Erase Resume command cycle (7AH/30h), then drives CE# high. To determine if the internal, self-timed Write operation completed, poll the WIP bit in the Status register, or wait the specified time TSE, TBE or TPP for Sector- Erase, Block-Erase, or Page-Programming, respectively. The total write time before suspend and after resume will not exceed the uninterrupted write times TSE, TBE or TPP.

Chingis Technology Corp. 37 DRAFT Date February. 2012, Rev: 05 ABSOLUTE MAXIMUM RATINGS (1) Storage Temperature -55oC to +125oC Surface Mount Lead Soldering Temperature Standard Package 240oC 3 Seconds Lead-free Package 260oC 3 Seconds Input Voltage with Respect to Ground on All Pins (2) -0.5 V to VCC + 0.5 V All Output Voltage with Respect to Ground -0.5 V to VCC + 0.5 V VCC (2) -0.5 V to +6.0 V Notes: 1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. The functional operation of the device conditions that exceed those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condition for extended periods may affect device reliability. 2. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may overshoot VCC by + 2.0 V for a period of time not to exceed 20 ns. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot GND by -2.0 V for a period of time not to exceed 20 ns. DC AND AC OPERATING RANGE Part Number Pm25LQ020/040 Operating Temperature -40oC to 125oC Vcc Power Supply 2.3 V – 3.6 V DC CHARACTERISTICS Applicable over recommended operating range from: TAC = -40°C to +125°C, VCC = 2.3 V to 3.6 V (unless otherwise noted). Symbol Parameter Condition Min Ty p Max Units ICC1 Vcc Active Read Current VCC = 3.6V at 33 MHz, SO = Open 10 12 mA ICC2 Vcc Program/Erase Current VCC = 3.6V at 33 MHz, SO = Open 15 20 mA ISB1 Vcc Standby Current CMOS VCC = 3.6V, CE# = VCC 10 30 A ISB3 Vcc Standby Current TTL VCC = 3.6V, CE# = VIH to VCC 3 mA ILI Input Leakage Current VIN = 0V to VCC 1 A ILO Output Leakage Current VIN = 0V to VCC, TAC = 0oC to 130oC 1 A VIL Input Low Voltage -0.5 0.3Vcc V VIH Input High Voltage 0.7VCC VCC + 0.3 V VOL Output Low Voltage 2.3V < VCC < 3.6V IOL = 2.1 mA 0.45 V VOH Output High Voltage IOH = -100 A VCC – 0.2 V

Chingis Technology Corp. 38 DRAFT Date February. 2012, Rev: 05 AC CHARACTERISTICS Applicable over recommended operating range from TA = -40°C to +125°C, VCC = 2.3 V to 3.6 V CL = 1 TTL Gate and 30 pF (unless otherwise noted). Symbol Parameter Min Typ Max Units fCT Clock Frequency for fast read mode 0 104 MHz fC Clock Frequency for read mode 0 33 MHz tRI Input Rise Time 8 ns tFI Input Fall Time 8 ns tCKH SCK High Time 4 ns tCKL SCK Low Time 4 ns tCEH CE# High Time 25 ns tCS CE# Setup Time 10 ns tCH CE# Hold Time 5 ns tDS Data In Setup Time 2 ns tDH Data in Hold Time 2 ns tHS Hold Setup Time 15 ns tHD Hold Time 15 ns tV Output Valid 8 ns tOH Output Hold Time Normal Mode 0 ns tLZ Hold to Output Low Z 200 ns tHZ Hold to Output High Z 200 ns tDIS Output Disable Time 100 ns tEC Secter Erase Time 120 300 ms Block Erase Time(64Kbyte) 0.25 1 s Chip Erase Time (2Mb) 0.75 1.5 s Chip Erase Time (4Mb) 1.5 3 s tPP Page Program Time 0.5 1 ms tres1 3 s tdp 3 s tw Write Status Register time 2 10 ms Tws Suspend time 20 us

Chingis Technology Corp. 39 DRAFT Date February. 2012, Rev: 05 AC CHARACTERISTICS (CONTINUED) SERIAL INPUT/OUTPUT TIMING (1) Note: 1. For SPI Mode 0 (0,0)

Chingis Technology Corp. 40 DRAFT Date February. 2012, Rev: 05 AC CHARACTERISTICS (CONTINUED) HOLD TIMING PIN CAPACITANCE (f = 1 MHz, T = 25°C ) Typ Max Units Conditions CIN 4 6 pF VIN = 0 V COUT 8 12 pF VOUT = 0 V Note: These parameters are characterized but not 100% tested. OUTPUT TEST LOAD INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL 30pf

Chingis Technology Corp. 41 DRAFT Date February. 2012, Rev: 05 POWER-UP AND POWER-DOWN At Power-up and Power-down, the device must not be selected (CE# must follow the voltage applied on Vcc) until Vcc reaches the correct value: - Vcc(min) at Power-up, and then for a further delay of tVCE - Vss at Power-down Usually a simple pull-up resistor on CE# can be used to insure safe and proper Power-up and Power-down. To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while Vcc is less than the POR threshold value (Vwi) during power up, the device does not respond to any instruction until a time delay of tPUW has elapsed after the moment that Vcc rised above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, Vcc is still below Vcc(min). No Write Status Register, Program or Erase instructions should be sent until the later of: - tPUW after Vcc passed the VWI threshold - tVCE after Vcc passed the Vcc(min) level At Power-up, the device is in the following state: - The device is in the Standby mode - The Write Enable Latch (WEL) bit is reset At Power-down, when Vcc drops from the operating voltage, to below the Vwi, all write operations are disabled and the device does not respond to any write instruction. Chip Selection Not Allowed All Write Commands are Rejected tVCE Read Access Allowed Device fully accessible tPUW Vcc Vcc(max) Vcc(min) Reset State V (write inhibit) Time Symbol Parameter Min. Max. Unit tVCE *1 Vcc(min) to CE# Low 10 us tPUW *1 Power-Up time delay to Write instruction 1 10 ms VWI *1 Write Inhibit Voltage 2.4 V Note : *1. These parameters are characterized only. 2.0 150

Chingis Technology Corp. 42 DRAFT Date February. 2012, Rev: 05 PROGRAM/ERASE PERFORMANCE Parameter Unit Typ Max Remarks Sector Erase Time ms 120 300 Block Erase Time (64KB) ms 250 1000 Chip Erase Time (2Mb) s 0.75 1.5 Chip Erase Time (4Mb) s 1.5 3 Page Programming Time ms 0.5 1 Byte Program us 8 25 Note: These parameters are characterized and are not 100% tested. RELIABILITY CHARACTERISTICS Parameter Min Typ Unit Test Method Endurance 100,000 Cycles JEDEC Standard A117 Data Retention 20 Years JEDEC Standard A103 ESD – Human Body Model 2,000 Volts JEDEC Standard A114 ESD – Machine Model 200 Volts JEDEC Standard A115 Latch-Up 100 + ICC1 mA JEDEC Standard 78 Note: These parameters are characterized and are not 100% tested.

Chingis Technology Corp. 43 DRAFT Date February. 2012, Rev: 05 PACKAGE TYPE INFORMATION 8-Pin JEDEC 150mil Broad Small Outline Integrated Circuit (SOIC) Package (measure in millimeters)

Chingis Technology Corp. 44 DRAFT Date February. 2012, Rev: 05 PACKAGE TYPE INFORMATION (CONTINUED) 8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit (SOIC) Package (measure in millimeters)

Chingis Technology Corp. 45 DRAFT Date February. 2012, Rev: 05 PACKAGE TYPE INFORMATION (CONTINUED) 8-pin USON Package (measure in millimeters)

Chingis Technology Corp. 46 DRAFT Date February. 2012, Rev: 05 PACKAGE TYPE INFORMATION (CONTINUED) 8-Contact Ulta-Thin Small Outline No-Lead (WSON) Package (measure in millimeters)

Chingis Technology Corp. 47 DRAFT Date February. 2012, Rev: 05 PACKAGE TYPE INFORMATION (CONTINUED) 8-pin VVSOP 150mil

Chingis Technology Corp. 48 DRAFT Date February. 2012, Rev: 05

Chingis Technology Corp. 49 DRAFT Date February. 2012, Rev: 05 Appendix1: Safe Guard function Safe Guard function is a security function for customer to protect by sector (4Kbyte). Every sector has one bit register to decide it will under safe guard protect or not. (“0”means protect and “1” means not protect by safe guard.) Pm25LQ020 (sector 0~sector 63) Pm25LQ040 (sector 0~sector 127) Mapping table for safe guard register Address D7 D6 D5 D4 D3 D2 D1 D0 Sector 0 000h 1 1 1 1 1 1 1 0 Sector 1 000h 1 1 1 1 1 1 0 1 Sector 2 000h 1 1 1 1 1 0 1 1 Sector 3 000h 1 1 1 1 0 1 1 1 Sector 4 000h 1 1 1 0 1 1 1 1 Sector 5 000h 1 1 0 1 1 1 1 1 Sector 6 000h 1 0 1 1 1 1 1 1 Sector 7 000h 0 1 1 1 1 1 1 1 Sector 56 006h 1 1 1 1 1 1 1 0 Sector 57 006h 1 1 1 1 1 1 0 1 Sector 58 006h 1 1 1 1 1 0 1 1 Sector 59 006h 1 1 1 1 0 1 1 1 Sector 60 006h 1 1 1 0 1 1 1 1 Sector 61 006h 1 1 0 1 1 1 1 1 Sector 62 006h 1 0 1 1 1 1 1 1 Sector 63 006h 0 1 1 1 1 1 1 1 Sector 120 00Fh 1 1 1 1 1 1 1 0 Sector 121 00Fh 1 1 1 1 1 1 0 1 Sector 122 00Fh 1 1 1 1 1 0 1 1 Sector 123 00Fh 1 1 1 1 0 1 1 1 Sector 124 00Fh 1 1 1 0 1 1 1 1 Sector 125 00Fh 1 1 0 1 1 1 1 1 Sector 126 00Fh 1 0 1 1 1 1 1 1 Sector 127 00Fh 0 1 1 1 1 1 1 1

Chingis Technology Corp. 50 DRAFT Date February. 2012, Rev: 05 Read Safe Guard register The READ Safe Guard instruction code is transmitted via the SlO line, followed by three address bytes (A23 - A0) of the first register location to be read. The first byte data (D7 - D0) addressed is then shifted out on the SO line, MSb first. The address is automatically incremented after each byte of data is shifted out. The read operation can be terminated at any time by driving CE# high (VIH) after the data comes out. Fig a. Timing waveform of Read Safe guard register Erase Safe Guard register If we want to erase the safe guard register to let the flash into unprotect status, it needs five continuous instructions. If any instruction is wrong, the erase command will be ignored. Erase wait time follow product erase timing spec. Fig b. shows the complete steps for Erase safe guard register. Program Safe Guard register If we want to erase the safe guard register to let the flash into unprotect status, it needs five continuous instructions. If any instruction is wrong, the program command will be ignored. The Program safe guard instruction allows up to 256 bytes data to be programmed into memory in a single operation. Program wait time follow product program timing spec. Fig c. shows the complete steps for program safe guard register. CS SCK SI 1 2 7 8 2Fh 9 10 23 24 A23-A0 25 26 31 32 D7-D0 D7-D0 33 34 39 40 SO 41 42 47 48 1st byte 2nd byte

Chingis Technology Corp. 51 DRAFT Date February. 2012, Rev: 05 Fig b. Erase safe guard register CS SCK SI 1 2 7 8 9 10 31 32 55h A23-A0 Sector Protection Mode Erase CS SCK SI 1 2 7 8 9 10 31 32 AAh A23-A0 CS SCK SI 1 2 7 8 9 10 31 32 80h A23-A0 CS SCK SI 1 2 7 8 9 10 31 32 AAh A23-A0 CS SCK SI 1 2 7 8 2Bh

Chingis Technology Corp. 52 DRAFT Date February. 2012, Rev: 05 Fig c. program safe guard register SCK SI 1 2 7 8 9 10 31 32 23h A23-A0 CS D7-D0 D7-D0 33 34 39 40 41 42 47 48 CS SCK SI 1 2 7 8 9 10 31 32 55h A23-A0 CS SCK SI 1 2 7 8 9 10 31 32 AAh A23-A0 CS SCK SI 1 2 7 8 9 10 31 32 A0h A23-A0 CS SCK SI 1 2 7 8 9 10 31 32 55h A23-A0 1st byte 2nd byte

Chingis Technology Corp. 53 DRAFT Date February. 2012, Rev: 05 Appendix2: Sector Unlock function Instruction Name Hex Code Operation Command Cycle Maximum Frequency SECT_UNLOCK 26h Sector unlock 4 Bytes 100 MHz SECT_LOCK 24h Sector lock 1 Byte 100 MHz SEC_UNLOCK COMMAND OPERATION The Sector unlock command allows the user to select a specific sector to allow program and erase operations. This instruction is effective when the blocks are designated as write-protected through the BP0, BP1, BP2 and BP3 bits in the status register. Only one sector can be enabled at any time. To enable a different sector, a previously enabled sector must be disabled by executing a Sector Lock command. The instruction code is followed by a 24-bit address specifying the target sector, but A0 through A11 are not decoded. The remaining sectors within the same block remain in read-only mode. Figure d. Sector Unlock Sequence Note: 1.If the clock number will not match 8 clocks(command)+ 24 clocks (address), it will be ignored. 2.It must be executed write enable (06h) before sector unlock instructions. CS SCK SI 1 2 7 8 9 10 15 16 17 18 23 24 25 26 31 321 2 7 8 06h 26h A23-A16 A15-A8 A7-A0 In the sector unlock procedure, [A11:A0] needs equal to “0”, unlock procedure is completed, otherwise chip will regard it as illegal command. Sector unlock

Chingis Technology Corp. 54 DRAFT Date February. 2012, Rev: 05 SECT_LOCK COMMAND OPERATION The Sector Lock command reverses the function of the Sector Unlock command. The instruction code does not require an address to be specified, as only one sector can be enabled at a time. The remaining sectors within the same block remain in read-only mode. Figure e. Sector Lock Sequence

Chingis Technology Corp. 55 DRAFT Date February. 2012, Rev: 05

REVISION HISTORY

Date Revision No. Description of Changes Page No. May,2012 0.1 Preliminary Product Specification All May,2012 0.2 Added 2Mb All June , 2012 0.3 Modify page program time 1,38,42 June, 2012 0.4 Added SOIC 150mil package 1,2,43 December , 2012 0.5 Added USON package Revised VVSOP dimension Revised tPP,tSE,tBE,tCE,tWRSR 1,2,45 47,48 38,42