PM25LD512 ETC2 | Alldatasheet
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Chingis Technology Corp. 1 DRAFT Date: August, 2010, Rev:0.4
FEATURES
- Single Power Supply Operation - Low voltage range: 2.3 V – 3.6 V
- Memory Organization - Pm25LD512: 64K x 8 (512 Kbit) - Pm25LD010: 128K x 8 (1 Mbit) - Pm25LD020: 256K x 8 (2 Mbit)
- Cost Effective Sector/Block Architecture - 512Kb : Uniform 4KByte sectors / Two uniform 32KByte blocks - 1Mb : Uniform 4KByte sectors / Four uniform 32KByte blocks - 2Mb : Uniform 4KByte sectors / Four uniform 64KByte blocks
- Low standby current 1uA (Typ)
- Serial Peripheral Interface (SPI) Compatible - Supports single- or dual-output - Supports SPI Modes 0 and 3 - Maximum 33 MHz clock rate for normal read - Maximum 100 MHz clock rate for fast read
- Page Program (up to 256 Bytes) Operation - Typical 2 ms per page program
- Sector, Block or Chip Erase Operation - Maximum 10 ms sector, block or chip erase
- Low Power Consumption - Typical 10 mA active read current - Typical 15 mA program/erase current
- Hardware Write Protection - Protect and unprotect the device from write operation by Write Protect (WP#) Pin
- Software Write Protection - The Block Protect (BP2, BP1, BP0) bits allow partial or entire memory to be configured as read- only
- High Product Endurance - Guaranteed 200,000 program/erase cycles per single sector - Minimum 20 years data retention
- Industrial Standard Pin-out and Package - 8-pin 150mil SOIC - 8-pin 208mil SOIC for Pm25LD040 - 8-pin 300mil PDIP for Pm25LD040 - 8-contact WSON - 8-pin TSSOP - Lead-free (Pb-free), halogen-free package GENERAL DESCRIPTION The Pm25LD512/010/020 are 512Kbit/ 1Mbit / 2Mbit Serial Peripheral Interface (SPI) Flash memories, providing single- or dual-output. The devices are designed to support a 33 MHz clock rate in normal read mode, and 100 MHz in fast read, the fastest in the industry. The devices use a single low voltage power supply, wide operating voltage ranging from 2.3 Volt to 3.6 Volt, to perform read, erase and program operations. The devices can be programmed in standard EPROM programmers. The Pm25LD512/010/020 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output (SlO), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. They comply with all recognized command codes and operations. The dual-output fast read operation provides and effective serial data rate of 200MHz. The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in one program operation. These devices are divided into uniform 4 KByte sectors or uniform 32 KByte blocks.(Pm25LD020 is uniform 4 KByte sectors or uniform 64 KByte). The Pm25LD512/010/020 are manufactured on pFLASH™’s advanced non-volatile technology. The devices are offered in 8-pin SOIC 150mil, 8-contact WSON and 8-pin TSSOP. The devices operate at wide temperatures between -40°C to +105°C. 512Kbit/ 1 Mbit / 2 Mbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus Interface
Chingis Technology Corp. 2 DRAFT Date: August, 2010, Rev:0.4 PRODUCT ORDERING INFORMATION Pm25LDxxx - S C E Environmental Attribute E = Lead-free (Pb-free) and Halogen- free package Temperature Range C = Commercial Grade (-40°C to +105°C) Package Type S = 8-pin SOIC 150mil (8S) B = 8-pin SOIC 208mil (8B) P = 8-pin PDIP 300 mil (8P) K = 8-contact WSON (8K) pFlash Device Number Pm25LD512/010/020 Part Number Operating Frequency (MHz) Package Temperature Range Pm25LD512-SCE Pm25LD010-SCE Pm25LD020-SCE 100 8S 150mil SOIC Pm25LD512-KCE Pm25LD010-KCE Pm25LD020-KCE 100 8K WSON (Back Side Metal) Pm25LD040-PCE 100 8P 300mil PDIP Pm25LD040-BCE 100 8B 208mil SOIC Pm25LD512-DCE Pm25LD010-DCE Pm25LD020-DCE 100 8-pin TSSOP Commercial Grade (-40 oC to +105oC)
Chingis Technology Corp. 3 DRAFT Date: August, 2010, Rev:0.4 CONNECTION DIAGRAMS Vcc HOLD# SCK SIO SO GND WP# CE# Vcc HOLD# SCK SIO SO GND WP# CE# PIN DESCRIPTIONS SYMBOL TYPE DESCRIPTION CE# INPUT Chip Enable: CE# low activates the devices internal circuitries for device operation. CE# high deselects the devices and switches into standby mode to reduce the power consumption. When a device is not selected, data will not be accepted via the serial input pin (SlO), and the serial output pin (SO) will remain in a high impedance state. SCK INPUT Serial Data Clock SIO INPUT/OUTPUT Serial Data Input/Output SO OUTPUT Serial Data Output GND Ground Vcc Device Power Supply WP# INPUT Write Protect: A hardware program/erase p rotection for all or part of a memory array. When the WP# pin is low, memory array write-protection depends on the setting of BP2, BP1 and BP0 bits in the Status Register. When the WP# is high, the devices are not write-protected. HOLD# INPUT Hold: Pause serial communication by the master device without resetting the serial sequence. CE# CE# SO WP# GND Vcc HOLD# SCK SIO SIO SCK HOLD# Vcc SO WP# GND 8-Pin SOIC 8-Contact WSON 8-Pin TSSOP 8-Pin PDIP
Chingis Technology Corp. 4 DRAFT Date: August, 2010, Rev:0.4 BLOCK DIAGRAM SIO
Chingis Technology Corp. 6 DRAFT Date: August, 2010, Rev:0.4 SYSTEM CONFIGURATION The Pm25LD512/010/020 devices are designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of the Motorola MC68HCxx series of microcontrollers or any SPI interface-equipped system controllers. The devices have two superset features that can be enabled through specific software instructions and the Configuration Register: Block No. Block Size (Kbytes) Sector No. Sector Size (Kbytes) Address Range Sector 0 (1) 4 000000h - 000FFFh Sector 1 4 001000h - 001FFFh : : : Sector 7 4 007000h - 007FFFh Sector 8 4 008000h - 008FFFh Sector 9 4 009000h - 009FFFh : : 000000h - 006FFFh Sector 15 4 00F000h - 00FFFFh Block 2 32 " " 010000h - 017FFFh Block 3 32 " " 018000h - 01FFFFh Memory Density
1 Mbit
512 Kbit
Table 1-1. Block/Sector Addresses of Pm25LD512/010/020 Memory Density Block No. Block Size (KBytes) Sector No. Sector Size (KBytes) Address Range Sector 0 4 000000h - 000FFFh Sector 1 4 001000h - 001FFFh : : : Block 0 64 Sector 15 4 00F000h - 00FFFFh Sector 16 4 010000h - 010FFFh Sector 17 4 011000h - 011FFFh : : : Block 1 64 Sector 31 4 01F000h - 01FFFFh : : : : :
2 Mbit
Block 3 64 : 4 030000h – 03FFFFh
Status Register Bit Definitions. Register (RDSR). Refer to Table 10 for Instruction Set. reset after the completion of a write instruction. (WP#) signal to provide a Hardware Protection Mode. Register can be changed by a WRSR instruction. Table 5. Status Register Format
Table 6. Status Register Bit Definition Table 8. Block Write Protect Bits for Pm25LD512/010/020
protection mechanisms: hardware and software. command sequence will be ignored. STATUS REGISTER description. instruction will be ignored. or the whole memory area to be write-protected. Table 9. Hardware Write Protection on Status
0 Low Writable
1 Low Protected
0 High Writable
1 High Writable
Clock (SCK) after Chip Enable (CE#) is driven low (V IL ). sequence has been shifted in. following operational descriptions. Table 10. Instruction Set
1 Byte 100 MHz
50 MHz
Table 11. Product Identification Figure 3. Read Product Identification Sequence
3 Dummy Bytes
Figure 4. Read Product Identification by JEDEC ID READ Sequence
11 Product Identification for pFlash Manufacturer ID
followed by a 24-bit address pointing to an ID table. Figure 5. Read Product Identification by RDMDID READ Sequence
Chingis Technology Corp. 14 DRAFT Date: August, 2010, Rev:0.4 Note : (1) ADDRESS A0 = 0, will output the 1st manufacture ID (9Dh) first -> device ID1 -> 2nd manufacture ID (7Fh) ADDRESS A0 = 1, will output the device ID1 -> 1st manufacture ID (9D) -> 2nd manufacture ID (7Fh)
Table 12. Address Key Figure 12. Read Data Sequence
data at up to a 100 MHz clock. Figure 13. Fast Read Data Sequence
two output pins each at up to a 100 MHz clock. Figure 14. Fast Read Dual-Output Sequence
area set by the Block Protection (BP2, BP1, BP0) bits. into a page that is write-protected will be ignored. Write Enable (WREN) instruction. bytes data are kept to be programmed into the page. The starting byte can be anywhere within the page. erasing the whole sector or block. Figure 15. Page Program Sequence
Chingis Technology Corp. 21 DRAFT Date: August, 2010, Rev:0.4 DEVICE OPERATION (CONTINUED) ERASE OPERATION The memory array of the Pm25LD512/010 is organized into uniform 4 KByte sectors or 32 KByte uniform blocks (a block consists of eight adjacent sectors). Pm25LD020 is organized into uniform 4 KByte sectors or 64 KByte uniform blocks (a block consists of sixteen adjacent sectors) Before a byte can be reprogrammed, the sector or block that contains the byte must be erased (erasing sets bits to “1”). In order to erase the devices, there are three erase instructions available: Sector Erase (SECTOR_ER), Block Erase (BLOCK_ER) and Chip Erase (CHIP_ER). A sector erase operation allows any individual sector to be erased without affecting the data in other sectors. A block erase operation erases any individual block. A chip erase operation erases the whole memory array of a device. A sector erase, block erase or chip erase operation can be executed prior to any programming operation. SECTOR_ER COMMAND (SECTOR ERASE) OPERATION A SECTOR_ER instruction erases a 4 KByte sector Before the execution of a SECTOR_ER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is reset automatically after the completion of sector an erase operation. A SECTOR_ER instruction is entered, after CE# is pulled low to select the device and stays low during the entire instruction sequence The SECTOR_ER instruction code, and three address bytes are input via SI. Erase operation will start immediately after CE# is pulled high. The internal control logic automatically handles the erase voltage and timing. Refer to Figure 14 for Sector Erase Sequence. During an erase operation, all instruction will be ignored except the Read Status Register (RDSR) instruction. The progress or completion of the erase operation can be determined by reading the WIP bit in the Status Register using a RDSR instruction. If the WIP bit is “1”, the erase operation is still in progress. If the WIP bit is “0”, the erase operation has been completed. BLOCK_ER COMMAND (BLOCK ERASE) OPERATION A Block Erase (BLOCK_ER) instruction erases a 64 KByte block of the Pm25LD512/010/020. Before the execution of a BLOCK_ER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically after the completion of a block erase operation. The BLOCK_ER instruction code and three address bytes are input via SI. Erase operation will start immediately after the CE# is pulled high, otherwise the BLOCK_ER instruction will not be executed. The internal control logic automatically handles the erase voltage and timing. Refer to Figure 15 for Block Erase Sequence. CHIP_ER COMMAND (CHIP ERASE) OPERATION A Chip Erase (CHIP_ER) instruction erases the entire memory array of a Pm25LD512/010/020. Before the execution of CHIP_ER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically after completion of a chip erase operation. The CHIP_ER instruction code is input via the SI. Erase operation will start immediately after CE# is pulled high, otherwise the CHIP_ER instruction will not be executed. The internal control logic automatically handles the erase voltage and timing. Refer to Figure 16 for Chip Erase Sequence.
Chingis Technology Corp. 23 DRAFT Date: August, 2010, Rev:0.4 ABSOLUTE MAXIMUM RATINGS (1) Temperature Under Bias -65 oC to +125 oC Storage Temperature -65 oC to +125 oC Standard Package 240 oC 3 Seconds Surface Mount Lead Soldering Temperature Lead-free Package 260 oC 3 Seconds Input Voltage with Respect to Ground on All Pins (2) -0.5 V to VCC + 0.5 V All Output Voltage with Respect to Ground -0.5 V t o VCC + 0.5 V VCC (2) -0.5 V to +6.0 V Notes: 1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. The functional operation of the device conditions that exceed those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condition for extended periods may affect device reliability. 2. Maximum DC voltage on input or I/O pins is V CC + 0.5 V. During voltage transitions, input or I/O pins may overshoot V CC by + 2.0 V for a period of time not to exceed 20 ns. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot GND by -2.0 V for a period of time not to exceed 20 ns. DC AND AC OPERATING RANGE Part Number Pm25LD512/010/020 Operating Temperature (Commercial Grade) -40 oC to105oC Vcc Power Supply 2.3 V – 3.6 V DC CHARACTERISTICS Applicable over recommended operating range from: TAC = -40°C to +105°C, V CC = 2.3 V to 3.6 V (unless otherwise noted). Symbol Parameter Condition Min Typ Max Units ICC1 Vcc Active Read Current V CC = 3.6V at 33 MHz, SO = Open 10 15 mA ICC2 Vcc Program/Erase Current V CC = 3.6V at 33 MHz, SO = Open 15 30 mA ISB1 Vcc Standby Current CMOS V CC = 3.6V, CE# = V CC 10 µA ISB2 Vcc Standby Current TTL V CC = 3.6V, CE# = V IH to V CC 3 mA ILI Input Leakage Current V IN = 0V to V CC 1 µA ILO Output Leakage Current V IN = 0V to V CC , T AC = 0 oC to 85 oC 1 µA V IL Input Low Voltage -0.5 0.8 V V IH Input HIgh Voltage 0.7V CC V CC + 0.3 V V OL Output Low Voltage I OL = 2.1 mA 0.45 V V OH Output High Voltage 2.3V < V CC < 3.6V IOH = -100 µA V CC - 0.2 V
Chingis Technology Corp. 24 DRAFT Date: August, 2010, Rev:0.4 AC CHARACTERISTICS Applicable over recommended operating range from T A = -40°C to +105°C, V CC = 2.3 V to 3.6 V CL = 1 TTL Gate and 10 pF (unless otherwise noted). Symbol Parameter Min Typ Max Units fCT Clock Frequency for fast read mode 0 100 MHz fC Clock Frequency for read mode 0 33 MHz tRI Input Rise Time 8 ns tFI Input Fall Time 8 ns tCKH SCK High Time 4 ns tCKL SCK Low Time 4 ns tCEH CE# High Time 25 ns tCS CE# Setup Time 10 ns tCH CE# Hold Time 5 ns tDS Data In Setup Time 2 ns tDH Data in Hold Time 2 ns tHS Hold Setup Time 15 ns tHD Hold Time 15 ns tV Output Valid 8 ns tOH Output Hold Time Normal Mode 0 ns tLZ Hold to Output Low Z 200 ns tHZ Hold to Output High Z 200 ns tDIS Output Disable Time 100 ns tEC Secter/Block/Chip Erase Time 10 ms tPP Page Program Time 2 5 ms tVCS V CC Set-up Time 50 µs tw Write Status Register time (flash bit) 10 ms
Chingis Technology Corp. 25 DRAFT Date: August, 2010, Rev:0.4 AC CHARACTERISTICS (CONTINUED) SERIAL INPUT/OUTPUT TIMING (1) Note: 1. For SPI Mode 0 (0,0) SIO
Chingis Technology Corp. 26 DRAFT Date: August, 2010, Rev:0.4 AC CHARACTERISTICS (CONTINUED) HOLD TIMING PIN CAPACITANCE (f = 1 MHz, T = 25°C ) Typ Max Units Conditions CIN 4 6 pF V IN = 0 V COUT 8 12 pF V OUT = 0 V Note: These parameters are characterized but not 100% tested. OUTPUT TEST LOAD INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Chingis Technology Corp. 27 DRAFT Date: August, 2010, Rev:0.4 POWER-UP AND POWER-DOWN At Power-up and Power-down, the device must not be selected (CE# must follow the voltage applied on Vcc) until Vcc reaches the correct value: - Vcc(min) at Power-up, and then for a further delay of tVCE - Vss at Power-down Usually a simple pull-up resistor on CE# can be used to insure safe and proper Power-up and Power-down. To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while Vcc is less than the POR threshold value (Vwi) during power up, the device does not respond to any instruction until a time delay of tPUW has elapsed after the moment that Vcc rised above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, Vcc is still below Vcc(min). No Write Status Register, Program or Erase instructions should be sent until the later of: - tPUW after Vcc passed the VWI threshold - tVCE after Vcc passed the Vcc(min) level At Power-up, the device is in the following state: - The device is in the Standby mode - The Write Enable Latch (WEL) bit is reset At Power-down, when Vcc drops from the operating voltage, to below the Vwi, all write operations are disabled and the device does not respond to any write instruction. Chip Selection Not Allowed All Write Commands are Rejected tVCE Read Access Allowed Device fully accessible tPUW Vcc Vcc(max) Vcc(min) Reset State V (write inhibit) Time Symbol Parameter Min. Max. Unit tVCE *1 Vcc(min) to CE# Low 10 us tPUW *1 Power-Up time delay to Write instruction 1 10 ms V WI *1 Write Inhibit Voltage 2.1 V Note : *1. These parameters are characterized only. 1.8 1. 6
Chingis Technology Corp. 28 DRAFT Date: August, 2010, Rev:0.4 PROGRAM/ERASE PERFORMANCE Parameter Unit Typ Max Remarks Sector Erase Time ms 10 From writing erase command to erase completion Block Erase Time ms 10 From writing erase command to erase completion Chip Erase Time ms 10 From writing erase command to erase completion Page Programming Time ms 2 5 From writing program command to program completion Note: These parameters are characterized and are not 100% tested. RELIABILITY CHARACTERISTICS Parameter Min Typ Unit Test Method Endurance 200,000 Cycles JEDEC Standard A117 Data Retention 20 Years JEDEC Standard A103 ESD – Human Body Model 2,000 Volts JEDEC Standard A114 ESD – Machine Model 200 Volts JEDEC Standard A115 Latch-Up 100 + I CC1 mA JEDEC Standard 78 Note: These parameters are characterized and are not 100% tested.
Chingis Technology Corp. 29 DRAFT Date: August, 2010, Rev:0.4 PACKAGE TYPE INFORMATION 8-Pin JEDEC 150mil Broad Small Outline Integrated Circuit (SOIC) Package (measure in millimeters)
Chingis Technology Corp. 30 DRAFT Date: August, 2010, Rev:0.4 PACKAGE TYPE INFORMATION (CONTINUED) 8-Contact Ulta-Thin Small Outline No-Lead (WSON) Package (measure in millimeters)
Chingis Technology Corp. 31 DRAFT Date: August, 2010, Rev:0.4 PACKAGE TYPE INFORMATION (CONTINUED) PACKAGE TYPE INFORMATION (CONTINUED)
Chingis Technology Corp. 32 DRAFT Date: August, 2010, Rev:0.4
Chingis Technology Corp. 33 DRAFT Date: August, 2010, Rev:0.4
REVISION HISTORY
Date Revision No. Description of Changes Page No . March, 2009 0.0 Preliminary Product Specification All September, 2009 0.1 1. Modify the program frequency to 50MHz 2. Improve Erase time from 15ms to 10ms. 1,10 October, 2009 0.2 1. Modify the t HS , t HD to 15ns 24 October, 2009 0.3 1. fix the erase time November, 2009 0.31 1. change the operation voltage spec 2.3V~2.8V All August, 2010 0.4 1. Modify the operation voltage 2. 3V~3.6V 2. Modify the write inhibit 1.6V~1.8V ALL