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P/N: PM2517 MX25L12833F 3V, 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY Key Features
- Protocol Support - Single I/O, Dual I/O and Quad I/O
- Quad Peripheral Interface (QPI) available
- Support clock frequency up to 133MHz
- Program/Erase Suspend and Resume
- Additional 8K-bit secured OTP
Table 12. Security Register Definition Advanced Sector Protection ... Table 14. Reset Timing-(Other Operation) Table 15. ABSOLUTE MAXIMUM RATINGS Table 16. CAPACITANCE TA = 25°C, f = 1.0 MHz Table 17. DC CHARACTERISTICS Table 18. AC CHARACTERISTICS
- ERASE AND PROGRAMMING PERFORMANCE
- ERASE AND PROGRAMMING PERFORMANCE (Factory Mode)
- LATCH-UP CHARACTERISTICS
Rev. 1.0, October 17, 2017 P/N: PM2517 1. FEATURES GENERAL Supports Serial Peripheral Interface -- Mode 0 and Mode 3 Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations 134,217,728 x 1 bit structure or 67,108,864 x 2 bits (two I/O mode) structure or 33,554,432 x 4 bits (four I/O mode) structure Protocol Support - Single I/O, Dual I/O and Quad I/O Latch-up protected to 100mA from -1V to Vcc +1V Fast read for SPI mode - Support clock frequency up to 133MHz for all protocols - Support Fast Read, 2READ, DREAD, 4READ, QREAD instructions. - Configurable dummy cycle number for fast read operation Quad Peripheral Interface (QPI) available Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each Any Block can be erased individually Programming : - 256byte page buf fer - Quad Input/Output page program(4PP) to enhance program performance T ypical 100,000 erase/program cycles 20 years data retention SOFTW ARE FEATURES Input Data Format - 1-byte Command code Advanced Security Features - Block lock protection The BP0-BP3 and T/B status bit defines the size of the area to be protection against program and erase instructions Advanced sector protection function (Solid Protect) Additional 8K bit security OTP - Features unique identifier - Factory locked identifiable, and customer lockable 3V 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY
- Command Reset Program/Erase Suspend and Resume operation Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - REMS command for 1-byte manufacturer ID and 1-byte device ID Support Serial Flash Discoverable Parameters (SFDP) mode HARDW ARE FEATURES SCLK Input - Serial clock input SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode WP#/SIO2 - Hardware write protection or serial data Input/Out- put for 4 x I/O read mode RESET# (16-pin package) - Hardware Reset pin RESET#/SIO3 - Hardware Reset pin or Serial input & Output for 4 x I/O read mode P ACKAGE -8-pin SOP (200mil) -16-pin SOP (300mil) -8-land WSON (6x5mm) -8-land WSON (8X6mm) - All devices are RoHS Compliant and Halogen- free
access to the device is enabled by CS# input. ages) become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output. (Serial Multi I/O) provides sequential read operation on the whole chip. command can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it will remain in standby mode. 100,000 program and erase cycles. Table 1. Read performance Comparison
- R mean VCC range = 3.0V-3.6V.
Rev. 1.0, October 17, 2017 P/N: PM2517 3. PIN CONFIGURATIONS 4. PIN DESCRIPTION SYMBOL DESCRIPTION CS# Chip Select SI/SIO0 Serial Data Input (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O or 4xI/O read mode) SO/SIO1 Serial Data Output (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O or 4xI/O read mode) SCLK Clock Input WP#/SIO2 Write protection Active low or Serial Data Input & Output (for 4xI/O read mode) RESET#/SIO3 Hardware Reset Pin Active low or Serial Data Input & Output (for 4xI/O read mode) RESET# Hardware Reset Pin Active low VCC + 3V Power Supply GND Ground NC No Connection DNU Do not use 8-PIN SOP (200mil) CS# SO/SIO1 WP#/SIO2 GND VCC RESET#/SIO3 SCLK SI/SIO0 Notes: The pin of RESET#, RESET#/SIO3 or WP#/SIO2 will remain internal pull up function while this pin is not physically connected in system configuration. However, the internal pull up function will be disabled if the system has physical connection to RESET#, RESET#/SIO3 or WP#/SIO2 pin. 16-PIN SOP (300mil) DNU/SIO3 VCC RESET# NC NC NC CS# SO/SIO1 SCLK SI/SIO0 NC NC NC NC GND WP#/SIO2 8-WSON (6x5mm, 8x6mm) CS# SO/SIO1 WP#/SIO2 GND VCC RESET#/SIO3 SCLK SI/SIO0
Rev. 1.0, October 17, 2017 P/N: PM2517 5. BLOCK DIAGRAM Address Generator Memory Array Y-Decoder X-Decoder Data Register SRAM Buffer SI/SIO0 SO/SIO1 SIO2 * SIO3 * WP# * HOLD# * RESET# * CS# SCLK Clock Generator State Machine Mode Logic Sense Amplifier HV Generator Output Buffer * Depends on part number options.
Rev. 1.0, October 17, 2017 P/N: PM2517 6. DATA PROTECTION During power transition, there may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully. In the following, there are several features to protect the system from the accidental write cycles during VCC power- up and power-down or from system noise. V alid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. W rite Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig- nature command (RES), and softreset command. Advanced Security Features: there are some protection and security features which protect content from inad- vertent write and hostile access.
Table 2. Protected Area Sizes areas are more flexible which may protect various area by setting value of BP0-BP3 bits. our I/O and QPI mode, the feature of HPM will be disabled.
unique serial number - Which may be set by factory or system maker. and factory could lock the other. icates whether the second 4K-bit is locked by factory or not. register bit definition and "Table 3. 8K-bit Secured OTP Definition" for address range definition. mal program procedure, and then exiting secured OTP mode by writing EXSO command. more. While in 8K-bit Secured OTP mode, array access is not allowed. Table 3. 8K-bit Secured OTP Definition
Table 4. Memory Organization
4095 FFF000h FFFFFFh
4088 FF8000h FF8FFFh
4087 FF7000h FF7FFFh
4080 FF0000h FF0FFFh
4079 FEF000h FEFFFFh
4072 FE8000h FE8FFFh
4071 FE7000h FE7FFFh
4064 FE0000h FE0FFFh
4063 FDF000h FDFFFFh
4056 FD8000h FD8FFFh
4055 FD7000h FD7FFFh
4048 FD0000h FD0FFFh
- Before a command is issued, status register should be checked to ensure device is ready for the intended op-
mode until next CS# falling edge. In standby mode, SO pin of this device should be High-Z. data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 1. Serial Modes Supported".
- For the following instruct
otherwise, the instruction will be rejected and not executed. glected and will not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Modes Supported
Table 5. Command Set
- Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register.
Rev. 1.0, October 17, 2017 P/N: PM2517 Command Code SPI QPI Address Byte Dummay Cycle Data Byte Total ADD Byte Byte 1 Byte 2 Byte 3 Byte 4 NOP (No Operation) 00 (hex) V V 0 0 0 RSTEN (Reset Enable) 66 (hex) (Note2) V V 0 0 0 RST (Reset Memory) 99 (hex) (Note2) V V 0 0 0 GBLK (gang block lock) 7E (hex) V V 0 0 0 GBULK (gang block unlock) 98 (hex) V V 0 0 0 FMEN (factory mode enable) 41 (hex) V V 0 0 0 Register Access RDID (read identification) 9F (hex) V 0 0 3 RES (read electronic ID) AB (hex) V V 0 0 3 REMS (read electronic manufacturer & device ID) 90 (hex) V 0 0 3 QPIID (QPI ID Read) AF (hex) V 0 0 3 RDSFDP (Read SFDP Table) 5A (hex) V 3 ADD1 ADD2 ADD3 0 0 RDSR (read status register) 05 (hex) V V 0 0 1 RDCR (read configuration register) 15 (hex) V V 0 0 1 WRSR/WRCR (write status/configuration register) 01 (hex) V V 0 0 1-2 RDSCUR (read security register) 2B (hex) V V 0 0 0 WRSCUR (write security register) 2F (hex) V V 0 0 0 SBL (Set Burst Length) C0 (hex) V V 0 0 1 ENSO (enter secured OTP) B1 (hex) V V 0 0 0 EXSO (exit secured OTP) C1 (hex) V V 0 0 0 WRLR (write Lock register) 2C (hex) V 0 0 1 RDLR (read Lock register) 2D (hex) V 0 0 1 WRSPB (SPB bit program) E3 (hex) V 4 ADD1 ADD2 ADD3 ADD4 0 0 ESSPB (all SPB bit erase) E4 (hex) V 0 0 0 RDSPB (read SPB status) E2 (hex) V 4 ADD1 ADD2 ADD3 ADD4 0 1
Rev. 1.0, October 17, 2017 P/N: PM2517 Command Code SPI QPI Address Byte Dummay Cycle Data Byte Total ADD Byte Byte 1 Byte 2 Byte 3 Byte 4 WRDPB (write DPB register) E1 (hex) V 4 ADD1 ADD2 ADD3 ADD4 0 1 RDDPB (read DPB register) E0 (hex) V 4 ADD1 ADD2 ADD3 ADD4 0 1 Note 1: It is not recommended to adopt any other code/address not in the command definition table, which will potentially enter the hidden mode. Note 2: The RSTEN command must be executed before executing the RST command. If any other command is issued in-between RSTEN and RST , the RST command will be ignored.
The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high. Figure 8. Write Disable (WRDI) Sequence (SPI Mode)
the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. sign, please use RDID instruction. progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. Figure 13. Read Electronic Signature (RES) Sequence (SPI Mode)
3 Dummy Bytes
3 Dummy BytesCommand
Figure 14. Read Electronic Signature (RES) Sequence (QPI Mode) Figure 15. Release from Deep Power-down (RDP) Sequence (SPI Mode) Figure 16. Release from Deep Power-down (RDP) Sequence (QPI Mode)
are listed in "Table 6. ID Definitions". tinuously, alternating from one to the other. The instruction is completed by driving CS# high. Note: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first. Figure 17. Read Electronic Manufacturer & Device ID (REMS) Sequence (SPI Mode only)
2 Dummy Bytes
memory type, and device ID data byte will be output continuously, until the CS# goes high. Table 6. ID Definitions
- Issue RDSR to check BP[3:0].
- If WPSEL = 1, issue RDSPB and RDDPB to check the block status.
Figure 22. Program/Erase flow with read array data
Figure 23. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag)
- Issue RDSR to check BP[3:0].
- If WPSEL = 1, issue RDSPB and RDDPB to check the block status.
Table 7. Status Register Note 1: Please refer to the "Table 2. Protected Area Sizes". memory area, the instruction will be ignored and WEL will clear to “0”. disables the HPM feature and the RESET feature of 8-pin package. SRWD bit defaults to be "0".
delivered from factory. To write the ODS bits requires the Write Status Register (WRSR) instruction to be executed. device. To write the TB bits requires the Write Status Register (WRSR) instruction to be executed. Table 8. Configuration Register Table
Note: "R" mean VCC range= 3.0V-3.6V. Table 9. Output Driver Strength Table Table 10. Dummy Cycle and Frequency Table (MHz)
Table 11. Protection Modes
- As defined by the values in the Block Protect (BP3, BP2, BP1, BP
0) bits of the Status Register, as shown in "Table 2. BP0 and T/B bit, is at software protected mode (SPM). been set. It is rejected to write the Status Register and not be executed. BP1, BP0 and T/B bit and hardware protected mode by the WP#/SIO2 to against data modification. To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered. can use software protected mode via BP3, BP2, BP1, BP0 and T/B bit. If the system enter QPI or set QE=1, the feature of HPM will be disabled.
Figure 26. WRSR flow
Figure 27. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 Note: WP# must be kept high until the embedded operation finish.
The read instruction is for reading data out. SI→ data out on SO→to end READ operation can use CS# to high at any time during data out. Figure 28. Read Data Bytes (READ) Sequence (SPI Mode only)
the highest address has been reached. tion can use CS# to high at any time during data out. performance enhance mode and return to normal operation. pact on the Program/Erase/Write Status Register current cycle. Figure 29. Read at Higher Speed (FAST_READ) Sequence (SPI Mode)
instruction, the following data out will perform as 2-bit instead of previous 1-bit. use CS# to high at any time during data out. on the Program/Erase/Write Status Register current cycle. Figure 30. Dual Read Mode Sequence
instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. 2READ operation can use CS# to high at any time during data out. on the Program/Erase/Write Status Register current cycle. Figure 31. 2 x I/O Read Mode Sequence (SPI Mode only)
12 ADD Cycles
address after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction. the following data out will perform as 4-bit instead of previous 1-bit. use CS# to high at any time during data out. on the Program/Erase/Write Status Register current cycle. Figure 32. Quad Read Mode Sequence
Rev. 1.0, October 17, 2017 P/N: PM2517 9-16. 4 x I/O Read Mode (4READ) The 4READ instruction enabl e quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. 4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low → sending 4READ instruction→ 3-byte address interleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles (Default) →data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out. 4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The sequence of issuing 4READ instruction QPI mode is: CS# goes low → sending 4READ instruction→ 3-byte address interleave on SIO3, SIO2, SIO1 & SIO0 → 6 dummy cycles (Default) →data out interleave on SIO3, SIO2, SIO1 & SIO0 → to end 4READ operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
Figure 33. 4 x I/O Read Mode Sequence (SPI Mode)
6 ADD Cycles
- Hi-impedance is inhibited for the two clock cycles.
- P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
- Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in
Figure 34. 4 x I/O Read Mode Sequence (QPI Mode)
3 E D O M
Rev. 1.0, October 17, 2017 P/N: PM2517 9-18. Performance Enhance Mode The device could waive the command cycle bits if the two cycle bits after address cycle toggles. Performance enhance mode is supported in both SPI and QPI mode. In QPI mode, “EBh” and SPI “EBh” commands support enhance mode. The performance enhance mode is not supported in dual I/O mode. To enter performance-enhancing mode, P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can make this mode continue and skip the next 4READ instruction. To leave enhance mode, P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h along with CS# is afterwards raised and then lowered. Issuing ”FFh” data cycle can also exit enhance mode. The system then will leave performance enhance mode and return to normal operation. After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of the first clock as address instead of command cycle. This sequence of issuing 4READ instruction is especially useful in random access: CS# goes low→send 4READ instruction→3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit P[7:0]→ 4 dummy cycles (Default) →data out until CS# goes high → CS# goes low (the following 4READ instruction is ignored) → 3-bytes random access address. To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh data cycle, 8 clocks, should be is- sued in 1I/O sequence. In QPI Mode, FFFFFFFFh data cycle, 8 clocks, in 4I/O should be issued. If the system controller is being Reset during operation, the flash device will return to the standard SPI operation.
Figure 37. 4 x I/O Read enhance performance Mode Sequence (SPI Mode)
Figure 38. 4 x I/O Read enhance performance Mode Sequence (QPI Mode)
6 Address cycles
Rev. 1.0, October 17, 2017 P/N: PM2517 9-23. Page Program (PP) The Page Program (PP) instruction is for programming memory bits to "0". One to 256 bytes can be sent to the de- vice to be programmed. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If more than 256 data bytes are sent to the device, only the last 256 data bytes will be accepted and the previous data bytes will be disregarded. The Page Program instruction requires that all the data bytes fall within the same 256-byte page. The low order address byte A[7:0] specifies the starting address within the selected page. Bytes that will cross a page boundary will wrap to the beginning of the selected page. The device can accept (256 minus A[7:0]) data bytes without wrapping. If 256 data bytes are going to be pro- grammed, A[7:0] should be set to 0. The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at least 1-byte on data on SI→ CS# goes high. The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary ( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the Block is protected by BP bits (WPSEL=0; Block Lock (BP) protection mode) or SPB/DPB (WPSEL=1; Individual Sector protection mode) the Page Program (PP) instruction will not be executed. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode.
SIO3 as address and data input, which can improve programmer performance and the effectiveness of application. The other function descriptions are as same as standard page program. SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high. al Sector protection mode), the Quad Page Program (4PP) instruction will not be executed. Figure 49. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)
6 Address cycle Data
Rev. 1.0, October 17, 2017 P/N: PM2517 9-26. Enter Secured OTP (ENSO) The ENSO instruction is for entering the additional 8K-bit secured OTP mode. The additional 8K-bit secured OTP is independent from main array, which may use to store unique serial number for system identifier. After entering the Secured OTP mode, and then follow standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down. The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP mode→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. Please note that after issuing ENSO command user can only access secure OTP region with standard read or pro- gram procedure. Furthermore, once security OTP is lock down, only read related commands are valid. 9-27. Exit Secured OTP (EXSO) The EXSO instruction is for exiting the additional 8K-bit secured OTP mode. The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP mode→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. 9-28. Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register data out on SO→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. 9-29. W rite Security Register (WRSCUR) The WRSCUR instruction is for changing the values of Security Register Bits. The WREN (Write Enable) instruction is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer to lock-down the 1 st 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
Write Protection Selection bit. Please reference to "9-30. Write Protection Selection (WPSEL)". succeeds. Please note that it will not interrupt or stop any operation in the flash memory. program operation succeeds. Please note that it will not interrupt or stop any operation in the flash memory. is set to "1". ESB is cleared to "0" after erase operation resumes. PSB is set to "1". PSB is cleared to "0" after program operation resumes. OTP area cannot be updated any more. While it is in 8K-bit secured OTP mode, main array access is not allowed. factory or not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock.
mand. Please note that the WPSEL bit is an OTP bit. Once WPSEL is set to “1”, it cannot be programmed back to “0”. The memory array is write protected by the BP3-BP0 bits. write protected regardless of the state of each SPB or DPB. Sector Protect mode → CS# goes high. Figure 52. Write Protection Selection
Figure 53. WPSEL Flow
individual 64KB blocks in the rest of memory. is write-protected from programming or erasing when its associated SPB or DPB is set to “1”. overview of Advanced Sector Protection. Figure 54. Advanced Sector Protection Overview
which is an unique bit assigned to control all SPB bit status. SPBLKDN bit itself can not be altered anymore, either. executed to set the WEL bit before sending the WRLR command.
6 SPBLKDN SPB Lock Down OTP 1 1 = SPB changeable
Figure 55. Read Lock Register (RDLR) Sequence Figure 56. Write Lock Register (WRLR) Sequence
Rev. 1.0, October 17, 2017 P/N: PM2517 9-31-2. Solid Protection Bits The Solid Protection Bits (SPBs) are nonvolatile bits for enabling or disabling write-protection to sectors and blocks. The SPB bits have the same endurance as the Flash memory. An SPB is assigned to each 4KB sector in the bottom and top 64KB of memory and to each 64KB block in the remaining memory. The factory default state of the SPB bits is “0”, which has the sector/block write-protection disabled. When an SPB is set to “1”, the associated sector or block is write-protected. Program and erase operations on the sector or block will be inhibited. SPBs can be individually set to “1” by the WRSPB command. However, the SPBs cannot be individually cleared to “0”. Issuing the ESSPB command clears all SPBs to “0”. A WREN command must be executed to set the WEL bit before sending the WRSPB or ESSPB command. The RDSPB command reads the status of the SPB of a sector or block. The RDSPB command returns 00h if the SPB is “0”, indicating write-protection is disabled. The RDSPB command returns FFh if the SPB is “1”, indicating write-protection is enabled. Note: If SPBLKDN=0, commands to set or clear the SPB bits will be ignored. SPB Register Bit Description Bit Status Default Type 7 to 0 SPB (Solid Protection Bit) 00h = Unprotect Sector / Block FFh = Protect Sector / Block 00h Non-volatile
Rev. 1.0, October 17, 2017 P/N: PM2517 9-31-4. Gang Block Lock/Unlock (GBLK/GBULK) These instructions are only ef fective if WPSEL=1. The GBLK and GBULK instructions provide a quick method to set or clear all DPB bits at once. The WREN (Write Enable) instruction is required before issuing the GBLK/GBULK instruction. The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction →CS# goes high. The GBLK and GBULK commands are accepted in both SPI and QPI mode. The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed. 9-31-5. Sector Protection States Summary T able Protection Status Sector/Block Protection State DPB SPB 0 0 Unprotected 0 1 Protected 1 0 Protected 1 1 Protected
Rev. 1.0, October 17, 2017 P/N: PM2517 9-32. Program/Erase Suspend/Resume The device allow the interruption of Sector-Erase, Block-Erase or Page-Program operations and conduct other operations. After issue suspend command, the system can determine if the device has entered the Erase-Suspended mode through Bit2 (PSB) and Bit3 (ESB) of security register. (please refer to "Table 12. Security Register Definition") Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. 9-33. Erase Suspend Erase suspend allow the interruption of all erase operations. After the device has entered Erase-Suspended mode, the system can read any sector(s) or Block(s) except those being erased by the suspended erase operation. Reading the sector or Block being erase suspended is invalid. After erase suspend, WEL bit will be clear, only read related, resume and reset command can be accepted. (including: 03h, 0Bh, 3Bh, 6Bh, BBh, EBh, 5Ah, C0h, 06h, 04h, 2Bh, 9Fh, AFh, 05h, ABh, 90h, B1h, C1h, B0h, 30h, 66h, 99h, 00h, 35h, F5h, 15h, 2Dh, E2h, E0h) If the system issues an Erase Suspend command after the sector erase operation has already begun, the device will not enter Erase-Suspended mode until tESL time has elapsed. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend command, ESB is set to "1". ESB is cleared to "0" after erase operation resumes. 9-34. Program Suspend Prog ram suspend allows the interruption of all program operations. After the device has entered Program- Suspended mode, the system can read any sector(s) or Block(s) except those be ing programmed by the suspended program operation. Reading the sector or Block being program suspended is invalid. After program suspend, WEL bit will be cleared, only read related, resume and reset command can be accepted. (including: 03h, 0Bh, 3Bh, 6Bh, BBh, EBh, 5Ah, C0h, 06h, 04h, 2Bh, 9Fh, AFh, 05h, ABh, 90h, B1h, C1h, B0h, 30h, 66h, 99h, 00h, 35h, F5h, 15h, 2Dh, E2h, E0h) Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may use PSB to identify the state of flash memory. After the flash memory is suspended by Program Suspend command, PSB is set to "1". PSB is cleared to "0" after program operation resumes.
Rev. 1.0, October 17, 2017 P/N: PM2517 9-35. W rite-Resume The Write operation is being resumed when Write-Resume instruction issued. ESB or PSB (suspend status bit) in Status register will be changed back to “0”. The operation of Write-Resume is as follows: CS# drives low → send write resume command cycle (30H) → drive CS# high. By polling Busy Bit in status register, the internal write operation status could be checked to be completed or not. The user may also wait the time lag of tSE, tBE, tPP for Sector-erase, Block-erase or Page-programming. WREN (command "06") is not required to issue before resume. Resume to another suspend operation requires latency time of 1ms. Please note that, if "performance enhance mode" is executed during suspend operation, the device can not be resumed. To restart the write command, disable the "performance enhance mode" is required. After the "performance enhance mode" is disabled, the write-resume command is effective. 9-36. No Operation (NOP) The “No Operation” command is only able to terminate the Reset Enable (RSTEN) command and will not affect any other command. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care during SPI mode. 9-37. Software Reset (Reset-Enable (RSTEN) and Reset (RST)) The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command following a Reset (RST) command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which makes the device return to the default status as power on. To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will be invalid. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. If the Reset command is executed during program or erase operation, the operation will be disabled, the data under processing could be damaged or lost. The reset time is different depending on the last operation. For details, please refer to "Table 14. Reset Timing- (Other Operation)" for tREADY2.
to high at any time during data out. SFDP is a JEDEC Standard, JESD216B. For SFDP register values detail, please contact local Macronix sales channel for Application Note. Figure 68. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
24 BIT ADDRESS
- All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on.
Figure 69. RESET Timing Table 13. Reset Timing-(Power On)
Rev. 1.0, October 17, 2017 P/N: PM2517 11. POWER-ON STATE The device is at below states when power-up: - Standby mode (please n ote it is not deep power-down mode) - W rite Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level: - VCC minimum at power- up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and the flash device has no response to any command. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The read, write, erase, and program command should be sent after the below time delay: - tVSL after VCC reached VCC minimum level Please refer to the "Figure 77. Power-up Timing". Note: To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend- ed. (generally around 0.1uF) At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during the stage while a write, program, erase cycle is in progress.
ypical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds). ypical value is calculated by simulation.
Rev. 1.0, October 17, 2017 P/N: PM2517 Notes: tCH + tCL must be greater than or equal to 1/ Frequency. T ypical values given for TA=25°C. Not 100% tested. Only applicable as a constraint for a WRSR instruction when SR WD is set at 1. 4. T est condition is shown as "Figure 72. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL" and "Figure 73. OUTPUT LOADING". By default dummy cycle value. Please refer to the "T able 1. Read performance Comparison". Latency time is required to complete Erase/Program Suspend operation until WIP bit is "0". 7. For tPRS, minimum timing must be observed before issuing the next program suspend command. However, a period equal to or longer than the typical timing is required in order for the program operation to make progress. 8. For tERS, minimum timing must be observed before issuing the next erase suspend command. However, a pe- riod equal to or longer than the typical timing is required in order for the erase operation to make progress. 9. Not 100% tested. 10.The value guaranteed by characterization, not 100% tested in production.
Table 17. AC CHARACTERISTICS. nored, the device will not operate correctly. selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL. Figure 75. AC Timing at Device Power-Up
Register contains 00h (all Status Register bits are 0). Figure 78. Power Up/Down and Voltage Drop Table 19. Power-Up/Down Voltage and Timing Down Voltage and Timing" below for more details. Note: These parameters are characterized only.
Rev. 1.0, October 17, 2017 P/N: PM2517 14. ERASE AND PROGRAMMING PERFORMANCE Note: T ypical program and erase time assumes the following conditions: 25°C, 3.3V, and checkerboard pattern. Under worst conditions of 85°C and 2.7V System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com- mand. 4. The maximum chip progra mming time is evaluated under the worst conditions of 0°C, VCC=3.3V, and 100K cy- cle with 90% confidence level. Parameter Min. Typ. (1) Max. (2) Unit Write Status Register Cycle Time 40 ms Sector Erase Cycle Time (4KB) 25 120 ms Block Erase Cycle Time (32KB) 0.14 0.65 s Block Erase Cycle Time (64KB) 0.25 0.65 s Chip Erase Cycle Time 26 60 s Byte Program Time (via page program command) 16 40 us Page Program Time 0.33 1.2 ms Erase/Program Cycle 100,000 cycles Notice: 1. Factory Mode must be operated in 20°C to 45°C and VCC 3.0V-3.6V. 2. In Factory mode, the Erase/Program operation should not exceed 50 cycles, and "ERASE AND PROGRAMMING PERFORMANCE" 100k cycles will not be affected. 3. During factory mode, Suspend command (B0) cannot be executed. Parameter Min. Typ. Max. Unit Sector Erase Cycle Time (4KB) 15 ms Block Erase Cycle Time (32KB) 100 ms Block Erase Cycle Time (64KB) 200 ms Chip Erase Cycle Time 25 s Page Program Time 0.33 ms Erase/Program Cycle 50 cycles 15. ERASE AND PROGRAMMING PERFORMANCE (Factory Mode)
Rev. 1.0, October 17, 2017 P/N: PM2517 16. DATA RETENTION Parameter Condition Min. Max. Unit Data retention 55˚C 20 years 17. LATCH-UP CHARACTERISTICS Min. Max. Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax Input Voltage with respect to GND on SO -1.0V VCC + 1.0V Current -100mA +100mA Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
Rev. 1.0, October 17, 2017 P/N: PM2517 18. ORDERING INFORMATION PART NO. TEMPERATURE PACKAGE Remark MX25L12833FM2I-10G -40°C to 85°C 8-SOP (200mil) MX25L12833FZNI-10G -40°C to 85°C 8-WSON (6x5mm) MX25L12833FZ2I-10G -40°C to 85°C 8-WSON (8x6mm) MX25L12833FMI-10G -40°C to 85°C 16-SOP (300mil) Please contact Macronix regional sales for the latest product selection and available form factors.
Rev. 1.0, October 17, 2017 P/N: PM2517 19. PART NAME DESCRIPTION MX 25 L 10M2 I G OPTION: G: RoHS Compliant & Halogen-free SPEED: 10: 104MHz TEMPERATURE RANGE: I: Industrial (-40°C to 85°C) PACKAGE: M2: 8-SOP (200mil) M: 16-SOP (300mil) ZN: 8-WSON (6x5mm) Z2: 8-WSON (8x6mm) DENSITY & MODE: 12833F: 128Mb TYPE: L: 3V DEVICE: 25: Serial NOR Flash 12833F
Rev. 1.0, October 17, 2017 P/N: PM2517 20. PACKAGE INFORMATION 20-1. 8-pin SOP (200mil)
Rev. 1.0, October 17, 2017 P/N: PM2517 20-2. 16-pin SOP (300mil)
Rev. 1.0, October 17, 2017 P/N: PM2517 20-3. 8-land WSON (6x5mm)
Rev. 1.0, October 17, 2017 P/N: PM2517 20-4. 8-land WSON (8x6mm)
Rev. 1.0, October 17, 2017 P/N: PM2517 21. REVISION HISTORY Revision No. Description Page Date 0.01 1. Updated SFDP version P70 SEP/07/2017 2. Content and format modifications for 8-WSON package outline P87 3. Format modifications for package outline P85-86 4. Content correction P4,15,22,81 1.0 1. Removed "Advanced Information" to align with the All OCT/17/2017 product status Added 8-land WSON (8X6mm) package informaion P4,6,83,84,88 3. Updated Program and Erase values P76,81
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