PM0212 STMICROELECTRONICS | Alldatasheet

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Technical content

Datasheet sections

  • 1 Glossary
  • 2 Memory organization
  • 2.1 Memory features
  • 3 Memory protection strategy
  • 3.1 Readout protection
  • 3.2 Proprietary code area protection
  • 3.3 User Boot Code area protection
  • 3.4 Unwanted memory access protection
  • 4 Programming STM8 Flash micr ocontrollers
  • 4.1 Unlocking the Memory Access Security System (MASS)
  • 4.2 Block programming
  • 4.3 Word programming
  • 4.4 Byte programming
  • 4.5 Programming the option bytes
  • 4.5.1 Summary of memory dedicated option bytes
  • 4.5.2 How to program the option bytes
  • 4.6 Memory access versus programming method
  • 4.6.1 ICP methods
  • 4.6.2 IAP method
  • 5 Flash program memory and data EEPROM summary
  • 6 Revision history

April 2012 Doc ID 022351 Rev 2 1/22 PM0212 Programming manual How to program the STM8TL5xxx Flash program memory and data EEPROM Introduction This manual describes how to program Flash program memory and data EEPROM on STM8TL5xxx microcontrollers. It applies to STM8TL5xxx devices. It is intended to provide information to the programming tool manufacturers and to the customers who want to implement programming by themselves on their production line. The in-circuit programming (ICP) method is used to update the content of Flash program memory and data EEPROM while the user software is not running. It uses the Single wire interface module (SWIM) to communicate between the programming tool and the device. In contrast to the ICP method, in-application programming (IAP) can use any communication interface supported by the microcontroller (I/Os, SPI, USART, I 2C, USB, CAN...). IAP has been implemented for users who want their application software to update itself by re-programming the Flash program memory during program execution. The main advantage of IAP is its ability to re-program Flash program memory and data EEPROM when the chip has already been soldered on the application board and while the user software is running. Nevertheless, part of the Flash program memory has to be previously programmed using ICP . For details on memory implementation and features, registers or stack top addresses, refer to the product datasheet. Related documents

  • STM8TL5xxx microcontroller family reference manual (RM0312)
  • STM8TL5xxx datasheet
  • STM8 SWIM communication protocol and debug module (UM0470)
  • Basic in-application programming example using the STM8 I2C and SPI peripherals AN2737)

1 Glossary

This section gives a brief definition of acronyms and terms used in this document:

  • Block A block is a set of bytes that can be programmed or erased in one single programming operation. Operations that are available on a block are fast programming, erase only, and standard programming (which includes an erase operation). Refer to Section 2: Memory organization for details on block size according to the device.
  • Driver A driver is a control program defined by the application developer. It is used to manage the allocation of system resources to start application programs. In this document two drivers are described, ICP and IAP drivers.
  • In-application programming (IAP) IAP is the ability to re-program the Flash program memory and data EEPROM (DATA) of a microcontroller while the device is already plugged-in to the application and the application is running.
  • In-circuit programming (ICP) ICP is the ability to program the Flash program memory and data EEPROM of a microcontroller using the SWIM protocol while the device is plugged-in to the application.
  • In-circuit debugging (ICD) ICD is the ability to debug the user software using the SWIM protocol. The user has the ability to connect the device to a debugger and insert breakpoints in his firmware. Debugging may be intrusive (application patched to allow debugging) or non intrusive (using a debug module).
  • Memory access security system (MASS) keys The Memory access security system (MASS) consists of a memory write protection lock designed to prevent unwanted memory modifications due to EMS or program counter loss. To unlock the memory protection, one or more keys must be written in a dedicated register and in a specific order. When the operation (write or erase) is completed, the MASS must be activated again to provide good memory security.
  • Page A page is a set of blocks. The number of blocks in a page may differ from one device to another. Refer to Section 2: Memory organization for details on page size according to the device. Dedicated option bytes can be used to configure by increments of one page the size of the user boot code, the proprietary code, and the data EEPROM.
  • Proprietary code area (PCODE) The proprietary code area (PCODE) can be used to protect proprietary software libraries used to drive peripherals. Refer to Section 3.2: Proprietary code area protection for details.
  • Single wire interface module (SWIM) The SWIM is a communication protocol managed by hardware in the STM8 microcontrollers. The SWIM main purpose is to provide non intrusive debug capability. It can also be used to download programs into RAM and execute them. It can also write (registers or RAM) or read any part of the memory space and jump to any memory address. The SWIM protocol is used for ICP . It is accessed by providing a specific sequence on the SWIM pin either during the reset phase or when the device is running (if allowed by the application).
  • User boot code area (UBC) The user boot code area is a write-protected area which contains reset vector, interrupt vectors, and IAP routine for the device to be able to recover from interrupted or erroneous IAP programming.
  • User mode The user mode is the standard user software running mode in the STM8. It is entered either by performing a power-on-reset on the device or by issuing the SWIM SRST command from a development tool.
  • Word A word is a set of 4 bytes and corresponds to the memory granularity.

Memory organization PM0212 6/22 Doc ID 022351 Rev 2

2 Memory organization

STM8TL5xxx microcontrollers feature up to 16 Kbytes of Flash program memory including up to 2 Kbytes of data EEPROM. A memory accelerator takes advantage of the parallel 4-byte storage, which corresponds to a word. The Flash program memory and data EEPROM can be erased and programmed at byte level, word level or block level. In word programming mode, 4 bytes are programmed/erased during the same cycle, while in block programming mode, a whole block is programmed/erase during the same cycle.

2.1 Memory features

The STM8TL5xxx memory features are as follows:

  • Up to 16 Kbytes of Flash program memory including up to 2 Kbytes of data EEPROM. The whole memory array is divided into 256 pages of one block (64 bytes) each. The Flash program memory is divided into 3 areas: – The user boot code area (UBC) – A configurable data EEPROM area (DATA) – The main program area The DATA and main program areas can be write protected independently by using the memory access security mechanism (MASS). The size of UBC, and DATA areas can be configured through option bytes.
  • One block (64 bytes) of option bytes of which 5 bytes are already used to configure device hardware features. The option bytes can be programmed only in ICP/SWIM mode. Refer to Table 1: STM8TL5xxx memory partitions for a detailed description of STM8TL5xxx memory partitioning.

Table 1. STM8TL5xxx memory partitions (1)

  1. The memory mapping is given for the devic es featuring 16 Kbytes of Flash program memory including up to 2 Kbytes of
  2. The size of the data EEPROM area is configurable from 0 to 32 pages starting from the last page of the Flash program

Memory protection strategy PM0212 8/22 Doc ID 022351 Rev 2

3 Memory protection strategy

The STM8 devices feature several mechanisms allowing to protect the content of the Flash program and data EEPROM areas:

  • Readout protection The software can prevent application code and data stored in the Flash program memory and data EEPROM from being read and modified in ICP/SWIM mode. The readout protection is enabled and disabled by programming an option byte in ICP/SWIM mode. Refer to Section 3.1: Readout protection for details.
  • Proprietary code area (PCODE) To protect proprietary peripheral software driver libraries, some STM8 devices features a permanently readout protected area, the proprietary code area (PCODE). This area is part of the Flash program memory. Its content cannot be modified and can only be read/executed in user privileged mode. The size of the PCODE area can be configured in ICP/SWIM mode through an option byte by increments of one page. Refer to Section 3.2 for details on PCODE area.
  • User boot code area (UBC) In order to guaranty the capability to recover from an interrupted or erroneous IAP programming, all STM8 devices provide a write-protected area called user boot code (UBC). This area is a part of the Flash program memory which cannot be modified in user mode (that is protected against modification by the user software). The content of the UBC area can be modified only in ICP/SWIM mode after clearing the UBC option byte. The size of the user boot code area can be configured through an option byte by increments of one page. Refer to Section 3.3: User Boot Code area protection for details on user boot code area.
  • Unwanted memory access protection All STM8 devices offer unwanted memory access protection, which purpose is to prevent unintentional modification of program memory and data EEPROM (for example due to a firmware bug or EMC disturbance). This protection consists of authorizing write access to the memory only through a specific software sequence which is unlikely to happen randomly or by mistake. Access to Flash program and data EEPROM areas is enabled by writing MASS keys into key registers. Refer to Section 3.4: Unwanted memory access protection for details on unwanted memory access protection.

3.1 Readout protection

second writing, AA, unprotects the device, and then the AA value remains in the ROP byte. Please note the EOP should be checked each time. The readout protection can only be disabled in ICP/SWIM mode. protected against read and write access through ICP . memory, the DATA area and the option bytes to be erased.

3.2 Proprietary code area protection

proprietary code area (PCODE). Note: Values 1 and 2 do not protect any address, but the PCODE option byte is write-protected. Table 2. PCODE size

0 All interrupt vectors can be

3 Only TRAP is write-protected 1 0x8080-0x80BF

4 Only TRAP is write-protected 2 0x8080-0x80FF

3.3 User Boot Code area protection

error by applying a reset and restarting the SWIM communication. programming (such as power failure). table for the minimum and maximum size of the UBC area.

3.4 Unwanted memory access protection

into dedicated MASS key registers. protection of the area by resetting the PUL bit in FLASH_IAPSR. by resetting the DUL bit in FLASH_IAPSR. Table 3. Recommended minimum and maximum sizes of the UBC area

PM0212 Memory protection strategy Doc ID 022351 Rev 2 11/22 the FLASH_DUKR register, new keys can be entered without the device being previously reset. The size of the DATA area can be configured through the DATASIZE option byte. In order to be as effective as possible, the application software must lock again the unwanted memory access protection as soon as the programming is completed. Otherwise, the protection level of the MASS is significantly reduced. To activate the MASS protection again, the user must reset the corresponding bits in the FLASH_IAPSR register (DUL bit for data EEPROM or PUL bit for Flash program memory). Note: 1 The mechanism to lock and unlock unwanted memory access protection is identical for option bytes and data EEPROM (see Table 4: MASS).

2 Before starting programming program memory or data EEPROM, the software must verify

that the area is not write protected by checking that the PUL or DUL bit is effectively set.

4 Programming STM8 Flash microcontrollers

This section describes how to program STM8 single-voltage Flash microcontrollers.

4.1 Unlocking the Memory Ac cess Security System (MASS)

The memory must be unlocked before attempting to perform any erase or write operation. protection, and Table 4: MASS. and data EEPROM, respectively.

4.2 Block programming

programming) and combined erase/write cycle (also called standard block programming). The programming mode is selected through FLASH_CR2 register. The memory must be unlocked before performing any of these operations. Table 4. MASS

  1. In STM8TL5xxx devices, the option by tes are not accessible in user/IAP mode.
  2. The OPT bit of the FLASH_CR2 register must be set/cleared to enable access to the option bytes.
  3. If wrong keys have been entered, a reset must to be generated to be able to reprogram the right keys.

PM0212 Programming STM8 Flash microcontrollers Doc ID 022351 Rev 2 13/22 Block program operations can be performed both to main program memory and DATA area:.

  • Programming a block of main program memory: The block program operation has to be executed totally from RAM. The program execution continues from RAM. If the program goes back to main program memory, it is stalled until the block program operation is complete. The DMA controller can be programmed to perform a block transfer to Flash program memory, and put the CPU in Wait mode.
  • Programming a block of data EEPROM: The block program operation must be executed totally from RAM. The programming can also be performed directly through the SWIM interface. In this case, it is recommended to stall the device in order to prevent the core from accessing the Flash program memory during the block program or erase operation. This can be done by setting the STALL bit in the DM_CSR2 debug module register. Refer to the STM8 SWIM communication protocol and debug module (UM0470) for more information. Caution: During a block program or erase operation, it is recommended to avoid executing instructions performing a read access to program memory. Caution: If the number of written memory locations is higher than what is required in the block program/erase sequence, the additional locations are handled as redundant byte write operations. If the number of written memory locations is lower than what is specified in the block program/erase sequence, the block program/erase process does not start and the CPU stalls waiting for the remaining operations to be performed. Caution: EOP and WR_PG_DIS bits of FLASH_IAPSR register are automatically cleared when a program/erase operation starts. Caution: If a block program or erase sequence is interrupted by a reset, the data programmed in the memory may be corrupted. Standard block programming The following sequence is required to perform a standard block program sequence (block erased and programmed): 1. Unlock the memory if not already done. The UBC option byte can be read to check if the block to program is not in the UBC area. If necessary, reprogram it to allow erasing and programming the targeted block. 2. Write 0x01 in FLASH_CR2 (PRG bit active). 3. Write all the data bytes of the block you want to program starting with the very first address of the block. No read or write access to the program memory is allowed during these load operations as they might corrupt the values to be programmed. The programming cycle starts automatically when all the data in the block have been written. 4. Check the WR_PG_DIS bit in FLASH_IAPSR to verify if the block you attempted to program was not write protected (optional) 5. To check if the program operation is co mplete, poll the EOP bit in FLASH_IAPSR from program memory. EOP is set to ‘1’ when the standard block program operation has completed. To avoid polling the EOP bit, an interrupt can be generated when EOP is set.

Programming STM8 Flash microcontrollers PM0212 14/22 Doc ID 022351 Rev 2 Note: It is mandatory to execute steps 2 to 4 from RAM. Caution: EOP and WR_PG_DIS bits are cleared by reading the FLASH_IAPSR register. It is consequently strongly recommended to perform one single read operation to the FLASH_IAPSR register to check the values of these bits. Fast block programming operation The following sequence is required to perform a fast block program sequence (block programmed without previous erase): 1. Unlock the memory if not already done. The UBC option byte can be read to check if the block to program is not in the UBC area. If necessary, reprogram it to allow programming the targeted block. 2. Write 0x10 in FLASH_CR2 (FPRG bit active). 3. Write all the data bytes of the block you want to program starting with the very first address of the block. No read or write access to the program memory is allowed during these load operations as they might corrupt the values to be programmed. The programming cycle starts automatically when the complete block has been written. 4. Check the WR_PG_DIS bit in FLASH_IAPSR to verify if the block you attempted to program was not write protected (optional). 5. To check if the program operation is co mplete, poll the EOP bit in FLASH_IAPSR from program memory. EOP is set to ‘1’ when the block program operation has completed. To avoid polling the EOP bit, an interrupt can be generated when EOP is set. Note: It is mandatory to execute steps 2 to 4 from RAM. Caution: EOP and WR_PG_DIS bits are cleared by reading the FLASH_IAPSR register. It is consequently strongly recommended to perform one single read operation to the FLASH_IAPSR register to check the values of these bits. Caution: The memory block must be empty when performing a fast block programming operation. Block erase operation The following sequence is required to perform a block erase sequence: 1. Unlock the memory if not already done. The UBC option byte can be read to check if the block to erase is not in the UBC area. If necessary, reprogram it to allow erasing the targeted block. 2. Write 0x20 in FLASH_CR2 (ERASE bit active). 3. Write '0x00 00 00 00' to any word inside the block to be erased using a LOAD instruction. 4. Check the WR_PG_DIS bit in FLASH_IAPSR to verify if the block you attempted to erase was not write protected (optional). 5. To check if the erase operation is comp lete, poll the EOP bit in FLASH_IAPSR from program memory. EOP is set to ‘1’ when the block erase operation has completed. To avoid polling the EOP bit, an interrupt can be generated when EOP is set. Note: It is mandatory to execute steps 2 to 4 from RAM. Caution: EOP and WR_PG_DIS bits are cleared by reading the FLASH_IAPSR register. It is consequently strongly recommended to perform one single read operation to the FLASH_IAPSR register to check the values of these bits.

PM0212 Programming STM8 Flash microcontrollers Doc ID 022351 Rev 2 15/22

4.3 Word programming

Both main program memory and data EEPROM can be programmed and erased at word level. Word operations are performed in the same way as block operations. They can be executed either from program memory or from RAM. When a new word program operation starts, EOP and WR_PG_DIS bits of FLASH_IAPSR register are automatically cleared. The EOP bit can then be used to know if the previous operation has completed. This bit is automatically reset when reading FLASH_IAPSR. The following sequence is required to perform a word program operation: 1. Unlock the memory if not already done. The UBC option byte can be read to check if the word you want to program is not in the UBC area. If necessary, reprogram it to allow programming the targeted word. 2. Write 0x40 in FLASH_CR2 (WP bit active). 3. Write the 4 data bytes to the memory starting with the very first address of the word to be programmed. The programming cycle starts automatically when the 4 bytes have been written. 4. Check the WR_PG_DIS bit in FLASH_IAPSR to verify if the word you attempted to program was not write-protected (optional). 5. To check if the program operation is complete, poll the EOP bit in FLASH_IAPSR register for the end of operations. EOP is set to ‘1’ when the word program operation has completed. To avoid polling the EOP bit, an interrupt can be generated when EOP is set. Caution: EOP and WR_PG_DIS bits are cleared by reading the FLASH_IAPSR register. It is consequently strongly recommended to perform one single read operation to the FLASH_IAPSR register to check the values of these bits. Caution: If a word program operation is interrupted by a reset, the data programmed in the memory may be corrupted.

4.4 Byte programming

Both main program memory and data EEPROM can be programmed and erased at byte level. Byte programming is performed by executing a write instruction (ld, mov...) to an address in main program memory when the memory is unlocked. The write instruction initiates the erase/program cycle and any core access to the memory is blocked until the cycle has completed. This means that program execution from the Flash program memory is stopped until the end of the erase/program cycle. When a new byte program operation starts, EOP and WR_PG_DIS bits of FLASH_IAPSR register are automatically cleared. At the end of the program operation, the EOP bit in the FLASH_IAPSR register is set and the program execution restarts from the instruction following the write/erase instruction. The EOP bit can then be used in order to know if the previous operation has completed. To avoid polling the EOP bit, an interrupt can be generated when EOP is set. This bit is automatically reset when reading FLASH_IAPSR.

Programming STM8 Flash microcontrollers PM0212 16/22 Doc ID 022351 Rev 2 The erase/program cycle lasts longer if the whole word containing the byte to be programmed is not empty because in this case an erase operation is performed automatically. If the word is empty, the erase operation is not performed. However, if a defined programming time is wanted, the FIX bit in the FLASH_CR1 register forces the programming operation to always erase first whatever the contents of the memory. Therefore a fixed programming time is guaranteed (erase time + write time). To erase a byte location, just write ‘0x00’ to the byte location. Caution: A byte programming operation performs a word (4-byte) access to the Flash program memory. If a byte program operation is interrupted by a reset, the 4 bytes programmed in the memory may be corrupted.

4.5 Programming the option bytes

Option bytes are used to configure the device hardware features as well as the memory protection. They are stored in a dedicated memory block.

4.5.1 Summary of memory dedicated option bytes

The Flash program memory includes several option bytes dedicated to memory protection:

  • ROP The ROP option byte is used to prevent the Flash program memory from being read and modified in ICP/SWIM mode. Refer to Section 3.1: Readout protection for a detailed description of readout protection.
  • PCODESIZE The PCODESIZE option byte is used to configure the size of the proprietary code area (PCODE) which can be used to store proprietary software libraries. The minimum size of the proprietary code area is of 1 page (64 bytes) and the maximum size of 253 pages. The PCODESIZE option byte can be modified only in ICP/SWIM mode. Refer to Section 3.2: Proprietary code area protection for a detailed description of the PCODE area and PCODESIZE option byte.
  • UBC The UBC option byte is used to program the size of the write protected user boot code area. The boot area always includes the reset and interrupt vectors and can go up to the full program memory size. The boot area size granularity is of one page. Refer to Section 3.3: User Boot Code area protection for a detailed description of the UBC area.
  • DATASIZE The DATASIZE option byte is used to configure the size of the data EEPROM area. This option byte specifies the number of pages starting from the end of the memory. The maximum size of the data EEPROM area is of 2 Kbytes. Refer to STM8TL5xxx datasheet for details on DATASIZE value programming.

4.5.2 How to program the option bytes

The option bytes are stored only once. register in the reference manual).

4.6 Memory access vers us programming method

Table 5. Memory access versus programming method

4.6.1 ICP methods

is used to communicate with an external programming device connected via a cable. more details on the SWIM mode entry and SWIM protocol.

  1. R/W/E = Read; Write and Execute;

ROP = Protected, write forbidden except for ROP option byte.

  1. When no UBC area has been defined, the interrupt vect ors, except for TRAP, can be modified in user
  2. The data memory is write protected (locked) until the correct MASS key is written in the

FLASH_DUKR. It is possible to lock the memory again by resetting the DUL bit in the IAPSR register.

  1. The PCODE area can be read and executed only in privileged mode through the TRAP vector. The

PCODE cannot be directly accessed through the SWIM.

  1. To program the UBC area the applicati on must first clear the UBC option byte.
  2. When ROP is removed, the whole memo ry is erased, including option bytes.
  3. The Flash program memory is write protected (lo cked) until the correct MASS key is written in the

register. If wrong keys are provided, the device must be reset and new keys programmed. Table 5. Memory access versus programming method (continued)

PM0212 Programming STM8 Flash microcontrollers Doc ID 022351 Rev 2 19/22 First method The first method consists of writing directly into the Flash registers and memory locations through the write memory command of the SWIM protocol. To make sure that the CPU is not accessing the memory during block Flash programming, the core must be stalled by setting the STALL bit in the DM_CSR2 debug module register. The following sequence is required: 1. Apply a RESET 2. Activate the SWIM by sending the entry sequence on the SWIM pin 3. Activate the SWIM_CSR register by writing 1 to the DM bit in SWIM_CSR 4. Disable interrupts by settin g the SAFE_MASK bit in SWIM_CSR 5. Release RESET 6. Verify the DeviceID by reading it using ROTF command 7. Send the SWIM SRST command 8. Unlock the memory by writing the MASS keys 9. Program the Flash program memory using the SWIM WOTF command Second method The second method uses the same sequence of operations as the first method except that the ICP driver firmware must be downloaded in RAM before being launched: 1. Apply a RESET 2. Activate the SWIM by sending the entry sequence on the SWIM pin 3. Activate the SWIM_CSR register by writing 1 to the DM bit in SWIM_CSR 4. Disable interrupts by settin g the SAFE_MASK bit in SWIM_CSR 5. Release RESET 6. Verify the DeviceID by reading it using ROTF command 7. Send the SWIM SRST command 8. Unlock the memory by writing the MASS keys 9. Download the ICP driver firmware into the device RAM using the SWIM WOTF command 10. Execute the ICP driver: a) Modify the CPU registers (new PC, X, Y , CC...) using the WOTF commands b) Set the FLASH bit in the DM_CSR2 register c) Clear the STALL bit in the DM_CSR2 register

4.6.2 IAP method

Refer to application note AN2737- Basic in-application programming example using the STM8 I2C and SPI peripherals.

5 Flash program memory and data EEPROM summary

Table 6. STM8TL5xxx summary

  1. Block program/erase sequence must be executed from RAM.
  2. Any word in the block programmed to 0.

6 Revision history

Table 7. Document revision history 20-Oct-2011 1 Initial release. Replaced “STM8TL53xx” with “STM8TL5xxx”. Added PCODE information throughout the document. Removed all references to TLI. Section 4.3: Word programming, Section 4.4: Byte programming.