TLV3601-Q1_V04 TI | Alldatasheet
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Technical content
TLV360x-Q1 325 MHz High-Speed Comparators with 2.5 ns Propagation Delay
1 Features
- Qualified for automotive applications
- AEC-Q100 qualified with the following results: – Device temperature grade 1: –40°C to 125°C ambient operating temperature range – Device HBM ESD classification level 2 – Device CDM ESD classification level C3
- Fast propagation delay: 2.5 ns
- Low overdrive dispersion: 600 ps
- High toggle frequency: 325 MHz
- Narrow pulse width detection capability: 1.25 ns
- Push-pull output
- Wide supply range: 2.4 V to 5.5 V
- Input common-mode range extends 200 mV beyond both rails
- Low input offset voltage: ±5 mV
- Known startup condition at output
- TLV3603 specific features: – Adjustable hysteresis control pin – Latch function
- Packages: TLV3601 (SC70-5), (SOT23-5), TLV3603 (SC70-6), TLV3602 (VSSOP-8), (WSON-8)
- Functional Safety Capable – Documentation available to aid functional safety system design [TLV3601/2-Q1] – Documentation available to aid functional safety system design [TLV3603-Q1]
2 Applications
- DC/DC converter
- Inverter and motor control
- Fuel Cell Control Unit (FCCU)
- Battery Management System (BMS)
- Mechanically scanning LIDAR
- Audio amplifier
3 Description
The TLV360x are a family of 325 MHz, high-speed comparators with rail-to-rail inputs and a propagation delay of 2.5 ns. The combination of fast response and wide operating voltage range make the comparators suitable for narrow signal pulse detection and data and clock recovery applications in LIDAR, range finders, and line receivers. The push-pull (single-ended ) outputs of the TLV360x family simplify and save cost on board-to-board wiring for I/O interfaces while reducing power consumption when compared to alternative high-speed differential output comparators. They can directly interface most prevailing digital controllers and IO expanders in the downstream circuit. The TLV3601-Q1 is available in tiny 5-pin SC70 and SOT23 packages which makes it well suited for space constrained equipment that benefit from the comparators fast response time. TLV3603-Q1 is packaged in a 6-pin SC70 package and maintains the same speed and size as TLV3601-Q1 while offering the additional features of adjustable hysteresis control and output latch capability. The TLV3602-Q1 is a dual channel version of the TLV3601-Q1 and is packaged in 8-pin VSSOP and WSON packages. Device Information PART NUMBER PACKAGE (1) BODY SIZE (NOM) TLV3601-Q1 SC70 (5) 1.25 mm × 2.00 mm SOT-23 (5) 2.90 mm × 1.60 mm TLV3603-Q1 SC70 (6) 1.25 mm × 2.00 mm TLV3602-Q1 VSSOP (8) 3.00 mm × 3.00 mm WSON (8) (Preview) 2.00 mm × 2.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. + TDC VBIAS LE/HYST TLV3603 OPA858 VREF VCC VEE OUT TLV3601 (TLV3602 per Channel) VEE OUT TLV3603 LE/HYST Functional Block Diagrams TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
11.2 Receiving Notification of Documentation Updates.. 27
12 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (July 2022) to Revision D (August 2022) Page Changes from Revision B (November 2021) to Revision C (July 2022) Page Changes from Revision A (August 2021) to Revision B (November 2021) Page Changes from Revision * (June 2021) to Revision A (August 2021) Page TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 www.ti.com
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5 Pin Configuration and Functions
Figure 5-1. DCK, DBV Package 5-Pin SC70, SOT-23 Top View 1OUT VEE IN+ IN- LE/HYS VCC Figure 5-2. DCK Package 6-Pin SC70 Top View Table 5-1. Pin Functions PIN I/O DESCRIPTION NAME TLV3601 TLV3603 IN+ 3 3 I Non-inverting input IN– 4 4 I Inverting input OUT 1 1 O Output (Push-pull) VEE 2 2 I Negative power supply VCC 5 6 I Positive power supply LE/HYS - 5 I Adjustable hysteresis control and latch www.ti.com TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TLV3601-Q1 TLV3602-Q1 TLV3603-Q1
IN1– IN2– IN2+ Figure 5-3. TLV3602 DGK, DSG Packages 8-Pin VSSOP, WSON Table 5-2. Pin Functions: TLV3602 (Dual) PIN I/O DESCRIPTION NAME NO. IN1+ 1 I Noninverting input, channel 1 IN1– 2 I Inverting input, channel 1 IN2– 3 I Inverting input, channel 2 IN2+ 4 I Noninverting input, channel 2 OUT1 7 O Output, channel 1 OUT2 6 O Output, channel 2 V- 5 P Negative (lowest) supply or ground V+ 8 P Positive (highest) supply Thermal PAD - Connect directly to V- pin TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 www.ti.com
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Product Folder Links: TLV3601-Q1 TLV3602-Q1 TLV3603-Q1
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Input Supply Voltage: VCC – VEE –0.3 6 V Input Voltage (IN+, IN–)(2) VEE – 0.3 VCC + 0.3 V Differential Input Voltage (VDI = IN+ – IN–) –(VCC – VEE + 0.3) + (VCC –VEE + 0.3) V Output Voltage (OUT)(3) VEE – 0.3 VCC + 0.3 V Latch and Hysteresis Control (LE/HYS) VEE – 0.3 VCC + 0.3 V Current into Input pins (IN+, IN–, LE/HYS)(2) ±10 mA Current into Output pins (OUT)(3) ±50 mA Junction temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails must be current-limited to 10 mA or less. (3) Output terminals are diode-clamped to the power-supply rails. Output signals that can swing more than 0.3 V beyond the supply rails must be current-limited to 50 mA or less.
6.2 ESD Ratings
TLV3601(DCK), TLV3603 V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V Charged-device model (CDM), per AEC Q100-011 ±1000 TLV3601(DBV) V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V Charged-device model (CDM), per AEC Q100-011 ±750 TLV3602 V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V Charged-device model (CDM), per AEC Q100-011 ±500 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Input Supply Voltage: VCC – VEE 2.4 5.5 V Input Voltage Range (IN+, IN–) VEE – 0.3 VCC + 0.3 V Latch and Hysteresis Control (LE/HYS) VEE – 0.3 VCC + 0.3 V Ambient temperature, TA –40 125 °C www.ti.com TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TLV3601-Q1 TLV3602-Q1 TLV3603-Q1
6.4 Thermal Information
TLV3601 TLV3601 TLV3602 TLV3602 TLV3603 UNITDBV (SOT-23) DCK (SC70) DGK (VSSOP) DSG (WSON) DCK (SC70)
5 PINS 5 PINS 8 PINS 8 PINS 6 PINS
Rθ JC(top Rθ JC(bot tom) Junction-to-case (bottom) thermal resistance N/A N/A N/A 5.5 N/A °C/W ψJT Junction-to-top characterization ψJB Junction-to-board characterization TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 www.ti.com
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6.5 Electrical Characteristics
VCC = 2.5, 3.3 and 5 V, VEE = 0 V, VCM = VEE + 300 mV, CL = 5 pF probe capacitance, typical at TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC Input Characteristics VIO Input offset voltage TA = –40°C to +125℃ –5 ±0.5 5 mV dVIO/dT Input offset voltage drift ±3.0 μV/°C VCM Input common mode voltage range TA = –40℃ to +125℃ VEE – 0.2 VCC + 0.2 V VHYST (TLV3601) Input hysteresis voltage TA = –40℃ to +125℃ 1.5 3 5(1) mV CIN Input capacitance 1 pF RDM Input differential mode resistance 67 kΩ RCM Input common mode resistance 5 MΩ IB Input bias current TA = –40℃ to +125℃ 1 5 uA IOS Input offset current ±0.03 uA CMRR Common-mode rejection ratio VCM = VEE – 0.2V to VCC + 0.2V 80 dB PSRR Power-supply rejection ratio VCC = 2.4 to 5.5V 80 dB DC Output Characteristics VOH Output high voltage from VCC ISOURCE = 1 mA TA = –40℃ to +125℃ 60 80 mV VOL Output low voltage from VEE ISINK = 1 mA TA = –40℃ to +125℃ 60 80 mV ISC_SOURCE Output Short-Circuit Current - Source TA = –40℃ to +125℃ 10 30 mA ISC_SINK Output Short-Circuit Current - Sink TA = –40℃ to +125℃ 10 30 mA Power Supply ICC (TLV3601) quiescent current Output being high TA = –40℃ to +125℃ 4.9 7 mA ICC (TLV3602) quiescent current per channel Output being high TA = –40℃ to +125℃ 4.9 7 mA ICC (TLV3603) quiescent current Output being high TA = –40℃ to +125℃ 5.7 7.8 mA VPOR (postive) Power-On Reset Voltage 2.1 V AC Characteristics tPD Propagation delay VOVERDRIVE = VUNDERDRIVE = 50mV 2.5 3.5(1) ns tPD Propagation delay VOVERDRIVE = VUNDERDRIVE = 50mV ΔtPD (TLV3602 only) Channel-to-channel propagation delay skew(2) VCM = VCC/2, VOVERDRIVE = VUNDERDRIVE = 50mV, 50 MHz Squarewave 24 ps tCM_DISPERSION Common dispersion VCM varied from VEE to VCC 80 ps tOD_DISPERSION Overdrive dispersion Overdrive varied from 10 mV to 125 mV 600 ps tUD_DISPERSION Underdrive dispersion Underdrive varied from 10mV to 125 mV 330 ps tR Rise time 10% to 90% 0.75 ns tF Fall time 90% to 10% 0.75 ns tJITTER RMS Jitter VIN = 100mVP-P, fIN = 100MHz, Jitter BW = 10Hz – 50MHz 4 ps fTOGGLE Input toggle frequency VIN = 200 mVPP Sine Wave, When output high reaches 90% of VCC - VEE or output low reaches 10% of VCC - VEE
325 MHz
PulseWidth Minimum allowed input pulse width VOVERDRIVE = VUNDERDRIVE = 50mV PWOUT = 90% of PWIN 1.25 ns www.ti.com TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TLV3601-Q1 TLV3602-Q1 TLV3603-Q1
6.5 Electrical Characteristics (continued)
VCC = 2.5, 3.3 and 5 V, VEE = 0 V, VCM = VEE + 300 mV, CL = 5 pF probe capacitance, typical at TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Latching/Adjustable Hysteresis VHYST Input hysteresis voltage VHYST = Logic High 0 mV VHYST Input hysteresis voltage RHYST = Floating 3 mV VHYST Input hysteresis voltage RHYST = 150 kΩ 30 mV VHYST Input hysteresis voltage RHYST = 56 kΩ 60 mV VIH_LE LE pin input high level TA = –40℃ to +125℃ VEE + 1.5 V VIL_LE LE pin input low level TA = –40℃ to +125℃ VEE + 0.35 V IIH_LE LE pin input leakage current VLE = VCC TA = –40℃ to +125℃ 15 uA IIL_LE LE pin input leakage current VLE = VEE, TA = –40℃ to +125℃ 40 uA tSETUP Latch setup time –1.4 ns tHOLD Latch hold time 7.2 ns tPL Latch to OUT delay 7 ns (1) Ensured by characterization (2) Differential propagation delay is defined as the larger of the two: ΔtPDLH = tPDLH(MAX) – tPDLH(MIN) ΔtPDHL = tPDHL(MAX) – tPDHL(MIN) where (MAX) and (MIN) denote the maximum and minimum values of a given measurement across the different comparator channels.
6.6 Timing Diagrams
50% tR tF tPLH tPHL 90% 10% Figure 6-1. General Timing Diagram TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 www.ti.com
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VOD = 10mV VOD = 125mV IN+ VOUT IN- Figure 6-2. Overdrive Dispersion www.ti.com TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TLV3601-Q1 TLV3602-Q1 TLV3603-Q1
6.7 Typical Characteristics
At TA = 25°C, VCC - VEE = 2.5 V to 5 V, VCM = 300 mV, RHYST = 150 kΩ (TLV3603-Q1 only), and input overdrive = 50 mV, unless otherwise noted. Temperature ( C) Input Offset Voltage (mV) -40 -25 -10 5 20 35 50 65 80 95 110 125 -1.5 -0.5 0.5 1.5 For 33 units Figure 6-3. TLV3601 Offset vs. Temperature Temperature ( C) Hysteresis (mV) -40 -25 -10 5 20 35 50 65 80 95 110 125 2.8 2.9 3.1 3.2 V CC = 2.5V V CC = 3.3V V CC = 5V Figure 6-4. TLV3601 Hysteresis vs. Temperature Input Common-Mode Voltage (V) Input Offset Voltage (mV) -0.6 -0.2 0.2 0.6 1.4 1.8 For 33 units Figure 6-5. TLV3601 Offset vs. Common-Mode, 2.5 V Figure 6-6. TLV3601 Hysteresis vs. Common-Mode, 2.5 V Input Common-Mode Voltage (V) Input Offset Voltage (mV) -0.6 -0.2 0.2 0.6 1.4 1.8 For 33 units Figure 6-7. TLV3601 Offset vs. Common-Mode, 3.3 V Input Common Mode Voltage (V) Hysteresis (mV) 0.5 1.5 2.5 3.5 4.5 -40 C 25 C 85 C 125 C Figure 6-8. TLV3601 Hysteresis vs. Common-Mode, 3.3 V TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 www.ti.com
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6.7 Typical Characteristics (continued)
At TA = 25°C, VCC - VEE = 2.5 V to 5 V, VCM = 300 mV, RHYST = 150 kΩ (TLV3603-Q1 only), and input overdrive = 50 mV, unless otherwise noted. Input Common-Mode Voltage (V) Input Offset Voltage (mV) -0.6 -0.2 0.2 0.6 1.4 1.8 For 33 units Figure 6-9. TLV3601 Offset vs. Common-Mode, 5 V Input Common Mode Voltage (V) Hysteresis (mV) 0.5 1.5 2.5 3.5 4.5 -40 C 25 C 85 C 125 C Figure 6-10. TLV3601 Hysteresis vs. Common-Mode, 5 V Temperature ( C) Input Offset Voltage (mV) -40 -25 -10 5 20 35 50 65 80 95 110 125 -1.5 -0.5 0.5 1.5 For 33 units Figure 6-11. TLV3603 Offset vs. Temperature Temperature ( C) Hysteresis (mV) -40 -25 -10 5 20 35 50 65 80 95 110 125 V CC = 2.5V V CC = 3.3V V CC = 5V Figure 6-12. TLV3603 Hysteresis vs. Temperature Input Common-Mode Voltage (V) Input Offset Voltage (mV) -0.6 -0.2 0.2 0.6 1.4 1.8 For 33 units Figure 6-13. TLV3603 Offset vs. Common-Mode, 2.5 V Input Common-Mode Voltage (V) Hysteresis (mV) -40 C 25 C 85 C 125 C Figure 6-14. TLV3603 Hysteresis vs. Common-Mode, 2.5 V www.ti.com TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TLV3601-Q1 TLV3602-Q1 TLV3603-Q1
At TA = 25°C, VCC - VEE = 2.5 V to 5 V, VCM = 300 mV, RHYST = 150 kΩ (TLV3603-Q1 only), and input overdrive = 50 mV, unless otherwise noted. Input Common-Mode Voltage (V) Input Offset Voltage (mV) -0.6 -0.2 0.2 0.6 1.4 1.8 For 33 units Figure 6-15. TLV3603 Offset vs. Common-Mode, 3.3 V Input Common-Mode Voltage (V) Hysteresis (mV) -40 C 25 C 85 C 125 C Figure 6-16. TLV3603 Hysteresis vs. Common-Mode, 3.3 V Input Common-Mode Voltage (V) Input Offset Voltage (mV) -0.6 -0.2 0.2 0.6 1.4 1.8 For 33 units Figure 6-17. TLV3603 Offset vs. Common-Mode, 5 V Input Common-Mode Voltage (V) Hysteresis (mV) -40 C 25 C 85 C 125 C Figure 6-18. TLV3603 Hysteresis vs. Common-Mode, 5 V R HYST (k ) V HYST (mV) 0 200 400 600 800 1,000 -40 C 25 C 85 C 125 C Figure 6-19. TLV3603 Hysteresis vs. Resistance, 2.5 V R HYST (k ) V HYST (mV) 0 200 400 600 800 1,000 -40 C 25 C 85 C 125 C Figure 6-20. TLV3603 Hysteresis vs. Resistance, 3.3 V TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 www.ti.com
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At TA = 25°C, VCC - VEE = 2.5 V to 5 V, VCM = 300 mV, RHYST = 150 kΩ (TLV3603-Q1 only), and input overdrive = 50 mV, unless otherwise noted. R HYST (k ) V HYST (mV) 0 200 400 600 800 1,000 -40 C 25 C 85 C 125 C Figure 6-21. TLV3603 Hysteresis vs. Resistance, 5 V Figure 6-22. Bias Current vs. Input Voltage, 2.5 V Input Voltage (V) Input Bias Current ( A) -40 C 25 C 85 C 125 C Figure 6-23. Bias Current vs. Input Voltage, 3.3 V Figure 6-24. Bias Current vs. Input Voltage, 5 V Output Sourcing Current (A) 100 1m 10m 100m 100m 10m Output Voltage to V CC (V) -40 C 25 C 85 C 125 C Figure 6-25. Output Voltage vs. Output Sourcing Current, 2.5 V Figure 6-26. Output Voltage vs. Output Sinking Current, 2.5 V www.ti.com TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TLV3601-Q1 TLV3602-Q1 TLV3603-Q1
At TA = 25°C, VCC - VEE = 2.5 V to 5 V, VCM = 300 mV, RHYST = 150 kΩ (TLV3603-Q1 only), and input overdrive = 50 mV, unless otherwise noted. Figure 6-27. Output Voltage vs. Output Sourcing Current, 3.3 V Figure 6-28. Output Voltage vs. Output Sinking Current, 3.3 V Figure 6-29. Output Voltage vs. Output Sourcing Current, 5 V Figure 6-30. Output Voltage vs. Output Sinking Current, 5 V Supply Voltage (V) Supply Current (mA) 2 2.5 3 3.5 4 4.5 5 5.5 4.5 4.7 4.9 5.1 5.3 5.5 -40 C 25 C 85 C 125 C Figure 6-31. TLV3601 Supply Current vs. Voltage (Output Low) Supply Voltage (V) Supply Current (mA) 2 2.5 3 3.5 4 4.5 5 5.5 4.5 4.7 4.9 5.1 5.3 5.5 -40 C 25 C 85 C 125 C Figure 6-32. TLV3601 Supply Current vs. Voltage (Output High) TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 www.ti.com
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At TA = 25°C, VCC - VEE = 2.5 V to 5 V, VCM = 300 mV, RHYST = 150 kΩ (TLV3603-Q1 only), and input overdrive = 50 mV, unless otherwise noted. Figure 6-33. TLV3601 Supply Current vs. Temp (Output Low) Figure 6-34. TLV3601 Supply Current vs. Temp (Output High) Supply Voltage (V) Supply Current (mA) 2 2.5 3 3.5 4 4.5 5 5.5 5.2 5.4 5.6 5.8 6.2 -40 C 25 C 85 C 125 C Figure 6-35. TLV3603 Supply Current vs. Voltage (Output Low) Supply Voltage (V) Supply Current (mA) 2 2.5 3 3.5 4 4.5 5 5.5 5.2 5.4 5.6 5.8 6.2 -40 C 25 C 85 C 125 C Figure 6-36. TLV3603 Supply Current vs. Voltage (Output High) Temperature ( C) Supply Current (mA) -40 -25 -10 5 20 35 50 65 80 95 110 125 5.2 5.4 5.6 5.8 6.2 V CC = 2.5V V CC = 3.3V V CC = 5V Figure 6-37. TLV3603 Supply Current vs. Temp (Output Low) Temperature ( C) Supply Current (mA) -40 -25 -10 5 20 35 50 65 80 95 110 125 5.2 5.4 5.6 5.8 6.2 V CC = 2.5V V CC = 3.3V V CC = 5V Figure 6-38. TLV3603 Supply Current vs. Temp (Output High) www.ti.com TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TLV3601-Q1 TLV3602-Q1 TLV3603-Q1
At TA = 25°C, VCC - VEE = 2.5 V to 5 V, VCM = 300 mV, RHYST = 150 kΩ (TLV3603-Q1 only), and input overdrive = 50 mV, unless otherwise noted. Input Overdrive (mV) Propagation Delay, Low to High (ns) 10 20 30 40 50 70 100 200 300 500 700 1000 1.5 2.5 3.5 4.5 -40 C 25 C 85 C 125 C Figure 6-39. Propagation Delay, Low to High, 2.5 V Input Overdrive (mV) Propagation Delay, High to Low (ns) 10 20 30 40 50 70 100 200 300 500 700 1000 1.5 2.5 3.5 4.5 -40 C 25 C 85 C 125 C Figure 6-40. Propagation Delay, High to Low, 2.5 V Figure 6-41. Propagation Delay, Low to High, 3.3 V Input Overdrive (mV) Propagation Delay, High to Low (ns) 10 20 30 40 50 70 100 200 300 500 700 1000 1.5 2.5 3.5 4.5 -40 C 25 C 85 C 125 C Figure 6-42. Propagation Delay, High to Low, 3.3 V Figure 6-43. Propagation Delay, Low to High, 5 V Figure 6-44. Propagation Delay, High to Low, 5 V TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 www.ti.com
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At TA = 25°C, VCC - VEE = 2.5 V to 5 V, VCM = 300 mV, RHYST = 150 kΩ (TLV3603-Q1 only), and input overdrive = 50 mV, unless otherwise noted. Output Capacitive Load (pF) Propagation Delay (ns) 0 10 20 30 40 50 60 70 80 90 100 t PHL t PLH Figure 6-45. Propagation Delay vs. Load Capacitance, 3.3 V Output Capacitive Load (pF) Propagation Delay (ns) 0 10 20 30 40 50 60 70 80 90 100 t PHL t PLH Figure 6-46. Propagation Delay vs. Load Capacitance, 5 V Figure 6-47. Minimum Pulse Width vs. Temperature www.ti.com TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TLV3601-Q1 TLV3602-Q1 TLV3603-Q1
7 Detailed Description
7.1 Overview
TheTLV360x family are high-speed comparators with single-ended (push-pull) output stages. The fast response time of these comparators make them well suited for applications that require narrow pulse width detection or high toggle frequencies. The TLV3601-Q1 is available in a 5-pin SC70 and SOT23 package, while the TLV3603-Q1 is packaged in a 6-pin SC70. The TLV3602-Q1 is a dual channel version of the TLV3601-Q1 and is packaged in an 8-pin VSSOP and WSON package.
7.2 Functional Block Diagram
7.3 Feature Description
The TLV3601-Q1,TLV3603-Q1, and TLV3602-Q1 are single and dual channel, high speed comparators with a typical propagation delay of 2.5 ns and push-pull outputs. The minimum pulse width detection capability is 1.25 ns and the typical toggle rate is 325 MHz. These comparators are well-suited for distance measurement applications that utilize a time-of-flight arechitecture as well as systems that suffer from capacitive loading and require data and clock recovery. In addition to their high speed, the TLV360x family offers rail-to-rail input stages capable of operating up to 200 mV beyond each power supply rail combined with a maximum 5 mV input offset. The TLV3603-Q1 also provides adjustable hysteresis via an external resistor for noise suppression or a latching mode to hold the output of the comparators.
7.4 Device Functional Modes
The TLV3601-Q1 has a single functional mode and is active when the power supply voltage is greater than 2.4V. The TLV3603-Q1 has two modes of operation. The first is an active mode where the output reflects the condition at the inputs when an external resistor is connected to ground on the LE/HYS pin. The second is a latch mode where the output is held at its last active state when the LE/HYS pin is pulled low. The TLV3603-Q1 returns to active mode after a short delay when the pin is pulled high.
7.4.1 Inputs
The TLV360x family features input stages capable of operating 200 mV below negative power supply (ground) and 200 mV beyond the positive supply voltage, allowing for zero cross detection and maximizing input dynamic range given a certain power supply. The input stages are protected from conditions where the voltage on either pin exceeds this level by internal ESD protection diodes to VCC and VEE. To avoid damaging the inputs when exceeding the recommended input voltage range, an external resistor should be used to limit the current.
7.4.2 Push-Pull (Single-Ended) Output
The TLV360x outputs have excellent drive capability and are designed to connect directly to CMOS logic input devices. Likewise, the comparator output stages can drive capacitive loads. Transient performance parameters in the Electrical Characteristics Tables and Typical Characteristics section are for a load of 5pF, corresponding to a standard CMOS load. Device performance for larger capacitive loads can be found in the typical performance curves titled Propagation Delay vs Capacitive Load. For optimal speed and performance, output load capacitance should be reduced as much as possible. TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 www.ti.com
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7.4.3 Known Startup Condition
The TLV360x have a Power-on-Reset (POR) circuit which provides system designers a known start-up condition for the output of the comparators. When the power supply (VCC) is ramping up or ramping down, the POR circuit will be active when VCC is below VPOR. When active, the POR circuit holds the output low at VEE. When VCC is greater than or equal to VPOR as stated in Section 6.5 , the comparator output reflects the state of the input pins. Figure 7-1 shows how the TLV360x outputs respond for VCC rising. The input is configured with a logic high input to highlight the transition from the POR circuit control (logic low output) to a standard comparator operation where the output reflects the input condition. Note how the output goes high when VCC reaches 2.1V. Figure 7-1. TLV3601/TLV3603 Output for VCC Rising www.ti.com TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TLV3601-Q1 TLV3602-Q1 TLV3603-Q1
8 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Adjustable Hysteresis
As a result of a comparator’s high open loop gain, there is a small band of input differential voltage where the output can toggle back and forth between “logic high” and “logic low” states. This can cause design challenges for inputs with slow rise and fall times or systems with excessive noise. These challenges can be overcome by adding hysteresis to the comparator. Since the TLV3601-Q1 and TLV3602-Q1 only has a minimal amount of internal hysteresis, external hysteresis can be applied in the form of a positive feedback loop that adjusts the trip point of the comparator depending on its current output state. See the Implementing Hysteresis section for more details. The TLV3603-Q1 on the other hand has a LE/HYS pin that can be used to increase or eliminate the internal hysteresis of the comparator. In order to increase the internal hysteresis of the TLV3603-Q1, connect a single resistor as shown in the adjusting hysteresis figure between the LE/HYS pin and VEE. A curve of hysteresis versus resistance is provided below to provide guidance in setting the desired amount of hysteresis. Likewise, for applications where no hysteresis is desired, the LE/HYS pin can be connected to VCC. OUT VEE VCC LE/HYS IN+ IN- TLV3603 Figure 8-1. Adjustable Hysteresis with an External Resistor R HYST (k ) V HYST (mV) 0 200 400 600 800 1,000 -40 C 25 C 85 C 125 C Figure 8-2. VHYST (mV) vs RHYST (kΩ), VCC = 5 V TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 www.ti.com
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8.1.2 Capacitive Loads
For capacitive loads under 100 pF, the propagation delay has minimum change (see Propagation Delay vs. Capacitive Load). However, excessive capacitive loading under high switching frequencies may increase supply current, propagation delay, or induce decreased slew rate.
8.1.3 Latch Functionality
The latch pin for the TLV3603-Q1 holds the output state of the device when the voltage at the LE/HYS pin is a logic low. This is particularly useful when the output state is intended to remain unchanged. An important consideration of the latch functionality is the latch hold and setup times. Latch hold time is the minimum time required (after the latch pin is asserted) for properly latching the comparator output. Likewise, latch setup time is defined as the time that the input must be stable before the latch pin is asserted low. The figure below illustrates when the input can transition for a valid latch. Note that the typical setup time in the EC table is negative; this is due to the internal trace delays of the LE/HYS pin relative to the input pin trace delays. A small delay (t PL) in the output response is shown below when the TLV3603-Q1 exits a latched output stage. Invalid Input Transition Region Valid Input Transition Region tSETUP tHOLD Valid Input Transition Region LE/HYS IN Figure 8-3. Input Change Properly Latched LE/HYS IN tPL OUT Figure 8-4. Latch Disable with Input Change
8.2 Typical Application
8.2.1 Implementing Hysteresis
A comparator may produce “chatter” (multiple transitions) at the output when there are noise or signal variations around the reference threshold; this causes the output to change states in rapid random successions as the comparator input goes above and below the threshold of the reference. This usually occurs when the input signal www.ti.com TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TLV3601-Q1 TLV3602-Q1 TLV3603-Q1
is moving very slowly across the switching threshold of the comparator. This problem can be prevented by using the internal hysteresis feature of the comparator or by the addition of external hysteresis. The TLV3603-Q1 has a LE/HYS pin that allows for variable internal hysteresis depending on the resistor value connected between the pin and VEE, where increasing the resistance decreases the hysteresis to a minimum level. 5 V 0 V VL VH VO 2.485 V 2.515 V VIN LE/HYS TLV3603 VO VIN VREF 2.5 V VCC VEE 150 kΩ Figure 8-5. Adjustable Hysteresis with a 150kΩ Resistor using TLV3603 Since the TLV3601-Q1 and TLV3602-Q1 only have a minimal amount of internal hysteresis, external hysteresis can be added in the form of a positive feedback loop. A non-inverting comparator with hysteresis requires a two-resistor network and a voltage reference (VREF) at the inverting input, as shown in Figure 8-6. VREF 2.5 V 10 k VOVA 5 V 0 V VL VH VO 2.485 V 2.515 V VIN VIN Figure 8-6. Non-Inverting Configuration for Hysteresis using TLV3601
8.2.1.1 Design Requirements
For this design, follow these design requirements. Table 8-1. Design Parameters PARAMETER VALUE Supply Voltage (VCC) 5 V VREF 2.5 V VHYS 30 mV Lower Threshold (VL) 2.485 V Upper Threshold (VH) 2.515 V
8.2.1.2 Detailed Design Procedure
For the TLV3603-Q1, the hysteresis vs. resistance curve ( Figure 8-2 ) can be used as a guidance to set the desired amount of hysteresis. Figure 8-2 shows that for a 30-mV hysteresis, a 150 k Ω resistor must be placed from the LE/HYS pin to VEE. For the TLV3601-Q1 and TLV3602-Q1, the following procedure can be used to add external hysteresis for a non-inverting configuration. Note that V HYST << V REF, so V HYST can be ignored and is not included in the following equations for simpler calculation. TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 www.ti.com
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The equivalent resistor networks when the output is high and low are shown in Figure 8-7. VA = VREF VO High VCC VA = VREF VO Low VH VL Figure 8-7. Equivalent Resistor Networks for Non-Inverting Configuration with Hysteresis When VIN is less than V REF, the output is low. For the output to switch from low to high, V IN must rise above the VH threshold. Use Equation 1 to calculate VH. VH = (R1 x VREF/R2) + VREF (1) When VIN is greater than V REF, the output is high. For the comparator to switch back to a low state, V IN must drop below the VL threshold. Use Equation 2 to calculate VL. VL = [VREF (R1 + R2) - VCC x R1] / R2 (2) The hysteresis of this circuit is the difference between VH and VL, as shown in Equation 3. ΔVIN = VHYS = (VCC x R1/R2) (3) Select a value for R2. Plug in given values for V CC, VREF, VH, and VL . For the given example, R2 = 10 k Ω, and R1 is solved as 60 Ω. For more information, please see Application Notes SNOA997 "Inverting Comparator with Hysteresis Circuit" , SBOA313 "Non-Inverting Comparator With Hysteresis Circuit" , SBOA219 " Comparator with and without hysteresis circuit".
8.2.1.3 Application Curve
VO (V) VIN (V) Figure 8-8. Hysteresis Transfer Curve using TLV3601/TLV3603 www.ti.com TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TLV3601-Q1 TLV3602-Q1 TLV3603-Q1
8.2.2 Optical Receiver
The TLV360x can be used in conjunction with a high speed amplifier such as the OPA858 to create an optical receiver as shown in the figure below. The photodiode is connected to a bias voltage and is being driven with a pulsed laser. The OPA858 takes the current conducting through the diode and translates it into a voltage for a high speed comparator to detect. The comparators will then output the proper output signal according to the threshold set (VREF). + TDC VBIAS LE/HYST TLV3603 OPA858 VREF Figure 8-9. Optical Receiver
8.2.3 Over-Current Latch Condition
When it is important for a system to detect a brief over-current condition, it is advisable to utilize the latching feature of the TLV3603-Q1. By latching the comparator output, the MCU is reassured not to miss the over- current occurrence. The circuit below shows one way to implement the latching function. When an over-current condition is detected by the TLV3603-Q1, the output will go high. The occurrence of the output going high coupled with a logic high from the RESET signal from the MCU will create a logic low signal at the output of the 2-channel NAND gate. This will cause the output of the TLV3603-Q1 to be held in a logic high state (latched), thus allowing the MCU to detect the fault condition regardless of how narrow the over-current condition persists. The addition of the NAND gate also provides a means of clearing the latch state of the comparator once the MCU is done processing the event. This is accomplished by the MCU passing a logic low state to the NAND input causing the LE/HYS pin of the comparator to be returned to a logic high state. The TLV3603-Q1 latched status is cleared and the TLV3603-Q1 output can continue to track the status of the input pins. LE/HYS TLV3603 VREF System IS RS MCU RESET ALERT Figure 8-10. Over-Current Latched Output Circuit TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 www.ti.com
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8.2.4 External Trigger Function for Oscilloscopes
Below is a typical configuration for creating an external trigger on oscilliscopes. The user adjusts the trigger level by programming a DAC that the TLV360x can use as a reference. The input from an oscilloscope channel is then compared to the trigger reference voltage, and the comparator sends a signal to a downstream FPGA to begin a capture. VCC = 5V FPGATLV3601 DAC VIN Trigger Input Figure 8-11. External Trigger Function
9 Power Supply Recommendations
The TLV360x are specified for operation from 2.4 V to 5.5 V. While most applications will require single supply operation where VEE is connected to the ground plane and VCC is connected to the intended power supply level, the comparators can also be operated with split supplies. One caution when using split supplies is that the output logic levels are determined by the VCC and VEE levels. For example, if split supplies of +/- 2.5V are used, the output levels will be 2.5V and -2.5V accordingly. In addition, the logic level of the LE/HYS pin will also be referenced to VEE. This means that the external hysteresis resistor on the TLV3603-Q1 needs to be connected between the LE/HYS pin and VEE (not to ground) for proper operation. Regardless of single supply or split supply operation, proper decoupling capacitors are required. It is recommended to use a scheme of multiple, low-ESR ceramic capacitors from the supply pins to the ground plane for optimum performance. A good combination would be 100 pF, 10 nF, and 1 uF with the lowest value capacitor closest to the comparator. www.ti.com TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TLV3601-Q1 TLV3602-Q1 TLV3603-Q1
10 Layout
10.1 Layout Guidelines
Comparators are very sensitive to input noise. For best results, adhere to the following layout guidelines. 1. Use a printed-circuit-board (PCB) with a good, unbroken, low-inductance ground plane. Proper grounding (use of a ground plane) helps maintain specified device performance. Likewise, high performance board materials such as Rogers or high speed FR4 is also recommended. 2. Place a decoupling capacitor (100-pF ceramic, surface-mount capacitor) between VCC and VEE as close to the device as possible. Using multiple bypass capacitors in different decade ranges such as 100-pF, 100-nF, and 1-µF provides the best noise reduction across frequency ranges. 3. On the inputs and the output, keep lead lengths as short and minimize capacitive coupling to the traces by having a keepout area around the traces that is 3x the width of the traces. It is also recommended to keep inputs away from the output. 4. Solder the device directly to the PCB rather than using a socket.
10.2 Layout Example
Figure 10-1. TLV3603 Layout Example TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 www.ti.com
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
LIDAR Pulsed Time of Flight Reference Design
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 SNOSDC3D – JUNE 2021 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TLV3601-Q1 TLV3602-Q1 TLV3603-Q1
www.ti.com 5-Jan-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PLV3602QDGKRQ1 ACTIVE VSSOP DGK 8 2500 TBD Call TI Call TI -40 to 125 Samples PLV3603QDCKTQ1 ACTIVE SC70 DCK 6 250 TBD Call TI Call TI -40 to 125 Samples TLV3601QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 601Q Samples TLV3601QDCKRQ1 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1JG Samples TLV3602QDGKRQ1 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 602Q Samples TLV3603QDCKRQ1 ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1JH Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1
www.ti.com 5-Jan-2023 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV3601-Q1, TLV3602-Q1, TLV3603-Q1 :
- Catalog : TLV3601 , TLV3602 , TLV3603 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 6-Jan-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 6-Jan-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV3601QDBVRQ1 SOT-23 DBV 5 3000 210.0 185.0 35.0 TLV3601QDCKRQ1 SC70 DCK 5 3000 183.0 183.0 20.0 TLV3602QDGKRQ1 VSSOP DGK 8 2500 366.0 364.0 50.0 TLV3603QDCKRQ1 SC70 DCK 6 3000 183.0 183.0 20.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 0.22
0.08 TYP
0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15
0.00 TYP
5X 0.5 0.3 0.6
0.3 TYP
0 TYP
1.9 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/F 06/2021 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side.
0.2 C A B
0.1 C SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/F 06/2021 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/F 06/2021 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4
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