TLV3231-Q1 TI | Alldatasheet
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Technical content
TLV323x-Q1 20ns High-Speed Comparator with Rail-to-Rail Input
1 Features
- Qualified for automotive applications
- AEC-Q100 qualified with the following results: – Device temperature grade 1: –40°C to 125°C ambient operating temperature range – Device HBM ESD classification level H1C – Device CDM ESD classification level C6
- Propagation delay: 20ns
- Input offset voltage: +/- 4mV maximum
- Low supply current: 200µA per channel
- Input voltage range extends 300mV beyond either rail
- Internal hysteresis: 1.55mV
- Power-on-reset provides a known startup condition
- Push-pull output
2 Applications
- Telematics eCall
- Automotive head unit
- Instrument Cluster
- On-board (OBC) & wireless chargers
3 Description
The TLV323x -Q1 are a family of 5V single and dual channel comparators with push-pull outputs. The family has an excellent speed-to-power combination with a propagation delay of 20ns and a full supply voltage range of 2.7V to 5V with a quiescent supply current of only 200μA per channel. All devices include a Power-On Reset (POR) feature. Until the minimum supply voltage has been reached and the output responds to the inputs, POR places the output is in a known state, thus preventing false outputs during system power-up and power down. The TLV323x -Q1 comparators have a push-pull output stage capable of sinking and sourcing milliamps of current when controlling an LED or driving a capacitive load such as a MOSFET gate. Device Information PART NUMBER PACKAGE (1) BODY SIZE (NOM (2) TLV3231-Q1 SC-70 (5) 1.25mm × 2.00mm SOT-23 (5) (Preview) 1.60mm × 2.90mm TLV3232-Q1 VSSOP (8) (Preview) 3.00mm × 3.00mm WSON (8) (Preview) 2.00mm × 2.00mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. OUT IN+ IN- Bias Power-On Reset V- V- Output Control * * * Push-Pull Version Only Power Clamp V+ V+ ESD CLAMPS Block Diagram REF MCU TLV3231 INA Shunt Resistor Load Current 3.3V Low-Side Current Sensing ADVANCE INFORMATION TLV3231-Q1, TLV3232-Q1 SNOSDK2 – JUNE 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.
10 Mechanical, Packaging, and Orderable
TLV3231-Q1, TLV3232-Q1 SNOSDK2 – JUNE 2024 www.ti.com
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4 Pin Configuration and Functions
Pin Configurations: TLV3231 and TLV3232 3 4 IN- IN+ OUT DCK, DBV Packages SC70, SOT-23-5 Top View (Standard "North West" Pinout) Table 4-1. Pin Functions: TLV3231-Q1 PIN I/O DESCRIPTION NAME NO. OUT 1 O Output V- 2 - Negative supply voltage IN+ 3 I Non-inverting (+) input IN- 4 I Inverting (-) input V+ 5 - Positive supply voltage www.ti.com TLV3231-Q1, TLV3232-Q1 SNOSDK2 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TLV3231-Q1 TLV3232-Q1 ADVANCE INFORMATION
IN2± IN2+ OUT1 IN1± IN1+ Figure 4-1. DGK, DSG Packages 8-Pin VSSOP, WSON Top View Table 4-2. Pin Functions: TLV3232-Q1 PIN I/O DESCRIPTION NAME NO. IN1+ 1 I Noninverting input, channel 1 IN1– 2 I Inverting input, channel 1 IN2– 3 I Inverting input, channel 2 IN2+ 4 I Noninverting input, channel 2 OUT1 7 O Output, channel 1 OUT2 6 O Output, channel 2 V- 5 - Negative (lowest) supply or ground V+ 8 - Positive (highest) supply TLV3231-Q1, TLV3232-Q1 SNOSDK2 – JUNE 2024 www.ti.com
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage VS = (V+) - (V-) 6 V Differential input voltage, VID Differential input voltage, VID -6 6 V Input pins (IN+, IN–) from (V-) (2) – 0.5 (V+) + 0.5 V Current into input pins (IN+, IN-) Current into input pins (IN+, IN-) -10 10 mA Output (OUT) from (V-) – 0.5 (V+) + 0.5 V Output short-circuit current Output short-circuit current -100 100 mA Output short-circuit duration 10 s Junction temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Input terminals are diode-clamped to (V–) and (V+). Input signals that can swing more than 0.5V beyond the supply rails must be current-limited to 10mA or less.
5.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V Charged-device model (CDM), per AEC Q100-011 ±1000 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Supply voltage VS = (V+) - (V-) 2.7 5.5 V Input voltage range (V-) - 0.3 (V+) + 0.3 V Ambient temperature, TA –40 125 °C
5.4 Thermal Information
THERMAL METRIC (1) TLV3231 UNITDBV (SOT-23) DCK (SC70)
5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 220 °C/W RθJC(top) Junction-to-case (top) thermal resistance 135 °C/W RθJB Junction-to-board thermal resistance 65 °C/W ΨJT Junction-to-top characterization parameter 34 °C/W ΨJB Junction-to-board characterization parameter 65 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com TLV3231-Q1, TLV3232-Q1 SNOSDK2 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TLV3231-Q1 TLV3232-Q1 ADVANCE INFORMATION
5.5 Electrical Characteristics
VS = 2.7V to 5V, VCM = VS / 2; at TA = 25°C (unless otherwise noted). Typical values are at TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC Input Characteristics VIO Input Offset Voltage VS = 5V, VCM = VS / 2 ±0.1 ±4 mV VIO Input Offset Voltage VS = 5V, VCM = VS / 2, TA = -40 to 125℃ ±5 mV VHYS Hysteresis VS = 5V, VCM = VS / 2 0.5 1.55 2 mV VHYS Hysteresis VS = 5V, VCM = VS / 2, TA = -40 to 125℃ 2.5 mV VCM Common-mode voltage range (V-) - 0.1 (V+)+0.1 V IB Input bias current VS = 5V, VCM = VS / 2 1 nA IB Input bias current VS = 5V, VCM = VS / 2, TA = -40 to 125℃ 10 nA IOS Input offset current VS = 5V, VCM = VS / 2 1 nA CIN Input capacitance 2 pF RDM Input differential mode resistance 9000 MΩ RCM Input common mode resistance 9000 MΩ CMRR Common-mode rejection ratio VCM = VEE - 0.1V to VCC + 0.1V 82 dB DC Output Characteristics VOH Voltage swing from (V+) VS = 5V, (V-) = 0V, ISource = 2mA 300 mV VOL Voltage swing from (V-) VS = 5V, (V-) = 0V, ISink = 2mA 300 mV ISC Short-circuit current VS = 5V, sourcing 50 mA VS = 5V, sinking 50 Power Supply ICC Supply current / Channel VS = 2.7V and 5V, no load, Output Low 200 250 uA ICC Supply current / Channel VS = 2.7V and 5V, no load, Output Low, TA = -40 to 125℃ 350 uA PSRR Power Supply Rejection Ratio VS = 2.7V to 5.5V, no load, TA = -40 to 125℃ 92 dB TLV3231-Q1, TLV3232-Q1 SNOSDK2 – JUNE 2024 www.ti.com
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5.6 Switching Characteristics
For VS = 5V, VCM = VS / 2; CL = 15pF at TA = 25°C (Unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPHL Propagation delay time, high to- low Midpoint of input to midpoint of output, VOD = 10mV 25 ns tPHL Propagation delay time, high to- low Midpoint of input to midpoint of output, VOD = 50mV 20 30 ns tPLH Propagation delay time, low-to high Midpoint of input to midpoint of output, VOD = 10mV 25 ns tPLH Propagation delay time, low-to high Midpoint of input to midpoint of output, VOD = 50mV 20 30 ns fTOGGLE Input toggle frequency VIN = 200mVPP Sine Wave, When output high reaches 90% of VCC - VEE or output low reaches 10% of VCC - VEE
75 MHz
tR Rise time Measured from 20% to 80% 2.5 ns tF Fall time Measured from 20% to 80% 2.5 ns tON Power-up time During power on, (V+) must exceed 2V for 4µs before the output reflects the input. 4 µs www.ti.com TLV3231-Q1, TLV3232-Q1 SNOSDK2 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TLV3231-Q1 TLV3232-Q1 ADVANCE INFORMATION
6 Detailed Description
6.1 Overview
The TLV323x-Q1 devices are micropower comparators with push-pull outputs.
6.2 Functional Block Diagrams
- * * Push-Pull Version Only Power Clamp V+ V+ ESD CLAMPS Figure 6-1. Block Diagram
6.3 Feature Description
The TLV323x-Q1 consumes only 200uA per channel with 20ns of propagation delay. The TLV323x -Q1 detects fast voltage and current transients while maintaining low power consumption. Likewise, an internal power-on reset circuit verifies that the output remains in a known state during power-up and power-down.
6.4 Device Functional Modes
6.4.1 Inputs
The inputs incorporate internal ESD protection circuits to (V+) and (V-). Voltages on the inputs are limited to 0.3V beyond the rails.. If the inputs are to be connected to a low impedance source, such as a power supply or buffered reference line, TI recommends adding a current-limiting resistor in series with the input to limit any transient currents should the clamps conduct. Limit the current to 10mA or less. One form of series resistance is any resistive input dividers or networks.
6.4.1.1 Unused Inputs
If a channel is not to be used, DO NOT tie the inputs together. Due to the high equivalent bandwidth and low offset voltage, tying the inputs directly together can cause high frequency oscillations as the device triggers on it's own internal wideband noise. Instead, the inputs should be tied to any available voltage that resides within the specified input voltage range and provides a minimum of 50mV differential voltage. For example, one input can be grounded and the other input connected to a reference voltage, or even (V+).
6.4.2 Internal Hysteresis
The device hysteresis transfer curve is shown below. This curve is a function of three components: V TH, VOS, and VHYST:
- VTH is the actual set voltage or threshold trip voltage.
- VOS is the internal offset voltage between VIN+ and VIN–. This voltage is added to VTH to form the actual trip point at which the comparator must respond to change output states.
- VHYST is the internal hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise. (1.55mV for the TLV323x-Q1 family) TLV3231-Q1, TLV3232-Q1 SNOSDK2 – JUNE 2024 www.ti.com
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VTH + VOS ± (VHYST / 2) VTH + VOS + (VHYST / 2)VTH + VOS Figure 6-2. Hysteresis Transfer Curve
6.4.3 Outputs
The TLV323x-Q1 features a push-pull output stage capable of both sinking and sourcing current. This allows driving loads such as LED's and MOSFET gates, as well as eliminating the need for a power-wasting external pull-up resistor. The push-pull output must never be connected to another output. Directly shorting the output to the supply rails ((V+) when output "low" or (V-) when output "High") can result in thermal runaway and eventual device destruction. If output shorts are possible, a series current limiting resistor is recommended to limit the power dissipation. Unused push-pull outputs should be left floating, and never tied to a supply, ground, or another output.
6.4.4 ESD Protection
The inputs and outputs incorporate internal ESD protection circuits to (V+) and (V-). Voltages on the inputs are limited to 0.3V beyond the rails. If the inputs are to be connected to a low impedance source, such as a power supply or buffered reference line, TI recommends adding a current-limiting resistor in series with the input to limit any transient currents should the clamps conduct. Limit the current to 10mA or less.
6.4.5 Power-On Reset (POR)
The TLV323x-Q1 devices have an internal Power-on-Reset (POR) circuit for known start-up or power-down conditions. While the power supply (V+) is ramping up or ramping down, the POR circuitry will be activated for up to 4us after the V POR of 2V is crossed. When the supply voltage is equal to or greater than the minimum supply voltage, and after the delay period, the comparator output reflects the state of the differential input (VID). For the TLV3231-Q1 devices, the output is held low during the POR period (ton). tON VOH/2 GND OUT VCC GND + 1.5VGND Figure 6-3. Power-On Reset Timing Diagram www.ti.com TLV3231-Q1, TLV3232-Q1 SNOSDK2 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TLV3231-Q1 TLV3232-Q1 ADVANCE INFORMATION
7 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
7.1 Application Information
7.1.1 Basic Comparator Definitions
7.1.1.1 Operation
The basic comparator compares the input voltage (V IN) on one input to a reference voltage (V REF) on the other input. In the Figure 7-1 example below, if V IN is less than V REF, the output voltage (V O) is logic low (V OL). If VIN is greater than V REF, the output voltage (V O) is at logic high (V OH). Table 7-1 summarizes the output conditions. The output logic can be inverted by simply swapping the input pins. Table 7-1. Output Conditions Inputs Condition Output IN+ > IN- HIGH (VOH) IN+ = IN- Indeterminate (chatters - see Hysteresis) IN+ < IN- LOW (VOL)
7.1.1.2 Propagation Delay
There is a delay between from when the input crosses the reference voltage and the output responds. This is called the Propagation Delay. Propagation delay can be different between high-to low and low-to-high input transitions. This is shown as t pLH and t pHL in Figure 7-1 and is measured from the mid-point of the input to the midpoint of the output. Figure 7-1. Comparator Timing Diagram TLV3231-Q1, TLV3232-Q1 SNOSDK2 – JUNE 2024 www.ti.com
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7.1.1.3 Overdrive Voltage
The overdrive voltage, VOD, is the amount of input voltage beyond the reference voltage (and not the total input peak-to-peak voltage). The overdrive voltage can influence the propagation delay (t p). The smaller the overdrive voltage, the longer the propagation delay, particularly when <100mV. If the fastest speeds are desired, it is recommended to apply the highest amount of overdrive possible. The risetime (tr) and falltime (tf) is the time from the 20% and 80% points of the output waveform.
7.1.2 Hysteresis
The basic comparator configuration may produce a noisy "chatter" output if the applied differential input voltage is near the comparator's offset voltage. This usually occurs when the input signal is moving very slowly across the switching threshold of the comparator. This problem can be prevented by adding external hysteresis to the comparator. Since the TLV3231-Q1 devices only have a minimal amount of internal hysteresis of 1.55mV, external hysteresis can be applied in the form of a positive feedback loop that adjusts the trip point of the comparator depending on its current output state. The hysteresis transfer curve is shown in Figure 7-2. This curve is a function of three components: V TH, VOS, and VHYST:
- VTH is the actual set voltage or threshold trip voltage.
- VOS is the internal offset voltage between VIN+ and VIN–. This voltage is added to VTH to form the actual trip point at which the comparator must respond to change output states.
- VHYST is the hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise. VTH + VOS ± (VHYST / 2) VTH + VOS + (VHYST / 2)VTH + VOS Figure 7-2. Hysteresis Transfer Curve For more information, please see Application Note SBOA219 "Comparator with and without hysteresis circuit".
7.1.2.1 Inverting Comparator With Hysteresis
The inverting comparator with hysteresis requires a three-resistor network that is referenced to the comparator supply voltage (VCC), as shown in Figure 7-3. 1 0 +VCC +5 V VIN 1 0 1 0 VO VA 5 V 0 V VA2 VA1 VO 1.67 V 3.33 V VIN Figure 7-3. TLV3231-Q1 in an Inverting Configuration With Hysteresis www.ti.com TLV3231-Q1, TLV3232-Q1 SNOSDK2 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TLV3231-Q1 TLV3232-Q1 ADVANCE INFORMATION
The equivalent resistor networks when the output is high and low are shown in Figure 7-3. VA1 VO High +VCC VA2 VO Low +VCC Figure 7-4. Inverting Configuration Resistor Equivalent Networks When VIN is less than V A, the output voltage is high (for simplicity, assume V O switches as high as V CC). The three network resistors can be represented as R1 || R3 in series with R2, as shown in Figure 7-4. Equation 1 below defines the high-to-low trip voltage (VA1). V = VA1 CC /c180 R2 (R1 || R3) + R2 (1) When VIN is greater than VA, the output voltage is low. In this case, the three network resistors can be presented as R2 || R3 in series with R1, as shown in Equation 2. Use Equation 2 to define the low to high trip voltage (VA2). V = VA2 CC /c180 R2 || R3 R1 + (R2 || R3) (2) Equation 3 defines the total hysteresis provided by the network. /c68 /c45V = V VA A1 A2 (3)
7.1.2.2 Non-Inverting Comparator With Hysteresis
A non-inverting comparator with hysteresis requires a two-resistor network and a voltage reference (V REF) at the inverting input, as shown in Figure 7-5, VREF 2.5 V 1 0 330 N VOVA 5 V 0 V VIN2 VIN1 VO 1.675 V 3.325 V VIN VIN Figure 7-5. TLV3231-Q1 in a Non-Inverting Configuration With Hysteresis The equivalent resistor networks when the output is high and low are shown in Figure 7-6. TLV3231-Q1, TLV3232-Q1 SNOSDK2 – JUNE 2024 www.ti.com
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VA = VREF VO High +VCC VA = VREF VO Low +VIN1 VIN2 Figure 7-6. Non-Inverting Configuration Resistor Networks When VIN is less than VREF,, the output is low. For the output to switch from low to high, V IN must rise above the VIN1 threshold. Use Equation 4 to calculate VIN1. V = R1IN1 /c180VREF + VREF (4) When VIN is greater than V REF, the output is high. For the comparator to switch back to a low state, V IN must drop below VIN2. Use Equation 5 to calculate VIN2. V =IN2 VREF CC(R1 + R2) V R1/c45 /c180 (5) The hysteresis of this circuit is the difference between VIN1 and VIN2, as shown in Equation 6. /c68V = VIN CC /c180 R1 (6) For more information, please see Application Notes SNOA997 " Inverting comparator with hysteresis circuit " and SBOA313 "Non-Inverting Comparator With Hysteresis Circuit".
7.2 Typical Applications
7.2.1 Low-Side Current Sensing
The figure below shows a simple low-side current sensing circuit using an amplifier and a high-speed comparator. The amplifier is used to amplify the voltage drop across the shunt resistor. When the voltage at the output reaches the critical over-current threshold, the comparator output will change stage. REF MCU TLV3231 INA Shunt Resistor Load Current 3.3V Figure 7-7. Current Sensing
7.2.1.1 Design Requirements
For this design, follow these design requirements:
- Alert (logic high output) when the amplifier output is greater than 1.1V www.ti.com TLV3231-Q1, TLV3232-Q1 SNOSDK2 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TLV3231-Q1 TLV3232-Q1 ADVANCE INFORMATION
- Alert signal is active high
- Operate from a 3.3V power supply
7.2.1.2 Detailed Design Procedure
Configure the circuit as shown in the figure above.
7.3 Power Supply Recommendations
Due to the fast output edges, it is critical to have bypass capacitors on the supply pin to prevent supply ringing and false triggers and oscillations. Bypass the supply directly at each device with a low ESR 0.1µF ceramic bypass capacitor directly between the (V+) pin and ground pins. Narrow peak currents will be drawn during the output transition time, particularly for the push-pull output device. These narrow pulses can cause un-bypassed supply lines and poor grounds to ring, possibly causing variation that can eat into the input voltage range and create an inaccurate comparison or even oscillations. The device may be powered from both "split" supplies ((V+) &(V-)), or "single" supplies ((V+) and GND), with GND applied to the (V-) pin. Input signals must stay within the recommended input range for either type. Note that with a "split" supply the output will now swing "low" (VOL) to (V-) potential and not GND.
7.4 Layout
7.4.1 Layout Guidelines
For accurate comparator applications it is important maintain a stable power supply with minimized noise and glitches. Output rise and fall times are in the tens of nanoseconds, and should be treated as high speed logic devices. The bypass capacitor should be as close to the supply pin as possible and connected to a solid ground plane, and preferably directly between the (V+) and GND pins. Minimize coupling between outputs and inputs to prevent output oscillations. Do not run output and input traces in parallel unless there is a (V+) or GND trace between output to reduce coupling. When series resistance is added to inputs, place resistor close to the device. A low value (<100ohms) resistor may also be added in series with the output to dampen any ringing or reflections on long, non-impedance controlled traces. For best edge shapes, controlled impedance traces with back-terminations should be used when routing long distances.
7.4.2 Layout Example
F IN1- IN1+ OUT2 IN2- IN2+ OUT1 V+ OK V+ or GND Be er Input Resistors Close to device Figure 7-8. Dual Layout Example TLV3231-Q1, TLV3232-Q1 SNOSDK2 – JUNE 2024 www.ti.com
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8 Device and Documentation Support
8.1 Documentation Support
8.1.1 Related Documentation
Analog Engineers Circuit Cookbook: Amplifiers (See Comparators section) - SLYY137 Precision Design, Comparator with Hysteresis Reference Design— TIDU020 Comparator with and without hysteresis circuit - SBOA219 Inverting comparator with hysteresis circuit - SNOA997 Non-Inverting Comparator With Hysteresis Circuit - SBOA313
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES June 2024 * Initial Release
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TLV3231-Q1, TLV3232-Q1 SNOSDK2 – JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TLV3231-Q1 TLV3232-Q1 ADVANCE INFORMATION
www.ti.com 20-Jun-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PLV3231QDCKRQ1 ACTIVE SC70 DCK 5 3000 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
www.ti.com PACKAGE OUTLINE C 0.22
0.08 TYP
0.15 2.4 1.8 2X 0.65 1.3
1.1 MAX
0.1
0.0 TYP
5X 0.33 0.15 NOTE 5
0.1 C A B
0.46
0.26 TYP
0 TYP
1.3 A 2.15 1.85 B1.4 1.1 (0.9) (0.15) (0.1) SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR 4214834/E 06/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-203. 4. Support pin may differ or may not be present. 5. Lead width does not comply with JEDEC. 6. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25mm per side 0.1 C SCALE 5.600 ALTERNATIVE PACKAGE SINGULATION VIEW
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
5X (0.95) 5X (0.4) (2.2) (1.3) 2X (0.65) (R0.05) TYP 4214834/E 06/2024 SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 7. Publication IPC-7351 may have alternate designs. 8. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (2.2) (1.3) 2X(0.65) 5X (0.95) 5X (0.4) (R0.05) TYP SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR 4214834/E 06/2024 NOTES: (continued) 9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 10. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:18X SYMM PKG 3 4
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