PLV1831QDCKRQ1

TLV1831-Q1_V01 TI | Alldatasheet

Document overview

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Technical content

TLV183x-Q1 and TLV184x-Q1 Family of 40V, High-Speed Comparators

1 Features

• Qualified for automotive applications
• AEC-Q100 qualified with the following results: – Device temperature grade 1: –40°C to 125°C ambient operating temperature range – Device HBM ESD classification level 2 – Device CDM ESD classification level C2B
• Wide supply range: 2.7V to 40V
• 65ns propagation delay
• Low supply current: 75µA per channel
• Rail-to-rail inputs
• Low input offset voltage: 500μV
• Power-on-reset (POR) provides a known startup condition
• Push-pull output option (TLV183x-Q1)
• Open-drain output option (TLV184x-Q1)
• Temperature range: -40°C to +125°C
• Functional Safety Capable – Documentation available to aid functional safety system design

2 Applications

• Telematics eCall
• Automotive head unit
• Instrument Cluster
• On-board (OBC) & wireless chargers

3 Description

The TLV183x -Q1 and TLV184x -Q1 are high-speed comparators with operating voltages up to 40V. The comparators offer rail-to-rail inputs with push-pull and open-drain output options. These features coupled with 65ns propagation delay make this family well- suited for high speed current sensing and voltage protection applications. All devices include a Power-On Reset (POR) feature that makes sure the output is in a known state until the minimum supply voltage has been reached. Once this voltage has been reached, the output responds to the inputs, thus preventing false outputs during system power-up and power-down. The TLV183x -Q1 comparators have a push-pull output stage, which are designed for applications where symmetry between rising and falling output responses is desired. The TLV184x -Q1 comparators have an open-drain output stage, making them appropriate for level transition. Device Information PART NUMBER PACKAGE (1) BODY SIZE (NOM) (2) TLV1831-Q1, TLV1841-Q1 SC-70 (5) 2.00mm × 2.00mm TLV1832-Q1, TLV1842-Q1 VSSOP (8) 3.00mm × 3.00mm TSSOP (8) 3.00mm × 4.40mm WSON (8) (Preview) 2.00mm × 2.00mm TLV1834-Q1, TLV1844-Q1 SOT-23 (14) (Preview) 4.20mm × 2.00mm WQFN (16) (Preview) 3.00mm × 3.00mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. OUT IN+ IN- Bias Power-On Reset V- V- Output Control * * * Push-Pull Version Only Power Clamp V+ V+ ESD CLAMPS Functional Block Diagram I n p u t O v e r d r i v e ( m V ) Propagation Delay, Low to High (ns) 1 0 2 0 3 0 4 0 5 0 7 0 1 0 0 2 0 0 3 0 0 5 0 0 7 0 0 1 , 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 - 4 0  C 2 5  C 8 5  C 1 2 5  C Propagation Delay, (Low to High) vs. Input Overdrive, 12V TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

Pin Configuration and Functions: TLV1834-Q1 and

10 Mechanical, Packaging, and Orderable

TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 www.ti.com

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Product Folder Links: TLV1831-Q1 TLV1841-Q1 TLV1832-Q1 TLV1842-Q1

4 Pin Configuration and Functions

Pin Configuration: TLV1831-Q1 and TLV1841-Q1 3 4 IN- IN+ OUT DBV, DCK Packages SOT-23-5, SC-70-5 Top View (Standard "north west" pinout) Table 4-1. Pin Functions: TLV1831-Q1 and TLV1841-Q1 PIN I/O DESCRIPTION NAME NO. OUT 1 O Output V- 2 - Negative supply voltage IN+ 3 I Non-inverting (+) input IN- 4 I Inverting (-) input V+ 5 - Positive supply voltage www.ti.com TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TLV1831-Q1 TLV1841-Q1 TLV1832-Q1 TLV1842-Q1

Pin Configurations: TLV1832-Q1 and TLV1842-Q1 OUT2 IN2± IN2+ OUT1 IN1± IN1+ DGK, PW Packages 8-Pin VSSOP, TSSOP Top View 1OUT1 8 V+ 2IN1± 7 OUT2 3IN1+ 6 IN2 ± 4V± 5 IN2+ Exposed Thermal Die Pad on Underside NOTE: Connect exposed thermal pad directly to V- pin. 8-Pad WSON With Exposed Thermal Pad, Top View Table 4-2. Pin Functions: TLV1832-Q1 and TLV1842-Q1 PIN I/O DESCRIPTION NAME NO. OUT1 1 O Output pin of the comparator 1 IN1– 2 I Inverting input pin of comparator 1 IN1+ 3 I Noninverting input pin of comparator 1 V- 4 — Negative supply voltage IN2+ 5 I Noninverting input pin of comparator 2 IN2– 6 I Inverting input pin of comparator 2 OUT2 7 O Output pin of the comparator 2 V+ 8 — Positive supply voltage TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 www.ti.com

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Product Folder Links: TLV1831-Q1 TLV1841-Q1 TLV1832-Q1 TLV1842-Q1

Pin Configuration and Functions: TLV1834-Q1 and TLV1844-Q1 IN1± IN1+ IN2± IN2+ VCC OUT1 OUT2 IN4± IN3+ IN3± GND OUT4 OUT3 IN4+ 14-Pin SOT-23 Top View

16 OUT15IN2±

1V+ 12 V ±

15 OUT26IN2+

2IN1± 11 IN4+

14 OUT37IN3±

13 OUT48IN3+

4IN1+ 9 IN4 ± Not to scale Thermal Pad NOTE: Connect exposed thermal pad directly to V- pin. 16-Pad WQFN With Exposed Thermal Pad Top View Table 4-3. Pin Functions: TLV1834-Q1 and TLV1844-Q1 PIN I/O DESCRIPTION NAME SOT-23 WQFN OUT2 1 15 O Output pin of the comparator 2 OUT1 2 16 O Output pin of the comparator 1 V+ 3 1 - Positive supply voltage IN1- 4 2 I Inverting input pin of the comparator 1 IN1+ 5 4 I Noninverting input pin of the comparator 1 IN2- 6 5 I Inverting input pin of the comparator 2 IN2+ 7 6 I Noninverting input pin of the comparator 2 IN3- 8 7 I Inverting input pin of the comparator 3 IN3+ 9 8 I Noninverting input pin of the comparator 3 IN4- 10 9 I Inverting input pin of the comparator 4 IN4+ 11 11 I Noninverting input pin of the comparator 4 V- 12 12 - Negative supply voltage OUT4 13 13 O Output pin of the comparator 4 OUT3 14 14 O Output pin of the comparator 3 NC - 3 - No internal connection - leave floating or GND NC - 10 - No internal connection - leave floating or GND Thermal Pad - PAD - Connect directly to V- pin www.ti.com TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TLV1831-Q1 TLV1841-Q1 TLV1832-Q1 TLV1842-Q1

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage: VS = (V+) – (V–) –0.3 42 V Input pins (IN+, IN–) from (V–)(2) –0.3 (V+) + 0.3 V Current into input pins (IN+, IN–) –10 10 mA Output (OUT) (Open-Drain) from (V–)(3) –0.3 42 V Output (OUT) (Push-Pull) from (V–) –0.3 (V+) + 0.3 V Output short circuit current(4) –10 10 mA Junction temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C (1) Operation outside the Absolute Maximum Ratings can cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Input terminals are diode-clamped to (V–) and (V+). Input signals that can swing more than 0.3V beyond the supply rails must be current-limited to 10mA or less. (3) Output (OUT) for open drain can be greater than (V+) and inputs (IN+, IN–) as long as the voltage is within the –0.3V to 42V range (4) Continuous output short circuits at elevated supply voltages can result in excessive heating and exceeding the maximum allowed junction temperature, leading to eventual device destruction.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM) per AEC Q100-002(1) ±2000 V Charged-device model (CDM), per AEC Q100-0111 ±1000 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

5.3 Thermal Information

THERMAL METRIC(1) TLV183x/4x UNITDCK (SC-70) DBV (SOT-23) PW (TSSOP) DSG (WSON) DGK (VSSOP)

5 PINS 5 PINS 8 PINS 8 PINS 8 PINS

RqJC(bot) Junction-to-case (bottom) thermal resistance - - - 62.0 - °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics report.

5.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Supply voltage: VS = (V+) – (V–) 2.7 40 V Input voltage range from (V–) –0.2 (V+) + 0.2 V Output voltage for open drain –0.2 40 V Ambient temperature, TA –40 125 °C TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 www.ti.com

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5.5 Electrical Characteristics

For VS (TOTAL SUPPLY VOLTAGE) = (V+) – (V–) = 12V, VCM = VS/2 at TA = 25°C (Unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage TA = –40°C to +125°C –3.0 3.0 mV dVIO/dT Input offset voltage drift TA = –40°C to +125°C ±1.2 µV/°C POWER SUPPLY IQ Quiescent current per comparator, TLV18x1 Only No Load, Output High TA = 25°C TLV1831, TLV1841 75 100 µA No Load, Output High TA = –40°C to +125°C TLV1831, TLV1841 105 µA No Load, Output Low TA = 25°C TLV1831, TLV1841 100 135 µA No Load, Output Low TA = –40°C to +125°C TLV1831, TLV1841 140 µA IQ Quiescent current per comparator No Load, Output High TA = 25°C 75 95 µA No Load, Output High TA = –40°C to +125°C 100 µA No Load, Output Low TA = 25°C 95 130 µA No Load, Output Low TA = –40°C to +125°C 135 µA VPOR 1.9 V INPUT BIAS CURRENT IB Input bias current (1) 500 pA IB Input bias current (1) (2) TA = –40°C to +125°C -5 5 nA IOS Input offset current 10 pA INPUT CAPACITANCE CID Input Capacitance, Differential 5 pF CIC Input Capacitance, Common Mode 5 pF INPUT COMMON MODE RANGE VCM-Range Common-mode voltage range VS = 2.7V to 40V OUTPUT VOL Voltage swing from (V–) ISINK = 4mA TA = –40°C to +125°C 400 mV VOH Voltage swing from (V+) (for Push-Pull only) ISOURCE = 4mA TA = –40°C to +125°C 400 mV ILKG Open-drain output leakage current VID = +0.1V, VPULLUP = (V+) TA = –40°C to +125°C 3 70 nA IOL Short-circuit current Sinking TA = –40°C to +125°C 30 mA IOH Short-circuit current Sourcing TA = –40°C to +125°C 30 mA (1) Please see figure for IBIAS vs VID performance curve (2) This parameter is assured by design and/or characterization and is not tested in production. www.ti.com TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TLV1831-Q1 TLV1841-Q1 TLV1832-Q1 TLV1842-Q1

5.6 Switching Characteristics

For VS (TOTAL SUPPLY VOLTAGE) = (V+) – (V–) = 12V, VCM = VS/2, CL = 15pF at TA = 25°C (Unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output TPD-HL Propagation delay time, high- to-low VOD = 10mV, VUD = 100mV VPU = 5V and RPU = 10k (open-drain output only) 110 ns TPD-HL Propagation delay time, high- to-low VOD = 100mV, VUD = 100mV VPU = 5V and RPU = 10k (open-drain output only) 65 ns TPD-LH Propagation delay time, low-to- high, push-pull output VOD = 10mV, VUD = 100mV 110 ns TPD-LH Propagation delay time, low-to- high, push-pull output VOD = 100mV, VUD = 100mV 65 ns TRISE Output Rise Time, 20% to 80%, push-pull output VOD = 100mV, VUD = 100mV 5 ns TFALL Output Fall Time, 80% to 20% VOD = 100mV, VUD = 100mV 5 ns FTOGGLE Toggle Frequency VID = 200mV 7.5 MHz POWER ON TIME PON Power on-time 80 µs TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 www.ti.com

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Product Folder Links: TLV1831-Q1 TLV1841-Q1 TLV1832-Q1 TLV1842-Q1

5.7 Typical Characteristics

At TA = 25°C, VS = 12V, VCM = VS/2V, CL = 15pF, Input Overdrive = Input Underdrive =100mV, RPU = 10kΩ, unless otherwise noted. T e m p e r a t u r e (  C ) Input Offset Voltage (mV) - 4 0 - 2 5 - 1 0 5 2 0 3 5 5 0 6 5 8 0 9 5 1 1 0 1 2 5 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 F o r 5 u n i t s Figure 5-1. Offset vs. Temperature I n p u t C o m m o n - M o d e V o l t a g e ( V ) Input Offset Voltage (mV) - 5 - 4 - 3 - 2 - 1 F o r 5 u n i t s Figure 5-2. Offset vs. Common-Mode, 3.3V I n p u t C o m m o n - M o d e V o l t a g e ( V ) Input Offset Voltage (mV) - 5 - 4 - 3 - 2 - 1 F o r 5 u n i t s Figure 5-3. Offset Voltage vs. Common-Mode, 12V I n p u t C o m m o n - M o d e V o l t a g e ( V ) Input Offset Voltage (mV) - 5 - 4 - 3 - 2 - 1 F o r 5 u n i t s Figure 5-4. Offset Voltage vs. Common-Mode, 40V Figure 5-5. Bias Current vs. Temperature, 3.3V T e m p e r a t u r e (  C ) Input Bias Current (pA) - 4 0 - 2 5 - 1 0 5 2 0 3 5 5 0 6 5 8 0 9 5 1 1 0 1 2 5 - 2 0 - 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 V C M = V S / 2 Figure 5-6. Bias Current vs. Temperature, 40V www.ti.com TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TLV1831-Q1 TLV1841-Q1 TLV1832-Q1 TLV1842-Q1

5.7 Typical Characteristics (continued)

At TA = 25°C, VS = 12V, VCM = VS/2V, CL = 15pF, Input Overdrive = Input Underdrive =100mV, RPU = 10kΩ, unless otherwise noted. O u t p u t S o u r c i n g C u r r e n t ( A ) 1 0 0  1 m 1 0 m 1 m 1 0 m 1 0 0 m 1 0 1 0 0 1 0 0  Output Voltage to V+ (V) 1 0 0 m - 4 0  C 2 5  C 8 5  C 1 2 5  C Figure 5-7. Output Voltage vs. Sourcing Current, 3.3V, Push-Pull only O u t p u t S i n k i n g C u r r e n t ( A ) 1 0 0  1 m 1 0 m 1 m 1 0 m 1 0 0 m 1 0 1 0 0 1 0 0  Output Voltage to V- (V) 1 0 0 m - 4 0  C 2 5  C 8 5  C 1 2 5  C Figure 5-8. Output Voltage vs. Sinking Current, 3.3V O u t p u t S o u r c i n g C u r r e n t ( A ) 1 0 0  1 m 1 0 m 1 m 1 0 m 1 0 0 m 1 0 1 0 0 1 0 0  Output Voltage to V+ (V) 1 0 0 m - 4 0  C 2 5  C 8 5  C 1 2 5  C Figure 5-9. Output Voltage vs. Sourcing Current, 12V, Push-Pull only O u t p u t S i n k i n g C u r r e n t ( A ) 1 0 0  1 m 1 0 m 1 m 1 0 m 1 0 0 m 1 0 1 0 0 1 0 0  Output Voltage to V- (V) 1 0 0 m - 4 0  C 2 5  C 8 5  C 1 2 5  C Figure 5-10. Output Voltage vs. Sinking Current, 12V O u t p u t S o u r c i n g C u r r e n t ( A ) 1 0 0  1 m 1 0 m 1 m 1 0 m 1 0 0 m 1 0 1 0 0 1 0 0  Output Voltage to V+ (V) 1 0 0 m - 4 0  C 2 5  C 8 5  C 1 2 5  C Figure 5-11. Output Voltage vs. Sourcing Current, 40V, Push- Pull only O u t p u t S i n k i n g C u r r e n t ( A ) 1 0 0  1 m 1 0 m 1 m 1 0 m 1 0 0 m 1 0 1 0 0 1 0 0  Output Voltage to V- (V) 1 0 0 m - 4 0  C 2 5  C 8 5  C 1 2 5  C Figure 5-12. Output Voltage vs. Sinking Current, 40V TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 www.ti.com

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Product Folder Links: TLV1831-Q1 TLV1841-Q1 TLV1832-Q1 TLV1842-Q1

At TA = 25°C, VS = 12V, VCM = VS/2V, CL = 15pF, Input Overdrive = Input Underdrive =100mV, RPU = 10kΩ, unless otherwise noted. S u p p l y V o l t a g e ( V ) Supply Current, per Channel (A) 0 4 8 1 2 1 6 2 0 2 4 2 8 3 2 3 6 4 0 8 0 8 2 8 4 8 6 8 8 9 0 9 2 9 4 9 6 9 8 1 0 0 - 4 0  C 2 5  C 8 5  C 1 2 5  C Figure 5-13. Supply Current vs. Supply Voltage, Output Low, No Load S u p p l y V o l t a g e ( V ) Supply Current, per Channel (A) 0 4 8 1 2 1 6 2 0 2 4 2 8 3 2 3 6 4 0 6 0 6 2 6 4 6 6 6 8 7 0 7 2 7 4 7 6 7 8 8 0 - 4 0  C 2 5  C 8 5  C 1 2 5  C Figure 5-14. Supply Current vs. Supply Voltage, Output High, No Load I n p u t C o m m o n - M o d e V o l t a g e ( V ) Propagation Delay (ns) 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 T P H L T P L H Figure 5-15. Propagation Delay vs. Common-Mode, 3.3V I n p u t C o m m o n - M o d e V o l t a g e ( V ) Propagation Delay (ns) 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 T P H L T P L H Figure 5-16. Propagation Delay vs. Common-Mode, 12V I n p u t C o m m o n - M o d e V o l t a g e ( V ) Propagation Delay (ns) 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 T P H L T P L H Figure 5-17. Propagation Delay vs. Common-Mode, 40V C a p a c i t i v e L o a d ( p F ) Rise/Fall Time (ns) 1 0 2 0 3 0 4 0 5 0 7 0 1 0 0 2 0 0 3 0 0 5 0 0 7 0 0 1 , 0 0 0 1 0 2 0 3 0 5 0 7 0 1 0 0 2 0 0 R i s e T i m e F a l l T i m e Figure 5-18. Rise/Fall Time vs. Capacitive Load, 12V www.ti.com TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TLV1831-Q1 TLV1841-Q1 TLV1832-Q1 TLV1842-Q1

At TA = 25°C, VS = 12V, VCM = VS/2V, CL = 15pF, Input Overdrive = Input Underdrive =100mV, RPU = 10kΩ, unless otherwise noted. I n p u t O v e r d r i v e ( m V ) Propagation Delay, Low to High (ns) 1 0 2 0 3 0 4 0 5 0 7 0 1 0 0 2 0 0 3 0 0 5 0 0 7 0 0 1 , 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 - 4 0  C 2 5  C 8 5  C 1 2 5  C Figure 5-19. Propagation Delay, (Low to High) vs. Input Overdrive, 3.3V I n p u t O v e r d r i v e ( m V ) Propagation Delay, High to Low (ns) 1 0 2 0 3 0 4 0 5 0 7 0 1 0 0 2 0 0 3 0 0 5 0 0 7 0 0 1 , 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 - 4 0  C 2 5  C 8 5  C 1 2 5  C Figure 5-20. Propagation Delay, (High to Low) vs. Input Overdrive, 3.3V I n p u t O v e r d r i v e ( m V ) Propagation Delay, Low to High (ns) 1 0 2 0 3 0 4 0 5 0 7 0 1 0 0 2 0 0 3 0 0 5 0 0 7 0 0 1 , 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 - 4 0  C 2 5  C 8 5  C 1 2 5  C Figure 5-21. Propagation Delay, (Low to High) vs. Input Overdrive, 12V I n p u t O v e r d r i v e ( m V ) Propagation Delay, High to Low (ns) 1 0 2 0 3 0 4 0 5 0 7 0 1 0 0 2 0 0 3 0 0 5 0 0 7 0 0 1 , 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 - 4 0  C 2 5  C 8 5  C 1 2 5  C Figure 5-22. Propagation Delay, (High to Low) vs. Input Overdrive, 12V I n p u t O v e r d r i v e ( m V ) Propagation Delay, Low to High (ns) 1 0 2 0 3 0 4 0 5 0 7 0 1 0 0 2 0 0 3 0 0 5 0 0 7 0 0 1 , 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 - 4 0  C 2 5  C 8 5  C 1 2 5  C Figure 5-23. Propagation Delay, (Low to High) vs. Input Overdrive, 40V I n p u t O v e r d r i v e ( m V ) Propagation Delay, High to Low (ns) 1 0 2 0 3 0 4 0 5 0 7 0 1 0 0 2 0 0 3 0 0 5 0 0 7 0 0 1 , 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 - 4 0  C 2 5  C 8 5  C 1 2 5  C Figure 5-24. Propagation Delay, (High to Low) vs. Input Overdrive, 40V TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 www.ti.com

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At TA = 25°C, VS = 12V, VCM = VS/2V, CL = 15pF, Input Overdrive = Input Underdrive =100mV, RPU = 10kΩ, unless otherwise noted. I n p u t U n d e r d r i v e ( m V ) Propagation Delay, Low to High (ns) 1 0 2 0 3 0 4 0 5 0 7 0 1 0 0 2 0 0 3 0 0 5 0 0 7 0 0 1 , 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 - 4 0  C 2 5  C 8 5  C 1 2 5  C Figure 5-25. Propagation Delay, (Low to High) vs. Input Underdrive, 3.3V I n p u t U n d e r d r i v e ( m V ) Propagation Delay, High to Low (ns) 1 0 2 0 3 0 4 0 5 0 7 0 1 0 0 2 0 0 3 0 0 5 0 0 7 0 0 1 , 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 - 4 0  C 2 5  C 8 5  C 1 2 5  C Figure 5-26. Propagation Delay, (High to Low) vs. Input Underdrive, 3.3V I n p u t U n d e r d r i v e ( m V ) Propagation Delay, Low to High (ns) 1 0 2 0 3 0 4 0 5 0 7 0 1 0 0 2 0 0 3 0 0 5 0 0 7 0 0 1 , 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 - 4 0  C 2 5  C 8 5  C 1 2 5  C Figure 5-27. Propagation Delay, (Low to High) vs. Input Underdrive, 12V I n p u t U n d e r d r i v e ( m V ) Propagation Delay, High to Low (ns) 1 0 2 0 3 0 4 0 5 0 7 0 1 0 0 2 0 0 3 0 0 5 0 0 7 0 0 1 , 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 - 4 0  C 2 5  C 8 5  C 1 2 5  C Figure 5-28. Propagation Delay, (High to Low) vs. Input Underdrive, 12V I n p u t U n d e r d r i v e ( m V ) Propagation Delay, Low to High (ns) 1 0 2 0 3 0 4 0 5 0 7 0 1 0 0 2 0 0 3 0 0 5 0 0 7 0 0 1 , 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 - 4 0  C 2 5  C 8 5  C 1 2 5  C Figure 5-29. Propagation Delay, (Low to High) vs. Input Underdrive, 40V I n p u t U n d e r d r i v e ( m V ) Propagation Delay, Hight to Low (ns) 1 0 2 0 3 0 4 0 5 0 7 0 1 0 0 2 0 0 3 0 0 5 0 0 7 0 0 1 , 0 0 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 - 4 0  C 2 5  C 8 5  C 1 2 5  C Figure 5-30. Propagation Delay, (High to Low) vs. Input Underdrive, 40V www.ti.com TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TLV1831-Q1 TLV1841-Q1 TLV1832-Q1 TLV1842-Q1

6 Detailed Description

6.1 Overview

The TLV183x-Q1 and TLV184x -Q1 devices are 40V high-speed comparators with push-pull and open-drain output options. Operating down to 2.7V while only consuming only 75µA per channel, the TLV183x -Q1 and TLV184x-Q1 are designed for voltage and current sensing applications in high voltage industrial and automotive systems. An internal power-on reset circuit makes sure that the output remains in a known state during power-up and power-down.

6.2 Functional Block Diagrams

• * * Push-Pull Version Only Power Clamp V+ V+ ESD CLAMPS Figure 6-1. Block Diagram

6.3 Feature Description

The TLV183x-Q1 (push-pull output) and TLV184x -Q1 (open-drain output) devices are high speed comparators with a typical propagation delay of 65ns and are capable of operating at voltages up to 40V. These comparators are well-suited for high-voltage systems where it is essential to have short-circuit current and over voltage protection for its internal components. These comparators also feature a rail-to-rail input stage capable of operating up to 200mV beyond the power supply rails combined with a maximum 2.5mV input offset and Power-on Reset (POR) for known start-up conditions.

6.4 Device Functional Modes

6.4.1 Inputs

6.4.1.1 Rail-to-Rail Input

The input voltage range extends from 200mV below (V-) to 200mV above (V+), maximizing input dynamic range. The input stage has ESD clamps to the (V+) supply line and therefore the input voltages must not exceed the supply voltages by more than 200mV. Do not apply signals to the rail to rail inputs with no supply voltage. To avoid damaging the inputs when exceeding the recommended input voltage range, an external resistor must be used to limit the current to less than 1mA. Likewise, unlike high-speed amplifiers, the comparator inputs do not have clamping diodes between them. This allows for applications where the input differential voltage can match the supply voltage (V+). However, when the input differential voltage increases to 2V, bias current increases to the nA range occur. This is a result of internal circuitry intended to minimize propagation delay increases due to large input underdrive amplitudes. TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 www.ti.com

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6.4.1.2 Unused Inputs

If a channel is not to be used, DO NOT tie the inputs together. Due to the high equivalent bandwidth and low offset voltage, tying the inputs directly together can cause high frequency oscillations as the device triggers on it's own internal wideband noise. Instead, the inputs must be tied to any available voltage that resides within the specified input voltage range and provides a minimum of 50mV differential voltage. For example, one input can be grounded and the other input connected to a reference voltage, or even (V+).

6.4.2 Outputs

6.4.2.1 TLV183x-Q1 Push-Pull Output

The TLV183x-Q1 features a push-pull output stage capable of both sinking and sourcing current. This allows driving loads such as LED's and MOSFET gates, as well as eliminating the need for an external pull-up resistor. The push-pull output must never be connected to another output. Directly shorting the output to the supply rails ((V+) when output "low" or (V-) when output "High") can result in thermal runaway and eventual device destruction at high (>12V) supply voltages. If output shorts are possible, a series current limiting resistor is recommended to limit the power dissipation. Unused push-pull outputs must be left floating, and never tied to a supply, ground, or another output.

6.4.2.2 TLV184x-Q1 Open-Drain Output

The TLV184x -Q1 features an open-drain (also commonly called open collector) sinking-only output stage enabling the output logic levels to be pulled up to an external voltage up to 40V, independent of the comparator supply voltage (V+). The open-drain output also allows logical OR'ing of multiple open drain outputs and logic level translation. TI recommends setting the pull-up resistor current to between 100uA and 1mA to optimize V OL logic levels. Lower pull-up resistor values help increase the rising edge risetime, but at the expense of increasing VOL and higher power dissipation. The risetime is dependent on the time constant of the total pull-up resistance and total load capacitance. Large value pull-up resistors (>1M Ω) create an exponential rising edge due to the output RC time constant and increase the risetime. Directly shorting the output to (V+) can result in thermal runaway and eventual device destruction at high (>12V) pull-up voltages. If output shorts are possible, a series current limitng resistor is recommended to limit the power dissipation. Unused open drain outputs must be left floating, or can be tied to the (V-) pin if floating pins are not desired.

6.4.3 ESD Protection

6.4.3.1 Inputs

The rail-to-rail input does have an ESD clamp to (V+) and (V-) and therefore the input voltage must not exceed the supply voltages by more than 200mV. Do not apply signals to the rail to rail inputs with no supply voltage. To avoid damaging the inputs when exceeding the recommended input voltage range, an external resistor must be used to limit the current to less than 1mA. Similarly, if the inputs are to be connected to a low impedance source, such as a power supply or buffered reference line, add a current-limiting resistor in series with the input to limit any transient currents if the clamps conduct. Limit the current to 1mA or less. This series resistance can be part of any resistive input dividers or networks.

6.4.3.2 Outputs

The TLV183x-Q1 push-pull output ESD protection contains a conventional ESD clamp between the output and (V+), and a ESD clamp between the output and (V-). The output must not exceed the supply rails by more than 200mV. The TLV184x-Q1 open-drain output ESD protection consists of an ESD clamping circuit to (V-) only to allow the output to be pulled above (V+) to a maximum of 40V. There is no ESD clamp diode between the output and (V+) on the open-drain output. www.ti.com TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TLV1831-Q1 TLV1841-Q1 TLV1832-Q1 TLV1842-Q1

6.4.4 Power-On Reset (POR)

The TLV183x-Q1 and TLV184x -Q1 devices have an internal Power-on-Reset (POR) circuit for known start-up or power-down conditions. While the power supply (V+) is ramping up or ramping down, the POR circuitry is activated for up to 80µs after the V POR of 1.9V is crossed. When the supply voltage is equal to or greater than the minimum supply voltage, and after the delay period, the comparator output reflects the state of the differential input (VID). For both TLV183x-Q1 and TLV184x-Q1 devices, the POR circuit keeps the output high impedance (Hi-Z) during the POR period (Pon). Power On Reset Time (PON) VOH / 2 OUT V+ VPOR Determined by input conditions“High-Z” - Neither sinking or sourcing Figure 6-2. Power-On Reset Timing Diagram TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 www.ti.com

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7 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

7.1 Application Information

7.1.1 Basic Comparator Definitions

7.1.1.1 Operation

The basic comparator compares the input voltage (V IN) on one input to a reference voltage (V REF) on the other input. In the Figure 7-1 example below, if V IN is less than V REF, the output voltage (V O) is logic low (V OL). If VIN is greater than V REF, the output voltage (V O) is at logic high (V OH). Table 7-1 summarizes the output conditions. The output logic can be inverted by simply swapping the input pins. Table 7-1. Output Conditions Inputs Condition Output IN+ > IN- HIGH (VOH) IN+ = IN- Indeterminate (chatters - see Hysteresis) IN+ < IN- LOW (VOL)

7.1.1.2 Propagation Delay

There is a delay between from when the input crosses the reference voltage and the output responds. This is called the Propagation Delay. Propagation delay can be different between high-to low and low-to-high input transitions. This is shown as t pLH and t pHL in Figure 7-1 and is measured from the mid-point of the input to the midpoint of the output. Figure 7-1. Comparator Timing Diagram www.ti.com TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TLV1831-Q1 TLV1841-Q1 TLV1832-Q1 TLV1842-Q1

7.1.1.3 Overdrive Voltage

The overdrive voltage, VOD, is the amount of input voltage beyond the reference voltage (and not the total input peak-to-peak voltage). The overdrive voltage is 100mV as shown in the Figure 7-1 example. The overdrive voltage can influence the propagation delay (t p). The smaller the overdrive voltage, the longer the propagation delay, particularly when <100mV. If the fastest speeds are desired, TI recommends applying the highest amount of overdrive possible. The risetime (tr) and falltime (tf) is the time from the 20% and 80% points of the output waveform.

7.1.2 Hysteresis

The basic comparator configuration can produce a noisy "chatter" output if the applied differential input voltage is near the comparator's offset voltage. This usually occurs when the input signal is moving very slowly across the switching threshold of the comparator. This problem can be prevented by adding external hysteresis to the comparator. External hysteresis can be applied in the form of a positive feedback loop that adjusts the trip point of the comparator depending on the current output state. The hysteresis transfer curve is shown in Figure 7-2. This curve is a function of three components: V TH, VOS, and VHYST:

• VTH is the actual set voltage or threshold trip voltage.
• VOS is the internal offset voltage between VIN+ and VIN–. This voltage is added to VTH to form the actual trip point at which the comparator must respond to change output states.
• VHYST is the hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise. VTH + VOS ± (VHYST / 2) VTH + VOS + (VHYST / 2)VTH + VOS Figure 7-2. Hysteresis Transfer Curve For more information, please see Application Note SBOA219 "Comparator with and without hysteresis circuit".

7.1.2.1 Inverting Comparator With Hysteresis

The inverting comparator with hysteresis requires a three-resistor network that is referenced to the comparator supply voltage (VCC), as shown in Figure 7-3. 1 0Ÿ +VCC +5 V VIN 1 0Ÿ 1 0Ÿ VO VA 5 V 0 V VA2 VA1 VO 1.67 V 3.33 V VIN Figure 7-3. TLV183x-Q1 in an Inverting Configuration With Hysteresis TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 www.ti.com

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The equivalent resistor networks when the output is high and low are shown in Figure 7-3. VA1 VO High +VCC VA2 VO Low +VCC Figure 7-4. Inverting Configuration Resistor Equivalent Networks When VIN is less than V A, the output voltage is high (for simplicity, assume V O switches as high as V CC). The three network resistors can be represented as R1 || R3 in series with R2, as shown in Figure 7-4. Equation 1 below defines the high-to-low trip voltage (VA1). V = VA1 CC /c180 R2 (R1 || R3) + R2 (1) When VIN is greater than VA, the output voltage is low. In this case, the three network resistors can be presented as R2 || R3 in series with R1, as shown in Equation 2. Use Equation 2 to define the low to high trip voltage (VA2). V = VA2 CC /c180 R2 || R3 R1 + (R2 || R3) (2) Equation 3 defines the total hysteresis provided by the network. /c68 /c45V = V VA A1 A2 (3)

7.1.2.2 Non-Inverting Comparator With Hysteresis

A non-inverting comparator with hysteresis requires a two-resistor network and a voltage reference (V REF) at the inverting input, as shown in Figure 7-5, VREF 2.5 V 1 0Ÿ 330 NŸ VOVA 5 V 0 V VIN2 VIN1 VO 1.675 V 3.325 V VIN VIN Figure 7-5. TLV183x-Q1 in a Non-Inverting Configuration With Hysteresis The equivalent resistor networks when the output is high and low are shown in Figure 7-6. www.ti.com TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TLV1831-Q1 TLV1841-Q1 TLV1832-Q1 TLV1842-Q1

VA = VREF VO High +VCC VA = VREF VO Low +VIN1 VIN2 Figure 7-6. Non-Inverting Configuration Resistor Networks When VIN is less than VREF,, the output is low. For the output to switch from low to high, V IN must rise above the VIN1 threshold. Use Equation 4 to calculate VIN1. V = R1IN1 /c180VREF + VREF (4) When VIN is greater than V REF, the output is high. For the comparator to switch back to a low state, V IN must drop below VIN2. Use Equation 5 to calculate VIN2. V =IN2 VREF CC(R1 + R2) V R1/c45 /c180 (5) The hysteresis of this circuit is the difference between VIN1 and VIN2, as shown in Equation 6. /c68V = VIN CC /c180 R1 (6) For more information, please see Application Notes SNOA997 " Inverting comparator with hysteresis circuit " and SBOA313 "Non-Inverting Comparator With Hysteresis Circuit".

7.1.2.3 Inverting and Non-Inverting Hysteresis using Open-Drain Output

It is also possible to use an open drain output device, such as the TLV184x -Q1, but the output pull-up resistor must also be taken into account in the calculations. The pull-up resistor is seen in series with the feedback resistor when the output is high. Thus, the feedback resistor is actually seen as R2 + R PULLUP. TI recommends that the pull-up resistor be at least 10 times less than the feedback resistor value.

7.2 Typical Applications

7.2.1 Window Comparator

Window comparators are commonly used to detect undervoltage and overvoltage conditions. Figure 7-7 shows a simple window comparator circuit. Window comparators require open drain outputs (TLV184x-Q1 if the outputs are directly connected together. TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 www.ti.com

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3.3 V Sensor 10 M RPU UV_OV VTH- VTH+ VIN Low when VIN < VTH- Output high when VIN is within window 10 M 10 M Low when VIN > VTH+ Figure 7-7. Window Comparator

7.2.1.1 Design Requirements

For this design, follow these design requirements:

• Alert (logic low output) when an input signal is less than 1.1V
• Alert (logic low output) when an input signal is greater than 2.2V
• Alert signal is active low
• Operate from a 3.3V power supply

7.2.1.2 Detailed Design Procedure

Configure the circuit as shown in Figure 7-7. Connect V+ to a 3.3V power supply and V EE to ground. Make R1, R2 and R3 each 10M Ω resistors. These three resistors are used to create the positive and negative thresholds for the window comparator (VTH+ and VTH–). With each resistor being equal, V TH+ is 2.2V and V TH- is 1.1V. Large resistor values such as 10M Ω are used to minimize power consumption. The resistor values can be recalculated to provide the desired trip point values. The sensor output voltage is applied to the inverting and noninverting inputs of the two comparators. Using two open-drain output comparators allows the two comparator outputs to be Wire-OR'ed together. The respective comparator outputs will be low when the sensor is less than 1.1V or greater than 2.2V. The respective comparator outputs will be high when the sensor is in the range of 1.1V to 2.2V (within the "window"), as shown in Figure 7-8.

7.2.1.3 Application Curve

VTH+ = 2.2 V VTH± = 1.1 V VIN OUT Figure 7-8. Window Comparator Results For more information, please see Application note SBOA221 "Window comparator circuit". www.ti.com TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TLV1831-Q1 TLV1841-Q1 TLV1832-Q1 TLV1842-Q1

7.2.2 Square Wave Oscillator

Square-wave oscillator can be used as low cost timing reference or system supervisory clock source. A push- pull output (TLV183x) is recommended for best symmetry. 100 pF 100 kŸ VCC 100 kŸ OUT VA VC 100 kŸ 100 kŸ Figure 7-9. Square-Wave Oscillator

7.2.2.1 Design Requirements

The square-wave period is determined by the RC time constant of the capacitor C1 and resistor R4. The maximum frequency is limited by propagation delay of the device and the capacitance load at the output. The low input bias current allows a lower capacitor value and larger resistor value combination for a given oscillator frequency, which can help to reduce BOM cost and board space. TI recommends that R4 be over several kilo-ohms to minimize loading of the output.

7.2.2.2 Detailed Design Procedure

The oscillation frequency is determined by the resistor and capacitor values. The following calculation provides details of the steps. Figure 7-10. Square-Wave Oscillator Timing Thresholds First consider the output of Figure Square-Wave Oscillator as high, which indicates the inverted input VC is lower than the noninverting input (V A). This causes the C 1 to be charged through R 4, and the voltage V C increases until it is equal to the noninverting input. The value of VA at the point is calculated below. CC 2 2 1 3 V R V R R I IR u (7) if R1 = R2= R3, then VA1 = 2VCC/3 At this time the comparator output trips pulling down the output to the negative rail. The value of VAat this point is calculated below. TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 www.ti.com

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V ( R I I R )V R + R I I R (8) if R1 = R2 = R3, then VA2 = VCC/3 The C1 now discharges though the R 4, and the voltage V CC decreases until it reaches V A2. At this point, the output switches back to the starting state. The oscillation period equals to the time duration from for C 1 from 2VCC/3 to V CC / 3 then back to 2V CC/3, which is given by R 4C1 × ln 2 for each trip. Therefore, the total time duration is calculated as 2 R4C1 × ln 2. The oscillation frequency can be obtained below. f 1/ 2 R4 C1 In2 u u (9)

7.2.2.3 Application Performance Plots

The Square-Wave Oscillator Output Waveform shows the simulated results of an oscillator using the following component values:

• R1 = R2 = R3 = R4 = 10kΩ
• C1 =100pF, CL = 20pF
• V+ = 5V, V– = GND
• Cstray (not shown) from VA TO GND = 10pF Figure 7-11. Square-Wave Oscillator Output Waveform

7.3 Power Supply Recommendations

Due to fast output edges, bypass capacitors are critical on the supply pin to prevent supply ringing and false triggers and oscillations. Bypass the supply directly at each device with a low ESR 0.1µF ceramic bypass capacitor directly between the (V+) pin and ground pins. Narrow peak currents are drawn during the output transition time, particularly for the push-pull output device. These narrow pulses can cause un-bypassed supply lines and poor grounds to ring, possibly causing variation that can impact the input voltage range and create an inaccurate comparison or even oscillations. The device can be powered from both "split" supplies ((V+) & (V-)), or "single" supplies ((V+) and GND), with GND applied to the (V-) pin. Input signals must stay within the recommended input range for either type. Note that with a "split" supply the output now swings "low" (VOL) to (V-) potential and not GND. www.ti.com TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TLV1831-Q1 TLV1841-Q1 TLV1832-Q1 TLV1842-Q1

7.4 Layout

7.4.1 Layout Guidelines

For accurate comparator applications it is important to maintain a stable power supply with minimized noise and glitches. Output rise and fall times are in the tens of nanoseconds, and must be treated as high speed logic devices. The bypass capacitor must be as close to the supply pin as possible and connected to a solid ground plane, and preferably directly between the (V+) and GND pins. Minimize coupling between outputs and inputs to prevent output oscillations. As shown in the figure below, it is "OK" to run input and output traces in parallel as long as there is a (V+) or GND trace between output to reduce coupling. A "better" way to reduce coupling is to have the traces ran further away from each other. When series resistance is added to inputs, place the resistor close to the device. A low value (<100 ohms) resistor can also be added in series with the output to dampen any ringing or reflections on long, non-impedance controlled traces. For best edge shapes, controlled impedance traces with back-terminations must be used when routing long distances.

7.4.2 Layout Example

F IN1- IN1+ OUT2 IN2- IN2+ OUT1 V+ OK V+ or GND Be er Input Resistors Close to device Figure 7-12. Dual Layout Example TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 www.ti.com

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8 Device and Documentation Support

8.1 Documentation Support

8.1.1 Related Documentation

Analog Engineers Circuit Cookbook: Amplifiers (See Comparators section) - SLYY137 Precision Design, Comparator with Hysteresis Reference Design— TIDU020 Window comparator circuit - SBOA221 Reference Design, Window Comparator Reference Design— TIPD178 Comparator with and without hysteresis circuit - SBOA219 Inverting comparator with hysteresis circuit - SNOA997 Non-Inverting Comparator With Hysteresis Circuit - SBOA313 A Quad of Independently Func Comparators - SNOA654

8.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

8.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

8.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

8.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (September 2024) to Revision A (October 2024) Page www.ti.com TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TLV1831-Q1 TLV1841-Q1 TLV1832-Q1 TLV1842-Q1

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TLV1831-Q1, TLV1841-Q1, TLV1832-Q1, TLV1842-Q1 SNOSDG6A – SEPTEMBER 2024 – REVISED DECEMBER 2024 www.ti.com

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www.ti.com 21-Dec-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PLV1831QDCKRQ1 ACTIVE SC70 DCK 5 3000 TBD Call TI Call TI -40 to 125 Samples TLV1832QPWRQ1 ACTIVE TSSOP PW 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TL32Q Samples TLV1842QPWRQ1 ACTIVE TSSOP PW 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T1842Q Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

www.ti.com 21-Dec-2024 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV1831-Q1, TLV1832-Q1, TLV1842-Q1 :

• Catalog : TLV1831 , TLV1832 , TLV1842 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product Addendum-Page 2

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.15 2.4 1.8 2X 0.65 1.3

1.1 MAX

0.1

0.0 TYP

5X 0.33 0.15 NOTE 5

0.1 C A B

0.46

0.26 TYP

0 TYP

1.3 4X 0 -12 4X 4 -14 A 2.15 1.85 B1.4 1.1 (0.9) (0.15) (0.1) SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR 4214834/F 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-203. 4. Support pin may differ or may not be present. 5. Lead width does not comply with JEDEC. 6. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25mm per side 0.1 C SCALE 5.600

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (0.95) 5X (0.4) (2.2) (1.3) 2X (0.65) (R0.05) TYP 4214834/F 08/2024 SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 7. Publication IPC-7351 may have alternate designs. 8. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.2) (1.3) 2X(0.65) 5X (0.95) 5X (0.4) (R0.05) TYP SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR 4214834/F 08/2024 NOTES: (continued) 9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 10. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:18X SYMM PKG 3 4

www.ti.com PACKAGE OUTLINE C TYP6.6 6.2

1.2 MAX

6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT (5.8)

0.05 MAX

0.05 MIN

8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

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