Microcontroller

PLSP0010JA-A

Renesas Technology Corp

RENESAS MCU Rev.1.30 May 19, 2025

Manufacturer: Renesas Technology Corp

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RL78G16 RENESAS | Alldatasheet

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R01DS0431EJ0130 Rev.1.30 Page 1 of 85 May 19, 2025 DATASHEET 1. OUTLINE

1.1 Features

Low power consumption technology  VDD = single power supply voltage of 2.4 to 5.5 V  HALT mode  STOP mode RL78 CPU core  CISC architecture with 3-stage pipeline  Minimum instruction execution time: Can be changed from high speed (0.0625 μs: @ 16 MHz operation with high-speed on-chip oscillator) to ultra-low speed (30.5 μs: @ 32.768 kHz operation with subsystem clock)  Address space: 1 MB  General-purpose registers: (8-bit register × 8) × 4 banks  On-chip RAM: 2 KB Code flash memory  Code flash memory: 16 to 32 KB  Block size: 1 KB  Only write after erase is possible  On-chip debug function  Self-programming (with no boot swap function/flash shield window function) Data flash memory  Data flash memory: 1 KB  Block size: 512 B  Unit of rewrites: 32 bits  Background operation (BGO) is not supported (instructions cannot be executed from the code flash memory while rewriting the data flash memory)  Number of rewrites: 1,000,000 times (TYP.)  Voltage of rewrites: VDD = 2.4 to 5.5 V High-speed on-chip oscillator  Select from 16 MHz, 8 MHz, 4 MHz, 2 MHz, and

1 MHz

 Frequency accuracy ±1.0% (VDD = 2.4 to 5.5 V, TA = −20 to +85°C) (G: Industrial applications, M: Industrial applications)  Frequency accuracy ±1.5% (VDD = 2.4 to 5.5 V, TA = −40 to −20°C) (G: Industrial applications, M: Industrial applications)  Frequency accuracy ±1.5% (VDD = 2.4 to 5.5 V, TA = +85 to +105°C) (G: Industrial applications)  Frequency accuracy ±1.5% (VDD = 2.4 to 5.5 V, TA = +85 to +125°C) (M: Industrial applications)  Frequency accuracy ±2.0% (VDD = 2.4 to 5.5 V, TA = −40 to +85°C) (A: Consumer applications) Operating ambient temperature  TA = −40 to +85°C (A: Consumer applications)  TA = −40 to +105°C (G: Industrial applications)  TA = −40 to +125°C (M: Industrial applications) Power management and reset function  On-chip selectable power-on-reset (SPOR) circuit (Select reset from 3 levels, stop setting is available) Serial interface  Simplified SPI (CSINote 1): 1 to 3 channels  UART: 1 to 3 channel  Simplified I2C: 1 to 3 channels  I2C: 1 channel Note 1. Although the CSI function is generally called SPI, it is also called CSI in this product, so it is referred to as such in this manual. RL78/G16 RENESAS MCU True low-power platform, 61-µA/MHz operating current, TA = 125°C operation, from 10 to 32 pins, 16 to 32 KB code flash memory, 2 KB RAM, Capacitive touch sensing unit, 2.4 to 5.5 V R01DS0431EJ0130 Rev.1.30 May 19, 2025

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 2 of 85 May 19, 2025 Timer  16-bit timer: 8 channels  12-bit interval timer: 1 channel  Watchdog timer: 1 channel (operable with the dedicated low-speed on-chip oscillator)  Real-time clock 2: 1 channel (99-year calendar, alarm function, and clock correction function) A/D converter  8/10-bit resolution A/D converter (VDD = 2.4 to 5.5 V)  Analog input: 4 to 11 channels  Internal reference voltage (0.815 V (TYP.)), temperature sensor, and touch TSCAP voltage selection Comparator  1 to 2 channels  Operation mode: High-speed mode, low-speed mode  External reference voltage or internal reference voltage can be selected as the reference voltage. Capacitive touch sensing unit (CTSUb)  15 channels  Self-capacitance method: A single pin configures a single key, supporting up to 15 keys  Mutual capacitance method: A key can be created with a matrix configuration by selecting transmit/receive pins from 15 pins. Up to 16 keys are supported. I/O port  I/O port: 8 to 30 (N-ch open drain I/O [withstand voltage of 6 V]: 0 to 2)  Can be set to N-ch open drain and on-chip pull-up resistor  External interrupt function: 10 channels  On-chip clock output/buzzer output controller Others  On-chip BCD (binary-coded decimal) correction circuit Remark The functions mounted depend on the product. See 1.6 Outline of Functions. ROM, RAM capacities Flash ROM Data flash RAM RL78/G16 10 pins 16 pins 20 pins 24 pins 32 pins

32 KB 1 KB 2 KB R5F1211C R5F1214C R5F1216C R5F1217C R5F121BC

16 KB 1 KB 2 KB R5F1211A R5F1214A R5F1216A R5F1217A R5F121BA

<R>

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 3 of 85 May 19, 2025

1.2 List of Part Numbers

Figure 1-1. Part Number, Memory Size, and Package of RL78/G16 Part No. R 5 F 1 2 1 6 C M x x x S P #50 Packaging specifications #00, #20, #60: Tray (HWQFN) #10, #70: Tray (LSSOP (10-pin), SSOP, LQFP) #30: Tray (LSSOP (10-pin), SSOP, LQFP) Tube (LSSOP (20-pin))Note 1 #40: Embossed Tape (HWQFN) #50: Embossed Tape (LSSOP, SSOP, LQFP) #5F: Embossed Tape (TSSOP) #9F: Tube (TSSOP) ROM number (omitted for blank products) Package type FP: 32-pin, LQFP, 0.8-mm pitch SP: 10-pin, LSSOP, 0.65-mm pitch 16-pin, SSOP, 0.65-mm pitch 20-pin, LSSOP, 0.65-mm pitch NA: 16-pin, HWQFN, 0.5-mm pitch 24-pin, HWQFN, 0.5-mm pitch 32-pin, HWQFN, 0.5-mm pitch SM: 20-pin, TSSOP, 0.65mm pitch Fields of application A: Consumer applications, TA = –40°C to +85°C G: Industrial applications, TA = –40°C to +105°C M: Industrial applications, TA = –40°C to +125°C ROM capacity A: 16 KB C: 32 KB Pin count 1: 10-pin 4: 16-pin 6: 20-pin 7: 24-pin B: 32-pin RL78/G16 group: 121 Memory type F: Flash memory Renesas MCU Renesas semiconductor product Note 1. The packaging specification of the 20-pin LSSOP products is Tube. <R> <R>

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 4 of 85 May 19, 2025 Table 1-1. List of Ordering Part Numbers Pin count Package Fields of Application Ordering Part Number RENESAS Code Product Name Packaging Specifications 10 pins 10-pin plastic LSSOP (4.4 × 3.6 mm, 0.65-mm pitch) A R5F1211CASP, R5F1211AASP #10, #30, #50, #70 PLSP0010JA-A G R5F1211CGSP, R5F1211AGSP M R5F1211CMSP, R5F1211AMSP 16 pins 16-pin plastic SSOP (4.4 × 5.0 mm, 0.65-mm pitch) A R5F1214CASP, R5F1214AASP #10, #30, #50, #70 PRSP0016JC-B G R5F1214CGSP, R5F1214AGSP M R5F1214CMSP, R5F1214AMSP 16 pins 16-pin plastic HWQFN (3 × 3 mm, 0.5-mm pitch) A R5F1214CANA, R5F1214AANA #00, #20, #40, #60 PWQN0016KD-A G R5F1214CGNA, R5F1214AGNA M R5F1214CMNA, R5F1214AMNA 20 pins 20-pin plastic LSSOP (4.4 × 6.5 mm, 0.65-mm pitch) A R5F1216CASP, R5F1216AASP #30, #50 PLSP0020JB-A G R5F1216CGSP, R5F1216AGSP M R5F1216CMSP, R5F1216AMSP 20 pins 20-pin plastic TSSOP (4.4 × 6.5 mm, 0.65-mm pitch) A R5F1216CASM #5F, #9F PTSP0020JI-A M R5F1216CMSM 24 pins 24-pin plastic HWQFN (4.0 × 4.0 mm, 0.5-mm pitch) A R5F1217CANA, R5F1217AANA #00, #20, #40, #60 PWQN0024KF-A G R5F1217CGNA, R5F1217AGNA M R5F1217CMNA, R5F1217AMNA 32 pins 32-pin plastic HWQFN (5.0 × 5.0 mm, 0.5-mm pitch) A R5F121BCANA, R5F121BAANA #00, #20, #40, #60 PWQN0032KE-A G R5F121BCGNA, R5F121BAGNA M R5F121BCMNA, R5F121BAMNA 32 pins 32-pin plastic LQFP (7.0 × 7.0 mm, 0.8-mm pitch) A R5F121BCAFP, R5F121BAAFP #10, #30, #50, #70 PLQP0032GB-A G R5F121BCGFP, R5F121BAGFP M R5F121BCMFP, R5F121BAMFP Note 1. For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G16. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. <R>

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 5 of 85 May 19, 2025

1.3 Pin Configuration (Top View)

1.3.1 10-pin products  10-pin plastic LSSOP (4.4 × 3.6 mm, 0.65-mm pitch) RL78/G16 (Top View) 5 6 P125/RESET/INTP1/(VCOUT0)/(INTP0) P40/TOOL0/INTP2/(PCLBUZ0)/(TI01/TO01) P137/INTP0/TI00 VSS VDD P04/ANI3/IVREF0/INTP3/TS04/SDAA0/(TI01/TO01) P03/ANI2/IVCMP0/INTP4/TS03/TO00/SCLA0/(TI00) P02/PCLBUZ0/ANI1/VCOUT0/INTP7/TSCAP/TI01/TO01/SCK00/SCL00 P01/TOOLRxD/ANI0/INTP5/TS00/TI02/TO02/SI00/RxD0/SDA00/(TI01/TO01)/(SDAA0) P00/TOOLTxD/INTP6/SO00/TxD0/(TI02/TO02)/(SCLA0) Table 1-2. Multiplexed Functions of 10-pin Products Pin No. I/O Power supply, system, clock, debug Analog HMI Timer Communications Interface 10LSSOP Digital port A/D converter Comparator Interrupt function Capacitive touch sensing unit (CTSU) Timer array unit Serial array unit Serial interface IICA

1 P40 TOOL0

(PCLBUZ0) — — INTP2 — (TI01/TO01) — —

2 P125 RESET¯¯¯¯¯¯ — (VCOUT0) INTP1

(INTP0) — — — —

6 P00 TOOLTxD — — INTP6 — (TI02/TO02) SO00/TxD0 (SCLA0)

7 P01 TOOLRxD ANI0 — INTP5 TS00 TI02/TO02

(TI01/TO01) SI00/RxD0/ SDA00 (SDAA0)

8 P02 PCLBUZ0 ANI1 VCOUT0 INTP7 TSCAP TI01/TO01 SCK00/SCL00 —

9 P03 — ANI2 IVCMP0 INTP4 TS03 TO00

(TI00) — SCLA0

10 P04 — ANI3 IVREF0 INTP3 TS04 (TI01/TO01) — SDAA0

Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-6 Format of Peripheral I/O Redirection Registers 0 to 6 (PIOR0 to PIOR6) in the RL78/G16 User’s Manual.

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 6 of 85 May 19, 2025 1.3.2 16-pin products  16-pin plastic SSOP (4.4 × 5.0 mm, 0.65-mm pitch) RL78/G16 (Top View) 5 12 6 11 7 10 8 9 P41/RTC1HZ/TS13/TI03/TO03/(INTP3)/(INTP4)/ (TI02/TO02)/(VCOUT0)/(VCOUT1) P40/TOOL0/INTP2/(PCLBUZ0)/(TI01/TO01) P137/INTP0/TI00 P122/X2/XT2/EXCLK/EXCLKS/TI05/TO05/(INTP2) P121/X1/XT1/TI07/TO07/(INTP3)/(INTP4)/(INTP5) VSS VDD P07/ANI6/VCOUT1/TS07/TI04/TO04/SCK11/SCL11/SDAA0/(INTP5)/(TO03) P06/ANI5/IVREF1/TS06/SI11/SDA11/SCLA0/(PCLBUZ0)/(INTP7)/(TI03/TO03)/(SCK00/SCL00) P05/ANI4/IVCMP1/TS05/SO11/(INTP6)/(TI02/TO02)/(TI07/TO07)/(SCK00/SCL00)/(SI00/RxD0/SDA00) P04/ANI3/IVREF0/INTP3/TS04/TI06/TO06/TxD1/(TI01/TO01)/(SI00/RxD0/SDA00)/(SO00/TxD0) P03/ANI2/IVCMP0/INTP4/TS03/TO00/RxD1/(TI00)/(TI05/TO05)/(SO00/TxD0) P02/PCLBUZ0/ANI1/VCOUT0/INTP7/TSCAP/TI01/TO01/SCK00/SCL00/(TI02/TO02)/(SO11) P01/TOOLRxD/ANI0/INTP5/TS00/TI02/TO02/SI00/RxD0/SDA00/(TI01/TO01)/(SI11/SDA11)/(SDAA0) P00/TOOLTxD/INTP6/SO00/TxD0/(RTC1HZ)/(TI02/TO02)/(SCK11/SCL11)/(SCLA0) P125/RESET/INTP1/(VCOUT0)/(VCOUT1)/(INTP0)

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 7 of 85 May 19, 2025  16-pin plastic HWQFN (3 × 3 mm, 0.5-mm pitch) RL78/G16 (Top View) P137/INTP0/TI00 P122/X2/XT2/EXCLK/EXCLKS/TI05/TO05/(INTP2) P121/X1/XT1/TI07/TO07/(INTP3)/(INTP4)/(INTP5) P05/ANI4/IVCMP1/TS05/SO11/(INTP6)/(TI02/TO02)/(TI07/TO07)/(SCK00/SCL00)/(SI00/RxD0/SDA00) P04/ANI3/IVREF0/INTP3/TS04/TI06/TO06/TxD1/(TI01/TO01)/(SI00/RxD0/SDA00)/(SO00/TxD0) P03/ANI2/IVCMP0/INTP4/TS03/TO00/RxD1/(TI00)/(TI05/TO05)/(SO00/TxD0) P02/PCLBUZ0/ANI1/VCOUT0/INTP7/TSCAP/TI01/TO01/SCK00/SCL00/(TI02/TO02)/(SO11) P41/RTC1HZ/TS13/TI03/TO03/(INTP3)/(INTP4)/(TI02/TO02)/(VCOUT0)/(VCOUT1) P07/ANI6/VCOUT1/TS07/TI04/TO04/SCK11/SCL11/SDAA0/(INTP5)/(TO03) P06/ANI5/IVREF1/TS06/SI11/SDA11/SCLA0/(PCLBUZ0)/(INTP7)/(TI03/TO03)/ (SCK00/SCL00) P40/TOOL0/INTP2/(PCLBUZ0)/(TI01/TO01) VSS VDD P00/TOOLTxD/INTP6/SO00/TxD0/(RTC1HZ)/(TI02/TO02)/(SCK11/SCL11)/(SCLA0) P01/TOOLRxD/ANI0/INTP5/TS00/TI02/TO02/SI00/RxD0/SDA00/(TI01/TO01)/(SI11/SDA11)/ (SDAA0) 11 910 1 2 43 P125/RESET/INTP1/(VCOUT0)/(VCOUT1)/(INTP0) INDEX MARK exposed die pad

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 8 of 85 May 19, 2025 Table 1-3. Multiplexed Functions of 16-pin Products Pin No. I/O Power supply, system, clock, debug Analog HMI Timer Communications Interface 16SSOP 16HWQFN Digital port A/D converter Comparator Interrupt function Capacitive touch sensing unit (CTSU) Timer array unit Serial array unit Serial interface IICA 1 15 P41 RTC1HZ — (VCOUT0) (VCOUT1) (INTP3) (INTP4) TS13 TI03/TO03 (TI02/TO02) — — 2 16 P40 TOOL0 (PCLBUZ0) — — INTP2 — (TI01/TO01) — — (VCOUT1) INTP1 (INTP0) — — — — 4 2 P137 INTP0 — — — — TI00 — — 5 3 P122 X2/XT2/ EXCLK/ EXCLKS — — (INTP2) — TI05/TO05 — — 6 4 P121 X1/XT1 — — (INTP3) (INTP4) (INTP5) — TI07/TO07 — — 9 7 P00 TOOLTxD (RTC1HZ) — — INTP6 — (TI02/TO02) SO00/TxD0 (SCK11/SCL11) (SCLA0) 10 8 P01 TOOLRxD ANI0 — INTP5 TS00 TI02/TO02 (TI01/TO01) SI00/RxD0/ SDA00 (SI11/SDA11) (SDAA0) 11 9 P02 PCLBUZ0 ANI1 VCOUT0 INTP7 TSCAP TI01/TO01 (TI02/TO02) SCK00/SCL00 (SO11) 12 10 P03 — ANI2 IVCMP0 INTP4 TS03 TO00 (TI00) (TI05/TO05) RxD1 (SO00/TxD0) 13 11 P04 — ANI3 IVREF0 INTP3 TS04 TI06/TO06 (TI01/TO01) TxD1 (SI00/RxD0/ SDA00) (SO00/TxD0) 14 12 P05 — ANI4 IVCMP1 (INTP6) TS05 (TI02/TO02) (TI07/TO07) SO11 (SCK00/SCL00) (SI00/RxD0/ SDA00) 15 13 P06 (PCLBUZ0) ANI5 IVREF1 (INTP7) TS06 (TI03/TO03) SI11/SDA11 (SCK00/SCL00) SCLA0 16 14 P07 — ANI6 VCOUT1 (INTP5) TS07 TI04/TO04 (TO03) SCK11/SCL11 SDAA0 Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-6 Format of Peripheral I/O Redirection Registers 0 to 6 (PIOR0 to PIOR6) in the RL78/G16 User’s Manual. Remark 3. For the product in a QFN package, solder the exposed die pad onto a plated area of the PCB that has no electrical connections.

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 9 of 85 May 19, 2025 1.3.3 20-pin products  20-pin plastic LSSOP/TSSOP (4.4 × 6.5 mm, 0.65-mm pitch) RL78/G16 (Top View) 5 16 6 15 7 14 8 13 9 12 10 11 P21/ANI9/TS10/SO20/TxD2/(INTP7)/(TO00)/(RxD1) P20/ANI10/TS11/SI20/RxD2/SDA20/(INTP1)/(TI00)/(TO00)/(TI03/TO03)/ (SCK11/SCL11)/(TxD1)P41/RTC1HZ/TS13/TI03/TO03/SCK20/SCL20/(VCOUT0)/(VCOUT1)/(INTP3)/(INTP4)/ (TI02/TO02)/(SO11)/(SDA11) P40/TOOL0/INTP2/(PCLBUZ0)/(TI01/TO01) P137/INTP0/TI00 P122/X2/XT2/EXCLK/EXCLKS/TI05/TO05/(INTP2) P121/X1/XT1/TI07/TO07/(INTP3)/(INTP4)/(INTP5) VSS VDD P22/ANI8/TS09/(INTP5)/(TI06/TO06)/(SDA11) P23/ANI7/TS08/(INTP6)/(TI04/TO04)/(SCL11) P07/ANI6/VCOUT1/TS07/TI04/TO04/SCK11/SCL11/SDAA0/(INTP5)/(TO03) P06/ANI5/IVREF1/TS06/SI11/SDA11/SCLA0/(PCLBUZ0)/(INTP7)/(TI03/TO03)/(SCK00/SCL00) P05/ANI4/IVCMP1/TS05/SO11/(INTP6)/(TI02/TO02)/(TI07/TO07)/(SCK00/SCL00)/(SI00/RxD0/SDA00) P04/ANI3/IVREF0/INTP3/TS04/TI06/TO06/TxD1/(TI01/TO01)/(SI00/RxD0/SDA00)/(SO00/TxD0) P03/ANI2/IVCMP0/INTP4/TS03/TO00/RxD1/(TI00)/(TI05/TO05)/(SO00/TxD0) P02/PCLBUZ0/ANI1/VCOUT0/INTP7/TSCAP/TI01/TO01/SCK00/SCL00/(TI02/TO02)/(SO11) P01/TOOLRxD/ANI0/INTP5/TS00/TI02/TO02/SI00/RxD0/SDA00/(TI01/TO01)/(SI11/SDA11)/(SDAA0) P00/TOOLTxD/INTP6/SO00/TxD0/(RTC1HZ)/(TI02/TO02)/(SCK11/SCL11)/(SCLA0) P125/RESET/INTP1/(VCOUT0)/(VCOUT1)/(INTP0)/(SI11) Table 1-4. Multiplexed Functions of 20-pin Products (1/2) Pin No. I/O Power supply, system, clock, debug Analog HMI Timer Communications Interface 20LSSOP/ 20TSSOP Digital port A/D converter Comparator Interrupt function Capacitive touch sensing unit (CTSU) Timer array unit Serial array unit Serial interface IICA

1 P21 — ANI9 — (INTP7) TS10 (TO00) SO20/TxD2

(RxD1)

2 P20 — ANI10 — (INTP1) TS11 (TI00)

(TO00) (TI03/TO03) SI20/RxD2/SDA20 (SCK11/SCL11) (TxD1)

3 P41 RTC1HZ — (VCOUT0)

(VCOUT1) (INTP3) (INTP4) TS13 TI03/TO03 (TI02/TO02) SCK20/SCL20 (SO11)/(SDA11)

4 P40 TOOL0

(PCLBUZ0) — — INTP2 — (TI01/TO01) — — (VCOUT1) INTP1 (INTP0) — — (SI11) —

7 P122 X2/XT2

— — (INTP2) — TI05/TO05 — —

8 P121 X1/XT1 — — (INTP3)

(INTP4) (INTP5) — TI07/TO07 — —

11 P00 TOOLTxD

(RTC1HZ) — — INTP6 — (TI02/TO02) SO00/TxD0 (SCK11/SCL11) (SCLA0)

12 P01 TOOLRxD ANI0 — INTP5 TS00 TI02/TO02

(TI01/TO01) SI00/RxD0/SDA00 (SI11/SDA11) (SDAA0)

13 P02 PCLBUZ0 ANI1 VCOUT0 INTP7 TSCAP TI01/TO01

(TI02/TO02) SCK00/SCL00 (SO11)

14 P03 — ANI2 IVCMP0 INTP4 TS03 TO00

(TI00) (TI05/TO05) RxD1 (SO00/TxD0)

15 P04 — ANI3 IVREF0 INTP3 TS04 TI06/TO06

(TI01/TO01) TxD1 (SI00/RxD0/SDA00) (SO00/TxD0)

16 P05 — ANI4 IVCMP1 (INTP6) TS05 (TI02/TO02)

(TI07/TO07) SO11 (SCK00/SCL00) (SI00/RxD0/SDA00) <R>

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 10 of 85 May 19, 2025 Table 1-4. Multiplexed Functions of 20-pin Products (2/2) Pin No. I/O Power supply, system, clock, debug Analog HMI Timer Communications Interface 20LSSOP/ 20TSSOP Digital port A/D converter Comparator Interrupt function Capacitive touch sensing unit (CTSU) Timer array unit Serial array unit Serial interface IICA

17 P06 (PCLBUZ0) ANI5 IVREF1 (INTP7) TS06 (TI03/TO03) SI11/SDA11

(SCK00/SCL00) SCLA0

18 P07 — ANI6 VCOUT1 (INTP5) TS07 TI04/TO04

(TO03) SCK11/SCL11 SDAA0

19 P23 — ANI7 — (INTP6) TS08 (TI04/TO04) (SCL11) —

20 P22 — ANI8 — (INTP5) TS09 (TI06/TO06) (SDA11) —

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 11 of 85 May 19, 2025 1.3.4 24-pin products  24-pin plastic HWQFN (4 × 4 mm, 0.5-mm pitch) RL78/G16 (Top View) P07/ANI6/VCOUT1/TS07/TI04/TO04/SCK11/SCL11/(INTP5)/(TO03)/(SDAA0) P06/ANI5/IVREF1/TS06/SI11/SDA11/(PCLBUZ0)/(INTP7)/(TI03/TO03)/(SCK00/SCL00)/(SCLA0) P05/ANI4/IVCMP1/TS05/SO11/(INTP6)/(TI02/TO02)/(TI07/TO07)/(SCK00/SCL00)/(SI00/RxD0/SDA00) P137/INTP0/TI00 P04/ANI3/IVREF0/INTP3/TS04/TI06/TO06/TxD1/(TI01/TO01)/(SI00/RxD0/SDA00)/(SO00/TxD0) P122/X2/XT2/EXCLK/EXCLKS/TI05/TO05/(INTP2) P121/X1/XT1/TI07/TO07/(INTP3)/(INTP4)/(INTP5) VSS VDD P03/ANI2/IVCMP0/INTP4/TS03/TO00/RxD1/(TI00)/(TI05/TO05)/(SO00/TxD0) P02/PCLBUZ0/ANI1/VCOUT0/INTP7/TSCAP/TI01/TO01/SCK00/SCL00/(TI02/TO02)/(SO11) 1219 P40/TOOL0/INTP2/(PCLBUZ0)/(TI01/TO01) P41/RTC1HZ/TS13/TI03/TO03/SCK20/SCL20/(VCOUT0)/(VCOUT1)/(INTP3)/(INTP4)/ (TI02/TO02)/(SO11)/(SDA11) P20/ANI10/TS11/SI20/RxD2/SDA20/(INTP1)/(TI00)/(TO00)/(TI03/TO03)/(SCK11/SCL11)/(TxD1) P21/ANI9/TS10/SO20/TxD2/(INTP7)/(TO00)/(RxD1) P22/ANI8/TS09/(INTP5)/(TI06/TO06)/(SDA11) P23/ANI7/TS08/(INTP6)/(TI04/TO04)/(SCL11) P60/SCLA0/(INTP3)/(INTP6)/(SI11) P61/SDAA0/(INTP7)/(SO11)/(SDA11) P10/INTP8/(PCLBUZ0)/(TI03/TO03)/(SCK11/SCL11)/(RxD1) P11/INTP9/(PCLBUZ0)/(RTC1HZ)/(TI03/TO03)/(SCK11/SCL11)/(TxD1) P00/TOOLTxD/INTP6/SO00/TxD0/(RTC1HZ)/(TI02/TO02)/(SCK11/SCL11)/ (SI11/SDA11)/(SCLA0) P01/TOOLRxD/ANI0/INTP5/TS00/TI02/TO02/SI00/RxD0/SDA00/(TI01/TO01)/ (SI11/SDA11)/(SO11)/(SDAA0) 17 16 15 14 2 3 4 5 P125/RESET/INTP1/(VCOUT0)/(VCOUT1)/(INTP0)/(SI11) INDEX MARK exposed die pad

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 12 of 85 May 19, 2025 Table 1-5. Multiplexed Functions of 24-pin Products (1/2) Pin No. I/O Power supply, system, clock, debug Analog HMI Timer Communications Interface 24HWQFN Digital port A/D converter Comparator Interrupt function Capacitive touch sensing unit (CTSU) Timer array unit Serial array unit Serial interface IICA (VCOUT1) INTP1 (INTP0) — — (SI11) —

3 P122 X2/XT2

— — (INTP2) — TI05/TO05 — —

4 P121 X1/XT1 — — (INTP3)

(INTP4) (INTP5) — TI07/TO07 — —

7 P60 — — — (INTP3)

(INTP6) — — (SI11) SCLA0 (SDA11) SDAA0

9 P10 (PCLBUZ0) — — INTP8 — (TI03/TO03) (SCK11/SCL11)

(RxD1)

10 P11 (PCLBUZ0)

(RTC1HZ) — — INTP9 — (TI03/TO03) (SCK11/SCL11) (TxD1) (RTC1HZ) — — INTP6 — (TI02/TO02) SO00/TxD0 (SCK11/SCL11) (SI11/SDA11) (SCLA0) (TI01/TO01) SI00/RxD0/SDA00 (SI11/SDA11) (SO11) (SDAA0) (TI02/TO02) SCK00/SCL00 (SO11) (TI00) (TI05/TO05) RxD1 (SO00/TxD0) (TI01/TO01) TxD1 (SI00/RxD0/SDA00) (SO00/TxD0) (TI07/TO07) SO11 (SCK00/SCL00) (SI00/RxD0/SDA00) (SCK00/SCL00) (SCLA0) (TO03) SCK11/SCL11 (SDAA0)

21 P21 — ANI9 — (INTP7) TS10 (TO00) SO20/TxD2

(RxD1)

22 P20 — ANI10 — (INTP1) TS11 (TI00)

(TO00) (TI03/TO03) SI20/RxD2/SDA20 (SCK11/SCL11) (TxD1)

23 P41 RTC1HZ — (VCOUT0)

(VCOUT1) (INTP3) (INTP4) TS13 TI03/TO03 (TI02/TO02) SCK20/SCL20 (SO11) (SDA11)

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 13 of 85 May 19, 2025 Table 1-5. Multiplexed Functions of 24-pin Products (2/2) Pin No. I/O Power supply, system, clock, debug Analog HMI Timer Communications Interface 24HWQFN Digital port A/D converter Comparator Interrupt function Capacitive touch sensing unit (CTSU) Timer array unit Serial array unit Serial interface IICA

24 P40 TOOL0

(PCLBUZ0) — — INTP2 — (TI01/TO01) — — Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-6 Format of Peripheral I/O Redirection Registers 0 to 6 (PIOR0 to PIOR6) in the RL78/G16 User’s Manual. Remark 3. For the product in a QFN package, solder the exposed die pad onto a plated area of the PCB that has no electrical connections.

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 14 of 85 May 19, 2025 1.3.5 32-pin products  32-pin plastic HWQFN (5 × 5 mm, 0.5-mm pitch) RL78/G16 (Top View) P05/ANI4/IVCMP1/TS05/SO11/(INTP6)/(TI02/TO02)/(TI07/TO07)/(SCK00/SCL00)/(SI00/RxD0/SDA00) P04/ANI3/IVREF0/INTP3/TS04/TI06/TO06/TxD1/(TI01/TO01)/(SI00/RxD0/SDA00)/(SO00/TxD0) P03/ANI2/IVCMP0/INTP4/TS03/TO00/RxD1/(TI00)/(TI05/TO05)/(SO00/TxD0) P137/INTP0/TI00 P17/TS02/(TI04/TO04)/(SO20/TxD2)/(SDAA0) P122/X2/XT2/EXCLK/EXCLKS/TI05/TO05/(INTP2) P121/X1/XT1/TI07/TO07/(INTP3)/(INTP4)/(INTP5) VSS VDD P16/TS01/(TI03/TO03)/(SI20/RxD2/SDA20)/(SCLA0) P02/PCLBUZ0/ANI1/VCOUT0/INTP7/TSCAP/TI01/TO01/SCK00/SCL00/(TI02/TO02)/(SO11)/(SCK20/SCL20) P40/TOOL0/INTP2/(PCLBUZ0)/(TI01/TO01) P43/TS14 P01/TOOLRxD/ANI0/INTP5/TS00/TI02/TO02/SI00/RxD0/SDA00/(TI01/TO01)/(SI11/SDA11)/(SO11)/(SDAA0) P00/TOOLTxD/INTP6/SO00/TxD0/(RTC1HZ)/(TI02/TO02)/(SCK11/SCL11)/(SI11/SDA11)/(SCLA0) P41/RTC1HZ/TS13/TI03/TO03/SCK20/SCL20/(VCOUT0)/(VCOUT1)/(INTP3)/(INTP4)/(TI02/TO02)/ (SO11)/(SDA11) P42/TS12/(TI00)/(TxD1) P20/ANI10/TS11/SI20/RxD2/SDA20/(INTP1)/(TI00)/(TO00)/(TI03/TO03)/(SCK11/SCL11)/(RxD1)/ (TxD1) P21/ANI9/TS10/SO20/TxD2/(INTP7)/(TO00)/(RxD1) P22/ANI8/TS09/(INTP5)/(TI06/TO06)/(SDA11) P23/ANI7/TS08/(INTP6)/(TI04/TO04)/(SCL11) P07/ANI6/VCOUT1/TS07/TI04/TO04/SCK11/SCL11/(INTP5)/(TO03)/(SDAA0) P06/ANI5/IVREF1/TS06/SI11/SDA11/(PCLBUZ0)/(INTP7)/(TI03/TO03)/(SCK00/SCL00)/(SCLA0) P60/SCLA0/(INTP3)/(INTP6)/(SI11) P61/SDAA0/(INTP7)/(SO11)/(SDA11) P10/INTP8/(PCLBUZ0)/(TI03/TO03)/(SCK11/SCL11)/(RxD1) P11/INTP9/(PCLBUZ0)/(RTC1HZ)/(TI03/TO03)/(SCK11/SCL11)/(TxD1) P12/(INTP8) P13/(RTC1HZ)/(INTP2)/(INTP4)/(SCK11/SCL11)/(SCK20/SCL20) P14/(INTP2)/(SI11/SDA11)/(SI20/RxD2/SDA20) P15/(INTP9)/(SO11)/(SO20/TxD2) 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 P125/RESET/INTP1/(VCOUT0)/(VCOUT1)/(INTP0)/(SI11) INDEX MARK exposed die pad

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 15 of 85 May 19, 2025  32-pin plastic LQFP (7 × 7 mm, 0.8-mm pitch) RL78/G16 (Top View) P05/ANI4/IVCMP1/TS05/SO11/(INTP6)/(TI02/TO02)/(TI07/TO07)/(SCK00/SCL00)/(SI00/RxD0/SDA00) P04/ANI3/IVREF0/INTP3/TS04/TI06/TO06/TxD1/(TI01/TO01)/(SI00/RxD0/SDA00)/(SO00/TxD0) P03/ANI2/IVCMP0/INTP4/TS03/TO00/RxD1/(TI00)/(TI05/TO05)/(SO00/TxD0) P137/INTP0/TI00 P17/TS02/(TI04/TO04)/(SO20/TxD2)/(SDAA0) P122/X2/XT2/EXCLK/EXCLKS/TI05/TO05/(INTP2) P121/X1/XT1/TI07/TO07/(INTP3)/(INTP4)/(INTP5) VSS VDD P16/TS01/(TI03/TO03)/(SI20/RxD2/SDA20)/(SCLA0) P02/PCLBUZ0/ANI1/VCOUT0/INTP7/TSCAP/TI01/TO01/SCK00/SCL00/(TI02/TO02)/(SO11)/(SCK20/SCL20) 9 10 11 12 31 30 29 28 27 13 14 15 16 26 25 P40/TOOL0/INTP2/(PCLBUZ0)/(TI01/TO01) P43/TS14 P01/TOOLRxD/ANI0/INTP5/TS00/TI02/TO02/SI00/RxD0/SDA00/(TI01/TO01)/(SI11/SDA11)/(SO11)/(SDAA0) P00/TOOLTxD/INTP6/SO00/TxD0/(RTC1HZ)/(TI02/TO02)/(SCK11/SCL11)/(SI11/SDA11)/(SCLA0) P125/RESET/INTP1/(VCOUT0)/(VCOUT1)/(INTP0)/(SI11) P41/RTC1HZ/TS13/TI03/TO03/SCK20/SCL20/(VCOUT0)/(VCOUT1)/(INTP3)/(INTP4)/(TI02/TO02)/(SO11)/(SDA11) P42/TS12/(TI00)/(TxD1) P20/ANI10/TS11/SI20/RxD2/SDA20/(INTP1)/(TI00)/(TO00)/(TI03/TO03)/(SCK11/SCL11)/(RxD1)/(TxD1) P21/ANI9/TS10/SO20/TxD2/(INTP7)/(TO00)/(RxD1) P22/ANI8/TS09/(INTP5)/(TI06/TO06)/(SDA11) P23/ANI7/TS08/(INTP6)/(TI04/TO04)/(SCL11) P07/ANI6/VCOUT1/TS07/TI04/TO04/SCK11/SCL11/(INTP5)/(TO03)/(SDAA0) P06/ANI5/IVREF1/TS06/SI11/SDA11/(PCLBUZ0)/(INTP7)/(TI03/TO03)/(SCK00/SCL00)/(SCLA0) P60/SCLA0/(INTP3)/(INTP6)/(SI11) P61/SDAA0/(INTP7)/(SO11)/(SDA11) P10/INTP8/(PCLBUZ0)/(TI03/TO03)/(SCK11/SCL11)/(RxD1) P11/INTP9/(PCLBUZ0)/(RTC1HZ)/(TI03/TO03)/(SCK11/SCL11)/(TxD1) P12/(INTP8) P13/(RTC1HZ)/(INTP2)/(INTP4)/(SCK11/SCL11)/(SCK20/SCL20) P14/(INTP2)/(SI11/SDA11)/(SI20/RxD2/SDA20) P15/(INTP9)/(SO11)/(SO20/TxD2)

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 16 of 85 May 19, 2025 Table 1-6. Multiplexed Functions of 32-pin Products (1/2) Pin No. I/O Power supply, system, clock, debug Analog HMI Timer Communications Interface 32HWQFN 32LQFP Digital port A/D converter Comparator Interrupt function Capacitive touch sensing unit (CTSU) Timer array unit Serial array unit Serial interface IICA

2 P40 TOOL0

(PCLBUZ0) — — INTP2 — (TI01/TO01) — — (VCOUT1) INTP1 (INTP0) — — (SI11) —

5 P122 X2/XT2

— — (INTP2) — TI05/TO05 — —

6 P121 X1/XT1 — — (INTP3)

(INTP4) (INTP5) — TI07/TO07 — —

9 P60 — — — (INTP3)

(INTP6) — — (SI11) SCLA0 (SDA11) SDAA0

11 P10 (PCLBUZ0) — — INTP8 — (TI03/TO03) (SCK11/SCL11)

(RxD1)

12 P11 (PCLBUZ0)

(RTC1HZ) — — INTP9 — (TI03/TO03) (SCK11/SCL11) (TxD1)

14 P13 (RTC1HZ) — — (INTP2)

(INTP4) — — (SCK11/SCL11) (SCK20/SCL20)

15 P14 — — — (INTP2) — — (SI11/SDA11)

(SI20/RxD2/SDA20) (SO20/TxD2)

17 P00 TOOLTxD

(RTC1HZ) — — INTP6 — (TI02/TO02) SO00/TxD0 (SCK11/SCL11) (SI11/SDA11) (SCLA0)

18 P01 TOOLRxD ANI0 — INTP5 TS00 TI02/TO02

(TI01/TO01) SI00/RxD0/SDA00 (SI11/SDA11) (SO11) (SDAA0)

19 P02 PCLBUZ0 ANI1 VCOUT0 INTP7 TSCAP TI01/TO01

(TI02/TO02) SCK00/SCL00 (SO11) (SCK20/SCL20)

20 P16 — — — — TS01 (TI03/TO03) (SI20/RxD2/SDA20) (SCLA0)

21 P17 — — — — TS02 (TI04/TO04) (SO20/TxD2) (SDAA0)

22 P03 — ANI2 IVCMP0 INTP4 TS03 TO00

(TI00) (TI05/TO05) RxD1 (SO00/TxD0)

23 P04 — ANI3 IVREF0 INTP3 TS04 TI06/TO06

(TI01/TO01) TxD1 (SI00/RxD0/SDA00) (SO00/TxD0)

24 P05 — ANI4 IVCMP1 (INTP6) TS05 (TI02/TO02)

(TI07/TO07) SO11 (SCK00/SCL00) (SI00/RxD0/SDA00)

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 17 of 85 May 19, 2025 Table 1-6. Multiplexed Functions of 32-pin Products (2/2) Pin No. I/O Power supply, system, clock, debug Analog HMI Timer Communications Interface 32HWQFN 32LQFP Digital port A/D converter Comparator Interrupt function Capacitive touch sensing unit (CTSU) Timer array unit Serial array unit Serial interface IICA

25 P06 (PCLBUZ0) ANI5 IVREF1 (INTP7) TS06 (TI03/TO03) SI11/SDA11

(SCK00/SCL00) (SCLA0)

26 P07 — ANI6 VCOUT1 (INTP5) TS07 TI04/TO04

(TO03) SCK11/SCL11 (SDAA0)

27 P23 — ANI7 — (INTP6) TS08 (TI04/TO04) (SCL11) —

28 P22 — ANI8 — (INTP5) TS09 (TI06/TO06) (SDA11) —

29 P21 — ANI9 — (INTP7) TS10 (TO00) SO20/TxD2

(RxD1)

30 P20 — ANI10 — (INTP1) TS11 (TI00)

(TO00) (TI03/TO03) SI20/RxD2/SDA20 (SCK11/SCL11) (RxD1) (TxD1)

32 P41 RTC1HZ — (VCOUT0)

(VCOUT1) (INTP3) (INTP4) TS13 TI03/TO03 (TI02/TO02) SCK20/SCL20 (SO11) (SDA11) Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-6 Format of Peripheral I/O Redirection Registers 0 to 6 (PIOR0 to PIOR6) in the RL78/G16 User’s Manual. Remark 3. For the product in a QFN package, solder the exposed die pad onto a plated area of the PCB that has no electrical connections.

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 18 of 85 May 19, 2025

1.4 Pin Identification

ANI0 to ANI10 : Analog Input INTP0 to INTP9 : Interrupt Request From Peripherals P00 to P07 P10 to P17 P20 to P23 : Port 0 : Port 1 : Port 2 P40 to P43 : Port 4 P60, P61 : Port 6 P121, P122, P125 : Port 12 P137 : Port 13 PCLBUZ0 : Programmable Clock Output/Buzzer Output EXCLK : External Clock Input (Main System Clock) EXCLKS : External Clock Input (Subsystem Clock) X1, X2 : Crystal Oscillator (Main System Clock) XT1, XT2 : Crystal Oscillator (Subsystem Clock) IVCMP0, IVCMP1 : Comparator Input VCOUT0, VCOUT1 : Comparator Output IVREF0, IVREF1 : Comparator Reference Input RxD0, RxD1, RxD2 : Receive Data RTC1HZ : Real-time Clock Correction Clock (1 Hz) Output SCK00, SCK11, SCK20 : Serial Clock Input/Output SCL00, SCL11, SCL20, SCLA0 : Serial Clock Output SDA00, SDA11, SDA20, SDAA0 : Serial Data Input/Output SI00, SI11, SI20 : Serial Data Input SO00, SO11, SO20 : Serial Data Output TI00 to TI07 : Timer Input TO00 to TO07 : Timer Output TOOL0 : Data Input/Output for Tool TOOLRxD, TOOLTxD : Data Input/Output for External Device TxD0, TxD1, TxD2 : Transmit Data TS00 to TS14 : Electrostatic Capacitance Measurement Pin (Touch Pin) TSCAP : LPF (low-pass filter) Connection for CTSU VDD : Power Supply VSS : Ground

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 19 of 85 May 19, 2025

1.5 Block Diagram

1.5.1 10-pin products SAU0 (2ch) Clock Generator Reset Generator RAM 2 KB INTERRUPT CONTROL IIC00 CSI00 RESET VDD RxD0 TxD0 SCK00 SI00 SO00 SCL00 SDA00 SELECTABLE POWER ON RESET Low Speed ON-CHIP OSCILLATOR 15 kHz High Speed ON-CHIP OSCILLATOR 1 to 16 MHz VSS

4 ANI0 to ANI3

16, 32 KB DATA FLASH 1 KB RL78-S2 UART0 8/10-bit A/D CONVERTER 4ch Temp Sensor TSCAP Internal reference voltage REAL-TIME CLOCK WATCH DOG TIMER 12-bit INTERBAL TIMER LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ IICA0 COMP BCD ADJUSTMENT SCLA0 SDAA0 IVREF0 IVCMP0 VCOUT0 ON-CHIP DEBUG TOOL0 TOOLTxD TOOLRxD CTSU TSCAP TS00 TS03, TS04 2 TAU0 (8ch) TI00 TI01 TI02 ch02 ch01 ch00 ch03 ch04 ch05 ch06 ch07 TO00 TO01 TO02 PORT 0 P00 to P045 PORT 4 P40 PORT 12 P125 PORT 13 P137 BUZZER/CLOCK OUTPUT CONTROL PCLBUZ0 INTERRUPT CONTROL 8ch

8 INTP0 to INTP7

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 20 of 85 May 19, 2025 1.5.2 16-pin products SAU0 (4ch) Clock Generator Reset Generator Main OSC 1 to 12 MHz RAM 2 KB INTERRUPT CONTROL RESET TAU0 (8ch) TI00 TI01 TI02 X2/EXCLK CODE FLASH 16, 32 KB DATA FLASH 1 KB RL78-S2 ch02 ch01 ch00 ch03 ch04 ch05 ch06 ch07 TI03 TI05 TI07 RxD0 TxD0 UART0 ON-CHIP DEBUG TOOL0 TOOLTxD TOOLRxD BCD ADJUSTMENT IICA0SCLA0 SDAA0 COMP0 IVREF0 IVCMP0 VCOUT0 TO00 TO01 TO02 TO03 TI04 TO04 TO05 TI06 TO06 TO07 CSI11 SCK11 SI11 SO11 IIC11SCL11 SDA11 IIC00SCL00 SDA00 CSI00 SCK00 SI00 SO00 UART1RxD1 TxD1 COMP1 IVREF1 IVCMP1 VCOUT1 CTSU TSCAP TS00 TS03-TS07 5 TS13 VDD SELECTABLE POWER ON RESET Low Speed ON-CHIP OSCILLATOR 15 kHz High Speed ON-CHIP OSCILLATOR 1 to 16 MHz VSS XT1 XT2/EXCLKS

7 ANI0 to ANI6

Internal reference voltage REAL-TIME CLOCK WATCH DOG TIMER 12-bit INTERBAL TIMER LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ BUZZER/CLOCK OUTPUT CONTROL PORT 12 PORT 13 INTERRUPT CONTROL 8ch PCLBUZ0 P137 P121, P122, P1253 PORT 0 P00 to P078 PORT 4 P40, P412 Sub OSC 32.768 kHz

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 21 of 85 May 19, 2025 1.5.3 20-pin products SAU0 (4ch) Clock Generator Reset Generator Main OSC 1 to 12 MHz RAM 2 KB INTERRUPT CONTROL RESET TAU0 (8ch) TI00 TI01 TI02 X2/EXCLK CODE FLASH 16, 32 KB DATA FLASH 1 KB RL78-S2 ch02 ch01 ch00 ch03 ch04 ch05 ch06 ch07 TI03 TI05 TI07 RxD0 TxD0 UART0 ON-CHIP DEBUG TOOL0 TOOLTxD TOOLRxD BCD ADJUSTMENT IICA0SCLA0 SDAA0 COMP0 IVREF0 IVCMP0 VCOUT0 TO00 TO01 TO02 TO03 TI04 TO04 TO05 TI06 TO06 TO07 CSI11 SCK11 SI11 SO11 IIC11SCL11 SDA11 IIC00SCL00 SDA00 CSI00 SCK00 SI00 SO00 UART1RxD1 TxD1 COMP1 IVREF1 IVCMP1 VCOUT1 CTSU TSCAP TS00 TS03-TS11 9 TS13 VDD SELECTABLE POWER ON RESET Low Speed ON-CHIP OSCILLATOR 15 kHz High Speed ON-CHIP OSCILLATOR 1 to 16 MHz VSS XT1 XT2/EXCLKS

11 ANI0 to ANI10

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 22 of 85 May 19, 2025 1.5.4 24-pin products SAU0 (4ch) Clock Generator Reset Generator Main OSC 1 to 12 MHz RAM 2 KB INTERRUPT CONTROL RESET TAU0 (8ch) TI00 TI01 TI02 X2/EXCLK CODE FLASH 16, 32 KB DATA FLASH 1 KB RL78-S2 ch02 ch01 ch00 ch03 ch04 ch05 ch06 ch07 TI03 TI05 TI07 RxD0 TxD0 UART0 ON-CHIP DEBUG TOOL0 TOOLTxD TOOLRxD BCD ADJUSTMENT IICA0SCLA0 SDAA0 COMP0 IVREF0 IVCMP0 VCOUT0 TO00 TO01 TO02 TO03 TI04 TO04 TO05 TI06 TO06 TO07 CSI11 SCK11 SI11 SO11 IIC11SCL11 SDA11 IIC00SCL00 SDA00 CSI00 SCK00 SI00 SO00 UART1RxD1 TxD1 COMP1 IVREF1 IVCMP1 VCOUT1 CTSU TSCAP TS00 TS03-TS11 9 TS13 VDD SELECTABLE POWER ON RESET Low Speed ON-CHIP OSCILLATOR 15 kHz High Speed ON-CHIP OSCILLATOR 1 to 16 MHz VSS XT1 XT2/EXCLKS Internal reference voltage REAL-TIME CLOCK WATCH DOG TIMER 12-bit INTERBAL TIMER LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ BUZZER/CLOCK OUTPUT CONTROL PORT 12 PORT 13 INTERRUPT CONTROL 10ch PCLBUZ0 P137

10 INTP0 to INTP9

P121, P122, P1253 PORT 0 P00 to P078 PORT 4 P40, P412 SAU1 (2ch) RxD2 TxD2 UART2 IIC20SCL20 SDA20 CSI20 SCK20 SI20 SO20 PORT 2 P20 to P234 PORT 6 P60, P612 PORT 1 P10, P112 Sub OSC 32.768 kHz

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 23 of 85 May 19, 2025 1.5.5 32-pin products SAU0 (4ch) Clock Generator Reset Generator Main OSC 1 to 12 MHz RAM 2 KB INTERRUPT CONTROL RESET TAU0 (8ch) TI00 TI01 TI02 X2/EXCLK CODE FLASH 16, 32 KB DATA FLASH 1 KB RL78-S2 ch02 ch01 ch00 ch03 ch04 ch05 ch06 ch07 TI03 TI05 TI07 RxD0 TxD0 UART0 ON-CHIP DEBUG TOOL0 TOOLTxD TOOLRxD BCD ADJUSTMENT IICA0SCLA0 SDAA0 COMP0 IVREF0 IVCMP0 VCOUT0 TO00 TO01 TO02 TO03 TI04 TO04 TO05 TI06 TO06 TO07 CSI11 SCK11 SI11 SO11 IIC11SCL11 SDA11 IIC00SCL00 SDA00 CSI00 SCK00 SI00 SO00 UART1RxD1 TxD1 COMP1 IVREF1 IVCMP1 VCOUT1 CTSU TSCAP TS00 TS14 VDD SELECTABLE POWER ON RESET Low Speed ON-CHIP OSCILLATOR 15 kHz High Speed ON-CHIP OSCILLATOR 1 to 16 MHz VSS Sub OSC 32.768 kHz XT1 XT2/EXCLKS Internal reference voltage REAL-TIME CLOCK WATCH DOG TIMER 12-bit INTERBAL TIMER LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ BUZZER/CLOCK OUTPUT CONTROL PORT 12 PORT 13 INTERRUPT CONTROL 10ch PCLBUZ0 P137 P121, P122, P1253 PORT 0 P00 to P078 PORT 4 P40 to P434 SAU1 (2ch) RxD2 TxD2 UART2 IIC20SCL20 SDA20 CSI20 SCK20 SI20 SO20 PORT 2 P20 to P234 PORT 6 P60, P612 PORT 1 P10 to P178

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 24 of 85 May 19, 2025

1.6 Outline of Functions

This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H. Item 10-pin 16-pin 20-pin 24-pin 32-pin R5F1211A R5F1211C R5F1214A R5F1214C R5F1216A R5F1216C R5F1217A R5F1217C R5F121BA R5F121BC Code flash memory 16 KB 32 KB 16 KB 32 KB 16 KB 32 KB 16 KB 32 KB 16 KB 32 KB Data flash memory 1 KB RAM 2 KB Main system clock High-speed system clock — X1, X2 (crystal/ceramic) oscillation: 1 to 12 MHz: VDD = 2.4 to 5.5 V External main system clock input (EXCLK): 1 to 16 MHz: VDD = 2.4 to 5.5 V High-speed on-chip oscillator 1 to 16 MHz (VDD = 2.4 to 5.5 V) Subsystem clock — XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 32.768 kHz (TYP.): VDD = 2.4 to 5.5 V Low-speed on-chip oscillator clock 15 kHz (TYP.) General-purpose registers (8-bit register × 8) × 4 banks Minimum instruction execution time 0.0625 μs (16 MHz operation) Instruction set ● Data transfer (8/16 bits)

Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. I/O port Total 8 14 18 22 30 CMOS I/O 7 13 17 19 27 CMOS input 1 N-ch open drain I/O (withstand voltage of 6 V) — 2 Timer 16-bit timer 8 channels Watchdog timer 1 channel 12-bit interval timer 1 channel Real-time clock 2 — 1 channel Timer output 3 channels (PWM outputs: 2)Note 1 8 channels (PWM outputs: 7)Note 1 8 channels (PWM outputs: 7)Note 1 8 channels (PWM outputs: 7)Note 1 8 channels (PWM outputs: 7)Note 1 RTC output — 1 Hz (subsystem clock: fSUB = 32.768 kHz) Clock output/buzzer output 1 Up to 10 MHz (peripheral hardware clock: fMAIN = 10 MHz operation) Comparator 1 channel 2 channels 2 channels 2 channels 2 channels 8/10-bit resolution A/D converter 4 channels 7 channels 11 channels 11 channels 11 channels Serial interface Simplified SPI (CSI): 1 channel/ simplified I2C: 1 channel/ UART: 1 channel Simplified SPI (CSINote 2): 2 channels/ simplified I2C: 2 channels/ UART: 2 channels Simplified SPI (CSI): 3 channels/simplified I2C: 3 channels/UART: 3 channels I2C bus 1 channel CTSU 3 7 11 11 15 Number of Vectored interrupt sources Internal 23 26 30 30 30 External 8 8 8 10 10
Internal reset by watchdog timer
Internal reset by selectable power-on-reset
Internal reset by illegal instruction executionNote 3
Internal reset by data retention lower limit voltage
Internal reset by illegal-memory access
Internal reset by RAM parity error Selectable power-on-reset circuit ● Detection voltage On-chip debug function Provided Power supply voltage VDD = 2.4 to 5.5 V Operating ambient temperature TA = −40 to +85°C (A: Consumer applications), TA = −40 to +105°C (G: Industrial applications), TA = −40 to +125°C (M: Industrial applications)

RL78/G16 1. OUTLINE R01DS0431EJ0130 Rev.1.30 Page 25 of 85 May 19, 2025 Note 1. The number of outputs varies, depending on the setting of channels in use and the number of the master (see 6.9.3 Operation as multiple PWM output function in the RL78/G16 User’s Manual). Note 2. Although the CSI function is generally called SPI, it is also called CSI in this product, so it is referred to as such in this manual. Note 3. The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the on-chip debug emulator.

RL78/G16 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) R01DS0431EJ0130 Rev.1.30 Page 26 of 85 May 19, 2025 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) This chapter describes the electrical specifications of A: Consumer applications (TA = −40 to +85°C), G: Industrial applications (TA = −40 to +105°C), and M: Industrial applications (TA = −40 to +125°C) when they are used in the range of TA = −40 to +85°C. Caution 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. Caution 2. The pins mounted depend on the product. Refer to 2.1 Port Function, for the port functions, and 2.2.1 Functions for each product, for the other functions, in the RL78/G16 User’s Manual. Remark There are differences in the high-speed on-chip oscillator clock accuracy between G: Industrial applications and M: Industrial applications, and A: Consumer applications. Classification A: Consumer applications G: Industrial applications M: Industrial applications High-speed on-chip oscillator clock accuracy ±2.0% when TA = −40 to +85°C ±1.5% when TA = +85 to +105°C ±1.0% when TA = −20 to +85°C ±1.5% when TA = −40 to −20°C ±1.5% when TA = +85 to +125°C ±1.0% when TA = −20 to +85°C ±1.5% when TA = −40 to −20°C

RL78/G16 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) R01DS0431EJ0130 Rev.1.30 Page 27 of 85 May 19, 2025

2.1 Absolute Maximum Ratings

[TA = 25°C] Item Symbol Condition Rating Unit Supply voltage VDD −0.5 to +6.5 V Input voltage VI1 −0.3 to VDD + 0.3Note 1 V Output voltage VO1 −0.3 to VDD + 0.3 V Output current, high IOH1 Per pin −40 mA Total of all pins P06, P07, P20 to P23, P40 to P43, P121, P122, P125 −70 mA −170mA P00 to P05, P10 to P17 −100 mA Output current, low IOL1 Per pin 40 mA Total of all pins P06, P07, P20 to P23, P40 to P43, P121, P122, P125 100 mA 170mA P00 to P05, P10 to P17, P60, P61 100 mA Operating ambient temperature TA −40 to +85 °C Storage temperature Tstg −65 to +150 °C Note 1. This must be no greater than 6.5 V. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any item. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark 1. The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. Remark 2. The reference voltage is VSS.

RL78/G16 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) R01DS0431EJ0130 Rev.1.30 Page 28 of 85 May 19, 2025

2.2 Oscillator Characteristics

2.2.1 X1 and XT1 oscillator characteristics

[TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Resonator Condition MIN. TYP. MAX. Unit X1 clock oscillation frequency (fx)Note 1 Ceramic resonator/ crystal resonator 2.4 V ≤ VDD ≤ 5.5 V 1 12 MHz XT1 clock oscillation frequency (fXT)Note 1 Crystal resonator 32 32.768 35 kHz Note 1. Indicates only permissible oscillator frequency ranges. Refer to 2.4 AC Characteristics for instruction execution time. For actual applications, request evaluation by the manufacturer of the oscillator circuit mounted on a board so you can use appropriate values. Caution Since the CPU is started by the high-speed on-chip oscillator clock after release from the reset state, the user should use the oscillation stabilization time counter status register (OSTC) to check the X1 clock oscillation stabilization time. Specify the values for the oscillation stabilization time in the OSTC register and the oscillation stabilization time select register (OSTS) after having sufficiently evaluated the oscillation stabilization time with the resonator to be used. Remark When using the X1 or XT1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/G16 User’s Manual.

2.2.2 On-chip oscillator characteristics

[TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit High-speed on-chip oscillator clock frequencyNote 1, Note 2 fIH 1 16 MHz High-speed on-chip oscillator clock frequency accuracy Low-speed on-chip oscillator clock frequency fIL 15 kHz Low-speed on-chip oscillator clock frequency accuracy −15 +15 % Note 1. The high-speed on-chip oscillator frequency is selected by bits 0 to 2 of option byte (00C2H) and bits 0 to 2 of the HOCODIV register. Note 2. The listed values only indicate the characteristics of the oscillators. Refer to 2.4 AC Characteristics for instruction execution time.

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2.3 DC Characteristics

2.3.1 Pin characteristics

[TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] (1/2) Item Symbol Condition MIN. TYP. MAX. Unit Output current, high Note 1 IOH1 Per pin for P00 to P07, P10 to P17, P20 to P23, P40 to P43, P121, P122, P125 −10.0Note 2 mA Total of P06, P07, P20 to P23, P40 to P43, P121, P122, P125 (when duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V −65.0Note 5 mA 2.7 V ≤ VDD < 4.0 V −14.0 mA 2.4 V ≤ VDD < 2.7 V −10.5 mA Total of P00 to P05, P10 to P17 (when duty ≤ 70%Note 3) 4.0 V ≤ VDD ≤ 5.5 V −65.0 mA 2.7 V ≤ VDD < 4.0 V −12.0 mA 2.4 V ≤ VDD < 2.7 V −9.0 mA Total of all pins (when duty ≤ 70%Note 3) −105.0 mA Output current, low Note 4 IOL1 Per pin for P00 to P07, P10 to P17, P20 to P23, P40 to P43, P121, P122, P125 20.0Note 2 mA Per pin for P60, P61 15.0Note 2 mA Total of P06, P07, P20 to P23, P40 to P43, P121, P122, P125 (when duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V 85.0Note 6 mA 2.7 V ≤ VDD < 4.0 V 21.0 mA 2.4 V ≤ VDD < 2.7 V 4.2 mA Total of P00 to P05, P10 to P17, P60, P61 (when duty ≤ 70%Note 3) 4.0 V ≤ VDD ≤ 5.5 V 85.0 mA 2.7 V ≤ VDD < 4.0 V 18.0 mA 2.4 V ≤ VDD < 2.7 V 3.6 mA Total of all pins (when duty ≤ 70%Note 3) 145.0 mA Note 1. Device operation is guaranteed at the listed currents even if current is flowing from the VDD pin to an output pin. Note 2. The value for maximum total current must not be exceeded. Note 3. The listed currents apply when the duty cycle is no greater than 70%. Use the following formula to calculate the output current when the duty cycle is greater than 70%, where n is the duty cycle.  Total output current from the listed pins = (IOH × 0.7)/(n × 0.01) Example when n = 80% and IOH = –10.0 mA Total output current from the listed pins = (–10.0 × 0.7)/(80 × 0.01) ≅ –8.7 mA  Total output current from the listed pins = (IOL × 0.7)/(n × 0.01) Example when n = 80% and IOL = 10.0 mA Total output current from the listed pins = (10.0 × 0.7)/(80 × 0.01) ≅ 8.7 mA Note that the duty cycle has no effect on the current that is allowed to flow into a single pin. A current higher than the absolute maximum rating must not flow into a single pin. Note 4. Device operation is guaranteed at the listed currents even if current is flowing from an output pin to the VSS pin.

RL78/G16 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) R01DS0431EJ0130 Rev.1.30 Page 30 of 85 May 19, 2025 Note 5. When the multiplexed TSm pin is used as a mutual-capacitance transmit pin, the value is –30 mA. Note 6. When the multiplexed TSm pin is used as a mutual-capacitance transmit pin, the value is 40 mA. Caution P00, P01, P03 to P07, P14, P16, P17, P20, P22, and P41 do not output high level in N-ch open-drain mode. Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified.

RL78/G16 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) R01DS0431EJ0130 Rev.1.30 Page 31 of 85 May 19, 2025 [TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] (2/2) Item Symbol Condition MIN. TYP. MAX. Unit Input voltage, high VIH1 0.8 VDD VDD V VIH2 P60, P61 0.7 VDD 6.0 V Input voltage, low VIL1 0 0.2 VDD V VIL2 P60, P61 0 0.3 VDD V Output voltage, high Note 1 VOH1 4.0 V ≤ VDD ≤ 5.5 V IOH = −10 mA VDD − 1.5 V IOH = −3.0 mA VDD − 0.7 V 2.7 V ≤ VDD ≤ 5.5 V IOH = −2.0 mA VDD − 0.6 V 2.4 V ≤ VDD ≤ 5.5 V IOH = −1.5 mA VDD − 0.5 V Output voltage, low Note 2 VOL1 4.0 V ≤ VDD ≤ 5.5 V IOL = 20 mA 1.3 V IOL = 8.5 mA 0.7 V 2.7 V ≤ VDD ≤ 5.5 V IOL = 3.0 mA 0.6 V IOL = 1.5 mA 0.4 V 2.4 V ≤ VDD ≤ 5.5 V IOL = 0.6 mA 0.4 V P60, P61 4.0 V ≤ VDD ≤ 5.5 V IOL = 15 mA 2.0 V IOL = 5 mA 0.4 V

2.7 V ≤ VDD ≤

5.5 V IOL = 3.0 mA 0.4 V IOL = 2.0 mA 0.4 V

2.4 V ≤ VDD ≤

5.5 V IOL = 1.0 mA 0.4 V Input leakage current, high ILIH1 P00 to P07, P10 to P17, P20 to P23, P40 to P43, P60, P61, P125, P137 V I = VDD 1 µA ILIH2 P121, P122 (X1, X2, XT1, XT2, EXCLK, EXCLKS) VI = VDD In input port or external clock input 1 µA In resonator connection 10 µA Input leakage current, low ILIL1 P00 to P07, P10 to P17, P20 to P23, P40 to P43, P60, P61, P125, P137 V I = VSS −1 µA ILIL2 P121, P122 (X1, X2, XT1, XT2, EXCLK, EXCLKS) VI = VSS In input port or external clock input −1 µA In resonator connection −10 µA On-chip pull-up resistance RU Except P60 and P61 VI = VSS 10 20 100 kΩ Note 1. The value under the condition which satisfies the high-level output current (IOH1). Note 2. The value under the condition which satisfies the low-level output current (IOL1). Caution The maximum value of VIH of P00, P01, P03 to P07, P14, P16, P17, P20, P22, and P41 is VDD even in N- ch open-drain mode. These pins do not output high level in N-ch open-drain mode. Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified.

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2.3.2 Supply current characteristics

[TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Supply currentNote 1 IDD1 Operating mode Basic operation f IH = 16 MHzNote 4 VDD = 3.0 V, 5.0 V 0.97 mA Normal operation fIH = 16 MHzNote 4 VDD = 3.0 V, 5.0 V 2.11 2.76 mA fIH = 4 MHzNote 4 VDD = 3.0 V, 5.0 V 1.22 1.64 mA fEX = 16 MHzNote 5, Note 6 VDD = 3.0 V, 5.0 V Square wave input 1.97 2.62 mA fX = 12 MHzNote 5, Note 6 VDD = 3.0 V, 5.0 V Resonator connection 1.79 2.49 mA fMX = 4 MHzNote 5, Note 6 VDD = 3.0 V, 5.0 V Square wave input 1.07 1.49 mA Resonator connection 1.12 1.55 mA fSUB = 32.768 kHzNote 7 TA = −40°C Square wave input 3.65 5.80 µA Resonator connection 3.70 6.00 µA fSUB = 32.768 kHzNote 7 TA = +25°C Square wave input 3.90 5.80 µA Resonator connection 4.18 6.00 µA fSUB = 32.768 kHzNote 7 TA = +50°C Square wave input 4.04 6.20 µA Resonator connection 4.37 6.40 µA fSUB = 32.768 kHzNote 7 TA = +70°C Square wave input 4.20 6.50 µA Resonator connection 4.56 6.70 µA fSUB = 32.768 kHzNote 7 TA = +85°C Square wave input 4.40 7.80 µA Resonator connection 4.80 8.00 µA IDD2Note 2 HALT mode fIH = 16 MHzNote 4 VDD = 3.0 V, 5.0 V 385 800 µA fIH = 4 MHzNote 4 VDD = 3.0 V, 5.0 V 334 630 µA fEX = 16 MHzNote 5, Note 6 VDD = 3.0 V, 5.0 V Square wave input 229 638 µA fX = 12 MHzNote 5, Note 6 VDD = 3.0 V, 5.0 V Resonator connection 351 902 µA fMX = 4 MHzNote 5, Note 6 VDD = 3.0 V, 5.0 V Square wave input 167 452 µA Resonator connection 226 599 µA fSUB = 32.768 kHzNote 8 TA = −40°C Square wave input 0.69 1.45 µA Resonator connection 0.75 1.65 µA fSUB = 32.768 kHzNote 8 TA = +25°C Square wave input 0.75 1.45 µA Resonator connection 1.04 1.65 µA fSUB = 32.768 kHzNote 8 TA = +50°C Square wave input 0.84 1.74 µA Resonator connection 1.20 1.94 µA fSUB = 32.768 kHzNote 8 TA = +70°C Square wave input 0.97 2.20 µA Resonator connection 1.33 2.40 µA fSUB = 32.768 kHzNote 8 TA = +85°C Square wave input 1.13 3.10 µA Resonator connection 1.51 3.30 µA IDD3Note 3 STOP modeNote 9 VDD = 3.0 V 0.62 2.80 µA Note 1. The listed currents are the total currents flowing into VDD, including the input leakage currents flowing when the level of the input pin is fixed to VDD or VSS. Regarding the values for main system clock operation, the TYP. value does not include the peripheral operating current. The MAX. value includes the peripheral operating current, but does not include those flowing into the A/D converter, comparator, capacitive touch sensing unit (CTSU), I/O port, and on-chip pull-

RL78/G16 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) R01DS0431EJ0130 Rev.1.30 Page 33 of 85 May 19, 2025 up/pull-down resistors. Regarding the values for subsystem clock operation, the TYP. and MAX. values do not include the peripheral operating current. However, in HALT mode, the current flowing into the RTC is included. Regarding the values in STOP mode, the TYP. and MAX. values do not include the peripheral operating current. Note 2. When the HALT instruction is executed from the flash memory. Note 3. The listed currents do not include the current flowing into real-time clock 2, the clock output/buzzer output controller, 12-bit interval timer, and watchdog timer. Note 4. When the high-speed system clock and subsystem clock are stopped. Note 5. When the high-speed on-chip oscillator and subsystem clock are stopped. Note 6. 16-pin, 20-pin, 24-pin, and 32-pin products only. Note 7. When the high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (ultra- low power consumption oscillation). However, not including the current flowing into real-time clock 2, the 12- bit interval timer, watchdog timer, and capacitive touch sensing unit. Note 8. When the high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and AMPHS1 = 1 (ultra-low power consumption oscillation). Note 9. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode. Remark 1. fIH: High-speed on-chip oscillator clock frequency Remark 2. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 3. Except for subsystem clock operation, the temperature condition of the TYP. value is TA = 25°C. Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)

RL78/G16 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) R01DS0431EJ0130 Rev.1.30 Page 34 of 85 May 19, 2025 Peripheral Functions [TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Low-speed on-chip oscillator operating current IFIL Note 1 0.30 µA RTC2 operating current IRTC Note 1, Note 2, Note 8 fSUB = 32.768 kHz 0.02 µA 12-bit interval timer operating current ITMKA Note 1, Note 2, Note 3 0.02 µA Watchdog timer operating current IWDT Note 1, Note 4 0.02 µA A/D converter operating current IADC Note 1, Note 5 In conversion at maximum speed VDD = 5.0 V 1.30 1.90 mA VDD = 3.0 V 0.50 mA Temperature sensor operating current ITMPS Note 1 75.0 µA Comparator operating current ICMP Note 1, Note 6 In high-speed mode VDD = 5.0 V 6.50 µA In low-speed mode VDD = 5.0 V 1.70 µA Internal reference voltage operating current I VREG Note 1 10 µA Self-programming operating current IFSP Note 1, Note 7 2.0 12.20 mA Note 1. The current flowing into VDD. Note 2. When the high-speed on-chip oscillator and high-speed system clock are stopped. Note 3. This current only flows into the 12-bit interval timer. It does not include the operating current of the low-speed on-chip oscillator and XT1 oscillator. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IFIL and ITMKA when the 12-bit interval timer is in operation. Note 4. This current only flows into the watchdog timer. It does not include the operating current of the low-speed on- chip oscillator. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IFIL and IWDT when the watchdog timer is in operation. Note 5. This current only flows into the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter is operating or in the HALT mode. Note 6. This current only flows into a single comparator. The supply current of the RL78 microcontrollers is the sum of I DD1, IDD2 or IDD3 and ICMP when the comparator is in operation. Note 7. This current only flows during self-programming. Note 8. This current only flows into real-time clock 2. It does not include the operating current of the low-speed on- chip oscillator and XT1 oscillator. The supply current of the RL78 microcontrollers is the sum of the values of either I DD1 or IDD2, and IRTC, when real-time clock 2 operates in operation mode or HALT mode. When the low- speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of real-time clock 2. Remark The temperature condition of the TYP. value is TA = 25°C.

RL78/G16 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) R01DS0431EJ0130 Rev.1.30 Page 35 of 85 May 19, 2025

2.4 AC Characteristics

[TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Instruction cycle (minimum instruction execution time) TCY When high-speed on-chip oscillator clock (fIH) is selected 2.4 V ≤ VDD ≤ 5.5 V 0.0625 1.0 µs When high-speed system clock (fMX) is selected 2.4 V ≤ VDD ≤ 5.5 V 0.0833 1.0 µs Subsystem clock (fSUB) operation In the self-programming mode 2.4 V ≤ VDD ≤ 5.5 V 0.0625 1.0 µs External system clock frequency fEX 2.4 V ≤ VDD ≤ 5.5 V 1.0 16 MHz External system clock input high-level width, low-level width tEXH, tEXL 2.4 V ≤ VDD ≤ 5.5 V 30 ns TI00 to TI07 input high-level width, low-level width tTIH, tTIL Noise filter is not used 1/fMCK + 10 ns TO00 to TO07 output frequency fTO 4.0 V ≤ VDD ≤ 5.5 V 8 MHz 2.7 V ≤ VDD < 4.0 V 5 MHz 2.4 V ≤ VDD < 2.7 V 4 MHz PCLBUZ0 output frequency fPCL 4.0 V ≤ VDD ≤ 5.5 V 10 MHz 2.7 V ≤ VDD < 4.0 V 5 MHz 2.4 V ≤ VDD < 2.7 V 4 MHz RESET¯¯¯¯¯¯ low-level width tRSL 10 µs Remark fMCK: Timer array unit operating clock frequency (Operation clock to be set by timer clock select register 0 (TPS0) and the CKS0n1 bit of timer mode register 0n (TMR0n). n: Channel number (n = 0 to 7).)

RL78/G16 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) R01DS0431EJ0130 Rev.1.30 Page 36 of 85 May 19, 2025 Minimum Instruction Execution Time during Main System Clock Operation 1.0 0.1 Supply voltage VDD [V] 5.52.4 0.01 0.05 0.2 0.8 TCY vs VDD  When the high-speed on-chip oscillator clock is selected  During self-programming  When the high-speed system clock is selected Cycle time TCY [µs] At AC Timing VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL External System Clock Timing 1/fEX tEXL tEXH EXCLK

RL78/G16 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) R01DS0431EJ0130 Rev.1.30 Page 37 of 85 May 19, 2025 TI/TO Timing tTIL tTIH 1/fTO TI00 to TI07 TO00 to TO07 tRSL RESET

RL78/G16 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) R01DS0431EJ0130 Rev.1.30 Page 38 of 85 May 19, 2025

2.5 Serial Interface Characteristics

2.5.1 Serial array unit

(1) UART mode [TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Transfer rate fMCK/6 bps Theoretical value of the maximum transfer rate fCLK = fMCK = 16 MHz

2.6 Mbps

UART mode connection diagram RL78 microcontroller User device TxD0 RxD0 Rx Tx UART mode bit width (reference) Baud rate error tolerance High-/low-bit width 1/Transfer rate TxD0 RxD0 Remark fMCK: Serial array unit operation clock frequency (Operation clock to be set by serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 11, 20))

RL78/G16 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) R01DS0431EJ0130 Rev.1.30 Page 39 of 85 May 19, 2025 (2) Simplified SPI (CSI) mode (master mode, SCKp... internal clock output) [TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 2.4 V ≤ VDD ≤ 5.5 V 250 ns SCKp high-/low-level width tKH1, tKL1 2.7 V ≤ VDD ≤ 5.5 V tKCY1/2 − 18 ns 2.4 V ≤ VDD ≤ 5.5 V tKCY1/2 − 38 ns SIp setup time (to SCKp ↑)Note 1 tSIK1 2.7 V ≤ VDD ≤ 5.5 V 47 ns 2.4 V ≤ VDD ≤ 5.5 V 75 ns SIp hold time (from SCKp ↑) Note 1 tKSI1 19 ns Delay time from SCKp ↓ to SOp outputNote 2 tKSO1 C = 30 pFNote 3, Note 4 25 ns Note 1. When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The SIp setup time becomes “to SCKp ↓” and the SIp hold time becomes “from SCKp ↓” when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = Note 2. When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The delay time to SOp output becomes “from SCKp ↓” when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = 0. Note 3. C is the load capacitance of the SCKp and SOp output lines. Note 4. External loads on P60 and P61 in the case of the SOp output line: R = 1 kΩ, C = 30 pF (3) Simplified SPI (CSI) mode (slave mode, SCKp... external clock input) [TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5V, VSS = 0V] Item Symbol Condition MIN. TYP. MAX. Unit SCKp cycle time tKCY2 2.7 V ≤ VDD ≤ 5.5 V 6/fMCK ns 2.4 V ≤ VDD ≤ 5.5 V 6/fMCK and also 500 ns SCKp high-/low-level width tKH2,tKL2 2.4 V ≤ VDD ≤ 5.5 V tKCY2/2 − 18 ns SIp setup time (to SCKp ↑)Note 1 tSIK2 2.7 V ≤ VDD ≤ 5.5 V 1/fMCK + 20 ns 2.4 V ≤ VDD ≤ 5.5 V 1/fMCK + 30 ns SIp hold time (from SCKp ↑) Note 1 tKSI2 2.4 V ≤ VDD ≤ 5.5 V 1/fMCK + 31 ns Delay time from SCKp ↓ to SOp outputNote 2 tKSO2 C = 30 pF Note 3, Note 4 2.7 V ≤ VDD ≤ 5.5 V 2/fMCK + 50 ns 2.4 V ≤ VDD ≤ 5.5 V 2/fMCK + 75 ns Note 1. When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The SIp setup time becomes “to SCKp ↓” and the SIp hold time becomes “from SCKp ↓” when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = Note 2. When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The delay time to SOp output becomes “from SCKp ↓” when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = 0. Note 3. C is the load capacitance of the SOp output lines.

RL78/G16 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) R01DS0431EJ0130 Rev.1.30 Page 40 of 85 May 19, 2025 Note 4. External loads on P60 and P61 in the case of the SOp output line: R = 1 kΩ, C = 30 pF Remark 1. p: CSI number (p = 00, 11, 20), n: Channel number (n = 0, 1) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by serial clock select register 0 (SPS0) and the CKS0n bit of serial mode register 0n (SMR0n). n: Channel number (n = 0, 1)) Simplified SPI (CSI) mode connection diagram RL78 microcontroller User device SCKp SOp SCK SI SIp SO Simplified SPI (CSI) mode serial transfer timing (When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1) Input dataSIp SOp tKCY1, 2 tKL1, 2 tKH1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 SCKp Output data Remark p: CSI number (p = 00, 11, 20), n: Channel number (n = 0, 1)

RL78/G16 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) R01DS0431EJ0130 Rev.1.30 Page 41 of 85 May 19, 2025 (4) Simplified I2C mode [TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. MAX. Unit SCLr clock frequency fSCL Cb = 100 pF, Rb = 3 kΩ 400Note 1 kHz Hold time when SCLr = “L” tLOW Cb = 100 pF, Rb = 3 kΩ 1150 ns Hold time when SCLr = “H” tHIGH Cb = 100 pF, Rb = 3 kΩ 1150 ns Data setup time (reception) tSU:DAT Cb = 100 pF, Rb = 3 kΩ 1/fMCK + 145Note 2 ns Data hold time (transmission) tHD:DAT Cb = 100 pF, Rb = 3 kΩ 0 355 ns Note 1. The value must also be no greater than fMCK/4. Note 2. Set fMCK so that it will not exceed the hold time when SCLr = “L” or SCLr = “H”. Caution Select the N-ch open drain output (VDD tolerance) mode for the SDAr pin by using port output mode register 0, 1, 2, 4, or 6 (POM0, 1, 2, 4, or 6). Simplified I2C mode connection diagram RL78 microcontroller User device SDAr SCLr SDA SCL VDD Rb

RL78/G16 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) R01DS0431EJ0130 Rev.1.30 Page 42 of 85 May 19, 2025 Simplified I2C mode serial transfer timing SDAr tLOW 1/fSCL tHIGH tHD:DAT SCLr tSU:DAT Remark 1. Rb[Ω]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SCLr, SDAr) load capacitance Remark 2. r: IIC number (r = 00, 11, 20) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by serial clock select register 0 (SPS0) and the CKS0n bit of serial mode register 0n (SMR0n). n: Channel number (n = 0, 1))

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2.5.2 Serial interface IICA

[TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition Standard Mode Fast Mode Unit MIN. MAX. MIN. MAX. SCLA0 clock frequency fSCL Fast mode: fCLK ≥ 3.5 MHz 0 400 kHz Standard mode: fCLK ≥ 1 MHz 0 100 kHz Setup time of restart condition tSU:STA 4.7 0.6 µs Hold timeNote 1 tHD:STA 4.0 0.6 µs Hold time when SCLA0 = “L” tLOW 4.7 1.3 µs Hold time when SCLA0 = “H” tHIGH 4.0 0.6 µs Data setup time (reception) tSU:DAT 250 100 ns Data hold time (transmission)Note 2 tHD:DAT 0 3.45 0 0.9 µs Setup time of stop condition tSU:STO 4.0 0.6 µs Bus-free time tBUF 4.7 1.3 µs Note 1. The first clock pulse is generated after this period when the start or restart condition is detected. Note 2. The maximum value (MAX.) of tHD:DAT applies to normal transfer and a wait is inserted at the ACK (acknowledge) timing. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistance) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 kΩ Fast mode: Cb = 200 pF, Rb = 1.7 kΩ IICA serial transfer timing tLOW tR tHIGH tF tHD:STA tBUF Stop condition tHD:DAT SCLA0 SDAA0 Start condition Restart condition Stop condition tSU:DAT tSU:STA tHD:STA tSU:STO

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2.6 Analog Characteristics

2.6.1 A/D converter characteristics

Targets: ANI0 to ANI10, internal reference voltage, temperature sensor output voltage, and CTSU TSCAP voltage [TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Resolution RES 8 10 bit Overall errorNote 1, Note 2, Note 3 AINL 10-bit resolution VDD = 5 V ±1.7 ±3.1 LSB VDD = 3 V ±2.3 ±4.5 LSB Conversion time tCONV 10-bit resolution Targets: ANI0 to ANI10 2.7 V ≤ VDD ≤ 5.5 V 4.25 17 µs 2.4 V ≤ VDD ≤ 5.5 V Note 5 5.75 23 µs 10-bit resolution Target: Internal reference voltageNote 6 Target: Temperature sensor output voltage Note 6 Target: CTSU TSCAP voltage Note 6 2.4 V ≤ VDD ≤ 5.5 V 5.75 23 µs Zero-scale error Note 1, Note 2, Note 3, Note 4 EZS 10-bit resolution VDD = 5 V ±0.19 %FSR VDD = 3 V ±0.39 %FSR Full-scale error Note 1, Note 2, Note 3, Note 4 EFS 10-bit resolution VDD = 5 V ±0.29 %FSR VDD = 3 V ±0.42 %FSR Integral linearity error Note 1, Note 2, Note 3 ILE 10-bit resolution VDD = 5 V ±1.8 LSB VDD = 3 V ±1.7 LSB Differential linearity error Note 1, Note 2, Note 3 DLE 10-bit resolution VDD = 5 V ±1.4 LSB VDD = 3 V ±1.5 LSB Analog input voltage VAIN Targets: ANI0 to ANI10 0 VDD V Target: Internal reference voltageNote 6 VREG Note 7 V Target: Temperature sensor output voltageNote 6 VTMPS25 Note 7 V Target: CTSU TSCAP voltage (2.4 V ≤ VDD ≤ 5.5 V) VTSCAP V Note 1. The TYP. value is an average value at TA = 25°C. The MAX. value is an average value ±3σ at normal distribution. Note 2. These values are the results of characteristic evaluation and are not checked for shipment. Note 3. A quantization error (±1/2 LSB) is not included. Note 4. Expressed as a ratio (%FSR) relative to the full-scale value. Note 5. Be sure to set the LV0 bit in A/D converter mode register 0 (ADM0) to 0 when conversion is done in the operating voltage range of 2.4 V ≤ VDD < 2.7 V. Note 6. Be sure to set the LV0 bit in A/D converter mode register 0 (ADM0) to 0 when the internal reference voltage, temperature sensor output voltage, or CTSU TSCAP voltage is selected as the target for conversion. Note 7. Refer to 2.6.3 Temperature sensor/internal reference voltage characteristics.

RL78/G16 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) R01DS0431EJ0130 Rev.1.30 Page 45 of 85 May 19, 2025 Caution 1. Arrange wiring and insert the capacitor so that no noise appears on the power supply/ground line. Caution 2. Do not allow any pulses that rapidly change such as digital signals to be input/output to/from the pins adjacent to the conversion pin during A/D conversion. Caution 3. Note that the internal reference voltage cannot be used as the reference voltage of the comparator when the internal reference voltage is selected as the target for A/D conversion.

2.6.2 Comparator characteristics

[TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Input voltage range IVREF IVREFn pin input (CnVRF bit = 0) 0 VDD − 1.4 V Internal reference voltage (CnVRF bit = 1) Note 1 VREG Note 2 V IVCMP IVCMPn pin input −0.3 VDD + 0.3 V Output delay td VDD = 3.0 V, input slew rate > 50 mV/μs High-speed mode 0.5 µs Low-speed mode 2.0 µs Operation stabilization wait time tCMP 100 µs Note 1. When the internal reference voltage is selected as the reference voltage of the comparator, the internal reference voltage cannot be used as the target for A/D conversion. Note 2. Refer to 2.6.3 Temperature sensor/internal reference voltage characteristics. Remark n: Channel number (n = 0, 1)

2.6.3 Temperature sensor/internal reference voltage characteristics

[TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Temperature sensor output voltage VTMPS25 1.05 V Internal reference voltage V REG 0.74 0.815 0.89 V Temperature coefficient F VTMPS Temperature dependence of the temperature sensor voltage −3.6 mV/°C Operation stabilization wait time t AMP A/D converter is used (ADS register = 0DH) 5 µs Caution The internal reference voltage cannot be simultaneously used by the A/D converter and the comparator; only one of them must be selected.

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2.6.4 SPOR circuit characteristics

[TA = −40 to +85°C, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Detection voltage Power supply voltage level VSPOR0 Power supply rising 4.08 4.28 4.45 V VSPDR0 Power supply falling 4.00 4.20 4.37 V VSPOR1 Power supply rising 2.76 2.90 3.02 V VSPDR1 Power supply falling 2.70 2.84 2.96 V VSPOR2 Power supply rising 2.44 2.57 2.68 V VSPDR2 Power supply falling 2.40 2.52 2.62 V VSPOR3 Power supply rising 2.16 V VSPDR3 Power supply falling 2.11 V Minimum pulse widthNote 1 TSPW 300 µs Note 1. Time required for the reset operation by the SPOR circuit when VDD falls below VSPDR. Caution Make sure to keep the internal reset state by the SPOR or an external reset until the power supply voltage (VDD) reaches the operating voltage range shown in 2.4 AC Characteristics.

2.6.5 Power supply voltage rising slope characteristics

[TA = −40 to +85°C, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Power supply voltage rising slope SVDD 54 V/ms Caution Make sure to keep the internal reset state by the SPOR or an external reset until the power supply voltage (VDD) reaches the operating voltage range shown in 2.4 AC Characteristics.

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2.7 RAM Data Retention Characteristics

[TA = −40 to +85°C, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Data retention power supply voltage VDDDR 1.9 5.5 V Caution Data in RAM is retained until the power supply voltage falls below the MIN. value of the data retention power supply voltage (VDDDR). Note that data in the RESF register might not be cleared even if the power supply voltage falls below the MIN. value of the data retention power supply voltage (VDDDR). STOP mode VDD VDDDR Rising of VSPOR SPOR reset period (Retain data in RAM and RESF) Falling of VSPDR STOP instruction execution Normal operation

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2.8 Flash Memory Programming Characteristics

[TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Number of code flash rewrites Note 1, Note 2 Cerwr Retained for 20 years TA = +85°C 1000 Times Number of data flash rewrites Note 1, Note 2 Retained for 1 year TA = +25°C 1,000,000 Times Retained for 5 years TA = +85°C 100,000 Times Retained for 20 years TA = +85°C 10,000 Times Note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. Note 2. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics. Code flash/data flash self-programming time [TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol fCLK = 1 MHz fCLK = 16 MHz Unit Writing (4 bytes) tP4 104 905 53.8 504.9 µs Block erasure (1 KB) tE1K 7.9 262.3 5.5 214.1 ms Caution The listed values do not include the time until the operations of the flash memory start following execution of an instruction by software.

2.9 Dedicated Flash Memory Programmer Communication (UART)

[TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Transfer rate 115,200 bps Remark The transfer rate during flash memory programming is fixed to 115,200 bps.

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2.10 Timing of Entry to Flash Memory Programming Mode

[TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Time to complete the communication for the initial setting after the external reset is released t SUINIT The SPOR reset must be released before the external reset is released. 100 ms Time to release the external reset after the TOOL0 pin is set to the low level t SU The SPOR reset must be released before the external reset is released. 10 µs Time to hold the TOOL0 pin at the low level after the external reset is released t HD The SPOR reset must be released before the external reset is released. 1 ms RESET TOOL0 tSUINIT tHD 1-byte data for setting mode tSU <4>

• • <1> The low level is input to the TOOL0 pin. <2> The external reset is released (the SPOR reset must have been released before that). <3> The TOOL0 pin is released from the low level. <4> Setting of entry to the flash memory programming mode by UART reception is completed. Remark tSUINIT: During this period, the communications for the initial setting must be completed within 100 ms after release from the reset. tSU: Time to release the external reset after the TOOL0 pin is set to the low level tHD: Time to hold the TOOL0 pin at the low level after the external reset is released

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 50 of 85 May 19, 2025 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) This chapter describes the electrical specifications of the following target products. Target product G: Industrial applications TA = −40 to +105°C Target product M: Industrial applications TA = −40 to +125°C Caution 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. Caution 2. The pins mounted depend on the product. Refer to 2.1 Port Function, for the port functions, and 2.2.1 Functions for each product, for the other functions, in the RL78/G16 User’s Manual. Remark When the products are used in the range of TA = −40 to +85°C, refer to 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C). However, there are differences in the high-speed on-chip oscillator clock accuracy between G: Industrial applications and M: Industrial applications, and A: Consumer applications. Classification A: Consumer applications G: Industrial applications M: Industrial applications High-speed on-chip oscillator clock accuracy ±2.0% when TA = −40 to +85°C ±1.5% when TA = +85 to +105°C ±1.0% when TA = −20 to +85°C ±1.5% when TA = −40 to −20°C ±1.5% when TA = +85 to +125°C ±1.0% when TA = −20 to +85°C ±1.5% when TA = −40 to −20°C

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3.1 Absolute Maximum Ratings

[TA = 25°C] Item Symbol Condition Rating Unit Supply voltage VDD −0.5 to +6.5 V Input voltage VI1 −0.3 to VDD + 0.3Note 1 V Output voltage VO1 −0.3 to VDD + 0.3 V Output current, high IOH1 Per pin −40 mA Total of all pins P06, P07, P20 to P23, P40 to P43, P121, P122, P125 −70 mA −170mA P00 to P05, P10 to P17 −100 mA Output current, low IOL1 Per pin 40 mA Total of all pins P06, P07, P20 to P23, P40 to P43, P121, P122, P125 100 mA 170mA P00 to P05, P10 to P17, P60, P61 100 mA Operating ambient temperature TA G products −40 to +105 °C M products −40 to +125 °C Storage temperature Tstg −65 to +150 °C Note 1. This must be no greater than 6.5 V. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any item. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark 1. The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified. Remark 2. The reference voltage is VSS.

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3.2 Oscillator Characteristics

3.2.1 X1 and XT1 oscillator characteristics

[TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Resonator Condition MIN. TYP. MAX. Unit X1 clock oscillation frequency (fx)Note 1 Ceramic resonator/ crystal resonator 2.4 V ≤ VDD ≤ 5.5 V 1 12 MHz XT1 clock oscillation frequency (fXT)Note 1 Crystal resonator 32 32.768 35 kHz Note 1. Indicates only permissible oscillator frequency ranges. Refer to 3.4 AC Characteristics for instruction execution time. For actual applications, request evaluation by the manufacturer of the oscillator circuit mounted on a board so you can use appropriate values. Caution Since the CPU is started by the high-speed on-chip oscillator clock after release from the reset state, the user should use the oscillation stabilization time counter status register (OSTC) to check the X1 clock oscillation stabilization time. Specify the values for the oscillation stabilization time in the OSTC register and the oscillation stabilization time select register (OSTS) after having sufficiently evaluated the oscillation stabilization time with the resonator to be used. Remark When using the X1 or XT1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/G16 User’s Manual.

3.2.2 On-chip oscillator characteristics

[TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit High-speed on-chip oscillator clock frequencyNote 1, Note 2 fIH 1 16 MHz High-speed on-chip oscillator clock frequency accuracy Low-speed on-chip oscillator clock frequency fIL 15 kHz Low-speed on-chip oscillator clock frequency accuracy −15 +15 % Note 1. The high-speed on-chip oscillator frequency is selected by bits 0 to 2 of option byte (00C2H) and bits 0 to 2 of the HOCODIV register. Note 2. The listed values only indicate the characteristics of the oscillators. Refer to 3.4 AC Characteristics for instruction execution time.

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3.3 DC Characteristics

3.3.1 Pin characteristics

[TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] (1/2) Item Symbol Condition MIN. TYP. MAX. Unit Output current, highNote 1 IOH1 Per pin for P00 to P07, P10 to P17, P20 to P23, P40 to P43, P121, P122, P125 −3.0 Note 2 mA Total of P06, P07, P20 to P23, P40 to P43, P121, P122, P125 (when duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V −25.0 mA 2.4 V ≤ VDD < 4.0 V −7.0 mA Total of P00 to P05, P10 to P17 (when duty ≤ 70%Note 3) 4.0 V ≤ VDD ≤ 5.5 V −24.0 mA 2.4 V ≤ VDD < 4.0 V −6.0 mA Total of all pins (when duty ≤ 70%Note 3) −40.0 mA Output current, low Note 4 IOL1 Per pin for P00 to P07, P10 to P17, P20 to P23, P40 to P43, P121, P122, P125 8.5Note 2 mA Per pin for P60, P61 15.0Note 2 mA Total of P06, P07, P20 to P23, P40 to P43, P121, P122, P125 (when duty ≤ 70% Note 3)

4.0 V ≤ VDD

≤ 5.5 V TA = −40 to +105°C 50.0Note 5 mA TA = −40 to +125°C 40.0 mA 2.7 V ≤ VDD < 4.0 V 10.5 mA 2.4 V ≤ VDD < 2.7 V 4.2 mA Total of P00 to P05, P10 to P17, P60, P61 (when duty ≤ 70%Note 3) ≤ 5.5 V TA = −40 to +105°C 50.0Note 5 mA TA = −40 to +125°C 40.0 mA 2.7 V ≤ VDD < 4.0 V 9.0 mA 2.4 V ≤ VDD < 2.7 V 3.6 mA Total of all pins (when duty ≤ 70%Note 3) TA = −40 to +105°C 80.0 mA TA = −40 to +125°C 60.0 mA Note 1. Device operation is guaranteed at the listed currents even if current is flowing from the VDD pin to an output pin. Note 2. The value for maximum total current must not be exceeded. Note 3. The listed currents apply when the duty cycle is no greater than 70%. Use the following formula to calculate the output current when the duty cycle is greater than 70%, where n is the duty cycle.  Total output current from the listed pins = (IOH × 0.7)/(n × 0.01) Example when n = 80% and IOH = –10.0 mA Total output current from the listed pins = (–10.0 × 0.7)/(80 × 0.01) ≅ –8.7 mA  Total output current from the listed pins = (IOL × 0.7)/(n × 0.01) Example when n = 80% and IOL = 10.0 mA Total output current from the listed pins = (10.0 × 0.7)/(80 × 0.01) ≅ 8.7 mA Note that the duty cycle has no effect on the current that is allowed to flow into a single pin. A current higher than the absolute maximum rating must not flow into a single pin.

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 54 of 85 May 19, 2025 Note 4. Device operation is guaranteed at the listed currents even if current is flowing from an output pin to the VSS pin. Note 5. When the multiplexed TSm pin is used as a mutual-capacitance transmit pin, the value is 40 mA. Caution P00, P01, P03 to P07, P14, P16, P17, P20, P22, and P41 do not output high level in N-ch open-drain mode. Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified.

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 55 of 85 May 19, 2025 [TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] (2/2) Item Symbol Condition MIN. TYP. MAX. Unit Input voltage, high VIH1 0.8 VDD VDD V VIH2 P60, P61 0.7 VDD 6.0 V Input voltage, low VIL1 0 0.2 VDD V VIL2 P60, P61 0 0.3 VDD V Output voltage, high Note 1 VOH1 4.0 V ≤ VDD ≤ 5.5 V IOH = −3.0 mA VDD − 0.7 V 2.4 V ≤ VDD ≤ 5.5 V IOH = −1.0 mA VDD − 0.5 V Output voltage, low Note 2 VOL1 4.0 V ≤ VDD ≤ 5.5 V IOL = 8.5 mA 0.7 V 2.7 V ≤ VDD ≤ 5.5 V IOL = 1.5 mA 0.5 V 2.4 V ≤ VDD ≤ 5.5 V IOL = 0.6 mA 0.4 V P60, P61 4.0 V ≤ VDD ≤ 5.5 V IOL = 15 mA 2.0 V IOL = 5 mA 0.4 V 5.5 V IOL = 3.0 mA 0.4 V IOL = 2.0 mA 0.4 V 5.5 V IOL = 1.0 mA 0.4 V Input leakage current, high ILIH1 P00 to P07, P10 to P17, P20 to P23, P40 to P43, P60, P61, P125, P137 V I＝VDD 1 µA ILIH2 P121, P122 (X1, X2, XT1, XT2, EXCLK, EXCLKS) VI = VDD In input port or external clock input 1 µA In resonator connection 10 µA Input leakage current, low ILIL1 P00 to P07, P10 to P17, P20 to P23, P40 to P43, P60, P61, P125, P137 V I = VSS −1 µA ILIL2 P121, P122 (X1, X2, XT1, XT2, EXCLK, EXCLKS) VI = VSS In input port or external clock input −1 µA In resonator connection −10 µA On-chip pull-up resistance RU Except P60 and P61 VI = VSS 10 20 100 kΩ Note 1. The value under the condition which satisfies the high-level output current (IOH1). Note 2. The value under the condition which satisfies the low-level output current (IOL1). Caution The maximum value of VIH of P00, P01, P03 to P07, P14, P16, P17, P20, P22, and P41 is VDD even in N- ch open-drain mode. These pins do not output high level in N-ch open-drain mode. Remark The characteristics of functions multiplexed on a given pin are the same as those for the port pin unless otherwise specified.

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 56 of 85 May 19, 2025

3.3.2 Supply current characteristics

[TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Supply currentNote 1 IDD1 Operating mode Basic operation f IH = 16 MHzNote 4 VDD = 3.0 V, 5.0 V 0.97 mA Normal operation fIH = 16 MHzNote 4 VDD = 3.0 V, 5.0 V 2.11 2.78 mA fIH = 4 MHzNote 4 VDD = 3.0 V, 5.0 V 1.22 1.65 mA fEX = 16 MHzNote 5, Note 6 VDD = 3.0 V, 5.0 V Square wave input 1.97 2.64 mA fX = 12 MHzNote 5, Note 6 VDD = 3.0 V, 5.0 V Resonator connection 1.79 2.51 mA fMX = 4 MHzNote 5, Note 6 VDD = 3.0 V, 5.0 V Square wave input 1.07 1.5 mA Resonator connection 1.12 1.56 mA fSUB = 32.768 kHzNote 7 TA = −40°C Square wave input 3.65 5.80 µA Resonator connection 3.70 6.00 µA fSUB = 32.768 kHzNote 7 TA = +25°C Square wave input 3.90 5.80 µA Resonator connection 4.18 6.00 µA fSUB = 32.768 kHzNote 7 TA = +50°C Square wave input 4.04 6.20 µA Resonator connection 4.37 6.40 µA fSUB = 32.768 kHzNote 7 TA = +70°C Square wave input 4.20 6.50 µA Resonator connection 4.56 6.70 µA fSUB = 32.768 kHzNote 7 TA = +85°C Square wave input 4.40 7.80 µA Resonator connection 4.80 8.00 µA fSUB = 32.768 kHzNote 7 TA = +105°C Square wave input 4.92 9.12 µA Resonator connection 5.36 9.32 µA fSUB = 32.768 kHzNote 7 TA = +125°C Square wave input 6.14 15.37 µA Resonator connection 6.60 15.57 µA

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 57 of 85 May 19, 2025 Item Symbol Condition MIN. TYP. MAX. Unit Supply currentNote 1 IDD2Note 2 HALT mode fIH = 16 MHzNote 4 VDD = 3.0 V, 5.0 V 385 824 µA fIH = 4 MHzNote 4 VDD = 3.0 V, 5.0 V 334 637 µA fEX = 16 MHzNote 5, Note 6 VDD = 3.0 V, 5.0 V Square wave input 229 669 µA fX = 12 MHzNote 5, Note 6 VDD = 3.0 V, 5.0 V Resonator connection 351 960 µA fMX = 4 MHzNote 5, Note 6 VDD = 3.0 V, 5.0 V Square wave input 167 459 µA Resonator connection 226 620 µA fSUB = 32.768 kHzNote 8 TA = −40°C Square wave input 0.69 1.45 µA Resonator connection 0.75 1.65 µA fSUB = 32.768 kHzNote 8 TA = +25°C Square wave input 0.75 1.45 µA Resonator connection 1.04 1.65 µA fSUB = 32.768 kHzNote 8 TA = +50°C Square wave input 0.84 1.74 µA Resonator connection 1.20 1.94 µA fSUB = 32.768 kHzNote 8 TA = +70°C Square wave input 0.97 2.20 µA Resonator connection 1.33 2.40 µA fSUB = 32.768 kHzNote 8 TA = +85°C Square wave input 1.13 3.10 µA Resonator connection 1.51 3.30 µA fSUB = 32.768 kHzNote 8 TA = +105°C Square wave input 1.58 8.92 µA Resonator connection 1.99 9.12 µA fSUB = 32.768 kHzNote 8 TA = +125°C Square wave input 2.68 10.67 µA Resonator connection 3.12 10.87 µA IDD3Note 3 STOP modeNote 9 VDD = 3.0 V TA = +105°C 0.62 4.12 µA TA = +125°C 0.62 10.37 µA Note 1. The listed currents are the total currents flowing into VDD, including the input leakage currents flowing when the level of the input pin is fixed to VDD or VSS. Regarding the values for main system clock operation, the TYP. value does not include the peripheral operating current. The MAX. value includes the peripheral operating current, but does not include those flowing into the A/D converter, comparator, capacitive touch sensing unit (CTSU), I/O port, and on-chip pull- up/pull-down resistors. Regarding the values for subsystem clock operation, the TYP. and MAX. values do not include the peripheral operating current. However, in HALT mode, the current flowing into the RTC is included. Regarding the values in STOP mode, the TYP. and MAX. values do not include the peripheral operating current. Note 2. When the HALT instruction is executed from the flash memory. Note 3. The listed currents do not include the current flowing into real-time clock 2, the clock output/buzzer output controller, 12-bit interval timer, and watchdog timer. Note 4. When the high-speed system clock and subsystem clock are stopped. Note 5. When the high-speed on-chip oscillator and subsystem clock are stopped. Note 6. 16-pin, 20-pin, 24-pin, and 32-pin products only. Note 7. When the high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (ultra- low power consumption oscillation). However, not including the current flowing into real-time clock 2, the 12- bit interval timer, watchdog timer, and capacitive touch sensing unit.

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 58 of 85 May 19, 2025 Note 8. When the high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and AMPHS1 = 1 (ultra-low power consumption oscillation). Note 9. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode. Remark 1. fIH: High-speed on-chip oscillator clock frequency Remark 2. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 3. Except for subsystem clock operation, the temperature condition of the TYP. value is TA = 25°C. Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 59 of 85 May 19, 2025 Peripheral Functions [TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Low-speed on-chip oscillator operating current IFIL Note 1 0.30 µA RTC2 operating current IRTC Note 1, Note 2, Note 8 fSUB = 32.768 kHz 0.02 µA 12-bit interval timer operating current ITMKA Note 1, Note 2, Note 3 0.02 µA Watchdog timer operating current IWDT Note 1, Note 4 0.02 µA A/D converter operating current IADC Note 1, Note 5 In conversion at maximum speed VDD = 5.0 V 1.30 1.90 mA VDD = 3.0 V 0.50 mA Temperature sensor operating current ITMPS Note 1 75.0 µA Comparator operating current ICMP Note 1, Note 6 In high-speed mode VDD = 5.0 V 6.50 µA In low-speed mode VDD = 5.0 V 1.70 µA Internal reference voltage operating current I VREG Note 1 10 µA Self-programming operating current IFSP Note 1, Note 7 2.0 12.20 mA Note 1. The current flowing into VDD. Note 2. When the high-speed on-chip oscillator and high-speed system clock are stopped. Note 3. This current only flows into the 12-bit interval timer. It does not include the operating current of the low-speed on-chip oscillator and XT1 oscillator. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IFIL and ITMKA when the 12-bit interval timer is in operation. Note 4. This current only flows into the watchdog timer. It does not include the operating current of the low-speed on- chip oscillator. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IFIL and IWDT when the watchdog timer is in operation. Note 5. This current only flows into the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter is operating or in the HALT mode. Note 6. This current only flows into a single comparator. The supply current of the RL78 microcontrollers is the sum of I DD1, IDD2 or IDD3 and ICMP when the comparator is in operation. Note 7. This current only flows during self-programming. Note 8. This current only flows into real-time clock 2. It does not include the operating current of the low-speed on- chip oscillator and XT1 oscillator. The supply current of the RL78 microcontrollers is the sum of the values of either I DD1 or IDD2, and IRTC, when real-time clock 2 operates in operation mode or HALT mode. When the low- speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of real-time clock 2. Remark The temperature condition of the TYP. value is TA = 25°C.

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 60 of 85 May 19, 2025

3.4 AC Characteristics

[TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Instruction cycle (minimum instruction execution time) TCY When high-speed on-chip oscillator clock (fIH) is selected 2.4 V ≤ VDD ≤ 5.5 V 0.0625 1.0 µs When high-speed system clock (fMX) is selected 2.4 V ≤ VDD ≤ 5.5 V 0.0833 1.0 µs Subsystem clock (fSUB) operation In the self-programming mode 2.4 V ≤ VDD ≤ 5.5 V 0.0625 1.0 µs External system clock frequency fEX 2.4 V ≤ VDD ≤ 5.5 V 1.0 16 MHz External system clock input high-level width, low-level width tEXH, tEXL 2.4 V ≤ VDD ≤ 5.5 V 30 ns TI00 to TI07 input high-level width, low-level width tTIH, tTIL Noise filter is not used 1/fMCK + 10 ns TO00 to TO07 output frequency fTO 4.0 V ≤ VDD ≤ 5.5 V 8 MHz 2.7 V ≤ VDD < 4.0 V 5 MHz 2.4 V ≤ VDD < 2.7 V 4 MHz PCLBUZ0 output frequency fPCL 4.0 V ≤ VDD ≤ 5.5 V 10 MHz 2.7 V ≤ VDD < 4.0 V 5 MHz 2.4 V ≤ VDD < 2.7 V 4 MHz RESET¯¯¯¯¯¯ low-level width tRSL 10 µs Remark fMCK: Timer array unit operating clock frequency (Operation clock to be set by timer clock select register 0 (TPS0) and the CKS0n1 bit of timer mode register 0n (TMR0n). n: Channel number (n = 0 to 7).)

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 61 of 85 May 19, 2025 Minimum Instruction Execution Time during Main System Clock Operation 1.0 0.1 Supply voltage VDD [V] 5.52.4 0.01 0.05 0.2 0.8 TCY vs VDD  When the high-speed on-chip oscillator clock is selected  During self-programming  When the high-speed system clock is selected Cycle time TCY [µs] At AC Timing VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL External System Clock Timing 1/fEX tEXL tEXH EXCLK

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 62 of 85 May 19, 2025 TI/TO Timing tTIL tTIH 1/fTO TI00 to TI07 TO00 to TO07 tRSL RESET

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 63 of 85 May 19, 2025

3.5 Serial Interface Characteristics

3.5.1 Serial array unit

(1) UART mode [TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Transfer rate fMCK/12 bps Theoretical value of the maximum transfer rate fCLK = fMCK = 16 MHz

1.3 Mbps

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 64 of 85 May 19, 2025 (2) Simplified SPI (CSI) mode (master mode, SCKp... internal clock output) [TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 2.7 V ≤ VDD ≤ 5.5 V 250 ns 2.4 V ≤ VDD ≤ 5.5 V 500 ns SCKp high-/low-level width tKH1, tKL1 2.7 V ≤ VDD ≤ 5.5 V tKCY1/2 − 36 ns 2.4 V ≤ VDD ≤ 5.5 V tKCY1/2 − 76 ns SIp setup time (to SCKp ↑)Note 1 tSIK1 2.7 V ≤ VDD ≤ 5.5 V 66 ns 2.4 V ≤ VDD ≤ 5.5 V 113 ns SIp hold time (from SCKp ↑) Note 1 tKSI1 38 ns Delay time from SCKp ↓ to SOp outputNote 2 tKSO1 C = 30 pFNote 3, Note 4 66 ns Note 1. When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The SIp setup time becomes “to SCKp ↓” and the SIp hold time becomes “from SCKp ↓” when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = Note 2. When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The delay time to SOp output becomes “from SCKp ↓” when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = 0. Note 3. C is the load capacitance of the SCKp and SOp output lines. Note 4. External loads on P60 and P61 in the case of the SOp output line: R = 1 kΩ, C = 30 pF (3) Simplified SPI (CSI) mode (slave mode, SCKp... external clock input) [TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit SCKp cycle time tKCY2 2.7 V ≤ VDD ≤ 5.5 V 12/fMCK ns 2.4 V ≤ VDD ≤ 5.5 V 12/fMCK and also 1000 ns SCKp high-/low-level width tKH2,tKL2 2.7 V ≤ VDD ≤ 5.5 V tKCY2/2 − 16 ns 2.4 V ≤ VDD ≤ 5.5 V tKCY2/2 − 36 ns SIp setup time (to SCKp ↑)Note 1 tSIK2 2.7 V ≤ VDD ≤ 5.5 V 1/fMCK + 40 ns 2.4 V ≤ VDD ≤ 5.5 V 1/fMCK + 60 ns SIp hold time (from SCKp ↑) Note 1 tKSI2 2.4 V ≤ VDD ≤ 5.5 V 1/fMCK + 62 ns Delay time from SCKp ↓ to SOp output Note 2 tKSO2 C = 30 pF Note 3, Note 4 2.7 V ≤ VDD ≤ 5.5 V 2/fMCK + 66 ns 2.4V ≤ VDD ≤ 5.5V 2/fMCK + 113 ns Note 1. When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The SIp setup time becomes “to SCKp ↓” and the SIp hold time becomes “from SCKp ↓” when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = Note 2. When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The delay time to SOp output becomes “from SCKp ↓” when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = 0.

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 65 of 85 May 19, 2025 Note 3. C is the load capacitance of the SOp output lines. Note 4. External loads on P60 and P61 in the case of the SOp output line: R = 1 kΩ, C = 30 pF Remark 1. p: CSI number (p = 00, 11, 20), n: Channel number (n = 0, 1) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by serial clock select register 0 (SPS0) and the CKS0n bit of serial mode register 0n (SMR0n). n: Channel number (n = 0, 1)) Simplified SPI (CSI) mode connection diagram RL78 microcontroller User device SCKp SOp SCK SI SIp SO Simplified SPI (CSI) mode serial transfer timing (When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1) Input dataSIp SOp tKCY1, 2 tKL1, 2 tKH1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 SCKp Output data Remark p: CSI number (p = 00, 11, 20), n: Channel number (n = 0, 1)

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 66 of 85 May 19, 2025 (4) Simplified I2C mode [TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. MAX. Unit SCLr clock frequency fSCL 2.7 V ≤ VDD ≤ 5.5 V Cb = 100 pF, Rb = 3 kΩ 400Note 1 kHz 2.4 V ≤ VDD ≤ 5.5 V Cb = 100 pF, Rb = 3 kΩ 100Note 1 kHz Hold time when SCLr = “L” tLOW 2.7 V ≤ VDD ≤ 5.5 V Cb = 100 pF, Rb = 3 kΩ 1200 ns 2.4 V ≤ VDD ≤ 5.5 V Cb = 100 pF, Rb = 3 kΩ 4600 ns Hold time when SCLr = “H” tHIGH 2.7 V ≤ VDD ≤ 5.5 V Cb = 100 pF, Rb = 3 kΩ 1200 ns 2.4 V ≤ VDD ≤ 5.5 V Cb = 100 pF, Rb = 3 kΩ 4600 ns Data setup time (reception) tSU:DAT 2.7 V ≤ VDD ≤ 5.5 V Cb = 100 pF, Rb = 3 kΩ 1/fMCK + 220Note 2 ns 2.4 V ≤ VDD ≤ 5.5 V Cb = 100 pF, Rb = 3 kΩ 1/fMCK + 580Note 2 ns Data hold time (transmission) tHD:DAT 2.7 V ≤ VDD ≤ 5.5 V Cb = 100 pF, Rb = 3 kΩ 0 770 ns 2.4 V ≤ VDD ≤ 5.5 V Cb = 100 pF, Rb = 3 kΩ 0 1420 ns Note 1. The value must also be no greater than fMCK/4. Note 2. Set fMCK so that it will not exceed the hold time when SCLr = “L” or SCLr = “H”. Caution Select the N-ch open drain output (VDD tolerance) mode for the SDAr pin by using port output mode register 0, 1, 2, 4, or 6 (POM0, 1, 2, 4, or 6). Simplified I2C mode connection diagram RL78 microcontroller User device SDAr SCLr SDA SCL VDD Rb

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 67 of 85 May 19, 2025 Simplified I2C mode serial transfer timing SDAr tLOW 1/fSCL tHIGH tHD:DAT SCLr tSU:DAT Remark 1. Rb[Ω]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SCLr, SDAr) load capacitance Remark 2. r: IIC number (r = 00, 11, 20) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by serial clock select register 0 (SPS0) and the CKS0n bit of serial mode register 0n (SMR0n). n: Channel number (n = 0, 1))

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 68 of 85 May 19, 2025

3.5.2 Serial interface IICA

[TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition Standard Mode Fast Mode Unit MIN. MAX. MIN. MAX. SCLA0 clock frequency fSCL Fast mode: fCLK ≥ 3.5 MHz 0 400 kHz Standard mode: fCLK ≥ 1 MHz 0 100 kHz Setup time of restart condition tSU:STA 4.7 0.6 µs Hold timeNote 1 tHD:STA 4.0 0.6 µs Hold time when SCLA0 = “L” tLOW 4.7 1.3 µs Hold time when SCLA0 = “H” tHIGH 4.0 0.6 µs Data setup time (reception) tSU:DAT 250 100 ns Data hold time (transmission)Note 2 tHD:DAT 0 3.45 0 0.9 µs Setup time of stop condition tSU:STO 4.0 0.6 µs Bus-free time tBUF 4.7 1.3 µs Note 1. The first clock pulse is generated after this period when the start or restart condition is detected. Note 2. The maximum value (MAX.) of tHD:DAT applies to normal transfer and a wait is inserted at the ACK (acknowledge) timing. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistance) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 kΩ Fast mode: Cb = 200 pF, Rb = 1.7 kΩ IICA serial transfer timing tLOW tR tHIGH tF tHD:STA tBUF Stop condition tHD:DAT SCLA0 SDAA0 Start condition Restart condition Stop condition tSU:DAT tSU:STA tHD:STA tSU:STO

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 69 of 85 May 19, 2025

3.6 Analog Characteristics

3.6.1 A/D converter characteristics

Targets: ANI0 to ANI10, internal reference voltage, temperature sensor output voltage, and CTSU TSCAP voltage [TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Resolution RES 8 10 bit Overall errorNote 1, Note 2, Note 3 AINL 10-bit resolution VDD = 5 V ±1.7 ±3.1 LSB VDD = 3 V ±2.3 ±4.5 LSB Conversion time tCONV 10-bit resolution Targets: ANI0 to ANI10 2.7 V ≤ VDD ≤ 5.5 V 4.25 17 µs 2.4 V ≤ VDD ≤ 5.5 V Note 5 5.75 23 µs 10-bit resolution Target: Internal reference voltageNote 6 Target: Temperature sensor output voltage Note 6 Target: CTSU TSCAP voltage Note 6 2.4 V ≤ VDD ≤ 5.5 V 5.75 23 µs Zero-scale error Note 1, Note 2, Note 3, Note 4 EZS 10-bit resolution VDD = 5 V ±0.19 %FSR VDD = 3 V ±0.39 %FSR Full-scale error Note 1, Note 2, Note 3, Note 4 EFS 10-bit resolution VDD = 5 V ±0.29 %FSR VDD = 3 V ±0.42 %FSR Integral linearity error Note 1, Note 2, Note 3 ILE 10-bit resolution VDD = 5 V ±1.8 LSB VDD = 3 V ±1.7 LSB Differential linearity error Note 1, Note 2, Note 3 DLE 10-bit resolution VDD = 5 V ±1.4 LSB VDD = 3 V ±1.5 LSB Analog input voltage VAIN Targets: ANI0 to ANI10 0 VDD V Target: Internal reference voltageNote 6 VREG Note 7 V Target: Temperature sensor output voltageNote 6 VTMPS25 Note 7 V Target: CTSU TSCAP voltage (2.4 V ≤ VDD ≤ 5.5 V) VTSCAP V Note 1. The TYP. value is an average value at TA = 25°C. The MAX. value is an average value ±3σ at normal distribution. Note 2. These values are the results of characteristic evaluation and are not checked for shipment. Note 3. A quantization error (±1/2 LSB) is not included. Note 4. Expressed as a ratio (%FSR) relative to the full-scale value. Note 5. Be sure to set the LV0 bit in A/D converter mode register 0 (ADM0) to 0 when conversion is done in the operating voltage range of 2.4 V ≤ VDD < 2.7 V. Note 6. Be sure to set the LV0 bit in A/D converter mode register 0 (ADM0) to 0 when the internal reference voltage, temperature sensor output voltage, or CTSU TSCAP voltage is selected as the target for conversion. Note 7. Refer to 3.6.3 Temperature sensor/internal reference voltage characteristics.

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 70 of 85 May 19, 2025 Caution 1. Arrange wiring and insert the capacitor so that no noise appears on the power supply/ground line. Caution 2. Do not allow any pulses that rapidly change such as digital signals to be input/output to/from the pins adjacent to the conversion pin during A/D conversion. Caution 3. Note that the internal reference voltage cannot be used as the reference voltage of the comparator when the internal reference voltage is selected as the target for A/D conversion.

3.6.2 Comparator characteristics

[TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Input voltage range IVREF IVREFn pin input (CnVRF bit = 0) 0 VDD − 1.4 V Internal reference voltage (CnVRF bit = 1) Note 1 VREG Note 2 V IVCMP IVCMPn pin input −0.3 VDD + 0.3 V Output delay td VDD = 3.0 V, input slew rate > 50 mV/μs High-speed mode 0.5 µs Low-speed mode 2.0 µs Operation stabilization wait time tCMP 100 µs Note 1. When the internal reference voltage is selected as the reference voltage of the comparator, the internal reference voltage cannot be used as the target for A/D conversion. Note 2. Refer to 3.6.3 Temperature sensor/internal reference voltage characteristics. Remark n: Channel number (n = 0, 1)

3.6.3 Temperature sensor/internal reference voltage characteristics

[TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Temperature sensor output voltage VTMPS25 1.05 V Internal reference voltage V REG 0.74 0.815 0.89 V Temperature coefficient F VTMPS Temperature dependence of the temperature sensor voltage −3.6 mV/°C Operation stabilization wait time t AMP A/D converter is used (ADS register = 0DH) 5 µs Caution The internal reference voltage cannot be simultaneously used by the A/D converter and the comparator; only one of them must be selected.

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 71 of 85 May 19, 2025

3.6.4 SPOR circuit characteristics

[TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Detection voltage Power supply voltage level VSPOR0 Power supply rising 4.08 4.28 4.45 V VSPDR0 Power supply falling 4.00 4.20 4.37 V VSPOR1 Power supply rising 2.76 2.90 3.02 V VSPDR1 Power supply falling 2.70 2.84 2.96 V VSPOR2 Power supply rising 2.44 2.57 2.68 V VSPDR2 Power supply falling 2.40 2.52 2.62 V VSPOR3 Power supply rising 2.16 V VSPDR3 Power supply falling 2.11 V Minimum pulse widthNote 1 TSPW 300 µs Note 1. Time required for the reset operation by the SPOR circuit when VDD falls below VSPDR. Caution Make sure to keep the internal reset state by the SPOR or an external reset until the power supply voltage (VDD) reaches the operating voltage range shown in 3.4 AC Characteristics.

3.6.5 Power supply voltage rising slope characteristics

[TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Power supply voltage rising slope SVDD 54 V/ms Caution Make sure to keep the internal reset state by the SPOR or an external reset until the power supply voltage (VDD) reaches the operating voltage range shown in 3.4 AC Characteristics.

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 72 of 85 May 19, 2025

3.7 RAM Data Retention Characteristics

[TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Data retention power supply voltage VDDDR 1.9 5.5 V Caution Data in RAM is retained until the power supply voltage falls below the MIN. value of the data retention power supply voltage (VDDDR). Note that data in the RESF register might not be cleared even if the power supply voltage falls below the MIN. value of the data retention power supply voltage (VDDDR). STOP mode VDD VDDDR Rising of VSPOR SPOR reset period (Retain data in RAM and RESF) Falling of VSPDR STOP instruction execution Normal operation

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 73 of 85 May 19, 2025

3.8 Flash Memory Programming Characteristics

[TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Number of code flash rewrites Note 1, Note 2 Cerwr Retained for 20 years TA = +85°CNote 3 1000 Times Number of data flash rewrites Note 1, Note 2 Retained for 1 year TA = +25°C 1,000,000 Times Retained for 5 years TA = +85°CNote 3 100,000 Times Retained for 20 years TA = +85°CNote 3 10,000 Times Note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. Note 2. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics. Note 3. This temperature is the average value at which data are retained. Code flash/data flash self-programming time [TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol fCLK = 1 MHz fCLK = 16 MHz Unit Writing (4 bytes) tP4 104 905 53.8 504.9 µs Block erasure (1 KB) tE1K 7.9 262.3 5.5 214.1 ms Caution The listed values do not include the time until the operations of the flash memory start following execution of an instruction by software.

3.9 Dedicated Flash Memory Programmer Communication (UART)

[TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Transfer rate 115,200 bps Remark The transfer rate during flash memory programming is fixed to 115,200 bps.

RL78/G16 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) R01DS0431EJ0130 Rev.1.30 Page 74 of 85 May 19, 2025

3.10 Timing of Entry to Flash Memory Programming Mode

[TA = −40 to +105°C: G products, TA = −40 to +125°C: M products, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V] Item Symbol Condition MIN. TYP. MAX. Unit Time to complete the communication for the initial setting after the external reset is released t SUINIT The SPOR reset must be released before the external reset is released. 100 ms Time to release the external reset after the TOOL0 pin is set to the low level t SU The SPOR reset must be released before the external reset is released. 10 µs Time to hold the TOOL0 pin at the low level after the external reset is released t HD The SPOR reset must be released before the external reset is released. 1 ms RESET TOOL0 tSUINIT tHD 1-byte data for setting mode tSU <4>

• • <1> The low level is input to the TOOL0 pin. <2> The external reset is released (the SPOR reset must have been released before that). <3> The TOOL0 pin is released from the low level. <4> Setting of entry to the flash memory programming mode by UART reception is completed. Remark tSUINIT: During this period, the communications for the initial setting must be completed within 100 ms after release from the reset. tSU: Time to release the external reset after the TOOL0 pin is set to the low level tHD: Time to hold the TOOL0 pin at the low level after the external reset is released

RL78/G16 4. PACKAGE DRAWINGS R01DS0431EJ0130 Rev.1.30 Page 75 of 85 May 19, 2025 4. PACKAGE DRAWINGS 4.1 10-pin products R5F1211CMSP, R5F1211CGSP, R5F1211CASP R5F1211AMSP, R5F1211AGSP, R5F1211AASP

RL78/G16 4. PACKAGE DRAWINGS R01DS0431EJ0130 Rev.1.30 Page 76 of 85 May 19, 2025 4.2 16-pin products R5F1214CMSP, R5F1214CGSP, R5F1214CASP R5F1214AMSP, R5F1214AGSP, R5F1214AASP

RL78/G16 4. PACKAGE DRAWINGS R01DS0431EJ0130 Rev.1.30 Page 77 of 85 May 19, 2025 R5F1214CMNA, R5F1214CGNA, R5F1214CANA R5F1214AMNA, R5F1214AGNA, R5F1214AANA

RL78/G16 4. PACKAGE DRAWINGS R01DS0431EJ0130 Rev.1.30 Page 78 of 85 May 19, 2025 4.3 20-pin products R5F1216CMSP, R5F1216CGSP, R5F1216CASP R5F1216AMSP, R5F1216AGSP, R5F1216AASP

RL78/G16 4. PACKAGE DRAWINGS R01DS0431EJ0130 Rev.1.30 Page 79 of 85 May 19, 2025 R5F1216CMSM, R5F1216CASM <R>

RL78/G16 4. PACKAGE DRAWINGS R01DS0431EJ0130 Rev.1.30 Page 80 of 85 May 19, 2025 4.4 24-pin products R5F1217CMNA, R5F1217CGNA, R5F1217CANA R5F1217AMNA, R5F1217AGNA, R5F1217AANA

RL78/G16 4. PACKAGE DRAWINGS R01DS0431EJ0130 Rev.1.30 Page 81 of 85 May 19, 2025 4.5 32-pin products R5F121BCMFP, R5F121BCGFP, R5F121BCAFP R5F121BAMFP, R5F121BAGFP, R5F121BAAFP

RL78/G16 4. PACKAGE DRAWINGS R01DS0431EJ0130 Rev.1.30 Page 82 of 85 May 19, 2025 R5F121BCMNA, R5F121BCGNA, R5F121BCANA R5F121BAMNA, R5F121BAGNA, R5F121BAANA

R01DS0431EJ0130 Rev.1.30 Page 83 of 85 May 19, 2025 REVISION HISTORY RL78/G16 Datasheet

REVISION HISTORY

Description

Rev. Date Page Summary

1.00 Apr 28, 2023  First edition issued

1.10 Aug 31, 2023 1. OUTLINE p.1 1.1 Features: Features of the high-speed on-chip oscillator, modified p.2 1.1 Features: Features of the capacitive touch sensing unit (CTSUb), modified p.3 Figure 1-1. Part Number, Memory Size, and Package of RL78/G16: #06 and #07 were added to the packaging specifications p.4 Table 1-1. List of Ordering Part Numbers: Packaging Specifications, modified p.5 1.3.1 10-pin products: The pin connection diagram of the 10-pin plastic LSSOP, modified p.6 to p.8 1.3.2 16-pin products: The pin connection diagrams of the 16-pin plastic SSOP and the 16- pin plastic HWQFN, modified. Remark 3, added. modified. The pin connection diagram, modified. p.9, p.10 Table 1-4. Multiplexed Functions of 20-pin Products: The heading of Pin No., modified Remark 3, added. p.12, p.13 Table 1-5. Multiplexed Functions of 24-pin Products: The heading of Pin No., modified The pin connection diagram of the 32-pin plastic LQFP, modified. Remark 3, added. 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) p.26 2. ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C): The description, modified. Remark, added. p.32 2.3.2 Supply current characteristics: The unit in the list (condition: fSUB = 32.768 kHz), modified 3. ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C) p.50 3 ELECTRICAL SPECIFICATIONS (TA = −40 to +105°C, TA = −40 to +125°C): Remark, added modified 1.20 Jan 31, 2024 1. OUTLINE p.3 Figure 1-1. Part Number, Memory Size, and Package of RL78/G16: ROM number, added. Packaging Specifications, modified p.4 Table 1-1. List of Ordering Part Numbers: Packaging Specifications, modified 1.30 May 19, 2025 1. OUTLINE p.2 1.1 Features: The mutual capacitance method of the capacitive touch sensing unit (CTSUb), modified p.3 Figure 1-1. Part Number, Memory Size, and Package of RL78/G16: Part No., packaging specifications, package type, and Note 1, modified p.4 Table 1-1. List of Ordering Part Numbers: TSSOP package, added p.9, p.10 1.3.3 20-pin products: TSSOP, added 4. PACKAGE DRAWINGS p.79 4.3 20-pin products: PTSP0020JI-A package drawing, added

General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system- evaluation test for the given product.

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Product Information

PLSP0010JA-A specifications and overview.

Summary

RENESAS MCU Rev.1.30 May 19, 2025

Description

RENESAS MCU Rev.1.30 May 19, 2025

Source title PLSP0010JA-A Datasheet(PDF) - Renesas Technology Corp

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