PLSF0108QWRKSRQ1

LSF0108-Q1_V01 TI | Alldatasheet

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Technical content

LSF0108-Q1 Automotive 8-Channel Multi-Voltage Level Translator

1 Features

AEC-Q100 qualified with the following results: – Device HBM ESD classification level 2000-V – Device CDM ESD classification level 1000-V
Available in wettable flank VQFN (RKS) package
Provides bidirectional voltage translation with no direction pin
Supports up to 100 MHz up translation and greater than 100 MHz down translation at ≤ 30-pF capacitive load and up to 40 MHz up or down translation at 50-pF capacitive load
Supports hot insertion
Allow bidirectional voltage level translation between – 2.5 V ↔ 3.3 V, 5 V – 3.3 V ↔ 5 V
Low standby current
5-V tolerance I/O port to support TTL
Low ron provides less signal distortion
High-impedance I/O pins for EN = low
Flow-through pinout for easy PCB trace routing
Latch-up performance exceeds 100 mA per JESD
–40°C to +125°C operating temperature range Vref_AVref_B219345620EN18171615 1GND A1A2A3A4B1B2B3B4SW7891014131211A5A6A7A8B5B6B7B8 LSF0108-Q1SWSWSWSWSWSWSW Functional Block Diagram

2 Applications

GPIO, MDIO, PMBus, SMBus, SDIO, UART, I2C, and other interfaces in telecom infrastructure
Infotainment and cluster
Body electronics and lighting
Hybrid, electric, and powertrain systems
Passive safety
ADAS

3 Description

Supports up to 100 MHz up translation and greater than 100 MHz down translation at ≦ 30 pF cap load and up to 40 MHz up and down translation at 50 pF capacitive load: – Allows the LSF family to support more consumer or telecom interfaces (MDIO or SDIO)
Bidirectional voltage translation without DIR pin: – Minimizes system effort to develop voltage translation for bidirectional interface (PMBus, I2C, or SMbus)
5 V tolerance on IO port and 125°C support: – With 5 V tolerance and 125°C support, the LSF family is flexible and compliant with TTL levels in industrial and telecom applications
Channel specific translation: – The LSF family is able to set up different voltage translation levels on each channel Package Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LSF0108-Q1 PW (TSSOP, 20) 4.40 mm × 6.50 mm RKS (VQFN, 20)(2) 4.50 mm × 2.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Preview package LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

6.6 Switching Characteristics (Translating Down),

6.7 Switching Characteristics (Translating Down),

6.8 Switching Characteristics (Translating Up),

6.9 Switching Characteristics (Translating Up),

12.1 Receiving Notification of Documentation Updates..22

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (April 2021) to Revision E (November 2022) Page

Added the Auto Bidirectional Voltage Translation, Output Enable, Wettable Flanks, Up and Down Translation, Bias Circuitry, Mixed-Mode Voltage Translation, Single Supply Translation, and Voltage Translation for Vref_B Changes from Revision C (July 2018) to Revision D (April 2021) Page Changes from Revision B (June 2016) to Revision C (July 2018) Page Changes from Revision A (May 2016) to Revision B (June 2016) Page
Changed ANSI/ESDA/JEDEC JS-001 to AEC-Q100 - 002 and JEDEC specification JESD22- V C101 to LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 www.ti.com

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Changes from Revision * (May 2016) to Revision A (May 2016) Page www.ti.com LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LSF0108-Q1

5 Pin Configuration and Functions

All packages are on the same relative scale EN Vref_A Vref_B GND Figure 5-1. PW Package, 20-Pin TSSOP (Transparent Top View) Thermal Pad GND Vref_A EN Vref_B Figure 5-2. RKS (Preview) Package, 20-Pin VQFN (Transparent Top View) Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. A1 3 I/O Data port A2 4 I/O Data port A3 5 I/O Data port A4 6 I/O Data port A5 7 I/O Data port A6 8 I/O Data port A7 9 I/O Data port A8 10 I/O Data port B1 18 I/O Data port B2 17 I/O Data port B3 16 I/O Data port B4 15 I/O Data port B5 14 I/O Data port B6 13 I/O Data port B7 12 I/O Data port B8 11 I/O Data port EN 20 I Switch enable input; connect to Vref_B and pull-up through a high resistor (200 kΩ). GND 1 — Ground Vref_A 2 — Reference supply voltage A. For more information, see Application and Implementation section. Vref_B 19 — Reference supply voltage B. For more information, see Application and Implementation section. (1) I = input, O = output LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 www.ti.com

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)(1) MIN MAX UNIT VI Input voltage(2) –0.5 7 V VI/O Input/output voltage(2) –0.5 7 V Continuous channel current 128 mA IIK Input clamp current VI < 0 –50 mA TJ Max Junction temperature 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V Charged-device model (CDM), per AEC Q100-011 ±1000 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VI/O Input/output voltage 0 5 V Vref_A/B/EN Reference voltage 0 5 V IPASS Pass transistor current 64 mA TA Operating free-air temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) LSF0108-Q1 UNITPW (TSSOP) WRKS (VQFN)

20 PINS 20 PINS

RθJA Junction-to-ambient thermal resistance 110.7 TBD °C/W RθJC(top) Junction-to-case (top) thermal resistance 45.4 TBD °C/W RθJB Junction-to-board thermal resistance 62.6 TBD °C/W ψJT Junction-to-top characterization parameter 6.6 TBD °C/W ψJB Junction-to-board characterization parameter 61.9 TBD °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a TBD °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LSF0108-Q1

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VIK II = –18 mA, VEN = 0 –1.2 V IIH VI = 5 V VEN = 0 5 µA ICC Vref_B = VEN = 5.5 V, Vref_A = 4.5 V, IO = 0, VI = VCC or GND 6 µA CI(ref_A/B/EN) VI = 3 V or 0 11 pF Cio(off) VO = 3 V or 0, VEN = 0 4 6 pF Cio(on) VO = 3 V or 0, VEN = 3 V 10.5 12.5 pF ron (2) VI = 0, IO = 64 mA Vref_A = 3.3 V; Vref_B = VEN = 5 V 8 ΩVref_A = 1.8 V; Vref_B = VEN = 5 V 9 Vref_A = 1.0 V; Vref_B = VEN = 5 V 10 VI = 0, IO = 32 mA Vref_A = 1.8 V; Vref_B = VEN = 5 V 10 Ω Vref_A = 2.5 V; Vref_B = VEN = 5 V 15 VI = 1.8 V, IO = 15 mA Vref_A = 3.3 V; Vref_B = VEN = 5 V 9 Ω VI = 1.0 V, IO = 10 mA Vref_A = 1.8 V; Vref_B = VEN = 3.3 V 18 Ω VI = 0 V, IO = 10 mA Vref_A = 1.0 V; Vref_B = VEN = 3.3 V 20 Ω VI = 0 V, IO = 10 mA Vref_A = 1.0 V; Vref_B = VEN = 1.8 V 30 Ω (1) All typical values are at TA = 25°C. (2) Measured by the voltage drop between the A and B pins at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) pins. 6.6 Switching Characteristics (Translating Down), VGATE = 3.3 V over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 3.3 V, VIL = 0, and VM = 1.15 V (unless otherwise noted) (see Figure 7-1) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 1.9 1.4 0.75 ns tPHL 2 1.5 0.85 6.7 Switching Characteristics (Translating Down), VGATE = 2.5 V over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 2.5 V, VIL = 0, and VM = 0.75 V (unless otherwise noted) (see Figure 7-1) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 2 1.45 0.8 ns tPHL 2.1 1.55 0.9 LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 www.ti.com

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6.8 Switching Characteristics (Translating Up), VGATE = 3.3 V over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 2.3 V, VIL = 0, VT = 3.3 V, VM = 1.15 V and RL = 300 (unless otherwise noted) (see Figure 7-1) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 2.1 1.55 0.9 ns tPHL 2.2 1.65 1 6.9 Switching Characteristics (Translating Up), VGATE = 2.5 V over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 1.5 V, VIL = 0, VT = 2.5 V, VM = 0.75 V and RL = 300 (unless otherwise noted) (see Figure 7-1) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 1.8 1.35 0.8 ns tPHL 1.9 1.45 0.9

6.10 Typical Characteristics

±0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 5 10 15 20 Voltage (V) Time (ns) Input Output C005 Figure 6-1. Signal Integrity (1.8 to 3.3 V Translation Up at 50 MHz) www.ti.com LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LSF0108-Q1

7 Parameter Measurement Information

NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR≤ ≤ ≤10 MHz, Z = 50 t 2 ns, tO r f Ω, 2□ns. C. The outputs are measured one at a time, with one transition per measurement. From Output Under Test CL (see Note A) LOAD CIRCUIT TRANSLATING UP TRANSLATING DOWN RL Translating up Translating down USAGE SWITCH VM VM 3.3 V VIL Input VM VM 5 V VOL Output VM VM 5 V VIL Input VM VM 2 V VOL Output VT Open Figure 7-1. Load Circuit for Outputs LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 www.ti.com

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8 Detailed Description

8.1 Overview

The LSF0108-Q1 can be used in level-translation applications for interfacing devices or systems operating at different supply voltages. The LSF0108-Q1 is ideal for use in applications where an open-drain driver is connected to the data I/Os. LSF0108-Q1 can achieve 100 MHz with appropriate pull-up resistors and layout. The LSF0108-Q1 may also be used in applications where a push-pull driver is connected to the data I/Os. For an overview of device setup and operation, see The Logic Minute training series on Understanding the LSF Family of Bidirectional, Multi-Voltage Level Translators.

8.2 Functional Block Diagram

Vref_AVref_B2193456 20EN18171615 1GND A1A2A3A4B1B2B3B4SW7891014131211A5A6A7A8B5B6B7B8 LSF0108-Q1 SWSWSWSW SWSWSW www.ti.com LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LSF0108-Q1

8.3 Feature Description

8.3.1 Auto Bidirectional Voltage Translation

All devices in the LSF family are auto bidirectional voltage level translators that are operational from 0.95 V to 4.5 V on the Vref_A supply and from 1.8 V to 5.5 V on the Vref_B supply. This allows bidirectional voltage translation between 0.95 V and 5.5 V without the need for a direction pin in open-drain or push-pull applications. The LSF family supports level translation applications with transmission speeds greater than 100 Mbps for open-drain systems using a 30-pF capacitance and 250- Ω pullup resistor. Both the output driver of the controller and the peripheral device output can be push-pull or open-drain (pull-up resistors may be required). During operation of the device, the B-side is often referred to as the high side while the A-side is referred to as the low side.

8.3.2 Output Enable

To enable the I/O pins, the EN input should be tied directly to Vref_B during operation and both pins must be pulled up to the HIGH side (Vpu or VCCB) through a pull-up resistor (typically 200 k Ω). To ensure the high impedance state during power-up, power-down, or during operation, the EN pin must be LOW. The EN pin should always be tied directly to the Vref_B pin and is recommended to be disabled by an open-drain driver without a pullup resistor. This allows Vref_B to regulate the EN input and bias the channels for proper translation. A filter capacitor on Vref_B is recommended for a stable supply at the device. 1.8 V Vref_A VCCB EN 200 k Vref_B 3.3 V A1B1 0.1 F Figure 8-1. EN Pin Tied to Vref_B Directly and to VCCB Through a Pull-Up Resistor The supply voltage of open drain I/O devices can be completely different from the supplies used for the LSF and has no impact on the operation. For additional details on how to use the enable pin, see the Using the Enable Pin with the LSF Family video. Table 8-1. EN Pin Function Table INPUT EN(1) PIN Data Port State Tied directly to Vref_B An = Bn L Hi-Z (1) EN is controlled by Vref_B logic levels. LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 www.ti.com

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8.3.3 Wettable Flanks

This device includes wettable flanks for at least one package. See the Features section on the front page of the data sheet for which packages include this feature. Wettable flanks help improve side wetting after soldering which makes QFN packages easier to inspect with automatic optical inspection (AOI). A wettable flank can be dimpled or step-cut to provide additional surface area for solder adhesion which assists in reliably creating a side fillet as shown in the figure. Please see the mechanical drawing for additional details. Figure 8-2. Simplified Cutaway View of Wettable-Flank QFN Package and Standard QFN Package After Soldering Package We able Flank Lead PCB Pad Standard Lead Package Solder

8.4 Device Functional Modes

For each channel (n), when either the An or Bn port is LOW, the switch provides a low impedance path between the An and Bn ports; the corresponding Bn or An port will be pulled LOW. The low R ON of the switch allows connections to be made with minimal propagation delay and signal distortion. Table 8-1 provides a summary of device operation. For additional details on the functional operation of the LSF family of devices, see the Down Translation with the LSF Family and Up Translation with the LSF Family videos. Table 8-2. Device Functionality Signal Direction(1) Input State Switch State Functionality B to A (Down Translation) B = LOW ON (Low Impedance) A-side voltage is pulled low through the switch to the B-side voltage B = HIGH OFF (High Impedance) A-side voltage is clamped at Vref_A (2) A to B (Up Translation) A = LOW ON (Low Impedance) B-side voltage is pulled low through the switch to the A-side voltage A = HIGH OFF (High Impedance) B-side voltage is clamped at Vref_A and then pulled up to the Vpu# supply voltage (1) The downstream channel should not be actively driven through a low impedance driver, or else bus contention may occur. (2) The A-side can have a pullup to Vref_A for additional current drive capability or may also be pulled above Vref_A with a pullup resistor. Specifications in the Recommended Operating Conditions section should always be followed.

8.4.1 Up and Down Translation

Up Translation: When the signal is driven from A to B and the An port is HIGH, the switch will be OFF and the Bn port will then be driven to a voltage higher than Vref_A by the pullup resistor that is connected to the pull-up supply voltage. This functionality allows seamless translation between the higher and lower voltages selected by the user, without the need for directional control. Pull-up resistors are always required on the high side, and pull-ups are only required on the low side if the output of the low side device is open drain or its input has a leakage greater than 1 µA. www.ti.com LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LSF0108-Q1

Vref_A VCCB EN 200 k GND LSF0108-Q1 Vref_B 3.3 V Device 3.3 V RB1 0.1 μF 1.8 V Device 1.8 V VCCA B8 A8 Figure 8-3. Up Translation Example Schematic with Push-Pull and Open Drain Configuration Up translation with the LSF requires attention to two important factors: maximum data rate and sink current. Maximum data rate is directly related to the rising edge of the output signal. Sink current depends on supply values and the chosen pull-up resistor values. Equation 1 shows the maximum data rate formula, and Equation 2 presents the maximum sink current formula, both of which are estimations. A low RC value is needed to reach high speeds, which also require strong drivers. For estimated data rate and sink current calculations based on circuit component, see the Up Translation with the LSF Family video. 3 × 2 R B 1 C B 1 = 1

6 R B 1 C B 1 bi ts

s ec on d (1) I OL ≅ V C C A R A 1 + V C CB R B 1 A (2) Down Translation: When the signal is being driven HIGH from the Bn port to An port, the switch will be OFF, clamping the voltage on the An port to the voltage set by Vref_A. A pull-up resistor can be added on either side of the device. There are special circumstances that allow the removal of one or both of the pull-up resistors. If the signal is always going to be down translated from a push-pull transmitter, then the resistor on the B-side can be removed. If the leakage current into the receiver on the A-side is less than 1 µA, then the resistor on the A-side can also be removed. This arrangement, with no external pull-up resistors, can be used when down translating from a push-pull output to a low-leakage input. For an open drain transmitter, the pull-up resistor on the B-side is necessary because an open drain output cannot drive high by itself. Table 9-2 lists a summary of device operation. For additional details on the functional operation of the LSF family of devices, see the Up Translation with the LSF Family and Down Translation with the LSF Family videos. LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 www.ti.com

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9 Applications and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The LSF0108-Q1 device can perform voltage translation for open-drain or push-pull interface. Table 9-1 provides some consumer or telecom interfaces as reference to the different channel numbers that are supported by the LSF0108-Q1. Table 9-1. Voltage Translator for Consumer or Telecom Interface Part Name Channel Number Interface LSF0108-Q1 8 GPIO, MDIO, SDIO, SVID, UART, SMBus, PMBus, I2C, and SPI Some important reminders regarding the LSF family of devices are as follows:

LSF devices are switch-based, not buffer-based (see the TXB family for buffer-based devices)
Specific data rates cannot be calculated by using 1/Tpd
VCCB/VCCA are not the same as Vref_B or Vref_A: VCCB refers to the B-side supply voltage supplied to the LSF device, while Vref_B refers to the voltage at the Vref_B pin (pin 7 of Figure 9-1) on the other side of the 200 kΩ resistor

9.2 Typical Application

9.2.1 I2C PMBus, SMBus, GPIO

Vref_A Vref_B EN LSF0108-Q1 200 k Vcc Vcc Rpu GPIO GPIO GPIO GPIO Vref(A) = 1.8 V Vpu = 5.0 V RpuRpu Vpu = 3.3 V GPIO GPIO 1.8 V SCL SDA GPIO GPIO MDIO MDC SCL SDA MDIO MDC RpuRpu SW SW SW SW SW SW SW SW Vcc Figure 9-1. Bidirectional Translation to Multiple Voltage Levels www.ti.com LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LSF0108-Q1

9.2.1.1 Design Requirements

9.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines

As shown in Figure 9-1, the A1 and A2 channels have a maximum output voltage equal to Vref_A, and the B1 and B2 channels have a maximum output voltage equal to Vpu when Vref_B is connected through a 200-k Ω resistor to a 3.3-V Vpu power supply and Vref_A is set 1.8 V. The LSF0108-Q1 has an EN input that is used to disable the device by setting EN LOW, which places all I/Os in the high-impedance state. The power consumption is very low because LSF0108-Q1 is a switch-type voltage translator. It is recommended to always enable LSF0108-Q1 for bidirectional application (I2C, SMBus, PMBus, or MDIO). Table 9-2. Application Operating Condition PARAMETER MIN TYP MAX UNIT Vref_A(1) reference voltage (A) 0.95 4.5 V Vref_B reference voltage (B) Vref_A + 0.8 5.5 V VI(EN) input voltage on EN pin Vref_A + 0.8 5.5 V Vpu pull-up supply voltage 0 Vref_B V (1) Vref_A have to be the lowest voltage level across all of inputs and outputs. Note The 200 kΩ, pull-up resistor is required to allow Vref_B to regulate the EN input. A filter capacitor on Vref_B is recommended. Also Vref_B and V I(EN) are recommended to be at 1.0 V higher than Vref_A for best signal integrity.

9.2.1.1.2 Bias Circuitry

For proper operation, VCCA must always be at least 0.8 V less than VCCB (VCCA + 0.8 ≦ VCCB). The 200 k Ω pull-up resistor is required to allow Vref_B to regulate the EN input and properly bias the device for translation. A 0.1 µF capacitor is recommended for providing a path from Vref_B to ground for high frequency noise. Vref_B and VI (EN) are recommended to be 1.0 V higher than Vref_A for best signal integrity. Attempting to drive the EN pin directly with a push-pull output device is a very common design error with the LSF01 series of devices. It is also very important to note that current does flow into the A-side voltage supply during normal operation. Not all voltage sources can sink current, so be sure that applicable designs can handle this current. For more design details, see the Understanding the Bias Circuit for the LSF Family video. 1.8 V Vref_A VCCB EN 200 k Vref_B 3.3 V A1B1 0.1 mF Figure 9-2. Bias Circuitry Inside the LSF0108-Q1 Devices LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 www.ti.com

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9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Bidirectional Translation

For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage), the EN input must be connected to Vref_B and both pins pulled to HIGH side Vpu through a pull-up resistor (typically 200 k Ω). This allows Vref_B to regulate the EN input. A filter capacitor on Vref_B is recommended. The controller output driver can be push-pull or open-drain (pull-up resistors may be required) and the peripheral device output can be push-pull or open-drain (pull-up resistors are required to pull the Bn outputs to Vpu). Note If either output is push-pull, then data must be unidirectional or the outputs must be tri-state and be controlled by some direction-control mechanism to prevent HIGH-to-LOW contentions in either direction. If both outputs are open-drain, then no direction control is needed. Figure 9-1 shows how the reference supply voltage (Vref_A) is connected to the processor core power supply voltage. When Vref_B is connected through a 200 k Ω resistor to a 3.3 V Vpu power supply, and Vref_A is set 1 V. The output of A3 and B4 has a maximum output voltage equal to Vref_A, and the bidirectional interface (Ch1/2, MDIO) has a maximum output voltage equal to Vpu.

9.2.1.2.2 Pull-Up Resistor Sizing

The pull-up resistor value needs to limit the current through the pass transistor when it is in the ON state to about 15 mA. This ensures a voltage drop of 260 mV to 350 mV to have a valid LOW signal on the downstream channel. If the current through the pass transistor is higher than 15 mA, the voltage drop is also higher in the ON state. To set the current through each pass transistor at 15 mA, calculate the pull-up resistor value using the following equation: Rp u = Vpu − 0.35 V

0.015 A (3)

Table 9-3 summarizes resistor values, reference voltages, and currents at 8 mA, 5 mA, and 3 mA. The resistor value shown in the +10% column (or a larger value) should be used to ensure that the voltage drop across the transistor is 350 mV or less. The external driver must be able to sink the total current from the resistors on both sides of the LSF family device at 0.175 V, although the 15 mA applies only to current flowing through the LSF family device. The device driving the low state at 0.175 V must sink current from one or more of the pull-up resistors and maintain VOL. A decrease in resistance will increase current, and thus result in increased VOL. Table 9-3. Pull-Up Resistor Values VDPU (1) (2) 8 mA 5 mA 3 mA NOMINAL (Ω) +10%(3) (Ω) NOMINAL (Ω) +10%(3) (Ω) NOMINAL (Ω) +10%(3) (Ω)

5 V 581 639 930 1023 1550 1705

3.3 V 369 406 590 649 983 1082

2.5 V 269 296 430 473 717 788

1.8 V 181 199 290 319 483 532

1.5 V 144 158 230 253 383 422

1.2 V 106 117 170 187 283 312

(1) Calculated for VOL = 0.35 V (2) Assumes output driver VOL = 0.175 V at stated current (3) +10% to compensate for VDD range and resistor tolerance www.ti.com LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LSF0108-Q1

9.2.1.2.3 LSF0108-Q1 Bandwidth

The maximum frequency of the LSF0108-Q1 is dependent on the application. The device can operate at speeds of >100 MHz given the correct conditions. The maximum frequency is dependent upon the loading of the application. The LSF0108-Q1 behaves like a standard switch where the bandwidth of the device is dictated by the on resistance and on capacitance of the device. Figure 9-3 shows a bandwidth measurement of the LSF0108-Q1 using a two-port network analyzer. – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 0.1 1 10 100 1000 Gain (dB) Frequency (MHz) Figure 9-3. 3-dB Bandwidth The 3-dB point of the LSF0108-Q1 is ≅ 600 MHz; however, this measurement is an analog type of measurement. For digital applications the signal should not degrade up to the fifth harmonic of the digital signal. The frequency bandwidth should be at least five times the maximum digital clock rate. This component of the signal is very important in determining the overall shape of the digital signal. In the case of the LSF0108-Q1, a digital clock frequency of greater than 100 MHz can be achieved. The LSF0108-Q1 does not provide any drive capability. Therefore higher frequency applications will require higher drive strength from the host side. No pull-up resistor is needed on the host side (3.3 V) if the LSF0108-Q1 is being driven by standard CMOS totem pole output driver. Ideally, it is best to minimize the trace length from the LSF0108-Q1 on the sink side (1.8 V) to minimize signal degradation. All fast edges have an infinite spectrum of frequency components; however, there is an inflection (or knee) in the frequency spectrum of fast edges where frequency components higher than ƒknee are insignificant in determining the shape of the signal. To calculate the maximum practical frequency component, or the knee frequency (f knee), use Equation 4 and Equation 5: f k ne e = 0.5 RT 10 − 80 % (4) f k ne e = 0.4 RT 20 − 80 % (5) For signals with rise time characteristics based on 10% to 90% thresholds, f knee is equal to 0.5 divided by the rise time of the signal. For signals with rise time characteristics based on 20% to 80% thresholds, which is very common in many of today's device specifications, ƒknee is equal to 0.4 divided by the rise time of the signal. Some guidelines to follow that will help maximize the performance of the device:

Keep trace length to a minimum by placing the LSF0108-Q1 close to the I2C output of the processor.
The trace length should be less than half the time of flight to reduce ringing and line reflections or non- monotonic behavior in the switching region.
To reduce overshoots, a pull-up resistor can be added on the 1.8 V side; be aware that a slower fall time is to be expected. LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 www.ti.com

16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: LSF0108-Q1

9.2.1.3 Application Curves

0 50 100 150 200 250 300 350 400 450 500 Voltage (V) Time (ns) Input Output Figure 9-4. Captured Waveform From Above I2C Set-Up (1.8 V to 3.3 V at 2.5 MHz) Input (3.3V) Output (1.0V) Figure 9-5. Captured Waveform From Above MDIO Setup

9.2.2 Mixed-Mode Voltage Translation

The supply voltage (V pu#) for each channel can be individually set with a pull-up resistor. Figure 9-6 shows an example of this mixed-mode multi-voltage translation. For additional details on multi-voltage translation, see the Multi-voltage Translation with the LSF Family video. With the Vref_B pulled up to 5 V and Vref_A connected to 1.8 V, all channels will be clamped to 1.8 V at which point a pullup can be used to define the high level voltage for a given channel.

Push-Pull Down Translation (5 V to 1.8 V): Channel 1 is an example of this setup. When B1 is 5 V, A1 is clamped to 1.8 V, and when B1 is LOW, A1 is driven LOW through the switch.
Push-Pull Up Translation (1.8 V to 5 V): Channel 2 is an example of this setup. When A2 is 1.8 V, the switch is high impedance and the B2 channel is pulled up to 5 V. When A2 is LOW, B2 is driven LOW through the switch.
Push-Pull Down Translation (3.3 V to 1.8 V): Channels 3 and 4 are examples of this setup. When either B3 or B4 are driven to 3.3 V, A3 or A4 are clamped to 1.8 V, and when either B3 or B4 are LOW, A3 or A4 are driven LOW through the switch.
Open-Drain Bidirectional Translation (3.3 V ↔ 1.8 V): Channels 5 through 8 are examples of this setup. These channels are for bidirectional operation for I2C and MDIO to translate between 1.8 V and 3.3 V with open-drain drivers. www.ti.com LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LSF0108-Q1

9.2.2.1 Single Supply Translation

Sometimes, an external device will have an unknown voltage that could be above or below the desired translation voltage, preventing a normal connection of the LSF. Resistors are added on the A side in place of the second supply in this case – this is an example of when LSF single supply operation is utilized, shown in Figure 9-5. In the following figure, a single 3.3 V supply is used to translate between a 3.3 V device and a device that can change between 1.8 V and 5.0 V. R1 and R2 are added in place of the second supply. Note that due to some current coming out of the Vref_A pin, this cannot be treated as a simple voltage divider. LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 www.ti.com

18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: LSF0108-Q1

Vref_A VCCB EN 200 k GND LSF0108-Q1 Vref_B 3.3 V Device 3.3 V RB2RB1 0.1 mF RA1 RA2

1.8 V - 5 V

Figure 9-7. Single Supply Translation with 3.3 V Supply The steps to select the resistor values for R1 and R2 are as follows: 1. Select a value for R1. Typically, 1 MΩ is used to reduce current consumption. 2. Plug in values for your system into the the following equation. Note that Vref_A is the lowest voltage in the system. VCCB is the primary supply and R1 is the selected value from step 1. R 2 = 200 10 3 × R 1 × V R EF A 200 10 3 + R 1 V C C B − V R EF A − 0.85 × R 1 (6) The single supply used must be at least 0.8 V larger than the lowest desired translation voltage. The voltage at Vref_A must be selected as the lowest voltage to be used in the system. The LSF evaluation module (LSF-EVM) contains unpopulated pads to place R1 and R2 for single supply operation testing. For an example single supply translation schematic and details, see the Single Supply Translation with the LSF Family video. www.ti.com LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LSF0108-Q1

9.2.2.2 Voltage Translation for Vref_B < Vref_A + 0.8 V As described in Table 9-2, it is generally recommended that Vref_B > Vref_A + 0.8 V; however, the device can still operate in the condition where Vref_B < Vref_A + 0.8 V as long as additional considerations are made for the design. Typical Operation (Vref_B > Vref_A + 0.8 V): in this scenario, pullup resistors are not required on the A-side for proper down-translation as is shown for channels 1 and 2 of Figure 9-6. The typical operating mode of the device ensures that when down translating from B to A, the A-side I/O ports will clamp at Vref_A to provide proper voltage translation. For further explanation of device operation, see the Down Translation with the LSF Family video. Requirements for Vref_B < Vref_A + 0.8 V Operation: in this scenario, there is not a large enough voltage difference between Vref_A and Vref_B to ensure that the A side I/O ports will be clamped at Vref_A, but rather at a voltage approximately equal to Vref_B – 0.8 V. For example, if Vref_B = 1.8 V and Vref_A = 1.2 V, the A-side I/Os will clamp to a voltage around 1.0 V. Therefore, to operate in such a condition, the following additional design considerations must be met:

Vref_B must be greater than Vref_A during operation (Vref_B > Vref_A)
Pullup resistors should be populated on A-side I/O ports to ensure the line will be fully pulled up to the desired voltage Figure 9-8 shows an example of this setup, where 1.2 V ↔ 1.8 V translation is achieved with the LSF0108-Q1. This type of setup also applies for other voltage nodes such as 1.8 V ↔ 2.5 V, 1.05 V ↔ 1.5 V, and others as long as the Recommended Operating Conditions table is followed. 1.8 V SW SW 1.8 V Device1.2 V Device 200 k Vref_B RPU(B1) Vref_A 1.2 V RPU(B2) EN B2A2 RPU(A2) RPU(A1) 0.1 F Figure 9-8. 1.2 V to 1.8 V Level Translation with LSF0108-Q1 LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 www.ti.com

Product Folder Links: LSF0108-Q1

10 Power Supply Recommendations

There are no power sequence requirements for the LSF0108-Q1. For enable and reference voltage guidelines,

11 Layout

11.1 Layout Guidelines

Because the LSF0108-Q1 is a switch-type level translator, the signal integrity is highly related with a pull-up resistor and PCB capacitance condition.

Short signal trace as possible to reduce capacitance and minimize stub from pull-up resistor.
Place LSF close to high voltage side.
Select the appropriate pull-up resistor that applies to translation levels and driving capability of transmitter.

11.2 Layout Example

2Vref_A 19 Vref_B 3A1 18 B1 4A2 17 B2 10A8 11 B8 Minimize Stub as possible Short Signal Trace as possible Figure 11-1. Short Trace Layout Device PCB TP1SD Controller (1.8 V IO) TP2 LSF0108-Q1 SDIO level translator SDIO Connnector (3.3 V IO) Figure 11-2. Device Placement Time (ns) Voltage (V) -0.5 0.5 1.5 2.5 3.5 D011 Input Output Figure 11-3. Waveform From TP1 (Pull-Up Resistor: 160-Ω and 50-pF Capacitance 3.3 V to 1.8 V at 100 MHz) Time (ns) Voltage (V) 0 3 6 9 12 15 18 21 24 27 30 -0.5 0.5 1.5 2.5 3.5 D010 Input Output Figure 11-4. Waveform From TP2 (Pull-Up Resistor: 160-Ω and 50-pF Capacitance 1.8 V to 3.3 V at 100 MHz) www.ti.com LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LSF0108-Q1

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most- current data available for the designated device. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane. LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 www.ti.com

Product Folder Links: LSF0108-Q1

www.ti.com 14-Sep-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LSF0108QPWRQ1 ACTIVE TSSOP PW 20 2000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 LSF0108Q Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LSF0108-Q1 : Addendum-Page 1

www.ti.com 14-Sep-2022

Catalog : LSF0108 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Sep-2022 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Sep-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LSF0108QPWRQ1 TSSOP PW 20 2000 364.0 364.0 27.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 18X 0.65 5.85 20X 0.30 0.19 TYP6.6 6.2

1.2 MAX

0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 6.6 6.4 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0020A SMALL OUTLINE PACKAGE 4220206/A 02/2017

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

20X (1.5) 20X (0.45) 18X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0020A SMALL OUTLINE PACKAGE 4220206/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 10 11 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 20X (1.5) 20X (0.45) 18X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0020A SMALL OUTLINE PACKAGE 4220206/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 10 11

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2022, Texas Instruments Incorporated

Summary

LSF0108-Q1 Automotive 8-Channel Multi-Voltage Level Translator REVISED NOVEMBER 2022

Description

LSF0108-Q1 Automotive 8-Channel Multi-Voltage Level Translator REVISED NOVEMBER 2022

Source title PLSF0108QWRKSRQ1 Datasheet(PDF) - Texas Instruments

Read PLSF0108QWRKSRQ1 online.

LSF0108-Q1_V01 TI | Alldatasheet

Document overview

Technical content

1 Features

2 Applications

3 Description

6.6 Switching Characteristics (Translating Down),

6.7 Switching Characteristics (Translating Down),

6.8 Switching Characteristics (Translating Up),

6.9 Switching Characteristics (Translating Up),

13 Mechanical, Packaging, and Orderable

4 Revision History

2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

5 Pin Configuration and Functions

4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

6 Specifications

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

20 PINS 20 PINS

6.5 Electrical Characteristics

6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

6.10 Typical Characteristics

7 Parameter Measurement Information

8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Auto Bidirectional Voltage Translation

8.3.2 Output Enable

10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

8.3.3 Wettable Flanks

8.4 Device Functional Modes

8.4.1 Up and Down Translation

6 R B 1 C B 1 bi ts

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9 Applications and Implementation

9.1 Application Information

9.2 Typical Application

9.2.1 I2C PMBus, SMBus, GPIO

9.2.1.1 Design Requirements

9.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines

9.2.1.1.2 Bias Circuitry

14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Bidirectional Translation

9.2.1.2.2 Pull-Up Resistor Sizing

0.015 A (3)

5 V 581 639 930 1023 1550 1705

3.3 V 369 406 590 649 983 1082

2.5 V 269 296 430 473 717 788

1.8 V 181 199 290 319 483 532

1.5 V 144 158 230 253 383 422

1.2 V 106 117 170 187 283 312

9.2.1.2.3 LSF0108-Q1 Bandwidth

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9.2.1.3 Application Curves

9.2.2 Mixed-Mode Voltage Translation

9.2.2.1 Single Supply Translation

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1.8 V - 5 V

20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

10 Power Supply Recommendations

11 Layout

11.1 Layout Guidelines

11.2 Layout Example

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

12.2 Support Resources

12.3 Trademarks

12.4 Electrostatic Discharge Caution

12.5 Glossary

13 Mechanical, Packaging, and Orderable Information

22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

1.2 MAX

0.1 C A B