LSF0101_V01 TI1 | Alldatasheet
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Vref_A Vref_B A1 B1 6-Pin X2SON Transparent Top View 2 5 3 4 GND Vref_A EN Vref_B 6-Pin SON Transparent Top View 8-Pin DSBGA Bottom View 8-Pin X2SON Transparent Top View 20-Pin VQFN Transparent Top View A1 A2 ENGND Vref_A Vref_B A1 B1 B2A2 ENGND Vref_A Vref_B A1 B1 B2A2 LSF0101 LSF0102 LSF0108 Thermal Pad GND EN A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 Vref_A Vref_B Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains ADVANCE INFORMATION for pre-production products; subject to change without notice. LSF0101, LSF0102, LSF0108 SDLS966H –DECEMBER 2013–REVISED JUNE 2019 LSF010x1/2/8ChannelAuto-BidirectionalMulti-VoltageLevelTranslatorforOpen-Drain andPush-PullApplications
1 Features
1• Provides bidirectional voltage translation with no direction pin
- Supports up to 100-MHz up translation and greater than 100-MHz down translation at ≤ 30pF cap load and up To 40-MHz up/down translation at 50pF cap load
- Allows bidirectional voltage-level translation between – 2.5 V ↔ 3.3/5 V – 3.3 V ↔ 5 V
- Low standby current
- 5-V tolerance I/O port to support TTL
- Low RON provides less signal distortion
- High-impedance I/O pins for EN = Low
- Flow-through pinout for easy PCB trace routing
- Latch-up performance >100 mA per JESD 17
- –40°C to 125°C Operating temperature range
2 Applications
- GPIO, MDIO, PMBus, SMBus, SDIO, UART, I2C, and other interfaces in telecom infrastructure
- Enterprise Systems
- Communications Equipment
- Personal Electronics
- Industrial Applications
3 Description
The LSF family of devices supports bidirectional voltage translation without the need for DIR pin which minimizes system effort (for PMBus, I2C, SMBus, etc.). The LSF family of devices supports up to 100- MHz up translation and greater than 100-MHz down translation at ≤ 30pF cap load and up to 40-MHz up/down translation at 50pF cap load which allows the LSF family to support more consumer or telecom interfaces (MDIO or SDIO). LSF family supports 5-V tolerance on I/O port which makes it compatible with TTL levels in industrial and telecom applications. The LSF family is able to set up different voltage translation levels on each channel which makes it very flexible. Device Information(1) PART NUMBER PACKAGE(PINS) BODY SIZE (NOM) LSF0101DRY SON (6) 1.45 mm × 1.00 mm LSF0101DTQ(2) X2SON (6) 1.00 mm x 0.80 mm LSF0102DQE X2SON (8) 1.40 mm × 1.00 mm LSF0102YZT DSBGA (8) 1.90 mm × 1.00 mm LSF0102DCT SM8 (8) 2.80 mm × 2.95 mm LSF0102DCU VSSOP (8) 2.30 mm × 2.00 mm LSF0108RKS VQFN (20) 4.50 mm × 2.50 mm LSF0108PW TSSOP (20) 4.40 mm × 6.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Advance Information
LSF0101, LSF0102, LSF0108 SDLS966H –DECEMBER 2013–REVISED JUNE 2019 www.ti.com Product Folder Links: LSF0101 LSF0102 LSF0108 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Table of Contents
6.7 LSF0101/02 AC Performance (Translating Down)
6.8 LSF0108 AC Performance (Translating Down)
6.9 LSF0101/02 AC Performance (Translating Down)
6.10 LSF0108 AC Performance (Translating Down)
6.11 LSF0101/02 AC Performance (Translating Up)
6.12 LSF0108 AC Performance (Translating Up)
6.13 LSF0101/02 AC Performance (Translating Up)
6.14 LSF0108 AC Performance (Translating Up)
13 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (February 2016) to Revision H Page Changes from Revision F (October 2015) to Revision G Page Changes from Revision E (July 2015) to Revision F Page
- Changed Features from "Supports High Speed Translation, Greater Than 100 MHz" to "Supports Up to 100 MHz Up Translation and Greater Than 100 MHz Down Translation at ≤ 30pF Cap Load and Up To 40 MHz Up/Down Changes from Revision D (October 2014) to Revision E Page
LSF0101, LSF0102, LSF0108 www.ti.com SDLS966H –DECEMBER 2013–REVISED JUNE 2019 Product Folder Links: LSF0101 LSF0102 LSF0108 Submit Documentation FeedbackCopyright © 2013–2019, Texas Instruments Incorporated Changes from Revision C (May 2014) to Revision D Page Changes from Revision B (May 2014) to Revision C Page Changes from Revision A (January 2014) to Revision B Page Changes from Original (December 2013) to Revision A Page
Vref_A Vref_B ENGND 10 1 1 201 Thermal Pad Vref_A Vref_B ENGND 10 1 1 Vref_A A2 B2 A1 B1 Vref_B GND EN EN Vref_B GND Vref_A GND EN Vref_A Vref_B 4 5 2 5 3 4 GND EN Vref_BVref_A A1 B1 GND Vref_A EN Vref_B 3 4 LSF0101, LSF0102, LSF0108 SDLS966H –DECEMBER 2013–REVISED JUNE 2019 www.ti.com Product Folder Links: LSF0101 LSF0102 LSF0108 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated
5 Pin Configuration and Functions
Pinout drawings are not to scale. 6-Pin SON Transparent Top View 6-Pin X2SON Transparent Top View LSF0102 DCT or DCU Package 8-Pin SM8 or VSSOP Top View 8-Pin X2SON Transparent Top View 8-Pin DSBGA Bottom View 20-Pin TSSOP Top View 20-Pin VQFN Transparent Top View Pin Functions PIN I/O DESCRIPTION NAME DCT, DCU, DQE, YZT NO. DRY, DTQ NO. PW or RKS NO. An 3, 4 3 3 to 10 I/O Auto-Bidirectional Data port Bn 6, 5 4 18 to 11 I/O EN 8 6 20 I Enable input; connect to Vref_B and pull-up through a high resistor (200 kΩ). See Using the Enable Pin with the LSF Family GND 1 1 1 — Ground Vref_A 2 2 2 — Reference supply voltage. For proper device biasing, see Application and Implementation and Understanding the Bias Circuit for the LSF Family.Vref_B 7 5 19 —
LSF0101, LSF0102, LSF0108 www.ti.com SDLS966H –DECEMBER 2013–REVISED JUNE 2019 Product Folder Links: LSF0101 LSF0102 LSF0108 Submit Documentation FeedbackCopyright © 2013–2019, Texas Instruments Incorporated (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed.
6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature (unless otherwise noted) MIN MAX UNIT VI Input voltage(2) –0.5 7 V VI/O Input/output voltage(2) –0.5 7 V Continuous channel current 128 mA IIK Input clamp current VI < 0 –50 mA TJ Junction Temperature 150 °C Tstg Storage temperature range –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VI/O Input/output voltage 0 5 V Vref_A/B/EN Reference voltage 0 5 V IPASS Pass transistor current 64 mA TA Operating free-air temperature –40 125 °C
LSF0101, LSF0102, LSF0108 SDLS966H –DECEMBER 2013–REVISED JUNE 2019 www.ti.com Product Folder Links: LSF0101 LSF0102 LSF0108 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) Advance Information
6.4 Thermal Information: LSF0101, LSF0108
THERMAL METRIC(1) LSF0101 LSF0108 UNITDTQ (X2SON)(2) DRY (SON) RKS (VQFN) PW (TSSOP)
6 PINS 6 PINS 20 PINS 20 PINS
RθJA Junction-to-ambient thermal resistance 294.4 407.0 49.3 106.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 188.9 285.2 45.9 41.0 °C/W RθJB Junction-to-board thermal resistance 216.8 271.6 20.6 57.6 °C/W ψJT Junction-to-top characterization parameter 26.5 113.5 2.5 4.2 °C/W ψJB Junction-to-board characterization parameter 216.0 271.0 20.6 47.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a 3.4 n/a °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Thermal Information: LSF0102
THERMAL METRIC(1) LSF0102 UNITDCU (US8) DCT (SM8) DQE (X2SON) YZT (DSBGA)
8 PINS 8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 210.1 189.6 246.5 125.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 89.1 119.6 149.1 1.0 °C/W RθJB Junction-to-board thermal resistance 88.8 102.1 100.0 62.7 °C/W ψJT Junction-to-top characterization parameter 8.3 44.5 17.1 3.4 °C/W ψJB Junction-to-board characterization parameter 88.4 101.0 99.8 62.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a °C/W (1) All typical values are at TA = 25°C. (2) Measured by the voltage drop between the A and B pins at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) pins.
6.6 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VIK II = –18 mA, VEN = 0 –1.2 V IIH VI = 5 V VEN = 0 5.0 µA ICC Vref_B = VEN = 5.5 V, Vref_A = 4.5 V or 1 V, IO = 0, VI = VCC or GND 1 µA CI(ref_A/B/EN) VI = 3 V or 0 11 pF Cio(off) VO = 3 V or 0, VEN = 0 4.0 6.0 pF Cio(on) VO = 3 V or 0, VEN = 3 V 10.5 12.5 pF ron (2) VI = 0, IO = 64 mA Vref_A = 3.3 V; Vref_B = VEN = 5 V 8.0 ΩVref_A = 1.8 V; Vref_B = VEN = 5 V 9.0 Vref_A = 1.0 V; Vref_B = VEN = 5 V 10 VI = 0, IO = 32 mA Vref_A = 1.8 V; Vref_B = VEN = 5 V 10 Ω Vref_A = 2.5 V; Vref_B = VEN = 5 V 15 VI = 1.8 V, IO = 15 mA Vref_A = 3.3 V; Vref_B = VEN = 5 V 9.0 Ω VI = 1.0 V, IO = 10 mA Vref_A = 1.8 V; Vref_B = VEN = 3.3 V 18 Ω VI = 0 V, IO = 10 mA Vref_A = 1.0 V; Vref_B = VEN = 3.3 V 20 Ω VI = 0 V, IO = 10 mA Vref_A = 1.0 V; Vref_B = VEN = 1.8 V 30 Ω
LSF0101, LSF0102, LSF0108 www.ti.com SDLS966H –DECEMBER 2013–REVISED JUNE 2019 Product Folder Links: LSF0101 LSF0102 LSF0108 Submit Documentation FeedbackCopyright © 2013–2019, Texas Instruments Incorporated 6.7 LSF0101/02 AC Performance (Translating Down) Switching Characteristics , VGATE = 3.3 V over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 3.3 V, VIL = 0, and VM = 1.15 V (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 1.1 0.7 0.3 ns tPHL 1.2 0.8 0.4 6.8 LSF0108 AC Performance (Translating Down) Switching Characteristics, VGATE = 3.3 V over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 3.3 V, VIL = 0, and VM = 1.15 V (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 1.9 1.4 0.75 ns tPHL 2 1.5 0.85 6.9 LSF0101/02 AC Performance (Translating Down) Switching Characteristics, VGATE = 2.5 V over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 2.5 V, VIL = 0, and VM = 0.75 V (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 1.2 0.8 0.35 ns tPHL 1.3 1 0.5 6.10 LSF0108 AC Performance (Translating Down) Switching Characteristics, VGATE = 2.5 V over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 2.5 V, VIL = 0, and VM = 0.75 V (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 2 1.45 0.8 ns tPHL 2.1 1.55 0.9 6.11 LSF0101/02 AC Performance (Translating Up) Switching Characteristics, VGATE = 3.3 V over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 2.3 V, VIL = 0, VT = 3.3 V, VM = 1.15 V and RL = 300 (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 1 0.8 0.4 ns tPHL 1 0.9 0.4 6.12 LSF0108 AC Performance (Translating Up) Switching Characteristics, VGATE = 3.3 V over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 2.3 V, VIL = 0, VT = 3.3 V, VM = 1.15 V and RL = 300 (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) CL = 50 pF CL = 30 pF CL = 15 pF UNIT TYP MAX TYP MAX TYP MAX tPLH A or B B or A 2.1 1.55 0.9 ns tPHL 2.2 1.65 1
6.15 Typical Characteristics
Figure 1. Signal Integrity (1.8 to 3.3 V Up Translation at 50 MHz)
NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR≤ ≤ ≤10 MHz, Z = 50 t 2 ns, tO r f Ω, 2□ns. C. The outputs are measured one at a time, with one transition per measurement.
7 Parameter Measurement Information
Figure 2. Load Circuit for Outputs
8 Detailed Description
8.1 Overview
LSF Family of Bidirectional, Multi-Voltage Level Translators.
8.2 Functional Block Diagrams
Figure 3. LSF0101 Functional Block Diagram Figure 4. LSF0102 Functional Block Diagram
Figure 5. LSF0108 Functional Block Diagram
8.3 Feature Description
8.3.1 Auto Bidirectional Voltage Translation
Level Translators training series.
8.3.2 Output Enable
(1) EN is controlled by Vref_B logic levels. Table 1. Enable Pin Function Table
(1) The downstream channel should not be actively driven through a low impedance driver, or else there may be bus contention. (2) The A-side can have a pullup to Vref_A for additional current drive capability or may also be pulled above Vref_A with a pullup resistor. Specifications in the Recommended Operating Conditions should always be followed.
8.4 Device Functional Modes
connections to be made with minimal propagation delay and signal distortion. between higher and lower voltages selected by the user, without the need for directional control. family of devices, see the Down Translation with the LSF Family and Up Translation with the LSF Family videos. Table 2. Device Functionality
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Table 3. Voltage Translator for Common Interfaces
(1) Vref_A is required to be the lowest voltage level across all inputs and outputs.
9.2 Typical Applications
9.2.1 Open-Drain Interface (I2C, PMBus, SMBus, GPIO)
Figure 6. Typical Application Circuit for Open-Drain Translation (MDIO shown as an example)
9.2.1.1 Design Requirements
9.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines
Table 4. Application Operating Condition 1.0 V higher than Vref_A for best signal integrity.
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Bidirectional Translation
push-pull or open-drain (pull-up resistors are required to pull the Bn outputs to Vpu).
direction. If both outputs are open-drain, no direction control is needed. channels have has a maximum output voltage equal to Vpu.
9.2.1.2.2 Pull-up Resistor Sizing
Table 5. Pull-up Resistor Values(1)(2)
5 V 310 341 465 512 1550 1705
3.3 V 197 217 295 325 983 1082
2.5 V 143 158 215 237 717 788
1.8 V 97 106 145 160 483 532
1.5 V 77 85 115 127 383 422
1.2 V 57 63 85 94 283 312
9.2.1.3 Application Curve
Figure 7. Open Drain Translation (1.8 V to 3.3 V at 2.5 MHz)
9.2.2 Mixed-Mode Voltage Translation
the Multi-voltage Translation with the LSF Family video. point a pullup can be used to define the high level voltage for a given channel.
- Push-Pull Down Translation (5V to 1.8V): Channel 1 is an example of this setup. When B1 is 5V, A1 is clamped to 1.8V, and when B1 is LOW, A1 is driven LOW through the switch.
- Push-Pull Up Translation (1.8V to 5V): Channel 2 is an example of this setup. When A2 is 1.8V, the switch is high impedance and the B2 channel is pulled up to 5V. When A2 is LOW, B2 is driven LOW through the switch.
- Push-Pull Down Translation (3.3V to 1.8V): Channels 3 and 4 are examples of this setup. When either B3 or B4 are driven to 3.3V, A3 or A4 are clamped to 1.8V, and when either B3 or B4 are LOW, A3 or A4 are driven LOW through the switch.
- Open-Drain Bidirectional Translation (3.3V ↔ 1.8V): Channels 5 through 8 are examples of this setup. These channels are for bidirectional operation for I2C and MDIO to translate between 1.8V and 3.3V with open-drain drivers.
Figure 8. Multi-Voltage Translation with the LSF0108
(1) Vref_A is required to be the lowest voltage level across all inputs and outputs.
10 Power Supply Recommendations
supply and input pins, see Table 6. Table 6. Recommended Operating Voltages
11 Layout
11.1 Layout Guidelines
resistor and PCB capacitance condition.
- Short signal trace as possible to reduce capacitance and minimize stub from pull-up resistor.
- Place LSF close to high voltage side.
- Select the appropriate pull-up resistor that applies to translation levels and driving capability of transmitter.
11.2 Layout Example
Figure 9. Short Trace Layout Figure 10. Device Placement
12 Device and Documentation Support
12.1 Related Links
resources, tools and software, and quick access to sample or buy. Table 7. Related Links
- LSF Translator Family Evaluation Module
- The Logic Minute Video Training Series on Understanding the LSF Family of Devices
- Voltage Level Translation with the LSF Family Application Note
- Biasing Requirements for TXS, TXB, and LSF Auto-Bidirectional Translators Application Note
12.2 Community Resources
solve problems with fellow engineers. contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
12.4 Electrostatic Discharge Caution
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 26-Jun-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LSF0101DRYR ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 VD LSF0101DTQR PREVIEW X2SON DTQ 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 FC LSF0102DCTR ACTIVE SM8 DCT 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 NG2 (S, Y) LSF0102DCUR ACTIVE VSSOP DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 (G2, NG2P, NG2S) NY LSF0102DQER ACTIVE X2SON DQE 8 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 RV LSF0102YZTR ACTIVE DSBGA YZT 8 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 RV LSF0108PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LSF0108 LSF0108RKSR ACTIVE VQFN RKS 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LSF0108 PLSF0101DTQR ACTIVE X2SON DTQ 6 3000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
www.ti.com 26-Jun-2019 Addendum-Page 2 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LSF0102, LSF0108 :
- Automotive: LSF0102-Q1 , LSF0108-Q1 NOTE: Qualified Version Definitions:
- Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LSF0101DRYR SON DRY 6 5000 184.0 184.0 19.0 LSF0102DCTR SM8 DCT 8 3000 182.0 182.0 20.0 LSF0102DCUR VSSOP DCU 8 3000 182.0 182.0 20.0 LSF0102DCUR VSSOP DCU 8 3000 202.0 201.0 28.0 LSF0102DQER X2SON DQE 8 5000 184.0 184.0 19.0 LSF0102YZTR DSBGA YZT 8 3000 182.0 182.0 20.0 LSF0108PWR TSSOP PW 20 2000 364.0 364.0 27.0 LSF0108RKSR VQFN RKS 20 3000 202.0 201.0 28.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 4X 0.25 0.17 4X 0.30 0.22
0.40 MAX
0.05 0.00 2X 0.6 0.25 TYP+0.05 -0.03 0.4 B 1.05 0.95 A 0.85 0.75 (0.1) TYP (0.1) (0.08) (0.027) TYP X2SON - 0.4 mm max heightDTQ0006A PLASTIC SMALL OUTLINE - NO LEAD 4224056/A 11/2017 PIN 1 INDEX AREA SEATING PLANE 0.05 C 3 4
0.1 C A B
0.05 C NOTE 5 (OPTIONAL) PIN 1 ID PKG PKG NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance. 4. The size and shape of this feature may vary. 5. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes. SCALE 12.000
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MIN
4X (0.25) 4X (0.4) (0.25) TYP (R0.05) TYP (0.6) (0.8) (0.4) (0.2) TYP (0.027) TYP (0.2) TYP EXPOSED METAL CLEARANCE X2SON - 0.4 mm max heightDTQ0006A PLASTIC SMALL OUTLINE - NO LEAD 4224056/A 11/2017 NOTES: (continued) 6. This package is designed to be soldered to a thermal pads on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 7. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown. SYMM SYMM LAND PATTERN EXAMPLE SOLDER MASK DEFINED SCALE:50X METAL UNDER SOLDER MASK TYP TYP SOLDER MASK OPEING
www.ti.com EXAMPLE STENCIL DESIGN (0.21) (0.8) 4X (0.6) 4X (0.4) 4X (0.25) (R0.05) TYP (0.367) (0.279) TYP (0.2) TYP (0.2) TYP (0.027) TYP X2SON - 0.4 mm max heightDTQ0006A PLASTIC SMALL OUTLINE - NO LEAD 4224056/A 11/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.07 mm THICK STENCIL PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:50X SYMM SYMM SOLDER MASK EDGE, 2X METAL UNDER SOLDER MASK TYP
MPDS049B – MAY 1999 – REVISED OCTOBER 2002 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 0,60 0,20 0,25 0° – 8° 0,15 NOM Gage Plane 4188781/C 09/02 4,25 0,30 0,15 2,90 3,752,70 3,15 2,75 0,10 0,00 1,30 MAX Seating Plane 0,10 M0,130,65 PIN 1 INDEX AREA NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion D. Falls within JEDEC MO-187 variation DA.
Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. DRY 6 USON - 0.6 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4207181/G
www.ti.com PACKAGE OUTLINE C 6X 0.25 0.15 0.5 5X 0.35 0.25
0.6 MAX
0.05 0.00 3X 0.6 0.4 0.3 B 1.05 0.95 A 1.5 1.4 (0.05) TYP (0.127) TYP 4222894/A 01/2018 USON - 0.6 mm max heightDRY0006A PLASTIC SMALL OUTLINE - NO LEAD PIN 1 INDEX AREA SEATING PLANE 0.08 C 3 4 (OPTIONAL) PIN 1 ID 0.05 C SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. SCALE 8.500
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
5X (0.3) 6X (0.2) 4X (0.5) (0.6) (R0.05) TYP (0.35) 4222894/A 01/2018 USON - 0.6 mm max heightDRY0006A PLASTIC SMALL OUTLINE - NO LEAD SYMM 3 4 SYMM LAND PATTERN EXAMPLE 1:1 RATIO WITH PKG SOLDER PADS EXPOSED METAL SHOWN SCALE:40X NOTES: (continued) METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN 5X (0.3) 6X (0.2) 4X (0.5) (0.6)(R0.05) TYP (0.35) 4222894/A 01/2018 USON - 0.6 mm max heightDRY0006A PLASTIC SMALL OUTLINE - NO LEAD NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.075 - 0.1 mm THICK STENCIL SCALE:40X SYMM 3 4 SYMM
D: Max = E: Max = 1.918 mm, Min = 0.918 mm, Min = 1.858 mm 0.858 mm
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