Driver IC

PLP5009RUKR

Texas Instruments

9-, 12-Channel, 12-Bit PWM Ultra-low Quiescent Current I2C RGB LED Drivers

Manufacturer: Texas Instruments

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ADVANCE□INFORMATION EN SDA SCL OUT0 OUT1 OUT11 MCU VCC GND LP5012 ADDR0 OUT2 VLED VCC IREF OUT10 OUT09VCAP ADDR1 CVCAP RIREF VMCU CVCC Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. LP5009, LP5012 SLVSEH2 –MAY 2019 LP50xx9-,12-Channel,12-BitPWMUltra-lowQuiescentCurrent I2CRGBLEDDrivers

1 Features

1• Operating voltage range: – VCC range: 2.7 V to 5.5 V – EN, SDA, and SCL pins compatible with 1.8-V, 3.3-V, and 5-V power rails – Output maximum voltage: 6 V

12 Constant-current sinks with high precision – 25.5 mA Maximum per channel with VCC in full range – 35 mA Maximum per channel when VCC ≥ 3.3 V – Device-to-device error: ±5%; channel-to- channel error: ±5%
Ultra-low quiescent current: – Shutdown mode: 1 µA (maximum) with EN low – Power-saving mode: 10 µA (typical) with EN high and all LEDs off for > 30 ms
Integrated 12-bit, 29-kHz PWM generator for each channel: – Independent color-mixing register per channel – Independent brightness-control register per RGB LED module – Optional logarithmic- or linear-scale brightness control – Integrated 3-phase PWM-shifting scheme
3 Programmable banks (R, G, B) for easy software control of each color
2 External hardware address pins allow connecting up to 4 devices
Broadcast slave address allows configuring multiple devices simultaneously
Auto-increment allows writing or reading consecutive registers within one transmission
Up to 400-kHz fast-mode I2C speed

2 Applications

LED lighting, indicator lights, and fun lights for:

Smart speaker (with voice assistant)
Smart home appliances
Video doorbell
Electronic smart lock
Smoke and heat detector
STB and DVR
Smart router
Handheld device

3 Description

In smart homes and other applications that utilize human-machine-interaction, high-performance RGB LED drivers are required. LED animation effects such as flashing, breathing, and chasing greatly improve user experience, and minimal system noise is essential. The LP50xx device is an 9- or 12-channel constant current sink LED driver. The LP50xx device includes integrated color mixing and brightness control, and pre-configuration simplifies the software coding process. Integrated 12-bit, 29-kHz PWM generators for each channel enable smooth, vivid color for LEDs, and eliminate audible noise. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LP5009 WQFN (20) 3.00 mm × 3.00 mm LP5012 (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic

12.2 Receiving Notification of Documentation Updates 36

13 Mechanical, Packaging, and Orderable

4 Revision History

May 2019 * Initial release

5 Description (continued)

The LP50xx device controls each LED output with a 12-bit PWM resolution at 29-kHz switching frequency, which helps achieve a smooth dimming effect and eliminates audible noise. The independent color mixing and intensity control registers make the software coding straightforward. When targeting a fade-in, fade-out type breathing effect, the global R, G, B bank control reduces the microcontroller loading significantly. The LP50xx device also implements a PWM phase-shifting function to help reduce the input power budget when LEDs turn on simultaneously. The LP50xx device implements an automatic power-saving mode to achieve ultra-low quiescent current. When channels are all off for 30 ms, the device total power consumption is down to 10 µA, which makes the LP50xx device a potential choice for battery-powered end equipment.

ADVANCE□INFORMATION

20 IREF6OUT4

19 EN7OUT5

18 SCL8OUT6

17 SDA9OUT7

16 VCC10OUT8

6 Pin Configuration and Functions

20-Pin WQFN With Exposed Thermal Pad Top View 20-Pin WQFN With Exposed Thermal Pad Top View

ADVANCE□INFORMATION LP5009, LP5012 www.ti.com SLVSEH2 –MAY 2019 Product Folder Links: LP5009 LP5012 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated Pin Functions PIN I/O DESCRIPTION NAME NO. LP5009 LP5012 ADDR0 14 14 — I2C slave-address selection pin. This pin must not be left floating. ADDR1 15 15 — I2C slave-address selection pin. This pin must not be left floating. EN 19 19 I Chip enable input pin IREF 20 20 — Output current-reference global-setting pin NC 11, 12, 13 — — No internal connection OUT0 2 2 O Current sink output 0. If not used, this pin can be left floating. OUT1 3 3 O Current sink output 1. If not used, this pin can be left floating. OUT2 4 4 O Current sink output 2. If not used, this pin can be left floating. OUT3 5 5 O Current sink output 3. If not used, this pin can be left floating. OUT4 6 6 O Current sink output 4. If not used, this pin can be left floating. OUT5 7 7 O Current sink output 5. If not used, this pin can be left floating. OUT6 8 8 O Current sink output 6. If not used, this pin can be left floating. OUT7 9 9 O Current sink output 7. If not used, this pin can be left floating. OUT8 10 10 O Current sink output 8. If not used, this pin can be left floating. OUT9 — 11 O Current sink output 9. If not used, this pin can be left floating. OUT10 — 12 O Current sink output 10. If not used, this pin can be left floating. OUT11 — 13 O Current sink output 11. If not used, this pin can be left floating. SCL 18 18 I I2C bus clock line. If not used, this pin must be connected to GND or VCC. SDA 17 17 I/O I2C bus data line. If not used, this pin must be connected to GND or VCC. VCAP 1 1 — Internal LDO output pin, this pin must be connected to a 1-µF capacitor to GND. Place the capacitor as close to the device as possible. VCC 16 16 I Input power. GND — — — Exposed thermal pad also serves the ground pin for the device.

ADVANCE□INFORMATION LP5009, LP5012 SLVSEH2 –MAY 2019 www.ti.com Product Folder Links: LP5009 LP5012 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage on EN, IREF, OUTx, SCL, SDA, VCC –0.3 6 V Voltage on ADDRx –0.3 VCC+0.3 V Voltage on VCAP –0.3 2 V Continuous power dissipation Internally limited Junction temperature, TJ-MAX –40 125 °C Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted) MIN MAX UNIT Input voltage on VCC 2.7 5.5 V Voltage on OUTx 0 5.5 V Voltage on ADDRx, EN, SDA, SCL 0 5.5 V Operating ambient temperature, TA –40 85 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.4 Thermal Information

THERMAL METRIC(1) LP5009 or LP5012 UNITRUK (QFN)

20 PINS

RθJA Junction-to-ambient thermal resistance 53.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 55.3 °C/W RθJB Junction-to-board thermal resistance 27.4 °C/W ψJT Junction-to-top characterization parameter 1.9 °C/W ψJB Junction-to-board characterization parameter 27.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 12.9 °C/W

7.5 Electrical Characteristics

over operating ambient temperature range (-40°C < TA< 85°C) (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VCC) VVCC Supply voltage 2.7 5.5 V IVCC Shutdown supply current VEN = 0 V 0.2 1 µA Standby supply current VEN = 3.3 V, Chip_EN = 0 (bit) 6 10 Normal-mode supply current With 10-mA LED current per OUTx 4 6 mA Power-save mode supply current VEN = 3.3 V, Chip_EN = 1 (bit), Power_Save_EN = 1 (bit), all the LEDs off duration > tPSM 6 10 µA VUVR Undervoltage restart VVCC rising 2.5 V VUVF Undervoltage shutdown VVCC falling 2 V VUV_HYS Undervoltage shutdown hysteresis 0.2 V OUTPUT STAGE (OUTx) IMAX Maximum sink current (OUT0–OUTx) (For LP5012, x = 11. For LP5009, x = 8.) VVCC in full range, Max_Current_Option = 0 (bit), PWM = 100% 25.5 mA Maximum sink current (OUT0–OUTx) (For LP5012, x = 11. For LP5009, x = 8.) VVCC ≥ 3.3 V, Max_Current_Option = 1 (bit), PWM = 100% 35 ILIM Internal sink current limit (OUT0–OUTx) (For LP5012, x = 11. For LP5009, x = 8.) VVCC in full range, Max_Current_Option = 0 (bit), VIREF = 0 V 35 55 80 mA Internal sink current limit (OUT0–OUTx) (For LP5012, x = 11. For LP5009, x = 8.) VVCC ≥ 3.3V, Max_Current_Option=1 (bit), VIREF = 0 V 40 75 120 Ilkg Leakage current (OUT0–OUTx) (For LP5012, x = 11. For LP5009, x = 8.) PWM = 0% 0.1 1 µA IERR_DD Device to device current error, IERR_DD=(IAVE-ISET)/ISET×100% Channels' current are set to 10 mA. PWM = 100%. Already includes the VIREF and KIREF tolerance –5% 5% IERR_CC Channel to channel current error, IERR_CC=(IOUTX-IAVE)/IAVE×100% Channels' current are set to 10 mA. PWM = 100%. Already includes the VIREF and KIREF tolerance –5% 5% VIREF IREF voltage 0.7 V KIREF IREF ratio 105 ƒPWM PWM switching frequency 21 29 kHz VSAT Output saturation voltage VVCC in full range, Max_Current_Option = 0 (bit), output current set to 20 mA, the voltage when the LED current has dropped 5% 0.25 0.35 V VVCC ≥ 3.3 V, Max_Current_Option = 1 (bit), output current set to 20 mA, the voltage when the LED current has dropped 5% 0.3 0.4

7.6 Timing Characteristics

3 Clock high time 600 ns

4 Setup time for a repeated START condition 600 ns

5 Data hold time 0 ns

6 Data setup time 100 ns

9 Setup time for STOP condition 600 ns

Figure 1. I2C Timing Parameters

ADVANCE□INFORMATION OUT0 VLED

12 Bits

8 Detailed Description

8.1 Overview

The LP50xx device is an 9- or 12-channel constant-current-sink LED driver. The LP50xx device includes all necessary power rails, an on-chip oscillator, and a two-wire serial I2C interface. The maximum constant-current value of all channels is set by a single external resistor. Two hardware address pins allow up to four devices on the same bus. An automatic power-saving mode is implemented to keep the total current consumption under 10 µA, which makes the LP50xx device a potential choice for battery-powered end equipment. The LP50xx device is optimized for RGB LEDs regarding to both live effects and software efforts. The LP50xx device controls each LED output with 12-bit PWM resolution at 29-kHz switching frequency, which helps achieve a smooth dimming effect and eliminates audible noise. The independent color-mixing and intensity-control registers make the software coding straightforward. When targeting a fade-in, fade-out type breathing effect, the global RGB bank control reduces the microcontroller loading significantly. The LP50xx device also implements a PWM phase-shifting function to help reduce the input power budget when LEDs turn on simultaneously.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 PWM Control for Each Channel

Most traditional LED drivers are designed for the single-color LEDs, in which the high-resolution PWM generator is used for intensity control only. However, for RGB LEDs, both the color mixing and intensity control must be addressed to achieve the target effect. With the traditional solution, the users must handle the color mixing and intensity control simultaneously with a single PWM register. Several undesired effects occur: the limited dimming steps, the complex software design, and the color distortion when using a logarithmic scale control.

8 Bits Color

8 Bits Brightness

12 Bits / 29KHz PWM

dimming frequency, which helps achieve a smooth dimming effect and eliminates audible noise. See Figure 2. Figure 2. PWM Control Scheme for Each Channel

8.3.1.1 Independent Color Mixing Per RGB LED Module

RGB LED module to achieve >16 million (256 × 256 × 256) color-mixing.

8.3.1.2 Independent Intensity Control Per RGB LED Module

8.3.1.2.1 Intensity-Control Register Configuration

step intensity control for each RGB LED module, which helps achieve a smooth dimming effect. single-color LED application.

8.3.1.2.2 Logarithmic- or Linear-Scale Intensity Control

users to configure the dimming scale either logarithmically or linearly through the global Log_Scale_EN register.

Figure 3. Logarithmic- or Linear-Scale Intensity Control Figure 4. Logarithmic vs Linear Dimming Curve

8.3.1.3.1 PWM Generator

bits. When disabled, the output PWM duty-cycle accuracy is 9 bits. at 29 kHz, above the 20-kHz human hearing range.

8.3.1.4 PWM Phase-Shifting

grouped into three different phases.

Phase 1— the rising edge of the PWM pulse is fixed. The falling edge of the pulse is changed when the duty cycle changes. Phase 1 is applied to LED0, LED3, … , LED9.
Phase 2— the middle point of the PWM pulse is fixed. The pulse spreads in both directions when the PWM duty cycle is increased. Phase 2 is applied to LED1, LED4, … , LED10.
Phase 3— the falling edge of the PWM pulse is fixed. The rising edge of the pulse is changed when the duty cycle changes. Phase 3 is applied to LED2, LED5, … , LED11.

Figure 5. PWM Phase-Shifting

8.3.2 LED Bank Control

For most LED-animation effects, like blinking and breathing, all the RGB LEDs have the same lighting pattern. LP50xx device provides an easy coding approach, the LED bank control. on its own color-mixing and intensity-control registers. Figure 6. Bank PWM Control Scheme

Table 1. Bank Number and LED Number Assignment indicator and others with group breathing effect. Figure 7. Bank PWM Control Example

8.3.3 Current Range Setting

can be calculated by Equation 1.

KIREF = 105
VIREF = 0.7 V (1) With the IREF pin floating, the output current is close to zero. With the IREF pin shorted to GND, the LP50xx device provides internal current-limit protection, and the output-channel maximum current is limited to ILIM.

When VCC is in the range from 2.7 V to 5.5 V, and the Max_Current_Option (bit) = 0, IMAX = 25.5 mA.
When VCC is in the range from 3.3 V to 5.5 V, and the Max_Current_Option (bit) = 1, IMAX = 35 mA.

8.3.4 Automatic Power-Save Mode

When all the LED outputs are inactive, the LP50xx device is able to enter power-save mode automatically, thus lowering idle-current consumption down to 10 μA (typical). Automatic power-save mode is enabled when register bit Power_Save_EN = 1 (default) and all the LEDs are off for a duration of > 30 ms. Almost all analog blocks are powered down in power-save mode. If any I2C command to the device occurs, the LP50xx device returns to NORMAL mode.

8.3.5 Protection Features

8.3.5.1 Thermal Shutdown

The LP50xx device implements a thermal shutdown mechanism to protect the device from damage due to overheating. When the junction temperature rises to 160°C (typical), the device switches into shutdown mode. The LP50xx device releases thermal shutdown when the junction temperature of the device is reduced to 145°C (typical).

8.3.5.2 UVLO

The LP50xx device has an internal comparator that monitors the voltage at VCC. When VCC is below VUVF, reset is active and the LP50xx device is in the INITIALIZATION state.

8.4 Device Functional Modes

Figure 8. Functional Modes

INITIALIZATION: The device enters into INITIALIZATION mode when EN = H. In this mode, all the registers are reset. Entry can also be from any state, if the RESET (register) = FFh or UVLO is active.
NORMAL: The device enters the NORMAL mode when Chip_EN (register) = 1. ICC is 10 mA (typical).
POWER SAVE: The device automatically enters the POWER SAVE mode when Power_Save_EN (register) = 1 and all the LEDs are off for a duration of > 30 ms. In POWER SAVE mode, analog blocks are disabled to minimize power consumption, but the registers retain the data and keep it available via I2C. ICC is 10 µA (typical). In case of any I2C command to this device, it returns to the NORMAL mode.
SHUTDOWN: The device enters into SHUTDOWN mode from all states on VCC power up or when EN = L. ICC is < 1 µA (maximum).
STANDBY: The device enters the STANDBY mode when Chip_EN (register) = 0. In this mode, all the OUTx pins are shut down, but the registers retain the data and keep it available via I2C. STANDBY is the low- power-consumption mode, when all circuit functions are disabled. ICC is 10 µA (typical).
THERMAL SHUTDOWN: The device automatically enters the THERMAL SHUTDOWN mode when the junction temperature exceeds 160°C (typical). In this mode, all the OUTx outputs are shut down. If the junction temperature decreases below 145°C (typical), the device returns to the NORMAL mode.

8.5 Programming

8.5.1 I2C Interface

on the line and remain HIGH even when the bus is idle.

8.5.1.1 Data Validity

of the data line can only be changed when the clock signal is LOW. Figure 9. Data Validity

8.5.1.2 Start and Stop Conditions

repeated START conditions are functionally equivalent. Figure 10. Start and Stop Conditions

8.5.1.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most-significant bit (MSB) being transferred first. acknowledge after each byte has been received. but the SDA line is not pulled down. to write to the selected register. Figure 11. Acknowledge and Not Acknowledge on I2C Bus

8.5.1.4 I2C Slave Addressing

and ADDR1 pins (see Table 2 and Table 3). The device responds to a broadcast slave address regardless of the setting of the ADDR0 and ADDR1 pins. contain the same value in the addressed register.

Table 2. Slave-Address Combinations Table 3. Chip Address

8.5.1.5 Control-Register Write Cycle

The master device generates a start condition.
The master device sends the slave address (7 bits) and the data direction bit (R/W = 0).
The slave device sends an acknowledge signal if the slave address is correct.
The master device sends the control register address (8 bits).
The slave device sends an acknowledge signal.
The master device sends the data byte to be written to the addressed register.
The slave device sends an acknowledge signal.
If the master device sends further data bytes, the control register address of the slave is incremented by 1 after the acknowledge signal. To reduce program load time, the device supports address auto incrementation. The register address is incremented after each 8 data bits.
The write cycle ends when the master device creates a stop condition.

Figure 12. Write Cycle

8.5.1.6 Control-Register Read Cycle

The master device generates a start condition.
The master device sends the slave address (7 bits) and the data direction bit (R/W = 0).
The slave device sends an acknowledge signal if the slave address is correct.
The master device sends the control register address (8 bits).
The slave device sends an acknowledge signal.
The master device generates a repeated-start condition.
The master device sends the slave address (7 bits) and the data direction bit (R/W = 1).
The slave device sends an acknowledge signal if the slave address is correct.
The slave device sends the data byte from the addressed register.
If the master device sends an acknowledge signal, the control-register address is incremented by 1. The slave device sends the data byte from the addressed register. To reduce program load time, the device supports address auto incrementation. The register address is incremented after each 8 data bits.
The read cycle ends when the master device does not generate an acknowledge signal after a data byte and generates a stop condition.

Figure 13. Read Cycle

8.5.1.7 Auto-Increment Feature

8.6 Register Maps

Table 4 lists the memory-mapped registers of the device. Table 4. Register Maps

Table 4. Register Maps (continued)

Table 5. Access Type Codes

8.6.1 DEVICE_CONFIG0 (Address = 0h) [reset = 0h]

DEVICE_CONFIG0 is shown in Figure 14 and described in Table 6. Figure 14. DEVICE_CONFIG0 Register Table 6. DEVICE_CONFIG0 Register Field Descriptions

7 RESERVED R/W 0h Reserved

6 Chip_EN R/W 0h 1 = LP50xx enabled

8.6.2 DEVICE_CONFIG1 (Address = 1h) [reset = 3Ch]

DEVICE_CONFIG1 is shown in Figure 15 and described in Table 7. Figure 15. DEVICE_CONFIG1 Register Table 7. DEVICE_CONFIG1 Register Field Descriptions

5 Log_Scale_EN R/W 1h 1 = Logarithmic scale dimming curve enabled

4 Power_Save_EN R/W 1h 1 = Automatic power-saving mode enabled

3 Auto_Incr_EN R/W 1h 1 = Automatic increment mode enabled

2 PWM_Dithering_EN R/W 1h 1 = PWM dithering mode enabled

1 Max_Current_Option R/W 0h 1 = Output maximum current IMAX = 35 mA. 0 = Output maximum current IMAX = 25.5 mA.

0 LED_Global Off R/W 0h 1 = Shut down all LEDs

8.6.3 LED_CONFIG0 (Address = 2h) [reset = 00h]

LED_CONFIG0 is shown in Figure 16 and described in Table 8. Figure 16. LED_CONFIG0 Register Table 8. LED_CONFIG0 Register Field Descriptions

3 LED3_Bank_EN R/W 0h 1 = LED3 bank control mode enabled

2 LED2_Bank_EN R/W 0h 1 = LED2 bank control mode enabled

1 LED1_Bank_EN R/W 0h 1 = LED1 bank control mode enabled

0 LED0_Bank_EN R/W 0h 1 = LED0 bank control mode enabled

8.6.4 BANK_BRIGHTNESS (Address = 3h) [reset = FFh]

BANK_BRIGHTNESS is shown in Figure 17 and described in Table 9. Figure 17. BANK_BRIGHTNESS Register Table 9. BANK_BRIGHTNESS Register Field Descriptions

8.6.5 BANK_A_COLOR (Address = 4h) [reset = 00h]

BANK_A_COLOR is shown in Figure 18 and described in Table 10. Figure 18. BANK_A_COLOR Register

Table 10. BANK_A_COLOR Register Field Descriptions 7–0 Bank_A_Color R/W 0h FFh = The color mixing percentage is 100%. 80h = The color mixing percentage is 50%. 00h = The color mixing percentage is 0%.

8.6.6 BANK_B_COLOR (Address = 5h) [reset = 00h]

BANK_B_COLOR is shown in Figure 19 and described in Table 11. Figure 19. BANK_B_COLOR Register Table 11. BANK_B_COLOR Register Field Descriptions 7–0 Bank_B_Color R/W 0h FFh = The color mixing percentage is 100%. 80h = The color mixing percentage is 50%. 00h = The color mixing percentage is 0%.

8.6.7 BANK_C_COLOR (Address = 6h) [reset = 00h]

BANK_C_COLOR is shown in Figure 20 and described in Table 12. Figure 20. BANK_C_COLOR Register Table 12. BANK_C_COLOR Register Field Descriptions 7–0 Bank_C_Color R/W 0h FFh = The color mixing percentage is 100%. 80h = The color mixing percentage is 50%. 00h = The color mixing percentage is 0%.

8.6.8 LED0_BRIGHTNESS (Address = 7h) [reset = FFh]

LED0_BRIGHTNESS is shown in Figure 21 and described in Table 13. Figure 21. LED0_BRIGHTNESS Register

Table 13. LED0_BRIGHTNESS Register Field Descriptions

8.6.9 LED1_BRIGHTNESS (Address = 8h) [reset = FFh]

LED1_BRIGHTNESS is shown in Figure 22 and described in Table 14. Figure 22. LED1_BRIGHTNESS Register Table 14. LED1_BRIGHTNESS Register Field Descriptions

8.6.10 LED2_BRIGHTNESS (Address = 9h) [reset = FFh]

LED2_BRIGHTNESS is shown in Figure 23 and described in Table 15. Figure 23. LED2_BRIGHTNESS Register Table 15. LED2_BRIGHTNESS Register Field Descriptions

8.6.11 LED3_BRIGHTNESS (Address = 0Ah) [reset = FFh]

LED3_BRIGHTNESS is shown in Figure 24 and described in Table 16. Figure 24. LED3_BRIGHTNESS Register

Table 16. LED3_BRIGHTNESS Register Field Descriptions

8.6.12 OUT0_COLOR (Address = 0Bh) [reset = 00h]

OUT0_COLOR is shown in Figure 25 and described in Table 17. Figure 25. OUT0_COLOR Register Table 17. OUT0_COLOR Register Field Descriptions 7–0 OUT0_Color R/W 00h FFh = The color mixing percentage is 0%. 80h =The color mixing percentage is 50%. 00h = The color mixing percentage is 100%.

8.6.13 OUT1_COLOR (Address = 0Ch) [reset = 00h]

OUT1_COLOR is shown in Figure 26 and described in Table 18. Figure 26. OUT1_COLOR Register Table 18. OUT1_COLOR Register Field Descriptions 7–0 OUT1_Color R/W 00h FFh = The color mixing percentage is 0%. 80h =The color mixing percentage is 50%. 00h = The color mixing percentage is 100%.

8.6.14 OUT2_COLOR (Address = 0Dh) [reset = 00h]

OUT2_COLOR is shown in Figure 27 and described in Table 19. Figure 27. OUT2_COLOR Register

Table 19. OUT2_COLOR Register Field Descriptions 7–0 OUT2_Color R/W 00h FFh = The color mixing percentage is 0%. 80h =The color mixing percentage is 50%. 00h = The color mixing percentage is 100%.

8.6.15 OUT3_COLOR (Address = 0Eh) [reset = 00h]

OUT3_COLOR is shown in Figure 28 and described in Table 20. Figure 28. OUT3_COLOR Register Table 20. OUT3_COLOR Register Field Descriptions 7–0 OUT3_Color R/W 00h FFh = The color mixing percentage is 0%. 80h =The color mixing percentage is 50%. 00h = The color mixing percentage is 100%.

8.6.16 OUT4_COLOR (Address = 0Fh) [reset = 00h]

OUT4_COLOR is shown in Figure 29 and described in Table 21. Figure 29. OUT4_COLOR Register Table 21. OUT4_COLOR Register Field Descriptions 7–0 OUT4_Color R/W 00h FFh = The color mixing percentage is 0%. 80h =The color mixing percentage is 50%. 00h = The color mixing percentage is 100%.

8.6.17 OUT5_COLOR (Address = 10h) [reset = 00h]

OUT5_COLOR is shown in Figure 30 and described in Table 22. Figure 30. OUT5_COLOR Register

Table 22. OUT5_COLOR Register Field Descriptions 7–0 OUT5_Color R/W 00h FFh = The color mixing percentage is 0%. 80h =The color mixing percentage is 50%. 00h = The color mixing percentage is 100%.

8.6.18 OUT6_COLOR (Address = 11h) [reset = 00h]

OUT6_COLOR is shown in Figure 31 and described in Table 23. Figure 31. OUT6_COLOR Register Table 23. OUT6_COLOR Register Field Descriptions 7–0 OUT6_Color R/W 00h FFh = The color mixing percentage is 0%. 80h =The color mixing percentage is 50%. 00h = The color mixing percentage is 100%.

8.6.19 OUT7_COLOR (Address = 12h) [reset = 00h]

OUT7_COLOR is shown in Figure 32 and described in Table 24. Figure 32. OUT7_COLOR Register Table 24. OUT7_COLOR Register Field Descriptions 7–0 OUT7_Color R/W 00h FFh = The color mixing percentage is 0%. 80h =The color mixing percentage is 50%. 00h = The color mixing percentage is 100%.

8.6.20 OUT8_COLOR (Address = 13h) [reset = 00h]

OUT8_COLOR is shown in Figure 33 and described in Table 25. Figure 33. OUT8_COLOR Register

Table 25. OUT8_COLOR Register Field Descriptions 7–0 OUT8_Color R/W 00h FFh = The color mixing percentage is 0%. 80h =The color mixing percentage is 50%. 00h = The color mixing percentage is 100%.

8.6.21 OUT9_COLOR (Address = 14h) [reset = 00h]

OUT9_COLOR is shown in Figure 34 and described in Table 26. Figure 34. OUT9_COLOR Register Table 26. OUT9_COLOR Register Field Descriptions 7–0 OUT9_Color R/W 00h FFh = The color mixing percentage is 0%. 80h =The color mixing percentage is 50%. 00h = The color mixing percentage is 100%.

8.6.22 OUT10_COLOR (Address = 15h) [reset = 00h]

OUT10_COLOR is shown in Figure 35 and described in Table 27. Figure 35. OUT10_COLOR Register Table 27. OUT10_COLOR Register Field Descriptions 7–0 OUT10_Color R/W 00h FFh = The color mixing percentage is 0%. 80h =The color mixing percentage is 50%. 00h = The color mixing percentage is 100%.

8.6.23 OUT11_COLOR (Address = 16h) [reset = 00h]

OUT11_COLOR is shown in Figure 36 and described in Table 28. Figure 36. OUT11_COLOR Register

Table 28. OUT11_COLOR Register Field Descriptions 7–0 OUT11_Color R/W 00h FFh = The color mixing percentage is 0%. 80h =The color mixing percentage is 50%. 00h = The color mixing percentage is 100%.

8.6.24 RESET (Address = 17h) [reset = 00h]

RESET is shown in Figure 37 and described in Table 29. Figure 37. RESET Register Table 29. OUT14_COLOR Register Field Descriptions 7–0 Reset W 00h FFh = Reset all the registers to default value.

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

performance for RGB LEDs makes it a good choice for human-machine interaction applications.

9.2 Typical Application

Figure 38. Driving Dual LP5012 Application Example

ADVANCE□INFORMATION R IREF=KIREF × VIREF ISET LP5009, LP5012 SLVSEH2 –MAY 2019 www.ti.com Product Folder Links: LP5009 LP5012 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Typical Application (continued)

9.2.1 Design Requirements

Set the LED current to 15 mA using the RIREF resistor. Select the proper value for the other external components, like VCAP pin capacitor and the SCL/SDA pullup resisters.

9.2.2 Detailed Design Procedure

LP50xx scales up the reference current (IREF) set by the external resistor (RIREF) to sink the output current (IOUT) at each output port. The following formula can be used to calculate the external resistor (RIREF): (2) The SCL and SDA lines must each have a pullup resistor placed somewhere on the line (the pullup resistors are normally located on the bus master). In typical applications, values of 1.8 kΩ to 4.7 kΩ are used. VCAP is internal LDO output pin. This pin must be connected through a 1-µF capacitor to GND. Place the capacitor as close to the device as possible. TI recommends having a 1-µF capacitor between VCC and GND to ensure proper operation. Place the capacitor as close to the device as possible.

10 Power Supply Recommendations

The device is designed to operate from a VVCC input-voltage supply range from 2.7 V and 5.5 V. This input supply must be well-regulated and able to withstand maximum input current and maintain stable voltage without voltage drop even in a load-transition condition (start-up or rapid intensity change). The resistance of the input supply rail must be low enough that the input-current transient does not cause a drop below a 2.7-V level in the LP50xx VVCC supply voltage.

11 Layout

11.1 Layout Guidelines

To prevent thermal shutdown, the junction temperature, TJ, must be less than T(TSD). If the voltage drop across the output channels is high, the device power dissipation can be large. The LP50xx device has very good thermal performance because of the thermal pad design; however, the PCB layout is also very important to ensure that the device has good thermal performance. Good PCB design can optimize heat transfer, which is essential for the long-term reliability of the device. Use the following guidelines when designing the device layout:

Place the CVCAP, CVCCand RIREF as close to the device as possible. Also, TI recommends putting the ground plane as Figure 39 and Figure 40.
Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat flow path from the package to the ambient is through copper on the PCB. Maximum copper density is extremely important when no heat sinks are attached to the PCB on the other side from the package.
Add as many thermal vias as possible directly under the package ground pad to optimize the thermal conductivity of the board.
Use either plated-shut or plugged and capped vias for all the thermal vias on both sides of the board to prevent solder voids. To ensure reliability and performance, the solder coverage must be at least 85%.

11.2 Layout Examples

Figure 39. LP5009 Layout Example

Figure 40. LP5012 Layout Example

12 Device and Documentation Support

12.1 Related Links

resources, tools and software, and quick access to order now. Table 30. Related Links

12.2 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

solve problems with fellow engineers. contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.

www.ti.com 4-Jun-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LP5009RUKR PREVIEW WQFN RUK 20 3000 TBD Call TI Call TI -40 to 85 LP5012RUKR PREVIEW WQFN RUK 20 3000 TBD Call TI Call TI -40 to 85 PLP5009RUKR ACTIVE WQFN RUK 20 3000 TBD Call TI Call TI -40 to 85 PLP5012RUKR ACTIVE WQFN RUK 20 3000 TBD Call TI Call TI -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 4-Jun-2019 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2019, Texas Instruments Incorporated

Product Information

PLP5009RUKR specifications and overview.

Summary

9-, 12-Channel, 12-Bit PWM Ultra-low Quiescent Current I2C RGB LED Drivers

Description

9-, 12-Channel, 12-Bit PWM Ultra-low Quiescent Current I2C RGB LED Drivers

Source title PLP5009RUKR Datasheet(PDF) - Texas Instruments

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