PLMZM23601SILR

Texas Instruments

36-V, 1-A Step-Down DC-DC Nano Module

Manufacturer: Texas Instruments

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ADVANCE□INFORMATION C IN 1206 C OUT 0805 3.8 mm x 3.0 mm package 27 mm 2 Single Sided Layout Copyright © 2017, Texas Instruments Incorporated GND VIN C IN GND MODE/ SYNC VIN EN PGOOD FB VOUT VOUT GND C OUT Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. LMZM23601 SNVSAQ4 –DECEMBER 2017 LMZM2360136-V,1-AStep-DownDC-DCNanoModule

1 Features

1• 4-V to 36-V Wide Operating Input Voltage

Adjustable, 3.3-V, or 5-V Output Voltage Options
1-A Output Current
Only Input and Output Capacitor Needed for 5-V and 3.3-V Output Designs
27-mm2 Solution Size With Single Sided Layout
30-µA Supply Current at No Load
2-µA Shutdown Current
Power-Good Flag
External Frequency Synchronization
MODE Selection Pin – Forced PWM Mode for Constant Frequency Operation – Auto PFM Mode for High Efficiency at Light Load
Built-in Control Loop Compensation, Soft Start, Current Limit, and UVLO
Miniature 3.8-mm × 3-mm × 1.6-mm Package

2 Applications

Factory Automation, Test and Measurement
Space Constrained Applications
LDO Replacement

3 Description

The LMZM23601 nano module is specifically designed for space-constrained industrial applications and is available in fixed output voltage options of 5-V and 3.3-V and an adjustable (ADJ) output voltage option with 2.5-V to 15-V range. The LMZM23601 supports an input voltage range of 4-V to 36-V and can deliver up to 1000-mA of output current. This nano module is extremely easy to use, requiring only 2 external components for a 5-V or 3.3-V output design. All aspects of the LMZM23601 are optimized for performance driven industrial applications with space-constrained needs. An open-drain, Power- Good output provides a true indication of the system status. This feature negates the requirement for an additional supervisory component, saving cost and board space. Seamless transition between PWM and PFM modes along with a no-load supply current of only 30 µA ensures high efficiency and superior transient response for the entire load-current range. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LMZM23601 MicroSiP™ (10) 3.80 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. space space space Schematic for Fixed Output Option 24-V to 5-V, 1-A DC-DC Converter Single-Sided Layout Solution Size 24-V to 5-V, 1-A DC-DC Converter

12.2 Receiving Notification of Documentation Updates 29

13 Mechanical, Packaging, and Orderable

4 Revision History

December 2017 * Initial release

5 Device Comparison

(1) See Package Option Addendum for tape and reel details as well as links used to order parts. Table 1. LMZM23601 Device Options

ADVANCE□INFORMATION GND MODE /SYNC VIN EN PGOOD DNC DNC DNC FB VOUT Thermal Pad 5 6 LMZM23601 SNVSAQ4 –DECEMBER 2017 www.ti.com Product Folder Links: LMZM23601 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) G = Ground, I = Input, O = Output, P = Power

6 Pin Configuration and Functions

TYPE(1) DESCRIPTION NO. NAME 1 GND G Ground for all circuitry. Reference point for all voltages.

2 MODE/SYNC I

This is a multifunction mode control input which is tolerant of voltages up to the input voltage. With this input tied LOW, the device is in Auto PFM mode with automatic transition between PFM and PWM with diode emulation at light load. This mode is recommended when the application requires high efficiency at light load. With this input tied HIGH, the device is in forced PWM mode. The device switches at the internal clock frequency. This mode is recommended when the application requires constant switching frequency across the entire load current. With a valid synchronization signal at this pin, the device switches in forced PWM mode at the external clock frequency and synchronized with it at the rising edge of the clock. Do not float this pin. 3 VIN P Input supply to the regulator. Connect a high-quality bypass capacitor(s) directly to this pin and the GND pin (pin 1). 4 EN I Enable input to the regulator. HIGH = ON, LOW = OFF. This pin can be connected to VIN. Do not float. 5 PGOOD O Open-drain, power-good output. Connect to a suitable voltage supply through a current limiting resistor. HIGH = power is good, LOW = fault. This output terminal is LOW when EN is LOW.

6 VOUT O

Output voltage terminal. It is internally connected to one terminal of the integrated inductor. Connect an output filter capacitor from VOUT to GND and place the capacitor as close as possible to the VOUT pin.

7 FB I

Feedback input to the regulator. If using the fixed 3.3-V or 5-V options of the device, connect this pin to the positive end of the output filter capacitor (the VOUT node). If using the adjustable output option of the device connect this to the feedback voltage divider and keep this node as small as possible on the board layout. 8 DNC O Do not connect. Leave floating. This pin provides access to the internal VCC voltage of the device. 9 DNC O Do not connect. Leave floating. This pin provides access to the internal BOOT voltage for the high side MOSFET driver. 10 DNC O Do not connect. Leave floating. This pin provides access to the internal SW voltage of the device. Thermal Pad G This terminal is internally connected to GND and provides a wide thermal connection from the IC to the PCB. Connect to electrical ground plane for adequate heat sinking.

ADVANCE□INFORMATION LMZM23601 www.ti.com SNVSAQ4 –DECEMBER 2017 Product Folder Links: LMZM23601 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VIN to GND –0.3 42 V SW to GND –0.3 VIN + 0.3 V BOOT to SW –0.3 3.6 V EN to GND –0.3 42 V FB to GND (3.3-V and 5-V options) –0.3 16 V FB to GND (ADJ option) –0.3 5.5 V PGOOD to GND –0.3 16 V PGOOD sink current 8 mA MODE/SYNC to GND –0.3 42 V VCC to GND -0.3 3.6 V Operating junction temperature, TJ –40 125 °C Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage 4 36 V VOUT Output voltage (5 V) 0 5 V Output voltage (3.3 V) 0 3.3 V Output voltage (ADJ) 2.5 15 V IOUT Output current (1 A) 0 1 A Output current (0.5 A) 0 0.5 A TJ Operating junction temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.4 Thermal Information

THERMAL METRIC(1) LMZM23601 UNITSIL (USIP)

10 PINS

RθJA Junction-to-ambient thermal resistance 45 °C/W ΨJT Junction-to-top characterization parameter 3 °C/W ΨJB Junction-to-board characterization parameter 20 °C/W

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of -40°C to +125°C, unless otherwise stated. Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FEEDBACK VFB Initial output voltage accuracy (3.3-V and 5-V fixed output) VIN = 4 V to 36 V, open loop, TJ = 25°C –1% 1% VIN = 4 V to 36 V, open loop –1.5% 1.5% VREF Reference voltage (ADJ option) TJ = 25°C 0.993 1 1.007 V 0.985 1 1.015 IFB Input current from FB to GND (ADJ option) FB = 1 V 20 nA CURRENT IQ Operating quiescent current; measured at VIN pin VIN = 12 V, VFB = 5%, VOUT = 5 V 6.5 µA VIN = 12 V, VFB = 5%, VOUT = 5 V, TJ = 85°C 16 µA VIN = 12 V, VFB = 5%, VOUT = 5 V, TJ = 125°C TBD VIN = 24 V, VFB = 5%, VOUT = 5 V 15 VIN = 24 V, VFB = 5%, VOUT = 5 V, TJ = 85°C 30 VIN = 24 V, VFB = 5%, VOUT = 5 V, TJ = 125°C TBD IB Bias current into the VOUT pin VIN = 24 V, VFB = 5%, VOUT = 5 V, Mode = 0 V 46 80 µA ISD Shutdown quiescent current; measured at VIN pin EN = 0 V, VIN = 12 V, TJ = 25°C 1.8 µA EN = 0 V, VIN = 12 V, TJ = 85°C 3 EN = 0 V, VIN = 24 V, TJ = 25°C 7 EN = 0 V, VIN = 24 V, TJ = 85°C TBD UNDERVOLTAGE LOCKOUT (UVLO) VIN_UVLO Minimum input voltage to operate Rising 3.5 3.6 3.75 V VIN_UVLO_HYST UVLO hysteresis 0.28 0.3 0.35 V

ADVANCE□INFORMATION LMZM23601 www.ti.com SNVSAQ4 –DECEMBER 2017 Product Folder Links: LMZM23601 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) Limits apply over the recommended operating junction temperature range of -40°C to +125°C, unless otherwise stated. Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER GOOD FLAG (PGOOD) VPGOOD_OV PGOOD upper threshold voltage Rising, % of Vout 105% 106.5% 110% VPGOOD_UV PGOOD lower threshold voltage Falling, % of Vout 92% 94% 97% VPGOOD_GUARD Magnitude of PGOOD lower threshold difference from steady state output voltage. Steady state output voltage PGOOD threshold read at the same TJ and VIN 4.5% VPGOOD_HYST PGOOD hysteresis as a percent of output voltage set point 1% VPGOOD_VALID Minimum input voltage for proper PGOOD function 50-µA pullup to PGOOD pin, EN = 0 V, TJ = 25°C V tRESET_FILTER Glitch filter time constant for PGOOD function 90 µs VOL Low-level PGOOD function output voltage 50-µA pullup to PGOOD pin, VIN = 1.5 V, EN = 0 V 0.4 V0.5-mA pullup to PGOOD pin, VIN = 12 V, EN = 0 V 0.4 1-mA pullup to PGOOD pin, VIN = 12 V, EN = 3.3 V 0.4 RPGOOD_RDSON RDSON of the PGOOD output pull down 50 80 Ω SWITCHING FREQUENCY fSW Switching frequency VIN = 24 V, 5-V and 3.3-V fixed output options 675 750 825 kHz VIN = 24 V, ADJ output options 900 1000 1100 VIN = 36 V, 5-V and 3.3-V fixed output options 750 VIN = 36 V, ADJ output options 800 FREQUENCY SYNCHRONIZATION AND MODE fSYNC Sync frequency range 5-V and 3.3-V fixed output options VOUT + VDROPOUT < VIN < 36 V 500 825 kHz ADJ output options VOUT + VDROPOUT< VIN < 28 V 700 1100 DSYNC Sync input duty cycle range 2.3 V < HIGH state input < 5.5 V 25% 75% VMODE_HIGH MODE/SYNC input logic HIGH voltage to enter FPWM mode 1.5 V VMODE_LOW MODE/SYNC input logic LOW voltage to enter AUTO PFM mode 0.4 V IMODE MODE/SYNC leakage current VIN = 12 V, VMODE/SYNC = 3.3 V 1 µA VIN = 12 V, VMODE/SYNC = 12V 5 tMODE MODE transition time to FPWM VIN = 12 V, VOUT = 5 V, IOUT= 20 mA 300 µsMODE transition time to AUTO PFM VIN = 12 V, VOUT = 5 V, IOUT = 20 mA 300 CURRENT LIMIT PROTECTION IL-HS high-side switch current limit Duty cycle approaches 0% 1.45 1.81 2.18 A IL-LS low-side switch current limit 1 1.2 1.43 A IL-ZC Zero-cross current limit MODE/SYNC = logic LOW –0.01 A IL-NEG Low-side reverse current limit (positive current ino the SW pin to GND) MODE/SYNC = logic HIGH 0.5 0.8 A

ADVANCE□INFORMATION LMZM23601 SNVSAQ4 –DECEMBER 2017 www.ti.com Product Folder Links: LMZM23601 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) Limits apply over the recommended operating junction temperature range of -40°C to +125°C, unless otherwise stated. Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER STAGE CHARACTERISTICS HS RDS-ON High-side MOSFET on-resistance 220 mΩ LS RDS-ON Low-side MOSFET on-resistance 200 mΩ tON-MIN Minimum high-side on-time IOUT = 500 mA 50 75 ns tOFF-MIN Minimum high-side off-time IOUT = 500 mA 90 125 ns DMAX Maximum switch duty cycle 5-V and 3.3-V fixed output options 93% ADJ option 91% While I n frequency foldback 97% L Integrated inductor - inductance 10 µH LDCR Integrated inductor - DCR 390 mΩ ENABLE VEN Enable input threshold voltage Rising 1.7 1.9 V VEN_HYST Enable input threshold hysteresis 0.45 0.55 V VEN_WAKE Enable input wake-up threshold 0.4 V IEN Enable pin input current VIN = VEN = 12 V 2.7 µA VCC REGULATOR VCC Internal VCC voltage VIN = 12 V, VOUT < 3.3 V 3.05 V VIN = 12 V, VOUT ≥ 3.3V 3.15 VCC_UVLO Internal VCC voltage input UVLO VIN rising 2.75 2.81 2.87 V VCC_UVLO_HYST Internal VCC voltage input UVLO hysteresis Hysteresis below VCC_UVLO 160 205 mV SOFT START tSS Soft-start time Time for VREF to ramp from 0% to 90% 3 4 5.5 ms tEN_LV Turnon delay with low VIN VIN < 4.2 V 4 ms tEN Turnon delay VIN = 12 V 0.7 ms tW Short circuit wait time (hiccup time) 8.0 ms THERMAL PROTECTION TSD Thermal shutdown Rising threshold 155 169 °C TSD_HYST Thermal shutdown hysteresis 15 °C

7.6 System Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT VOLTAGE REGULATION 5-V OPTION VOUT 5-V option no load accuracy VIN = 24 V, IOUT = 0 A, AUTO PFM mode xxx 5 xxx V AUTO PFM mode, IOUT = 0 A to xx A xxx %/A AUTO PFM mode, IOUT > xx A xxx VIN = 24 V, IOUT = 0 A, FPWM mode xxx 5 xxx V FPWM mode, IOUT > xx A xxx %/A VIN = 6 V to 36 V xxx %/V OUTPUT VOLTAGE REGULATION 3.3-V OPTION VOUT 3.3-V option no load accuracy VIN = 24 V, FPWM mode, IOUT = 0 A, AUTO PFM mode xxx 3.3 xxx V AUTO PFM mode, IOUT = 0 A to xx A xxx %/A AUTO PFM mode, IOUT > xx A xxx VIN = 24 V, IOUT = 0 A, FPWM mode xxx 3.3 xxx V FPWM mode, IOUT > xx A xxx %/A VIN = 4.5 V to 36 V xxx %/V SUPPLY CURRENT IQ-VIN Input current to the VIN node of the DC-DC converter while in regulation VIN =12 V, VOUT = 3.3 V, IOUT = 0 A 23 µA VIN =12 V, VOUT = 5 V, IOUT = 0 A 30 VIN =24 V, VOUT = 3.3 V, IOUT = 0 A 30 VIN = 24 V, VOUT = 5 V, IOUT = 0 A 32 EFFICIENCY Efficiency Typical efficiency 12-V input VIN =12 V, VOUT = 5 V, IOUT = 1 A 87% VIN = 12 V, VOUT = 3.3 V, IOUT = 1 A 81% VIN = 12 V, VOUT = 5 V, IOUT = 0.5 A 90% VIN = 12 V, VOUT = 3.3 V, IOUT = 0.5 A 87% Typical efficiency 24-V input VIN = 24 V, VOUT = 5 V, IOUT = 1 A 85% VIN = 24 V, VOUT = 3.3 V, IOUT = 1 A 79% VIN = 24 V, VOUT = 5 V, IOUT = 0.5 A 87% VIN = 24 V, VOUT = 3.3 V, IOUT = 0.5 A 83% VIN = 24 V, VOUT = 12 V, IOUT = 1 A 92% Typical efficiency 24-V input VIN = 24 V, VOUT = 12 V, IOUT = 0.5 A 93%

ADVANCE□INFORMATION MOSFET DRIVER HS CURRENT SENSE LS CURRENT SENSE OSCILLATOR PWM COMP.ERROR AMPLIFIER VOUT VIN GND FB EN 1-V REFERENCE ENABLE LOGIC PGOOD PFM MODE CONTROL Copyright © 2017, Texas Instruments Incorporated INT. REG. BIAS VCC BOOT MODE/SYNC SW UVLO THERMAL PROTECTION CONTROL LOGIC MOSFET DRIVER VCC HS LS POWER GOOD CONTROL ADJ VOUT OPTION FIXED VOUT OPTION OR LMZM23601 SNVSAQ4 –DECEMBER 2017 www.ti.com Product Folder Links: LMZM23601 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The LMZM23601 is a 4-V to 36-V wide-input voltage range, low quiescent current, high-performance DC-DC module designed specifically for space constrained industrial applications. The device is available in an adjustable output voltage option with 2.5-V to 15-V output range, as well as fixed 5-V and 3.3-V output options. The high level of integration and innovative packaging technology utilized in this nano module makes it possible to design a 5-V or 3.3-V 1-A switching converter solution with only an input capacitor, an output capacitor, and 27 mm² of available board space.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Control Scheme

The LMZM23601 nano module utilizes peak-current-mode-control architecture. This enables the use of wide range of input voltages while maintaining constant switching frequency and good input and output transient response. The device can be used with 5-V, 12-V, or 24-V typical industrial input voltage rail. The short minimum on- and off-times ensure constant frequency regulation over a wide range of input to output voltage conversion ratios. The adjustable (ADJ) output voltage option operates at 1000-kHz switching frequency. The minimum on- and off- times allow for a duty factor window of 5% to 91% at 1000-kHz switching frequency. If the input voltage exceeds approximately 28 V on the ADJ version, the frequency is smoothly reduced from 1000 kHz as a function of input voltage. The switching frequency reduction allows output voltage regulation and the current mode control to operate with a duty factor below 5%. The fixed 5-V and 3.3-V output options operate at 750 kHz nominal switching frequency and the frequency fold back at high input voltage is not active or needed.

ADVANCE□INFORMATION LMZM23601 www.ti.com SNVSAQ4 –DECEMBER 2017 Product Folder Links: LMZM23601 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated Feature Description (continued) The control architecture also uses frequency foldback at low input voltage in order to achieve low dropout voltage, maintaining output regulation as the input voltage falls close to output voltage. The frequency foldback at low input voltage is active for the ADJ as well as the 5-V and 3.3-V output options. The reduction in frequency is smooth and continuous and is activated as the off-time approaches the minimum value. Under these conditions, the LMZM23601 device operates much like a constant off-time converter allowing the maximum duty cycle to reach 97%. This feature allows output voltage regulation with very low dropout. The LMZM23601 features exceptional conversion efficiency at light load. As the load current is reduced, the LMZM23601 transitions to light-load mode if the MODE/SYNC terminal is pulled low. In light-load mode the device uses diode emulation to reduce the RMS inductor current and the switching frequency is reduced. The fixed voltage versions (3.3-V and 5-V) do not need an external voltage divider connected to FB, which results in saving two components and lower standby current when the load is in standby. As a result, the consumed supply current is only 21 µA (typical) with 24-V to 3.3-V conversion and 24 µA (typical) with 24-V to 5-V conversion, while the output is regulated with no load.

8.3.2 Soft-Start Function

The LMZM23601 features an internally programmed soft-start time. The soft-start time is fixed internally at about 4 ms and is achieved by ramping the internal reference. The LMZM23601 device starts up properly even if there is a voltage present on output before the activation of the LMZM23601. In such cases, there is no switching until the output voltage value programmed by the ramping reference voltage is above the pre-biased output value. Once the pre-biased voltage level is reached by the reference ramp, the switching starts, and the output ramps up smoothly from the pre-biased value up to the final output voltage.

8.3.3 Enable and External UVLO Function

Some applications may require a precision enable or custom input voltage lock-out (UVLO) functionality. Setting up external UVLO based on the application needs would prevent the converter from trying to regulate the output voltage until after the input voltage has reached a desired minimum level. Such function can be used to lower the current demand from the input supply as the supply is still starting up. The LMZM23601 features a precision enable (EN) input terminal. The EN input logic has two internal thresholds. The first rising threshold is at 0.9V typical. Its purpose is to wake up the internal VCC regulator to bias the internal circuitry. The EN rising threshold to start switching is 1.8V (typical) with 0.5V (typical) hysteresis. A voltage divider from VIN to EN can be used to set the VIN voltage at which the regulator starts the voltage conversion. The EN terminal is rated for up to the input voltage and can be connected directly to VIN for an always-on operation. Pulling the EN pin below 0.4 V puts the LMZM23601 in shutdown mode. In shutdown mode and 12-V input voltage the LMZM23601 only consumes 1.8 µA (typical) of input current.

8.3.4 Current Limit

The LMZM23601 devices features two current limits inside the IC. A coarse high side or peak current limit is provided to protect against faults. The high-side current limit limits the duration of the on-period of the high-side power MOSFET during a given clock cycle. A precision cycle-by-cycle valley current limit prevents excessive average output current. A new switching cycle is not initiated until the inductor current drops below the valley current limit.

Figure 1. Current Limit Operation During Output Short Circuit a small number of cycles, hiccup mode is activated.

8.3.5 Hiccup Mode

ms. After the wait period, the device restarts operation beginning with a soft-start time interval. Figure 2. Hiccup Operation removed, the output ramps up during the next restart sequence.

8.3.6 Power Good (PGOOD) Function

The LMZM23601 has a built-in power-good signal presented at the PGOOD terminal. This signal indicates whether the output voltage is within the regulation window. The PGOOD terminal is an open-drain output that requires a pullup resistor to a nominal voltage source of 15 V or less. The absolute maximum PGOOD sink current is 8 mA. Typically, TI recommends a pullup resistor value between 10 kΩ and 100 kΩ. Refer to Electrical Characteristics for the power-good thresholds and hysteresis for undervoltage and overvoltage detection.

8.3.7 MODE/SYNC Function

8.3.7.1 Forced PWM Mode

When constant frequency operation is more important than light load efficiency, the MODE/SYNC input of the LMZM23601 device must be pulled high or a valid synchronization input must be provided. This activates forced- PWM-mode operation. Once activated, this feature ensures that the switching frequency stays constant across the entire load current range, while operating between the minimum and maximum duty cycle limits. The diode emulation feature is turned off in this mode. This means that the device remains in CCM under light loads. The switching frequency in forced PWM mode is only reduced when the input voltage-to-output voltage ratio results in minimum on-time limitation (ADJ version only) or minimum off-time limitation near dropout. This feature may be activated and deactivated while the part is regulating without removing the load. This feature activates and deactivates gradually, preventing perturbation of output voltage. When in FPWM mode, a limited reverse current is allowed through the inductor allowing power to pass from the regulators output to its input.

8.3.7.2 Auto PFM Mode

If the MODE/SYNC terminal is held low the LMZM23601 device enables automatic power-saving-mode transition at light load. With high load the LMZM23601 regulates the output using normal PWM operation. When the load is light, the control logic smoothly transitions to PFM operation and diode emulation. In this mode, the high side MOSFET is turned on for one or more pulses to provide energy to the load. The on-time of the high side in this mode depends on the input voltage level and a pre-programmed internal IPEAK-MIN current level. The higher the input voltage is, the shorter the on-time is. At this point, there is a longer off-time during which the output would still be in the regulation window because the load is light, and the output is not getting discharged as quickly. The duration of the off-time depends on the load current level. Lighter load results in longer off-time. This mode of operation results in excellent conversion efficiency at very light load. When auto-PFM mode is used, the output voltage at no load is approximately 1% higher than FPWM operation.

8.3.7.3 Dropout Mode

When the input voltage level decreases and approaches the output voltage level, the buck regulator reaches its maximum duty cycle or minimum off-time requirement for each switching cycle. At this point the output is no longer regulated and follows the input voltage minus the voltage drops from VIN to VOUT. In order to maximize the input voltage range for which the output is still regulated, the LMZM23601 features frequency foldback at low input voltage. This operation extends the switching period and, for a given fixed minimum off-time, it prolongs the maximum duty cycle of the regulator. As a result, the output voltage can still be well regulated even as the input voltage level is very close to the output voltage. This feature can be useful for battery applications (maximizing the useful battery range) or in applications where large input voltage variations can be expected.

8.3.7.4 SYNC Operation

technique results in better defined EMI behavior and can reduce the need for capacitance on some power rails. the LMZM23601 device replaces the internal free-running clock but does not affect frequency foldback operation. normal duty cycle range are reached. The device remains in FPWM mode and operates in CCM for light loads when synchronization input is provided. summarizes the MODE/SYNC function and the operating switching frequency with various conditions. Table 2. Switching Frequency and MODE/SYNC Function

8.3.8 Thermal Protection

junction temperature has decreased under the hysteresis level, typically 15°C below the shutdown temperature.

8.4 Device Functional Modes

8.4.1 Shutdown

The LMZM23601 device shuts down most internal circuitry and high-side and low-side power MOSFETs under any of the following conditions: 1. EN is low 2. VIN is below the falling UVLO threshold 3. Junction temperature exceeds TSD threshold The PGOOD flag remains operational with input voltage as low as 1.5 V.

8.4.2 FPWM Operation

If MODE/SYNC is above the VMODE/SYNC high threshold or a valid synchronizing is applied to MODE/SYNC, constant frequency operation is maintained across load. The ADJ option of the device folds back the frequency when VIN exceeds 28 V typical so that the output voltage can be properly regulated. See Table 2 for all use cases and options. FPWM mode requires negative current be allowed in the inductor if the load is light. If a large negative load is present, operation is halted by a reverse current limit, IL-NEG.

8.4.3 Auto PFM Mode Operation

If MODE/SYNC is below the VMODE/SYNC low threshold, reverse current in the inductor is not allowed. This feature is called diode emulation. While the load is heavy, the regulator uses PWM mode to control the output. If the load is light, the control logic transitions to PFM mode. The switching frequency is reduced, resulting in excellent energy savings while regulation is maintained. Because the frequency is reduced and switching pulses can come in groups, the output voltage ripple can increase slightly. Under this condition, the output ripple can be reduced by increasing the output capacitance.

9 Applications and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

simple design procedure for creating a DC-DC converter design with these modules.

9.2 Typical Applications

addition of two feedback resistors to the bill of materials. Figure 3. Fixed 5- V or 3.3-V Typical Application Circuit

Figure 4. Adjustable 2.5-V to 15-V Output Typical Application Circuit

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 3 as the input parameters. Table 3. Design Parameters

9.2.2 Detailed Design Procedure

9.2.2.1 Input Capacitor Selection

The input capacitor selection and placement on the board layout is very important for any buck converter design. rating are recommended when using the device with a 12-V input supply. Just like with any buck converter, place the input capacitor as close as possible and next to the LMZM23601.

Table 4. Input Capacitor Selection For this design example a single 10-µF, 50-V 1210 X7R capacitor is used.

9.2.2.2 Output Capacitor Selection

voltage. For this example with a 5-V output a 22-µF capacitor can be used. Table 5. Output Capacitor

2.5 V 47 µF 68 µF 390 µF

3.3 V 22 µF 33 µF 330 µF

5 V 15 µF 22 µF 220 µF

12 V 10 µF 15 µF 200 µF

15 V 10 µF 15 µF 200 µF

9.2.2.3 Feedback Voltage Divider for Adjustable Output Voltage Versions

Figure 5. Adjustable 2.5 V to 15 V Output Typical Application Circuit

external resistors, RFBT and RFBB. The range of adjustable output voltage is 2.5 V to 15 V. top feedback resistor RFBT can be set to 102 kΩ. The RFBB value results in 25.5 kΩ.

9.2.2.4 RPU - PGOOD Pull Up Resistor

necessary, the PGOOD terminal can be left floating.

9.2.2.5 VIN Divider and Enable

connected from VIN to the EN terminal to set the turnon threshold. Figure 6. Enable Divider to Set External UVLO Threshold Choose the top resistor RENB between 10 kΩ and 50 kΩ and calculate the RENT according to Equation 3.

VSTART is the rising input voltage level at which switching starts. Choose this value based on the application requirements.
VSTOP is the input voltage at which switching stops
VEN is the rising threshold on EN; see Electrical Characteristics
VEN_HYST is the hysteresis on the EN threshold; see Electrical Characteristics (3)

9.2.3 Application Curves

Unless otherwise stated, the following conditions apply: VIN = 24 V, TA = 25°C.

9.2.3.1 VOUT = 5 V

Figure 7. Efficiency Figure 8. Load Transient Figure 9. Output Ripple 20 MHz BW Figure 10. Output Ripple 250-MHz BW Figure 11. Line and Load Regulation Figure 12. Start-up With 24-V Input

9.2.3.3 VOUT = 12 V

Figure 19. Efficiency Figure 20. Load Transient Figure 21. Output Ripple 20-MHz BW Figure 22. Output Ripple 250-MHz BW Figure 23. Line and Load Regulation Figure 24. Start-up With 24-V Input

9.2.3.4 VOUT = 15 V

Figure 25. Efficiency Figure 26. Load Transient Figure 27. Output Ripple 20-MHz BW Figure 28. Output Ripple 250-MHz BW Figure 29. Line and Load Regulation Figure 30. Start-up with 24-V Input

9.3 Do's and Don't's

Don't: Exceed the absolute maximum ratings of the device.
Don't: Exceed the ESD ratings of the device.
Don't: Exceed the recommended operating conditions.
Don't: Allow the EN or MODE/SYNC terminals to float.
Don't: Allow the output voltage to exceed the input voltage, nor go below ground.
Do: Follow all of the guidelines and/or suggestions found in this data sheet, before committing your design to production.
Do: Review your designs with TI Application Engineers on the E2E forum.

ADVANCE□INFORMATION CER CABLE BULK C LESR t CERBULK C4C ut Ku ut INMIN OUTMAXOUT IN V IVI LMZM23601 SNVSAQ4 –DECEMBER 2017 www.ti.com Product Folder Links: LMZM23601 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated

10 Power Supply Recommendations

10.1 Supply Voltage Range

The voltage of the input supply must not exceed the absolute maximum ratings and the recommended operating conditions of the LMZM23601.

10.2 Supply Current Capability

The input supply must be able to supply the required input current to the LMZM23601 converter. The required input current depends on the application's minimum input voltage, the required maximum output current, the output voltage, and the converter efficiency η for this condition. (4) As an example, assuming that the adjustable output voltage version of the LMZM23601 is used for a 5-V, 1-A output converter design with 12-V minimum input voltage. The conversion efficiency for this condition is about 85 %. The required input current from the supply would be 0.49 A, so an input power supply with ≥ 0.5 A current capability would be recommended.

10.3 Supply Input Connections

Long input connection cables can cause issues with the normal operation of any buck converter. Some of the issues could be a voltage drop in the input voltage or stability probes because of the added series input inductance.

10.3.1 Voltage Drops

Using long input wires to connect the supply to the input of any converter adds impedance in series with the input supply. This impedance can cause a voltage drop at the VIN pin of the converter when the output of the converter is loaded. If the input voltage is near the minimum input operating voltage for the design, this added voltage drop can cause the converter to drop out or reset. If long wires are used during testing, it is recommended to add some bulk (for example, electrolytic) capacitance at the input of the converter.

10.3.2 Stability

The added inductance of long input cables together with the ceramic (and low ESR) input capacitor can result in an underdamped RLC network at the input of the buck converter. This circuit may cause instability, or over- voltage transients at the VIN pin each time the input supply is cycled on and off. If long wires are used, TI recommends adding some electrolytic bulk capacitance in parallel with the ceramic input capacitor. The ESR of the bulk capacitor improves the damping. Use an electrolytic capacitor with a capacitance at least four times larger than the ceramic input capacitance. (5) The required ESR from the bulk capacitor depends on the cable inductance. (6) For example, two cables (one for VIN and one for GND), each 1 meter (approximately 3 feet) long with ~1 mm diameter (18 AWG), placed 1 cm (approximately 0.4 inch) apart forms a rectangular loop resulting in about 1.2 µH of inductance. The inductance in this example can be decreased to almost half if the input wires are twisted. Based on a 10-µF ceramic input capacitor, the recommended parallel CBULK is ≥ 40 µF. Using a 47-µF capacitor is sufficient. Based on about 1.2 µH of inductance and 10 µF of ceramic input capacitance, the recommended ESR of the bulk capacitor is 0.35 Ω or larger. See TI User Guide, Simple Success with Conducted EMI for DC- DC Converters for more details on input filter design.

11 Layout

11.1 Layout Guidelines

Minimize the inductance in the switching current path of the converter. The switching current path in the buck

minimum. This results in the lowest possible inductance in the path of high di/dt current.

Protect any sensitive nodes in the converter design. The feedback node is usually a sensitive area of the

LMZM23601 device so that the feedback node is as small as possible.

Provide enough copper for heat dissipation. The board copper provides a thermal resistance path for the

board layers. TI recommends an unbroken GND plane or GND area of copper on the top and bottom layers.

11.2 Layout Example

Figure 37. Layout Example With Fixed Output Version

Figure 38. Layout Example With Adjustable Output Version

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation request the following: AN-1149 Layout Guidelines for Switching Power Supplies Constructing Your Power Supply – Layout Considerations AN-1229 Simple Switcher PCB Layout Guidelines (SNVA054) Using New Thermal Metrics PowerPAD Made Easy PowerPAD™ Thermally Enhanced Package Semiconductor and IC Package Thermal Metrics AN-2020 Thermal Design By Insight, Not Hindsight AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages TI User Guide, Simple Success with Conducted EMI for DC-DC Converters

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

MicroSiP, PowerPAD, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 12-Dec-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PLMZM23601SILR ACTIVE uSiP SIL 10 3000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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Product Information

PLMZM23601SILR specifications and overview.

Summary

36-V, 1-A Step-Down DC-DC Nano Module

Description

36-V, 1-A Step-Down DC-DC Nano Module

Source title PLMZM23601SILR Datasheet(PDF) - Texas Instruments

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