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PLMX1204RHAT

Texas Instruments

LMX1204 Low-Noise, High-Frequency JESD Buffer/Multiplier/Divider SNAS800 ??JULY 2021

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LMX1204 Low-Noise, High-Frequency JESD Buffer/Multiplier/Divider

1 Features

300-MHz to 12.8-GHz output frequency
Noise floor of –160 dBc/Hz at 6-GHz output
Under 30-fs additive jitter (DC to fCLK integration range)
4 high-frequency clocks with corresponding SYSREF outputs – Shared divide by 1 (Bypass), 2, 3, 4, 5, 6, 7, and 8 – Shared programmable multiplier x2, x3, and x4
LOGICLK output with corresponding SYSREF output – On separate divide bank – 1, 2, 4 pre-divider – 1 (bypass), 2, …, 1023 post divider
8 programmable output power levels
Synchronized SYSREF clock outputs – 508 delay step adjustments of less than 2.5 ps each at 12.8 GHz – Generator and repeater modes – Windowing feature for SYSREFREQ pins to optimize timing
SYNC feature to all divides and multiple devices
2.5-V operating voltage
–40ºC to +85ºC operating temperature

2 Applications

General purpose: – Data converter clocking – Clock distribution/multiplication/division
Test equipment: – Oscilloscopes – Wideband digitizers – Wireless equipment testers
Aerospace and defense: – Radar – Electronic warfare – Seeker front end – Munitions – Phased array antenna/beam forming

3 Description

The high frequency capability and extremely low jitter of this device, makes a great solution to clock precision, high-frequency data converters without degradation to the signal-to-noise ratio. Each of the 4 high frequency clock outputs and additional LOGICLK output with larger divider range, is paired with a SYSREF output clock signal. The SYSREF signal for JESD interfaces can either be internally generated or passed in as an input and re-clocked to the device clocks. For data converter clocking applications, it is critical to have the jitter of the clock be less than the aperture jitter of the data converter. In applications where more than 4 data converters need to be clocked, a variety of cascading architectures can be developed using multiple devices to distribute all the high frequency clocks and SYSREF signals required. With 30 fs of additive jitter and a noise floor of -160 dBc/Hz, this device combined with an ultra-low noise reference clock source is an exemplary solution for clocking data converters, especially when sampling above 3 GHz. Device Information(1) PART NUMBER PACKAGE BODY SIZE LMX1204 VQFN (40) 6.00 mm × 6.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Output Options PART NUMBER MULTIPLIER OUTPUT LMX1204 3.2 to 6.4 GHz CLKOUT0 SYSREFOUT0 CLKOUT1 SYSREFOUT1 CLKOUT2 SYSREFOUT2 CLKOUT3 SYSREFOUT3 LOGICLK LOGISYSREF CLKIN SYSREFREQ ÷2,3,..,8 ÷1,2,3,...4092 Digital Control SDI CS# MUXOUT CAL SCK RETIME RETIME Pulser÷2,3, … , 16380 SYSREF GENERATOR xM Block Diagram ADVANCE INFORMATION LMX1204 SNAS800 – JULY 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

11.1 Receiving Notification of Documentation Updates.. 25

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE VERSION NOTES July 2021 * Initial release. LMX1204 SNAS800 – JULY 2021 www.ti.com ADVANCE INFORMATION

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5 Pin Configuration and Functions

SYSREFOUT3_N GND CLKOUT3_P CLKOUT3_N VCC23 GND GND VCC_LOGICLK LOGISYSREFOUT_P LOGISYSREFOUT_N SYSREFOUT1_N SYSREFOUT1_P GND VCC01 CLKOUT0_N CLKOUT0_P GND SYSREFOUT0_N CLKOUT2_N SYSREFREQ_P SYSREFOUT0_P MUXOUT SYSREFREQ_N CLKIN_N VCC_CLKIN GND SCK CLKOUT2_P CLKIN_P DAP SDI CS# BIAS01 CLKOUT1_N CLKOUT1_P BIAS23 SYSREFOUT3_P SYSREFOUT2_P SYSREFOUT2_N LOGICLKOUT_P LOGICLKOUT_N 20 21 Figure 5-1. RHA Package 40-Pin VQFN Top View www.ti.com LMX1204 SNAS800 – JULY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LMX1204

Table 5-1. Pin Functions NAME NO. TYPE DESCRIPTION BIAS01 20 BYP If not using the multiplier, this pin may be left open. If using the multiplier, bypass this pin to GND with a 10-nF capacitor for optimal noise performancer. BIAS23 31 BYP If not using the multiplier, this pin may be left open. If using the multiplier, bypass this pin to GND with a 10-µF and 0.1-µF capacitor for optimal noise performance. CLKIN_N 7 I Differential reference input clock. Internal 50-Ω termination. AC-couple with a capacitor appropriate to the input frequency (typically 0.1 µF or smaller). If using single-ended, terminate unused side with external 50-Ω.CLKIN_P 6 CLKOUT0_N 15 O Differential clock output pairs. Each pin is an open-collector output with internally integrated 50-Ω resistor. AC coupling required. CLKOUT0_P 14 CLKOUT1_N 19 CLKOUT1_P 18 CLKOUT2_N 32 CLKOUT2_P 33 CLKOUT3_N 36 CLKOUT3_P 37 CS# 10 I SPI chip select. High impedance CMOS input. Accepts up to 3.3 V. DAP DAP GND Ground these pins. GND 5,13,17,26,34,38 LOGILKOUT_N 27 O Differential clock output pair. Selectable CML, LVDS, or LVPECL format. Programmable common-mode voltage.LOGILKOUT_P 28 LOGISYSREFOUT_N 23 O Differential clock output pair. Selectable CML, LVDS, or LVPECL format. External pullup required. Programmable common-mode voltage.LOGISYSREFOUT_P 24 MUXOUT 1 O Multiplexed pin serial data readback and lock status of the multiplier. SCK 8 I SPI clock. High impedance CMOS input. Accepts up to 3.3 V. SDI 9 I SPI data input. High impedance CMOS input. Accepts up to 3.3 V. SYSREFREQ_N 3 I Differential SYSREF request input for JESD204B support. Internal 50-Ω AC coupled to ground. Supports AC and DC coupling with programmable DC common-mode voltage from 1 V to 2 V.SYSREFREQ_P 2 SYSREFOUT0_N 12 O Differential SYSREF output pairs. Each pin is an open-collector output with internally integrated 50-Ω resistor and programmable bias level. SYSREFOUT0_P 11 SYSREFOUT1_N 22 SYSREFOUT1_P 21 SYSREFOUT2_N 29 SYSREFOUT2_P 30 SYSREFOUT3_N 39 SYSREFOUT3_P 40 VCC_CLKIN 4 PWR Connect to a 2.5-V supply. Recommend a shunt high frequency capacitor (typically 0.1 µF or smaller) close to the pin in parallel with larger capacitors (typically 1 µF and 10 µF) farther away. VCC_LOGICLK 25 VCC01 16 VCC23 35 LMX1204 SNAS800 – JULY 2021 www.ti.com ADVANCE INFORMATION

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDD Power supply voltage –0.3 2.75 V VIN DC Input Voltage (SCK, SDI, CSB) GND 3.6 V VIN DC Input Voltage (SYSREFREQ) GND VDD + 0.3 V VIN AC Input Voltage (CLKIN) VDD Vpp TJ Junction temperature 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2500 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply voltage 2.4 2.5 2.6 V TA Ambient temperature –40 85 °C TJ Junction temperature 125 °C

6.4 Thermal Information

THERMAL METRIC(1) LMX1204 UNITQFN

40 Pins

RθJA Junction-to-ambient thermal resistance 24.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 13.0 °C/W RθJB Junction-to-board thermal resistance 6.9 °C/W ΨJT Junction-to-top characterization parameter 0.1 °C/W ΨJB Junction-to-board characterization parameter 6.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com LMX1204 SNAS800 – JULY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LMX1204

6.5 Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Current Consumption ICC Supply Current (1) Powered up, all outputs and SYSREF on 1260 mA Powered up, all outputs on, all SYSREF off 625 Powered up, all outputs and SYSREF off 265 Powered down 10 SYSREF fSYSREF SYSREF output frequency Generator mode 400 MHz Repeater mode 100 MHz Δt SYSREF delay step size fCLKIN = 12.8 GHz 3 ps tRISE Rise time SYSOUT 45 ps LOGISYSOUT CML 120 ps LVDS 120 ps LVPECL 170 ps tFALL Fall time SYSOUT 45 ps LOGISYSOUT CML 120 ps LVDS 120 ps LVPECL 170 ps VOD Differential output voltage SYSOUT 0.85 V LOGISYSOUT CML 0.4 V LVDS 0.4 V LVPECL 0.8 V VSYSREFCM Common-mode voltage For min, SYSOUTx_PWR=5. For max SYSOUTx_PWR=2. 0.8 V SYSREFREQ Pin VSYSREFIN Voltage input range Differential, DC-coupled Set externally 0.8 2 Vpp VCM Input common mode Differential, AC-coupled Set Internally 1.2 1.3 2 V Clock Input fIN Input frequency 0.3 12.8 GHz PIN Input power Single-ended power between CLKIN_P or CLKIN_N 0 10 dBm Clock Outputs fOUT Output frequency Divide-by-2 0.15 6.4 GHzfOUT Output frequency Bypass 0.3 12.8 fOUT Output frequency x2, x3, x4 3.2 6.4 fOUT Output frequency LOGICLK output 1 800 MHz tCAL Calibration-time Multiplier calibration time fIN = 3.2 GHz; x2 700 μs pOUT Output power OUTx_PWR = 7 fCLKLOUT=12.8 GHz 4 dBm tRISE Rise time fCLKOUT = 300 MHz 45 ps tFALL Fall time fCLKOUT = 300 MHz 45 ps Propagation Delay and Skew tSKEW Skew between outputs CLKOUTx to CLKOUTy, not LOGICLK 5 ps LMX1204 SNAS800 – JULY 2021 www.ti.com ADVANCE INFORMATION

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PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Noise, Jitter, and Spurs JCKx Additive jitter Additive Jitter. 12k to

100 MHz integration

bandwidth. Bypass Mode 10 fs, rms x2 16 x3 26 x4 32 Flicker 1/f flicker noise Slew Rate > 8 V/ns, fCLK=1 GHz Bypass -161 dBc/Hz NF Noise Floor fOUT = 6 GHz; fOffset ≥

100 MHz

Bypass –157.5 dBc/HzNF Divide-by-2 –157.5 NF Multiplier (x2,x3,x4) –159.5 H2 Second harmonic fOUT = 6 GHz (differential), Bypass -30 dBcfOUT = 6 GHz (single-ended), Bypass -15 fOUT = 6 GHz, single-ended, Divide by 2 -17 H1/2 Input clock leakage spur fOUT = 6 GHz (single- ended) x2 (fSPUR = 3 GHz) -45 dBc H1/3 x3 (fSPUR = 2 GHz) –50 H1/4 x4 (fSPUR = 1.5 GHz) -54 dBc ISPUR LOGICLK to CLKOUT fSPUR = 300 MHz (single-ended) –60 dBc Digital Interface (SCK, SDI, CS#, MUXOUT, SYSREFREQ) VIH High-level input voltage SCK, SDI, CS# 1.4 3.3 V VIL Low-level input voltage 0 0.4 VOH Low-level output voltage IOH = 5 mA 1.4 Vcc VOL Low-level output voltage IOL = 5 mA 0.4 IIH High-level input current -40 40 uA IIL Low-level input current –25 25 (1) Unless Otherwise Stated, fCLKIN=6 GHz, CLK_MUX=Bypass, All clocks on with OUTx_PWR=7, LOGICLK_DIV_PRE=1, LOGICLK_DIV=2,SRREQ_MODE=1 www.ti.com LMX1204 SNAS800 – JULY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LMX1204

6.6 Timing Requirements

Back SPI readback speed 1/(tCWL + tCWH) 2 MHz tCE Clock to enable low time 20 ns tCS Clock to data wait time 20 ns tCH Clock to data hold time 20 ns tCWH Clock pulse width high 100 ns tCWL Clock pulse width low 100 ns tCES Enable to clock setup time 20 ns tEWH Enable pulse width high 50 ns tCD Falling clock edge to data wait time 100 ns

6.7 Typical Characteristics

Typical Performance plots are taken at 2.5 V and 25 C unless otherwise specified. Output Frequency (MHz) Phase Noise (dBc/Hz) 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 -166 -164 -162 -160 -158 -156 -154 Bypass Divide by 2 Figure 6-1. Bypass Noise Floor vs. Frequency Offset (Hz) Phase Noise (dBc/Hz) 1x103 1x104 1x105 1x106 1x107 1x108 -160 -155 -150 -145 -140 -135 -130 -125 -120 -115 -110 MULT=x2 MULT=x3 MULT=x4 Figure 6-2. Multiplier Phase Noise at 6 GHz Output Frequency (MHz) Input Leakage (dBc) 3200 3600 4000 4400 4800 5200 5600 6000 6400 -75 -70 -65 -60 -55 -50 -45 -40 MULT=x2 MULT=x3 MULT=x4 Figure 6-3. Multiplier Input Leakage vs. Frequency Output Frequency (MHz) Noise Floor at 95 MHz (dBc/Hz) 3000 3500 4000 4500 5000 5500 6000 6500 -163 -162.5 -162 -161.5 -161 -160.5 -160 -159.5 -159 -158.5 -158 x4 Figure 6-4. Multiplier Noise Floor vs. Frequency LMX1204 SNAS800 – JULY 2021 www.ti.com ADVANCE INFORMATION

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6.7 Typical Characteristics (continued)

Typical Performance plots are taken at 2.5 V and 25 C unless otherwise specified. Input Power (dBm) Phae Noise (dBc/Hz) -5 0 5 10 -160.5 -160 -159.5 -159 -158.5 -158 Figure 6-5. 6 GHz Multiplier Noise Floor vs. Input Power Output Frequency (MHz) Power (dBm) 1000 3000 5000 7000 9000 11000 13000 -10 OUTx_PWR=1 OUTx_PWR=2 OUTx_PWR=3 OUTx_PWR=4 OUTx_PWR=5 OUTx_PWR=6 OUTx_PWR=7 Figure 6-6. Output Power vs. Frequency and OUTx_PWR Output Frequency (MHz) 2nd Harmonic (dBc) 1000 3000 5000 7000 9000 11000 13000 -55 -52.5 -50 -47.5 -45 -42.5 -40 -37.5 -35 -32.5 -30 -27.5 -25 -22.5 -20 -17.5 -15 -12.5 -10 Bypass (Single-Ended) Bypass (Balun) Figure 6-7. Second Harmonic in Bypass Mode Input Frequency (MHz) Single-Ended 2nd Harmonic (dBc) 0 1000 2000 3000 4000 5000 6000 7000 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 Divide=2 Divide=3 Divide=4 Divide=5 Divide=6 Divide=7 Divide=8 Figure 6-8. Second Harmonic Divide Mode (Single-Ended) SYSREF Phase Shift Code Total SYSREF Delay (ps) 0 50 100 150 200 250 300 350 400 450 500 550 -1600 -1400 -1200 -1000 -800 -600 -400 -200 200 Temperature=-45 Temperature=25C Temperature = 105C Figure 6-9. SYSREF Delay vs. Temperature and Code (Fout = 10 GHz) SYSREF Phase Shift Code Change in Delay (ps) 0 50 100 150 200 250 300 350 400 450 500 550 0.5 1.5 2.5 3.5 4.5 Temperature=-45 C Temperature=25C Temperature = 105C Figure 6-10. SYSREF Delta Delay vs. Temperature and Code (Fout=10 GHz) www.ti.com LMX1204 SNAS800 – JULY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LMX1204

7 Detailed Description

7.1 Overview

The LMX1204 has four main clock outputs and another LOGICLK output. The main clock outputs are all the same frequency. This frequency can be the same, divided, or multiplied relative to the input clock. Each of these clock outputs has programmable power level. The LOGICLK output frequency is independent and typically lower frequency than the other four main clocks and has programmable output format (CML, LVDS, LVPECL) and power level. The SYSREF can be generated by either repeating the input from the SYSREFREQ pins, or internally generated. There is an internal SYSREF windowing feature that allows the internal timing of the device to be adjusted to optimize setup/hold times. This feature assumes that the delay between the SYSREF edge and the next rising clock edge is consistent. Each of the five outputs has a corresponding SYSREF output that has individual delays and programmable common mode. For the LOGISYS output, the output format is programmable as well.

7.1.1 Range of Dividers and Multiplier

There are dividers that allow the main and LOGICLK outputs to be a divided value of the input clock. The main clock outputs also have a multiplier. In addition to this, dividers are used for SYSREF generation in generator mode as well as generation of the delay block. Table 7-1. Range of Dividers and Multiplier CATEGORY RANGE COMMENTS Main Clocks Divide 1, 2, 3, 4, … 8 Odd divides (except 1) do not have 50% duty cycle Multiply 2, 3, 4 LOGICLK Divide PreDivide 1, 2, 4 TotalDivide = PreDivide × Divide Odd divides (except 1) do not have 50% duty cycleDivide 1, 2, 3, … 1023 SYSREF Divide for frequency generation PreDivide 1,2, 4 Pre-divides clock for phase interpolator. TotalDivide = PreDivide×Divide Odd divides do not have 50% duty cycleDivide 2, 3, 4,… 4095 Divide for delay generation Divide 2, 4, 8, 16 This divide is set according to the input frequency. LMX1204 SNAS800 – JULY 2021 www.ti.com ADVANCE INFORMATION

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7.2 Functional Block Diagram

÷1,2,4 SYSREF Windowing and Capture rb_SYSWND SYSWND_OFFSET SYSREF_MODE SYSREF_PULSE_COUNT xM CLK_MUX ÷2,3,..,8 ÷1,2,3,...1023 Digital Control SDI CS# MUXOUT VCC_CLKIN GND (x6) VBIAS01 CLK_MULT_CAL SCK VCC01 VCC23 VBIAS23 LOGICLK_DIV_PRE LOGICLK_DIV CLK_DIV CLK_MULT ÷1,2,4 LOGICLK_DIV_BYP SYSREF_DIV_PRE ÷2,3,..4095 SYSREF_DIV Pulser W SYSOUT0_DLY_QUAD SYSOUT0_DLY_I/Q SYSOUT0_DLY_ADJ W W W W ÷2,4,8,16 SYSREF_DLY_DIV SYSOUT1_DLY_QUAD SYSOUT1_DLY_I/Q SYSOUT1_DLY_ADJ SYSOUT2_DLY_QUAD SYSOUT2_DLY_I/Q SYSOUT2_DLY_ADJ SYSOUT3_DLY_QUAD SYSOUT3_DLY_I/Q SYSOUT3_DLY_ADJ LOGISYS_DLY_QUAD LOGISYS_DLY_I/Q LOGISYS_DLY_ADJ Figure 7-1. Functional Block Diagram www.ti.com LMX1204 SNAS800 – JULY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LMX1204

7.3 Feature Description

7.3.1 Power On Reset

When the device is powered up, the power on reset circuitry resets all registers to a default state as well as resets all state machines and dividers. It is also possible to do a software power on reset by writing RESET=1 in the SPI bus and then setting RESET=0. For the power on reset state, SYSREF is disabled and all the dividers are bypassed; the device performs as a 5-output buffer. The SPI bus can be used to override these states to the desired settings.

7.3.2 Clock Outputs

This device has four main output clocks which share a common frequency. This does not include the additional lower frequency LOGICLK output.

7.3.2.1 Clock Output Buffers

The output buffers have a format that is open collector with an integrated pull-up resistor, similar to CML. VCC CLKOUTx 50 : CLKOUTx_PWR Figure 7-2. CLKOUT Output Buffer The output buffers can be enabled with CLKOUTx_EN bits. In addition to this, their output power can be individually set with the CLKOUTx_PWR field. However, these fields only control the output buffer, not the internal channel path that drives this buffer, the SYSREF generator, or the SYSREF output. To power down the entire path, disable the CHx_EN bit. Table 7-2. Clock Output Power CHx_EN INTERNAL CHANNEL PATH CLKOUTx_EN CLKOUTx_PWR OUTPUT BUFFER

0 Powered Down Don't Care Don't Care Powered Down

1 Powered Up

0 Don't Care Powered Down

0 Minimum

...

7 Maximum

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7.3.2.2 Clock MUX

The four main clocks must be the same frequency, but this frequency can be bypassed, multiplied, or divided. This is determined by the CLK_MUX word. Table 7-3. Clock MUX CLK_MUX OPTION VALUES SUPPORTED

0 Bypass Bypass

1 Divided 2, 3, 4, 5, 6, 7, and 8

2 Multiplier x2, x3, x4

7.3.2.3 Clock Divider

Setting the CLK_MUX to Divided allows a divide value of 2, 3, 4, 5, 6, 7, and 8. This is set by the CLK_DIV word. When using the clock divider, any change to the input frequency requires the CLK_DIV_RST bit to be toggled from 1 to 0. Table 7-4. Clock Divider CLK_DIV DIVIDE DUTY CYCLE

0 Reserved n/a

1 2 50% 2 3 33% 3 4 50% 4 5 40% 5 6 50% 6 7 43% 7 8 50%

7.3.2.4 Clock Multiplier

The clock multiplier is PLL based and supports multiply values of x2, x3, and x4. Much of its functionality is automatic and does not need to be set by the user, but there are a few considerations.

The CLK_MULT field sets the multiplier value of x2, x3, or x4
Values other than 2,3, and 4 set the device in buffer mode
CLK_MULT and CLK_DIV are the same field
Calibration is required and performed by programming the R0 register with a valid input signal

7.3.3 SYSREF

SYSREF allows a low frequency JESD204B/C compliant signal to be produced that is reclocked to a main or LOGICLK output. The delay between the CLKOUT and SYSREF outputs are adjustable in the software. The SYSREF output can be configured as a generator using the internal SYSREF divider, or as a repeater duplicating the signal on the SYSREFREQ pins. The signal can be generated either from inputs from the SYSREFREQ pins or from an internal SYSREF generator. The SYSREF generator for both the main clocks and the LOGICLK output are the same. The output buffers for the LOGICLK and LOGISYS outputs also offer LVDS and LVPECL format and are designed for lower frequency.

7.3.3.1 SYSREF Output Buffers

7.3.3.1.1 SYSREF Output Buffer for Main Clocks

The SYSREF outputs within the clock output channels have the same output buffer structure as the clock output buffer, with the inclusion of the common mode adjust field. For the case of the main clocks, the only choice is CML outputs. For the CML outputs, the common mode can be adjusted with the SYSOUTx_VCM field, and the output level is programmable with the SYSOUTx_PWR field. This is to allow DC coupling. This bias adjust is only available on the SYSREF outputs and not the clocks. This is for noise performance reasons. www.ti.com LMX1204 SNAS800 – JULY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LMX1204

SYSOUTx_PWR SYSOUTx_VCM Figure 7-3. SYSOUT Output Buffer

7.3.3.1.2 SYSREF Output Buffer for LOGICLK

The LOGISYS output operates in a somewhat similar way to the SYSOUT outputs with the exception that the LOGISYS is lower frequency and supports the three formats of LVDS, LVPECL, and CML. The LOGISYSOUT_EN enables the output buffer and LOGISYS_FMT sets the format. LVDS mode allows programmable common mode, LVPECL and CML require external components, and CML allows programmable output power (see Table 7-5). Table 7-5. LOGISYSOUT Output Buffer Configuration LOGISYSOUT_EN LOGISYS_FMT LOGISYS FORMAT EXTERNAL TERMINIATION REQUIRED OUTPUT POWER OUTPUT COMMON MODE

0 Powered Down

0 LVDS None Fixed

LOGISYS_VCM

1 LVPECL Emitter Resistors Fixed Fixed

2 CML Pull-Up resistors Controlled by

LOGISYS_PWR Fixed

3 LVDS None Fixed

compensated, but controlled by LOGISYS_VCM

7.3.3.2 SYSREF Frequency and Delay Generation

The SYSREF circuitry can produce an output signal that is synchronized to f CLKIN. This output can be a single pulse, series of pulses, or a continuous stream of pulses. In generator mode, the SYSREF_DIV_PRE and SYSREF_DIV values are used to divide the CLKIN frequency to a lower frequency that is reclocked to the output. In repeater mode, this signal is instead input at the SYSREFREQ pins. For each of the outputs, there is an independent delay control. LMX1204 SNAS800 – JULY 2021 www.ti.com ADVANCE INFORMATION

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Table 7-6. SYSREF Modes SYSREF_MODE Description Generator Mode (Continuous) Internal generator creates a continuous stream of SYSREF pulses. The SYSREFREQ pins can be used to turn portions of the SYSREF circuitry without disrupting the synchronization of the SYSREF dividers. These pins need to be logic high for a SYSREF output to come out. Generator Mode (Pulser) Internal generator generates a burst of 1 - 16 pulses that is set by SYSREF_PULSE_COUNT that occurs after a rising edge on the SYSREFREQ pins

2 Repeater Mode

SYSREFREQ pins are reclocked at the clock outputs. ÷1, 2, 4 SYSRE F_DIV_PRE ÷2, Yðìõñ SYSRE F_DIV Re-clocking Circuit SYSRE FOUTx_P SYSRE FOUTx_N SYSRE FRE Q_N SYSRE FRE Q_P SYSRE Fx_DLY_I/Q SYSRE Fx_DLY_QUAD SYSRE Fx_DLY_ADJ SYSRE F_PULSE_COUNT CLKIN fIN TERP O LATO R SysRef Pulse Generator SYSRE F_MODE ÷2,4,8,16 SYSRE F_DLY_DIV Output Clock Programmable Delay Figure 7-4. SYSREF Generator Diagram For the frequency of the SYSREF output for continuous SYSREF output in generator mode, the SYSREF_DIV_PRE divider is necessary to ensure that the input of the SYSREF_DIV divider is not more than 3.2 GHz. Table 7-7. SYSREF_DIV_PRE Setup fCLKIN SYSREF_DIV_PRE TOTAL SYSREF DIVIDE RANGE 3.2 GHz or Less 1, 2, or 4 2,3,4,...16380 3.2 GHz < fCLKIN <= 6.4 GHz 2 or 4 4,6,8, … 16380 fCLKIN > 6.4 GHz 4 8,12,16, … 16380 For the delay, the input clock frequency is divided by SYSREF_DLY_DIV to generate f INTERPOLATOR, which has a restricted range as shown in Table 7-8. Note also that when SYSREF_MODE is set to continuous or pulser mode, the SYSREF output frequency must be a multiple of the phase interpolator frequency. fINTERPOLATOR % fSYSREF = 0. Table 7-8. SYSREF Delay Setup fCLKIN SYSREF_DLY_DIV SYSREFx_DLY_ADJ fINTERPOLATOR 6.4 to 12.8 GHz 16 0 0.4 to 0.8 GHz 3.2 to 6.4 GHz 8 0 0.4 to 0.8 GHz 1.6 to 3.2 GHz 4 0 0.4 to 0.8 GHz 0.8 to 1.6 GHz 2 0 0.4 to 0.8 GHz 0.4 to 0.8 GHz 2 1 0.2 to 0.4 GHz 0.3 to 0.4 GHz 2 2 0.15 to 0.2 GHz The maximum delay is equal to the phase interpolator period and there are 4x127 = 508 different delay steps. Use Equation 1 to calculate the size of each step. DelayStepSize = 1/( fINTERPOLATOR × 508) = SYSREF_DLY_DIV/( fCLKIN × 508) (1) www.ti.com LMX1204 SNAS800 – JULY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LMX1204

The total delay is calculated as with Equation 2. TotalDelay=DelayStepSize × StepNumber (2) The number of steps can be calculated as shown in Table 7-9. Table 7-9. Calculation of StepNumber SYSREFx_DLY_QUAD StepNumber 3 127 - SYSREFx_DLY_I 2 254 - SYSREFx_DLY_Q 0 381 - SYSREFx_DLY_I 1 508 - SYSREFx_DLY_Q The SYSREF_DLY_BYP field selects between the delay generator output and the repeater mode bypass signal. When using SYSREF_MODE set to continuous or pulser, it is recommended to set this to generator mode and when SYSREF_MODE is set to repeater mode, it is recommended to set this to bypass mode.

7.3.3.3 SYSREFREQ pins

The SYSREFREQ pins allow the user to send a SYSREFREQ signal to the device. This signal can be a constant high, a single pulse, or a series of pulses. This input can be used to synchronize the dividers or create a SYSREF output.

7.3.3.3.1 SYSREFREQ Pins Common Mode Voltage

The SYSREFREQ_P and SYSREFREQ_N pins can be driven either AC or DC coupled. When driven AC coupled, the common mode can be adjusted with the SRREQ_VCM bit. Table 7-10. SYSREFREQ Pin Common Mode Voltage SRREQ_VCM COMMON-MODE VOLTAGE 0 1.3 V AC-coupled 1 1.1 V AC-coupled 2 1.5 V AC-coupled

3 No Bias (DC Coupled)

7.3.3.3.2 SYSREFREQ Pin Windowing Feature

The SYSREF windowing can be used to internally calibrate the timing between the SYSREFREQ and CLKIN pins in order to optimize setup and hold timing and trim out the device's internal delay mismatch on the SYSREFREQ and CLKIN paths. This feature requires that the timing from the SYSREFREQ rising edge to the CLKIN rising edge is consistent. The timing from the SYSREFREQ rising edge to the CLKIN rising edges can be tracked with the rb_SYSWND field, which is the concatenation of the rb_SYSWND_L and rb_SYSWND_R fields. Once the timing to the rising edge of the CLKIN pin is found, then the SYSREFREQ rising edge can be internally delayed with the SYSWND_OFFSET field. LMX1204 SNAS800 – JULY 2021 www.ti.com ADVANCE INFORMATION

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trb_SYSWND[31:0] Adjusted SYSREFREQ tSYSWND_OFFSET 1000000000000 110000000000000000 1 Figure 7-5. SYSREFREQ Internal Timing Adjustment General Procedure

While programming the windowing feature for the first time, SYSREFREQ needs to be low.
Set SYSREF_MODE=2
Set SYSWND_DLY according to Table 7-11.
Program SYNC_SYSWND_CLR=1 and then SYNC_SYSWND_CLR=0
Send a rising edge to the SYSREFREQ pin(s)
Read back position with rb_SYSWND_L/R fields to determine timing from the SYSREQREQ rising edge to the next CLKIN rising edge. The number of 0's between the LSB '1' bit and the first series of '11' can be multiplied by the delay determined by SYSWND_DLY to determine the approximate timing to the first rising clock edge.
Program SYSWND_OFFSET field in delay steps to maximize margin between left and right rising edges of CLKIN Table 7-11. SYSWND_DLY INPUT FREQUENCY RECOMMENDED SYSWND_DLY<1:0> DELAY (ps) 1.4 - 2.7GHz 0 28 2.4 - 4.7 GHz 1 15 3.1 - 5.7 GHz 2 11 4.5 - 12.8 GHz 3 8 For glitch-free output
When switching from request mode to windowing mode and back to request mode, keep the SYSREFREQ pin state stays the same. For example, if the SYSREFREQ pin is high (or low) when windowing mode starts, make sure the pin state is high (or low) again after windowing mode ends before programing SRREQ_MODE.
The SYSREFREQ pin must be set low when switching from or to SYNC mode.
SYSREFREQ → SYSWND → SYNC, mode switching should be performed with SYSREFREQ pin set to low. If the device goes from SYSREF_MODE=1 to 2 with the SYSREFREQ pin high, then the user must come back to SYSREF_MODE=1 and set SYSREFREQ pin low and then switch to SYNC mode. Direct transition with the SYSREFREQ pins high may lead to a glitch at the output. www.ti.com LMX1204 SNAS800 – JULY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LMX1204

Other pointers with SYSREF windowing

The SYSREFREQ pins need to be held for a minimum of T1 > 3/fCLKIN + 1.6 ns and only after this time rb_SYSWND_L/R fields are valid.
If the user infers multiple valid SYSWND_OFFSET values from rb_SYSWND registers to avoid setup- hold violations, choosing the lowest valid SYSWND_OFFSET is recommended to minimize variation over temperature. If using SYNC feature
Only one SYSREFREQ pin rising edge is permitted per 75 input clock cycles
SYSREFREQ has to stay high for >6 clock cycles

7.3.3.4 SYNC Feature

The SYNC feature allows the user to synchronize the CLK_DIV, LOGICLK_DIV, LOGICLK_DIV_PRE, SYSREF_DIV, SYSREF_DIV_PRE, and SYSREF_DLY_DIV dividers so that the phase offset can be made consistent when multiple devices are used. The synchronization of the dividers can only be done through the SYSREFREQ pin, not the software. In addition to synchronizing the dividers within one device, the SYSREFREQ pins can be used to synchronize multiple devices that are using dividers as well.

7.3.4 LOGICLK Output

The LOGICLK output can be used to drive devices using lower frequency clocks, such as FPGAs. It has programmable output format and a corresponding SYSREF output.

7.3.4.1 LOGICLK Output Format

The LOGICLK output format can be programmed to LVDS, LVPECL, and CML modes. Depending on the format, the common mode may be programmable or external components may be required (see Table 7-12). Table 7-12. LOGICLK Formats and Properties LOGICLK_FMT FORMAT EXTERNAL COMPONENTS REQUIRED COMMON MODE

0 LVDS None

LOGICLK_VCM and compensated with temperature

1 LVPECL Emitter Resistors Not programmable

2 CML Pull-Up Resistors Not programmable

3 LVDS None

LOGICLK_VCM and NOT compensated with temperature

7.3.4.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers

The LOGICLK_DIV_PRE divider and LOGICLK_DIV dividers are used for the LOGICLK output. The LOGICLK_DIV_PRE divider is necessary to divide the frequency down to ensure that the input to the LOGICLK_DIV divider is 3.2 GHz or less. When LOGICLK_DIV is not even and not bypassed, the duty cycle will not be 50%. Both the LOGICLK dividers are synchronized by the SYNC feature, which allows synchronization across multiple devices. Table 7-13. Minimum N-Divider Restrictions fCLKIN (MHz) LOGICLK_DIV_PRE LOGICLK_DIV TOTAL DIVIDE RANGE Up to 3.2 GHz 1,2,4 1,2 ,3 ,…1023 [1, 2, ...1023 [2, 4, ... 2046] [4, 8, 4092] [4, 8, 4092] Above 6.4 GHz 4 1, 2, 3 ,…1023 [4, 8, 4092] LMX1204 SNAS800 – JULY 2021 www.ti.com ADVANCE INFORMATION

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7.4 Device Functional Modes

Table 7-14 shows the different modes for the LMX1204. The CLK_MUX field allows the user to configure the device as a buffer, divider, or multiplier. The SYSREF can also be enabled as well for applications that need this feature. Table 7-14. Device Configurations SYSREF_EN CLK_MUX MODE 1 Buffer Mode. 2 Divider Mode.

3 Multiplier Mode

1 SYSREF Buffer Mode

2 SYSREF Divider Mode

3 SYSREF Multiplier Mode

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Applications Information

The way that the device is set up is important to the performance. Knowing the current consumption and what to do with unused pins is very useful for optimization of layout.

8.1.1 Current Consumption

The current consumption varies as a function of the setup condition. By adding up all the block currents shown in Table 8-1, a reasonable estimate of the current for any setup condition can be obtained. Table 8-1. Current Consumption per Block BLOCK CONDITION CURRENT (mA) Input Path CLK_MUX = Bypass 257 CLK_MUX = Divide 295 CLK_MUX = Multiply 539 Channel Path SYSREF_EN = 0 28 SYSREF_EN = 1 42 CLKOUT Buffer CLKOUTx_EN = CHx_EN = 1 5.8 × (OUTx_PWR + 1) SYSOUT Buffer SYSOUT_EN = CHx_EN = 1 74 + SYSOUTx_PWR*5 SYSREF Generator SYSREF_EN = 1 200 SYSREF_EN = 0, SYNC_EN = 1 60 LOGICLK Path SYSREF_EN = 0 55 SYSREF_EN = 1 73 LOGICLK Buffer LOGICLK_FMT = LVDS 12 LOGICLK_FMT = LVPECL 40 LOGICLK_FMT = CML 12 LOGICLK Buffer LOGICLK_FMT = LVPECL 40 LOGICLK_FMT = CML 12 LOGICLK_FMT = LVDS 12 If all the output clocks, LOGICLK, multiplier, and multiplier are all enabled, it is possible for this device to consume a significant amount of current. In order to mitigate this, It is recommended to turn off the SYSREF output buffers when not using the SYSREF feature to conserve current.

8.1.2 Treatment of Unused Pins

In many cases, not all pins will be needed. Table 8-2 gives recommendation on handling of these unused pins. Table 8-2. Treatment of Unused or Partially Used Pins PIN(S) TREATMENT All Vcc Pins These pins must always be connected to the supply. If the block that this powers is not used, then the bypassing can be minimized or eliminated. SYSREFREQ If driving single-ended, the complimentary input should have a AC-coupling capacitor and 50 Ω to ground. If using continuous SYSREF Generator mode, these pins can be either used to turn the output buffers on and off or they can be pulled high. To pull high, set SYSREFREQP to 1.5 V and SYSREFREQN to 0.5 V. If not using SYSREF at all, pins can be left open. LMX1204 SNAS800 – JULY 2021 www.ti.com ADVANCE INFORMATION

Product Folder Links: LMX1204

Table 8-2. Treatment of Unused or Partially Used Pins (continued) PIN(S) TREATMENT CLKIN Complimentary Input If driving single-ended, the complimentary input should have a AC-coupling capacitor and 50 Ω to ground. BIAS01 and BIAS23 These pins can be left open if multiplier is not used. CLKOUT SYSOUT LOGICLKOUT LOGISYSOUT These pins can be left open if not used.

8.2 Typical Application

For this application, the additive noise impact of using the LMX1204 as a x2 multiplier is exported when added to the LMX2820 3-GHz output clock. LMX2820 OSCIN OSCIN# CPOUT RFOUTAP RFOUTAN VTUNE LMX1204 CLKIN_P CLKIN_N CLKOUT0_N CLKOUT0_P To Phase Noise Analyzer Wenzel Oscillator 2.2 nF2.2 nF 68 nF68 nF 470 pF470 pF +10 dBm Limiter 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.01 F 0.01 F

3 GHz 6 GHz

Bandwidth = 439 kHz 0.01 F 0.01 F Figure 8-1. Typical Application Schematic

8.2.1 Design Requirements

Table 8-3 shows the design parameters for this example. If not all the outputs or SYSREF are used, TI recommends to compress the layout to minimize trace lengths, especially that of the input trace. For the multiplier, however, there is a specific range where the multiplier works, so make sure to satisfy those requirements. Table 8-3. Design Parameters PARAMETER VALUE LMX2820 Input Frequency 100 MHz LMX2820 Output Frequency 3 GHz LMX1204 Input Clock Frequency 3 GHz LMX1204 Output Clock Frequency 6 GHz Multiplier Value x3 www.ti.com LMX1204 SNAS800 – JULY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LMX1204

8.2.2 Detailed Design Procedure

In this example, a 3-GHz input clock is being multiplied up to a 6-GHz input clock. The external components do not change that much based on internal configuration. The TICS Pro software is very useful in calculating the necessary register values and configuring the device. Figure 8-2. LMX1204 TICS Pro Setup LMX1204 SNAS800 – JULY 2021 www.ti.com ADVANCE INFORMATION

Product Folder Links: LMX1204

8.2.3 Application Curve

In Figure 8-3, the total plot is the sum of the noise of the LMX1204 multiplier noise and the LMX2820 3-GHz output (scaled to 6 GHz by adding 6 dB). Note that the LMX1204 does increase the phase noise in the 1-MHz to 20-MHz range, but beyond 20 MHz, the input multiplier actually filters the output noise floor. Offset (Hz) Phase Noise (dBc/Hz) 1x102 1x103 1x104 1x105 1x106 1x107 1x108 -160 -140 -120 -100 -80 LMX2820 Noise Scaled to 6 GHz LMX1204 Multiplier Noise LMX2820 + LMX1204 Figure 8-3. Multiplier Output Frequency

9 Power Supply Recommendations

This devices uses a 2.5-V supply for the whole device. This device does not have internal LDOs, so it is important that this device is connected to a low noise supply that does not have excessive spurious noise. A direct connection to a switching power supply will likely result in unwanted spurs at the output. Bypassing can be done individually at all the power pins, and TI recommends to have a capacitor suitable for higher frequency on the top layer so higher-value capacitors more suitable for lower frequencies can be farther away. The supply pins for the clocks and the LOGICLK should be isolated with a small resistor or ferrite bead if both are being used simultaneously. See the Pin Configuration and Functions section for additional recommendations for each pin. www.ti.com LMX1204 SNAS800 – JULY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LMX1204

10 Layout

10.1 Layout Guidelines

If using an output single-ended, terminate the complementary side in a similar way to the side that is used.
GND pins may be routed on the package back to the DAP.
The output clocks contain an internal pullup resistor, so extra pullup resistors are not needed.
Minimize the length of the CLKIN trace for optimal phase noise. Poor matching will impact noise floor.
Ensure the DAP on device is well-grounded with many vias, preferably copper filled.
Use a low loss dielectric material, such as Rogers 4350B, for optimal output power.

10.2 Layout Example

Figure 10-1. LMX1204 EVM Top Layer LMX1204 SNAS800 – JULY 2021 www.ti.com ADVANCE INFORMATION

Product Folder Links: LMX1204

11 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

11.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com LMX1204 SNAS800 – JULY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: LMX1204

www.ti.com PACKAGE OUTLINE C 40X 0.3 0.2 4.7 0.1 40X 0.5 0.3

1 MAX

(0.2) TYP 0.05 0.0036X 0.5 4.5 2X 4.5 A 6.1 5.9 B 6.1 5.9 0.3 0.2 0.5 0.3 VQFN - 1 mm max heightRHA0040C PLASTIC QUAD FLATPACK - NO LEAD 4219053/A 09/2016 PIN 1 INDEX AREA 0.08 C SEATING PLANE 10 21 11 20 40 31 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 EXPOSED THERMAL PAD DETAIL SEE TERMINAL SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. OPTIONAL TERMINAL SCALE 2.200 DETAIL TYPICAL LMX1204 SNAS800 – JULY 2021 www.ti.com ADVANCE INFORMATION

Product Folder Links: LMX1204

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

40X (0.25) 40X (0.6) ( 0.2) TYP VIA 36X (0.5) (5.8) (5.8) ( 4.7) (R0.05) TYP (1.5) (1.35) (0.75) TYP 4X (1.35) (0.75) TYP 4X (1.5) VQFN - 1 mm max heightRHA0040C PLASTIC QUAD FLATPACK - NO LEAD 4219053/A 09/2016 SYMM 11 20 3140 SYMM LAND PATTERN EXAMPLE SCALE:12X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METAL SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DETAILS DEFINED (PREFERRED) www.ti.com LMX1204 SNAS800 – JULY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: LMX1204

www.ti.com EXAMPLE STENCIL DESIGN 40X (0.6) 40X (0.25) 36X (0.5) (5.8) (5.8) 9X ( 1.3) (1.5) TYP (1.5) TYP (R0.05) TYP VQFN - 1 mm max heightRHA0040C PLASTIC QUAD FLATPACK - NO LEAD 4219053/A 09/2016 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP BASED ON 0.125 mm THICK STENCIL SOLDER PASTE EXAMPLE EXPOSED PAD 41: 69% PRINTED SOLDER COVERAGE BY AREA SCALE:15X SYMM 11 20 3140 LMX1204 SNAS800 – JULY 2021 www.ti.com ADVANCE INFORMATION

Product Folder Links: LMX1204

12.1 Package Option Addendum

Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball Finish MSL Peak Temp(3) Op Temp (°C) Device Marking(4) (5) (6) LMX1204RHAR ACTIVE VQFN RHA 40 Call TI RoHS & Green Call TI Call TI -40 to 85 LMX1204RHAT ACTIVE VQFN RHA 40 Call TI RoHS & Green Call TI Call TI -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. www.ti.com LMX1204 SNAS800 – JULY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: LMX1204

12.2 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant LMX1204RHAR VQFN RHA 40 2500 Call TI Call TI Call TI Call TI Call TI Call TI Call TI Call TI LMX1204RHAT VQFN RHA 40 250 Call TI Call TI Call TI Call TI Call TI Call TI Call TI Call TI LMX1204 SNAS800 – JULY 2021 www.ti.com ADVANCE INFORMATION

Product Folder Links: LMX1204

TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMX1204RHAR VQFN RHA 40 2500 Call TI Call TI Call TI LMX1204RHAT VQFN RHA 40 250 Call TI Call TI Call TI www.ti.com LMX1204 SNAS800 – JULY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: LMX1204

www.ti.com 7-Oct-2021 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PLMX1204RHAT ACTIVE VQFN RHA 40 250 TBD Call TI Call TI -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRHA 40 PLASTIC QUAD FLATPACK - NO LEAD6 x 6, 0.5 mm pitch 4225870/A

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Product Information

PLMX1204RHAT specifications and overview.

Summary

LMX1204 Low-Noise, High-Frequency JESD Buffer/Multiplier/Divider SNAS800 ??JULY 2021

Description

LMX1204 Low-Noise, High-Frequency JESD Buffer/Multiplier/Divider SNAS800 ??JULY 2021

Source title PLMX1204RHAT Datasheet(PDF) - Texas Instruments

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