PLMV321AIDBVR

LMV321A TI1 | Alldatasheet

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= 1 + V V OUT IN R R F G 1 + sR C1 1( ( ( ( 2/c112 R C1 1 f =/c45 3 dB Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. LMV321A,LMV358A,LMV324A SBOS923B – DECEMBER 2017– REVISED JUNE 2018 LMV3xxALow-VoltageRail-to-RailOutputOperationalAmplifiers

1 Features

1• Low Input Offset Voltage: ±1 mV

• Rail-to-Rail Output
• Unity-Gain Bandwidth: 1 MHz
• Low Broadband Noise: 30 nV/√Hz
• Low Input Bias Current: 10 pA
• Low Quiescent Current: 80 µA/Ch
• Unity-Gain Stable
• Internal RFI and EMI Filter
• Operational at Supply Voltages as Low as 2.5 V
• Easier to Stabilize With Higher Capacitive Load Due to Resistive Open-Loop Output Impedance
• Extended Temperature Range: –40°C to +125°C

2 Applications

• Smoke Detectors
• Motion Detectors
• Wearable Devices
• Large and Small Appliances
• EPOS
• Barcode Scanners
• Sensor Signal Conditioning
• Power Modules
• Personal Electronics
• Active Filters
• HVAC: Heating, Ventilating, and Air Conditioning
• Motor Control: AC Induction
• Low-Side Current Sensing

3 Description

The LMV3xxA family includes single - (LMV321A), dual - (LMV358A), and quad-channel (LMV324A) low- voltage (2.5 V to 5.5 V) operational amplifiers (op amps) with rail-to-rail output swing capabilities. These op amps provide a cost-effective solution for space- constrained applications such as large appliances, smoke detectors, and personal electronics where low- voltage operation and high capacitive-load drive are required. The capacitive-load drive of the LMV3xxA family is 500 pF, and the resistive open-loop output impedance makes stabilization easier with much higher capacitive loads. These op amps are designed specifically for low-voltage operation (2.5 V to 5.5 V) with performance specifications similar to the LMV3xx devices. The robust design of the LMV3xxA family simplifies circuit design. The op amps feature unity-gain stability, an integrated RFI and EMI rejection filter, and no-phase reversal in overdrive conditions. The LMV3xxA family is available in industry-standard packages such as SOIC, MSOP, SOT-23 and TSSOP packages. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LMV321A SC70 (5)(2) 1.25 mm × 2.00 mm LMV358A SOIC (8) 3.91 mm × 4.90 mm TSSOP (8)(2) 3.00 mm x 4.40 mm VSSOP (8) 3.00 mm × 3.00 mm LMV324A SOIC (14)(2) 8.65 mm × 3.91 mm TSSOP (14)(2) 4.40 mm × 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Package is for preview only. Single-Pole, Low-Pass Filter

LMV321A,LMV358A,LMV324A SBOS923B – DECEMBER 2017– REVISED JUNE 2018 www.ti.com Product Folder Links: LMV321A LMV358A LMV324A Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Table of Contents

11.3 Receiving Notification of Documentation Updates 23

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (May 2018) to Revision B Page Changes from Original (December 2017) to Revision A Page

OUT□B /c45IN□B +IN□B OUT□A /c45IN□A +IN□A V/c45 OUT +IN V/c45 /c45IN /c45IN OUT V/c45 +IN LMV321A,LMV358A,LMV324A www.ti.com SBOS923B – DECEMBER 2017– REVISED JUNE 2018 Product Folder Links: LMV321A LMV358A LMV324A Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated

5 Pin Configuration and Functions

(1) Package is preview only. 5-Pin SC70 Top View (1) Package is preview only. Pin Functions: LMV321A PIN I/O DESCRIPTION NAME DBV DCK –IN 4 3 I Inverting input +IN 3 1 I Noninverting input OUT 1 4 O Output V– 2 2 — Negative (lowest) supply or ground (for single-supply operation) V+ 5 5 — Positive (highest) supply LMV358A D, DGK, PW Packages 8-Pin SOIC, VSSOP, TSSOP(1) Top View (1) Package is preview only. Pin Functions: LMV358A PIN I/O DESCRIPTION NAME NO. –IN A 2 I Inverting input, channel A +IN A 3 I Noninverting input, channel A –IN B 6 I Inverting input, channel B +IN B 5 I Noninverting input, channel B OUT A 1 O Output, channel A OUT B 7 O Output, channel B V– 4 — Negative (lowest) supply or ground (for single-supply operation) V+ 8 — Positive (highest) supply

OUT□D /c45IN□D +IN□D V/c45 OUT□A /c45IN□A +IN□A +IN□C /c45IN□C OUT□C +IN□B /c45IN□B OUT□B A B D C LMV321A,LMV358A,LMV324A SBOS923B – DECEMBER 2017– REVISED JUNE 2018 www.ti.com Product Folder Links: LMV321A LMV358A LMV324A Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated LMV324A D, PW Packages(1) 14-Pin SOIC, TSSOP Top View (1) Packages are preview only. Pin Functions: LMV324A PIN I/O DESCRIPTION NAME NO. –IN A 2 I Inverting input, channel A +IN A 3 I Noninverting input, channel A –IN B 6 I Inverting input, channel B +IN B 5 I Noninverting input, channel B –IN C 9 I Inverting input, channel C +IN C 10 I Noninverting input, channel C –IN D 13 I Inverting input, channel D +IN D 12 I Noninverting input, channel D OUT A 1 O Output, channel A OUT B 7 O Output, channel B OUT C 8 O Output, channel C OUT D 14 O Output, channel D V– 11 — Negative (lowest) supply or ground (for single-supply operation) V+ 4 — Positive (highest) supply

LMV321A,LMV358A,LMV324A www.ti.com SBOS923B – DECEMBER 2017– REVISED JUNE 2018 Product Folder Links: LMV321A LMV358A LMV324A Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less. (3) Short-circuit to ground, one amplifier per package.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage, ([V+] – [V–]) 0 6 V Signal input pins Voltage(2) Common-mode (V–) – 0.5 (V+) + 0.5 V Differential (V+) – (V–) + 0.2 V Current(2) –10 10 mA Output short-circuit(3) Continuous mA Operating, TA –55 150 °C Operating junction temperature, TJ 150 °C Storag temperaturee, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VS Supply voltage 2.5 5.5 V TA Specified temperature –40 125 °C

LMV321A,LMV358A,LMV324A SBOS923B – DECEMBER 2017– REVISED JUNE 2018 www.ti.com Product Folder Links: LMV321A LMV358A LMV324A Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) Package is preview only.

6.4 Thermal Information: LMV321A

THERMAL METRIC (1) LMV321A UNITDBV (SOT-23)(2) DCK (SC70)(2)

5 PINS 5 PINS

RθJA Junction-to-ambient thermal resistance 232.8 239.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 153.8 148.5 °C/W RθJB Junction-to-board thermal resistance 100.9 82.3 °C/W ψJT Junction-to-top characterization parameter 77.2 54.5 °C/W ψJB Junction-to-board characterization parameter 100.4 81.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) Package is preview only.

6.5 Thermal Information: LMV358A

THERMAL METRIC(1) LMV358A UNITD (SOIC) DGK (VSSOP) PW (TSSOP)(2)

8 PINS 8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 147.4 201.2 205.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 94.3 85.7 106.7 °C/W RθJB Junction-to-board thermal resistance 89.5 122.9 133.9 °C/W ψJT Junction-to-top characterization parameter 47.3 21.2 34.4 °C/W ψJB Junction-to-board characterization parameter 89 121.4 132.6 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) Package is preview only.

6.6 Thermal Information: LMV324A

THERMAL METRIC(1) LMV324A UNITD (SOIC)(2) PW (TSSOP)(2)

14 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 102.1 148.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 56.8 68.1 °C/W RθJB Junction-to-board thermal resistance 58.5 92.7 °C/W ψJT Junction-to-top characterization parameter 20.5 16.9 °C/W ψJB Junction-to-board characterization parameter 58.1 91.8 °C/W

LMV321A,LMV358A,LMV324A www.ti.com SBOS923B – DECEMBER 2017– REVISED JUNE 2018 Product Folder Links: LMV321A LMV358A LMV324A Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated

6.7 Electrical Characteristics

For VS = (V+) – (V–) = 2.5 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25 °C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage Vs = 5 V ±1 ±4 mV Vs = 5 V, TA = –40°C to 125°C ±5 mV dVOS/dT VOS vs temperature TA = –40°C to 125°C ±1 μV/°C PSRR Power-supply rejection ratio VS = 2.5 to 5.5 V, VCM = (V–) 78 100 dB INPUT VOLTAGE RANGE VCM Common-mode voltage range No phase reversal, rail-to-rail input (V–) – 0.1 (V+) – 1 V CMRR Common-mode rejection ratio TA = –40°C to 125°C 86 dB TA = –40°C to 125°C 95 dB TA = –40°C to 125°C 63 77 dB TA = –40°C to 125°C 68 dB INPUT BIAS CURRENT IB Input bias current Vs = 5 V ±10 pA IOS Input offset current ±3 pA NOISE En Input voltage noise (peak-to-peak) ƒ = 0.1 Hz to 10 Hz, Vs = 5 V 5.1 μVPP en Input voltage noise density ƒ = 1 kHz, Vs = 5 V 33 nV/√Hz ƒ = 10 kHz, Vs = 5 V 30 nV/√Hz in Input current noise density ƒ = 1 kHz, Vs = 5 V 25 fA/√Hz INPUT CAPACITANCE CID Differential 1.5 pF CIC Common-mode 5 pF OPEN-LOOP GAIN AOL Open-loop voltage gain VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V, RL = 10 kΩ 100 115 dB FREQUENCY RESPONSE GBW Gain-bandwidth product Vs = 5 V 1 MHz φm Phase margin VS = 5.5 V, G = 1 76 degrees SR Slew rate Vs = 5 V 1.7 V/µs tS Settling time To 0.1%, VS = 5 V, 2-V Step , G = +1, CL = 100 pF 3 μs To 0.01%, VS = 5 V, 2-V Step , G = +1, CL = 100 pF 4 μs tOR Overload recovery time VS = 5 V, VIN × gain > VS 0.9 μs THD+N Total harmonic distortion + noise VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1, f = 1 kHz, 80 kHz measurement BW 0.005 % OUTPUT VO Voltage output swing from supply rails VS = 5.5 V, RL = 10 kΩ 20 50 mV VS = 5.5 V, RL = 2 kΩ 40 75 mV ISC Short-circuit current Vs = 5.5 V ±40 mA ZO Open-loop output impedance Vs = 5 V, f = 1 MHz 1200 Ω POWER SUPPLY VS Specified voltage range 2.5 (±1.25) 5.5 (±2.75) V IQ Quiescent current per amplifier IO = 0 mA, VS = 5.5 V 80 125 µA IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C 150 µA Power-on time VS = 0 V to 5 V, to 90% IQ level 50 µs

6.8 Typical Characteristics

Figure 1. IB and IOS vs Temperature Figure 2. IB and IOS vs Common-Mode Voltage Figure 3. Open-Loop Gain vs Temperature Figure 4. Open-Loop Gain and Phase vs Frequency Figure 5. Open-Loop Gain vs Output Voltage Figure 6. Closed-Loop Gain vs Frequency

Figure 31. Channel Separation

V (Ground) /c45 VBIAS2 VBIAS1 Class AB Control Circuitry VO LMV321A,LMV358A,LMV324A SBOS923B – DECEMBER 2017– REVISED JUNE 2018 www.ti.com Product Folder Links: LMV321A LMV358A LMV324A Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The LMV3xxA series is a family of low-power, rail-to-rail output op amps. These devices operate from 2.5 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications. The input common-mode voltage range includes the negative rail and allows the LMV3xxA series to be used in many single-supply applications. Rail-to-rail output swing significantly increases dynamic range, especially in low- supply applications, and makes them suitable for driving sampling analog-to-digital converters (ADCs).

7.2 Functional Block Diagram

LMV321A,LMV358A,LMV324A www.ti.com SBOS923B – DECEMBER 2017– REVISED JUNE 2018 Product Folder Links: LMV321A LMV358A LMV324A Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated

7.3 Feature Description

7.3.1 Operating Voltage

The LMV3xxA series of op amps are ensured for operation from 2.5 V to 5.5 V. In addition, many specifications apply from –40°C to +125°C. Parameters that vary significantly with operating voltages or temperature are shown in the section.

7.3.2 Input Common Mode Range

The input common-mode voltage range of the LMV3xxA family extends 100 mV beyond the negative supply rail and within 1 V below the positive rail for the full supply voltage range of 2.5 V to 5.5 V. This performance is achieved with a P-channel differential pair, as shown in the Functional Block Diagram. Additionally, a complementary N-channel differential pair has been included in parallel to eliminate issues with phase reversal that are common with previous generations of op amps. However, the N-channel pair is not optimized for operation. TI recommends limiting any voltages applied at the inputs to less than VCC– 1V to ensure that the op amp conforms to the specifications detailed in the Electrical Characteristics table.

7.3.3 Rail-to-Rail Output

Designed as a low-power, low-voltage operational amplifier, the LMV3xxA series delivers a robust output drive capability. A class-AB output stage with common-source transistors achieves full rail-to-rail output swing capability. For resistive loads of 10 kΩ, the output swings to within 20 mV of either supply rail, regardless of the applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the rails.

7.3.4 Overload Recovery

Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated state to a linear state. The output devices of the operational amplifier enter a saturation region when the output voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return to the linear state. After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore, the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew time. The overload recovery time for the LMV3xxA series is approximately 850 ns.

7.4 Device Functional Modes

The LMV3xxA family has a single functional mode. The devices are powered on as long as the power-supply voltage is between and 5.5 V (±2.75 V).

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

and allows the LMV3xxA to be used in many single-supply applications.

8.2 Typical Application

8.2.1 LMV3xxA Low-Side, Current Sensing Application

Figure 32 shows the LMV3xxA configured in a low-side current sensing application. Figure 32. LMV3xxA in a Low-Side, Current-Sensing Application

8.2.1.1 Design Requirements

• Load current: 0 A to 1 A
• Output voltage: 4.9 V
• Maximum shunt voltage: 100 mV

8.2.1.2 Detailed Design Procedure

sizes the resistors RF and RG, to set the gain of the LMV3xxA to 49 V/V. measured transfer function of the circuit shown in Figure 32.

8.2.1.3 Application Curve

Figure 33. Low-Side, Current-Sense Transfer Function

8.2.2 Single-Supply Photodiode Amplifier

Figure 34 is an example of a single-supply photodiode amplifier circuit using the LMV358A. Figure 34. Single-Supply Photodiode Amplifier Circuit

2 R C

IN PD CM DC C C C 47 pF 5 pF 1 pF 53 pF F F 3dB 1 1 C 10.3 pF 10 pF2 R f 2 309 k 50 kHz |uSu u uSu :u OUT REF F IN V V 3.2 V 0.1 V kVR 310 309 kI 10 A A | : P REFV 0.1 V 0.0303V 3.3 V 1 2 REF 1 2 R R V V R R OUT IN F REFV I R V u LMV321A,LMV358A,LMV324A www.ti.com SBOS923B – DECEMBER 2017– REVISED JUNE 2018 Product Folder Links: LMV321A LMV358A LMV324A Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated Typical Application (continued)

8.2.2.1 Design Requirements

The design requirements for this design are:

• Supply Voltage: 3.3 V
• Input: 0 µA to 10 µA
• Output: 0.1 V to 3.2 V
• Bandwidth: 50 kHz

8.2.2.2 Detailed Design Procedure

The transfer function between the output voltage (VOUT), the input current, (IIN) and the reference voltage (VREF) is defined in Equation 5. (5) Where: (6) Set VREF to 100 mV to meet the minimum output voltage level by setting R1 and R2 to meet the required ratio calculated in Equation 7. (7) The closest resistor ratio to meet this ratio sets R1 to 11.5 kΩ and R2 to 357 Ω. The required feedback resistance can be calculated based on the input current and desired output voltage. (8) Calculate the value for the feedback capacitor based RF and the desired –3-dB bandwidth, (f-3dB) using Equation 9. (9) The minimum op amp bandwidth required for this application is based on the value of RF, CF, and the capacitance on the IN– pin of the LMV358A which is equal to the sum of the photodiode shunt capacitance, (CPD) the common-mode input capacitance, (CCM) and the differential input capacitance (CD) as Equation 10 shows. (10) The minimum op amp bandwidth is calculated in Equation 11. (11) The 1-MHz bandwidth of the LMV3xxA meets the minimum bandwidth requirement and remains stable in this application configuration.

8.2.2.3 Application Curves

measured DC performance of the photodiode amplifier circuit is shown in Figure 36. Figure 35. Photodiode Amplifier Circuit AC Gain Results Figure 36. Photodiode Amplifier Circuit DC Results

9 Power Supply Recommendations

to operating voltage or temperature. Supply voltages larger than 6 V may permanently damage the device; see the table.

9.1 Input and ESD Protection

protection primarily consists of current-steering diodes connected between the input and power-supply pins. to a minimum in noise-sensitive applications. Figure 37. Input Current Protection

10 Layout

10.1 Layout Guidelines

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single- supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, see Circuit Board Layout Techniques.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible, as shown in Figure 39. Keeping RF and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Remember that the input traces are the most sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly reduce leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

10.2 Layout Example

Figure 38. Schematic Representation for Figure 39 Figure 39. Layout Example

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report

11.2 Related Links

resources, tools and software, and quick access to order now. Table 1. Related Links

11.3 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

11.4 Community Resources

solve problems with fellow engineers. contact information for technical support.

11.5 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.7 Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 11-Jul-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LMV321AIDBVR PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 LMV321AIDCKR PREVIEW SC70 DCK 5 3000 TBD Call TI Call TI -40 to 125 LMV324AIPWR PREVIEW TSSOP PW 14 2000 TBD Call TI Call TI -40 to 125 LMV358AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1MAX LMV358AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1MAX LMV358AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 MV358A PLMV321AIDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PLMV321AIDCKR ACTIVE SC70 DCK 5 3000 TBD Call TI Call TI -40 to 125 PLMV324AIPWR ACTIVE TSSOP PW 14 2000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

www.ti.com 11-Jul-2018 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 26-Jun-2018 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV358AIDGKR VSSOP DGK 8 2500 366.0 364.0 50.0 LMV358AIDGKT VSSOP DGK 8 250 366.0 364.0 50.0 LMV358AIDR SOIC D 8 2500 336.6 336.6 41.3 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jun-2018 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C TYP0.22 0.08 0.25 3.0 2.6 2X 0.95 1.9

1.45 MAX

TYP0.15 0.00 5X 0.5 0.3 TYP0.6 0.3 TYP8 1.9 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/C 04/2017 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

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