PLMT01HTA/EM

LMT01-SP TI1 | Alldatasheet

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ADVANCE□INFORMATION MCU/ FPGA/ ASIC VDD : 3.0V to 5.5V GPIO GPIO/ COMP LMT01-SP VP VN Up to 2m Min 2.0V LMT01 Pulse Count Interface Power Off Conversion Time ADC Conversion Result Power On -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 ±50 ±25 0 25 50 75 100 125 150 Temperature Accuracy (ƒC) LMT01 Junction Temperaure (ƒC) C014 Max Limit Min Limit Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. LMT01-SP SNIS205 –JANUARY 2019 LMT01-SPradiationhardened2-pinprecisiondigitaloutputtemperaturesensor

1 Features

1• 5962R18211301VXC – Radiation Hardness Assured (RHA) to 100- krad(Si) Total Ionizing Dose (TID) – Single Event Latchup (SEL) immune to LET =

93 MeV-cm2/mg

– 2-lead HTA ceramic package

• 1.5°C accuracy over –50°C to 150°C wide temperature range and radiation
• Pulse count current loop easily read by processor – Number of output pulses is proportional to temperature with 0.0625°C resolution
• Communication frequency: 88 kHz
• Conversion current: 34 µA
• Continuous conversion plus data-transmission period: 100 ms
• Floating 2-V to 5.5-V (VP – VN) supply operation with integrated EMI immunity

2 Applications

• Thermistor signal chain upgrade
• Space analog temp sensor upgrade
• Space satellite telemetry
• High-speed signal chain monitoring
• Power supply monitoring
• Digital output wired probes

3 Description

The LMT01-SP device is a radiation hardened, high- accuracy, 2-pin temperature sensor with an easy-to- use pulse count current loop interface. The pulsed output is designed to easily interface directly with a comparator or GPIO input, thereby simplifying the hardware implementation. For space applications looking to minimize board area, the LMT01-SP is an ideal replacement for traditional thermistor signal chains and is inherently robust against single event effects. Integrated EMI suppression and a simple 2- pin architecture makes the device suitable for sensing in a noisy environment. The LMT01-SP can be mounted directly to a board or converted into a two- wire temperature probe with a wire length up to two meters. It can also be used to replace thermistors or analog temperature sensors in space applications with the added benefit of connecting directly to an MCU or FPGA without the need for amplifiers or ADCs for signal conditioning, reducing board space and power consumption. Device Information(1) PART NUMBER GRADE PACKAGE 5962R18211301VXC RHA - 100 krad(Si) HTA (2) 5.57 mm × 3.00 mm LMT01SPHTA/EM Engineering Evaluation(2) PLMT01SPHTA/EM Prototype Engineering Evaluation(2) LMT01CVAL-EVM Evaluation Module(2) (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) These units are intended for engineering evaluation only. They are processed to a noncompliant flow. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance over the full MIL specified temperature range of –55°C to 125°C or operating life. LMT01-SP Accuracy Typical units plotted in center of curve. 2-Pin IC Temperature Sensor

ADVANCE□INFORMATION LMT01-SP SNIS205 –JANUARY 2019 www.ti.com Product Folder Links: LMT01-SP Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Table of Contents

6.6 Electrical Characteristics - Pulse Count to

11.1 Receiving Notification of Documentation Updates 20

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES January 2019 * Initial release.

ADVANCE□INFORMATION Pin 1 VP VN LMT01-SP www.ti.com SNIS205 –JANUARY 2019 Product Folder Links: LMT01-SP Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

5 Pin Configuration and Functions

NAME NO. VP 1 Input Positive voltage pin; may be connected to system power supply or bias resistor. VN 2 Output Negative voltage pin; may be connected to system ground or a bias resistor. LID — Floating The HTA package used for the LMT01-SP does not have an internal connection to the metal lid. If necessary, this lid can be connected to ground with no impact to device operation.

ADVANCE□INFORMATION LMT01-SP SNIS205 –JANUARY 2019 www.ti.com Product Folder Links: LMT01-SP Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)(1). MIN MAX UNIT Voltage drop (VP – VN) −0.3 6 V Storage temperature, Tstg −65 175 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750 (1) During transmission of pulses at a high level.

6.3 Recommended Operating Conditions

Free-air temperature −55 125 °C Voltage drop (VP – VN) 2(1) 5.5 V (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) LMT01-SP UNITHTA (CTO-92)

2 PINS

RθJA Junction-to-ambient thermal resistance 124.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 51.8 °C/W RθJB Junction-to-board thermal resistance 64.8 °C/W ψJT Junction-to-top characterization parameter 3.8 °C/W ψJB Junction-to-board characterization parameter 63.6 °C/W

ADVANCE□INFORMATION LMT01-SP www.ti.com SNIS205 –JANUARY 2019 Product Folder Links: LMT01-SP Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) Calculated using Pulse Count to Temperature LUT and 0.0625°C resolution per pulse, see Electrical Characteristics - Pulse Count to Temperature LUT section. (2) Error can be linearly interpolated between temperatures given in table as shown in the Accuracy vs Temperature curves in Typical Characteristics section. (3) Limit is using end point calculation.

6.5 Electrical Characteristics

Over operating free-air temperature range and operating VP-VN range (unless otherwise noted). PARAMETER SUBGROUPS TEST CONDITIONS MIN TYP MAX UNIT ACCURACY Temperature accuracy(1)(2) 1, 2, 3 VP – VN of

2.15 V to

5.5 V 150°C ±0.4 120°C ±0.3 110°C ±0.3 100°C ±0.3 90°C ±0.125 –20°C ±0.125 –30°C ±0.3 –40°C ±0.4 –55°C –5 5 PULSE COUNT TRANSFER FUNCTION Number of pulses at 25°C 1 1195 1201 1207 Output pulse range 15 3228 Theoretical max (exceeds device rating) 1 4095 Resolution of one pulse 0.0625 °C OUTPUT CURRENT IOL Output current variation 1, 2, 3 Low level 28 34 40 µA IOH High level 112.5 125 143 µA High-to-low level output current ratio 3.1 3.7 4.5 POWER SUPPLY Accuracy sensitivity to change in VP – VN 1 2.15 V ≤ VP – VN ≤ 5 V(3) 40 133 m°C/V Leakage current VP – VN 1, 2, 3 VDD ≤ 0.4 V 0.002 3.5 µA THERMAL RESPONSE Still air thermal response time to 63% of final value (package only) 40 ms

6.6 Electrical Characteristics - Pulse Count to Temperature LUT

noted). LUT is short for Look-up Table. (1) Conversion time includes power up time or device turn on time that is typically 3 ms after POR threshold of 1.2 V is exceeded.

6.7 Switching Characteristics

Over operating free-air temperature range and operating VP – VN range (unless otherwise noted). Figure 1. Timing Specification Waveform

6.8 Typical Characteristics

Figure 2. Accuracy vs LMT01-SP Junction Temperature Figure 3. Accuracy vs LMT01-SP Junction Temperature Figure 4. Accuracy vs LMT01-SP Junction Temperature Figure 5. Accuracy vs LMT01-SP Junction Temperature Figure 6. Accuracy vs LMT01-SP Junction Temperature Figure 7. Accuracy vs LMT01-SP Junction Temperature

ADVANCE□INFORMATION VN Voltage Regulator and Output Signal Conditioning VP LMT01-SP Interface Data ADC VREF Thermal Diode Analog Circuitry Chip VDD Chip VSS LMT01-SP SNIS205 –JANUARY 2019 www.ti.com Product Folder Links: LMT01-SP Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The LMT01-SP uses thermal diode analog circuitry to detect the temperature. The temperature signal is then amplified and applied to the input of a ΣΔ ADC that is driven by an internal reference voltage. The ΣΔ ADC output is then processed through the interface circuitry into a digital pulse train. The digital pulse train is then converted to a current pulse train by the output signal conditioning circuitry that includes high and low current regulators. The voltage applied across the pins of the LMT01-SP is regulated by an internal voltage regulator to provide a consistent Chip VDD used by the ADC and its associated circuitry. The current pulse train output can be converted into a voltage with a single resistor. A simple microcontroller comparator or external transistor can be used convert this signal to valid logic levels the microcontroller can process properly through a GPIO pin. The temperature can be determined by gating a simple counter on for a specific time interval to count the total number of output pulses. After power is first applied the device will remain in a low output state while the LMT01-SP determines the temperature. Once the conversion cycle completes, the pulse train begins with a pulse frequency of approximately 88 kHz. The LMT01-SP will continuously convert and transmit data when the power is applied approximately every 104 ms.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Output Interface

The LMT01-SP provides a digital output in the form of a pulse count that is transmitted by a train of current pulses. After the LMT01-SP is powered up, it transmits a very low current of 34 µA for less than 54 ms while the part executes a temperature to digital conversion, as shown in Figure 19. When the temperature-to-digital conversion is complete, the LMT01-SP starts to transmit a pulse train that toggles from the low current of 34 µA to a high current level of 125 µA. The pulse train total time interval is at maximum 50 ms. The LMT01-SP transmits a series of pulses equivalent to the pulse count at a given temperature as described in Electrical Characteristics - Pulse Count to Temperature LUT. After the pulse count has been transmitted the LMT01-SP current level will remain low for the remainder of the 50 ms. The total time for the temperature to digital conversion and the pulse train time interval is 104 ms (maximum). If power is continuously applied, the pulse train output will repeat start every 104 ms (maximum). The LMT01-SP can be powered down at any time to conserve system power. To avoid invalid data it is recommended that a minimum power-down wait time of 50 ms is used before the device is turned on again.

Figure 19. Temperature to Digital Pulse Train Timing Cycle

7.3.2 Output Transfer Function

the device degrades as well when 125°C is exceeded. Characteristics - Pulse Count to Temperature LUT.

• PC is the Pulse Count
• Temp is the temperature reading (1) Table 1 shows some sample calculations using Equation 1.

Table 1. Sample Calculations Using Equation 1

Figure 20. LMT01-SP Output Transfer Function interpolation of the values found in Electrical Characteristics - Pulse Count to Temperature LUT. results. For a wide temperature range, TI recommends that linear interpolation and the LUT be used. Figure 21. LMT01-SP Typical Accuracy When Using First Figure 22. LMT01-SP Accuracy Using Linear Interpolation

7.3.3 Current Output Conversion to Voltage

The minimum voltage drop across the LMT01-SP must be maintained at 2.15 V during the conversion cycle. resistor is driving (that is, MCU, GPIO, or Comparator).

simple RC time constant model as shown in Figure 23 can be used to determine the rise and fall times. Figure 23. Simple RC Model for Rise and Fall Times

• RC as shown in Figure 23
• VHL is the target high level
• the final voltage VF = 125 µA × R
• the start voltage VS = 34 µA × R (2) For the 10% to 90% level rise time (tr), Equation 2 simplifies to: (3) Take care to ensure that the LMT01-SP voltage drop does not exceed 300 mV under reverse bias conditions, as given in the Absolute Maximum Ratings.

7.4 Device Functional Modes

ADVANCE□INFORMATION CONV DATAOL OH SH OL CONV OL DATA JA CONV DATA CONV DATA t tPC I I 4096 PCT I V I V Rt t t t4096 2 4096 T LMT01-SP SNIS205 –JANUARY 2019 www.ti.com Product Folder Links: LMT01-SP Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Mounting, Temperature Conductivity, and Self-Heating

The LMT01-SP can be applied easily in the same way as other integrated-circuit temperature sensors. It can be glued or cemented to a surface to ensure good temperature conductivity. The temperatures of the lands and traces to the leads of the LMT01-SP also affect the temperature reading, so they must be a thin as possible. The LMT01-SP comes in a hermetically sealed ceramic package and as such the IC is not susceptible to moisture or corrosion. Accompanying wiring and circuits should be kept insulated and dry to avoid excessive leakage and corrosion. Printed-circuit coatings are often used to ensure that moisture cannot corrode the leads or circuit traces. The junction temperature of the LMT01-SP is the actual temperature being measured by the device. The thermal resistance junction-to-ambient (RθJA) is the parameter (from Thermal Information) used to calculate the rise of a device junction temperature (self-heating) due to its average power dissipation. The average power dissipation of the LMT01-SP is dependent on the temperature it is transmitting as it effects the output pulse count and the voltage across the device. Equation 4 is used to calculate the self-heating in the die temperature of the LMT01- SP (TSH). where

• TSH is the ambient temperature
• IOL and IOH are the output low and high current level, respectively
• VCONV is the voltage across the LMT01-SP during conversion
• VDATA is the voltage across the LMT01-SP during data transmission
• tCONV is the conversion time
• tDATA is the data transmission time
• PC is the output pulse count
• RθJA is the junction to ambient package thermal resistance (4) Plotted in the curve Figure 24 are the typical average supply current (black line using left y-axis) and the resulting self-heating (red and violet lines using right y-axis) during continuous conversions. A temperature range of –50°C to 150°C, a VCONV of 5 V (red line) and 2.15 V (violet line) were used for the self-heating calculation. As can be seen in the curve, the average power supply current and thus the average self-heating changes linearly over temperature because the number of pulses increases with temperature. A negligible self-heating of about 45 m°C is observed at 150°C with continuous conversions. If temperature readings are not required as frequently as every 100 ms, self-heating can be minimized by shutting down power to the part periodically thus lowering the average power dissipation.

Figure 24. Average Current Draw and Self-Heating Over Temperature

8.2 Typical Application

Figure 25. MSP430 Comparator Input Implementation

8.2.1.1 Design Requirements

The design requirements listed in Table 2 are used in the detailed design procedure. Table 2. Design Parameters

ADVANCE□INFORMATION CLmin REF N N_TOLV V 1 V_REF_TOL COMP_OFFSET 32 u u CHmax REF N N_TOLV V 1 V_REF_TOL COMP_OFFSET 32 u u LMT01-SP SNIS205 –JANUARY 2019 www.ti.com Product Folder Links: LMT01-SP Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

8.2.1.2 Detailed Design Procedure

First, select the R and determine the maximum logic low voltage and the minimum logic high voltage while ensuring that when the LMT01-SP is converting, the minimum (VP – VN) requirement of 2.15 V is met. 1. Select R using minimum VP – VN during data transmission (2 V) and maximum output current of the LMT01- SP (143.75 µA) – R = (3.0 V – 2 V) / 143.75 µA = 6.993 k the closest 1% resistor is 6.980 k – 6.993 k is the maximum resistance so if using 1% tolerance resistor the actual resistor value needs to be 2. Check to see if the 2.15-V minimum voltage during conversion requirement for the LMT01-SP is met with the maximum IOL of 39 µA and maximum R of 6.81 k + 1%: – VLMT01-SP = 3 V – (6.81 k × 1.01) × 39 µA = 2.73 V 3. Find the maximum low level voltage range using the maximum R of 6.81 k and maximum IOL of 39 µA: – VRLmax = (6.81 k × 1.01) × 39 µA = 268 mV 4. Find the minimum high level voltage using the minimum R of 6.81 k and minimum IOH of 112.5 µA: – VRHmin = (6.81 k × 0.99) × 112.5 µA = 758 mV Now select the MSP430 comparator threshold voltage that enables the LMT01-SP to communicate to the MSP430 properly. 1. The MSP430 voltage is selected by selecting the internal VREF and then choosing the appropriate 1 of n/32 settings for n of 1 to 31. – VMID= (VRLmax – VRHmin) / 2 + VRHmin = (758 mV – 268 mV) / 2 + 268 mV = 513 mV 2. To prevent oscillation of the comparator, output hysteresis must be implemented. The MSP430 allows this by enabling different n for the rising edge and falling edge of the comparator output. For a falling comparator output transition, N must be set to 6. 3. Determine the noise margin caused by variation in comparator threshold level. Even though the comparator threshold level theoretically is set to VMID, the actual level varies from device to device due to VREF tolerance, resistor divider tolerance, and comparator offset. For proper operation, the COMP_B worst case input threshold levels must be within the minimum high and maximum low voltage levels presented across R, VRHmin and VRLmax, respectively where

• VREF is the MSP430 COMP_B reference voltage for this example at 2.5 V
• V_REF_TOL is the tolerance of the VREF of 1% or 0.01
• N is the divisor for the MSP430 or 7
• N_TOL is the tolerance of the divisor or 0.5
• COMP_OFFSET is the comparator offset specification or 10 mV (5) where
• VREF is the MSP430 COMP_B reference voltage for this example at 2.5 V
• V_REF_TOL is the tolerance of the VREF of 1% or 0.01
• N is the divisor for the MSP430 for the hysteresis setting or 6
• N_TOL is the tolerance of the divisor or 0.5
• COMP_OFFSET is the comparator offset specification or 10 mV (6) The noise margin is the minimum of the two differences: (VRHmin – VCHmax) or (VCHmin – VRLmax) (7) which works out to be 145 mV.

Figure 26. Pulse Count Signal Amplitude Variation

8.2.1.2.1 Setting the MSP430 Threshold and Hysteresis

filter output transitions that occur too quickly.

8.2.1.3 Application Curves

Figure 27. MSP430 COMP_B Input Signal No Capacitance Figure 28. MSP430 COMP_B Input Signal 100-pF

8.3 System Examples

device can be configured to have a common ground with a high side signal (see Figure 31).

9 Power Supply Recommendations

voltage to internal circuitry. (yellow trace) is still ramping up to final value while the LMT01-SP (red trace) has already started a conversion. value before a conversion is used or that ramp rates be faster than 2.5 ms. Figure 32. Output Pulse Count With Appropriate Power Figure 33. Output Pulse Count With Slow Power Supply

10 Layout

10.1 Layout Guidelines

no internal connections to the die and is thus floating. If desired, a wire can be soldered from the lid to ground.

10.2 Layout Example

Figure 34. Layout Example (CTO-92/HTA Package)

ADVANCE□INFORMATION LMT01-SP SNIS205 –JANUARY 2019 www.ti.com Product Folder Links: LMT01-SP Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

11 Device and Documentation Support

11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 23-Feb-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PLMT01HTA/EM ACTIVE CTO HTA 2 1 TBD Call TI Call TI 25 to 25 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LMT01-SP :

www.ti.com 23-Feb-2019 Addendum-Page 2

• Catalog: LMT01
• Automotive: LMT01-Q1 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

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