PLMR51610XDBVR

LMR51610 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 36

Technical content

LMR516xx SIMPLE SWITCHER® Power Converter, 4-V to 65-V, 0.6-A/1-A, Buck Converter in a SOT-23 Package

1 Features

• Configured for rugged industrial applications – 4-V to 65-V input voltage range – Input transient protection up to 70 V – 0.6-A/1-A continuous output current – 80-ns minimum switching on time – 400-kHz and 1.1-MHz switching frequency – –40°C to 150°C junction temperature range – 98% maximum duty cycle – Monotonic start-up with pre-biased output – Short-circuit protection with hiccup mode – Precision enable – ±1.5% tolerance voltage reference
• Small solution size and ease of use – Integrated synchronous rectification – Internal compensation for ease of use – SOT-23 package
• Pin-to-pin compatible with the LMR16006, LV2862, LMR50410, TPS560430, LMR54406, and LMR54410
• Various options in pin-to-pin compatible package – PFM and forced PWM (FPWM) options
• Create a custom design using the LMR516xx with the WEBENCH® Power Designer

2 Applications

• Major appliances
• PLC, DCS, and PAC
• Smart meters
• Power delivery

3 Description

The LMR516xx is a wide-V IN, easy-to-use synchronous buck converter capable of driving up to 0.6-A and 1-A load current. With a wide input range of

4 V to 65V, the device is designed for a wide range of

industrial applications for power conditioning from an unregulated source. The LMR516xx operates at 400-kHz and 1.1-MHz switching frequency to support use of relatively small inductors for an optimized solution size. The LMR516xx has a PFM version to realize high efficiency at light load and a FPWM version to achieve constant frequency and small output voltage ripple over the full load range. Soft-start and compensation circuits are implemented internally, which allow the device to be used with minimal external components. The device has built-in protection features, such as cycle-by-cycle current limit, hiccup mode short-circuit protection, and thermal shutdown in case of excessive power dissipation. Device Information PART NUMBER PACKAGE(1) PACKAGE SIZE(2) LMR51610 DBV (SOT-23, 6) 2.90 mm × 2.80 mm LMR51606(3) (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. (3) Preview information (not Production Data). Simplified Schematic Efficiency Versus Output Current VOUT = 5 V, 400 kHz ADVANCE INFORMATION LMR51610 SLUSEY1 – JUNE 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains ADVANCE INFORMATION for pre-production products; subject to change without notice.

10.3 Receiving Notification of Documentation Updates..25

11 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES June 2023 * Initial Release LMR51610 SLUSEY1 – JUNE 2023 www.ti.com ADVANCE INFORMATION

2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: LMR51610

5 Device Comparison Table

ORDERABLE PART NUMBER OUTPUT CURRENT FREQUENCY PFM OR FPWM OUTPUT LMR51610XDBVR 1 A 400 kHz PFM Adjustable LMR51610XFDBVR 1 A 400 kHz FPWM Adjustable

6 Pin Configuration and Functions

Figure 6-1. 6-Pin SOT-23 DBV Package (Top View) Table 6-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO CB 1 P Bootstrap capacitor connection for high-side FET driver. Connect a high quality 100-nF capacitor from this pin to the SW pin. GND 2 G Power ground pins. Connected to the source of low-side FET internally. Connect to system ground, ground side of CIN and COUT. The path to CIN must be as short as possible. FB 3 A Feedback input to the converter. Connect a resistor divider to set the output voltage. Never short this terminal to ground during operation. EN 4 A Precision enable input to the converter. Do not float. High = on, low = off. Can be tied to VIN. Precision enable input allows an adjustable UVLO by an external resistor divider. VIN 5 P Supply input pin to the internal bias LDO and high-side FET. Connect to the input supply and input bypass capacitors CIN. Input bypass capacitors must be directly connected to this pin and GND. SW 6 P Switching output of the converter. Internally connected to source of the high-side FET and drain of the low-side FET. Connect to the power inductor. (1) A = Analog, P = Power, G = Ground www.ti.com LMR51610 SLUSEY1 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LMR51610

7 Specifications

7.1 Absolute Maximum Ratings

Over junction temperature range of -40°C to 150°C (unless otherwise noted)(1) MIN MAX UNIT Input voltage VIN to GND –0.3 70 V EN to GND –0.3 VIN+0.3 V FB to GND –0.3 5.5 V Output voltage SW to GND –0.3 70 V SW to GND less than 10-ns transients –3.5 70 V CBOOT to SW –0.3 5.5 V Junction Temperature TJ –40 150 °C Storage temperature, Tstg –55 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/ JEDEC JS-001(1) ±2500 V Charged-device model (CDM), per ANSI/ESDA/ JEDEC JS-002(2) ±750 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)(1) MIN NOM MAX UNIT Input voltage VIN to GND 4 65 V EN 0 VIN V FB 0 4.5 V Output voltage VOUT (2) 0.8 28 V Output current Iout (LM51606)(4) 0.6 A Output current Iout (LM51610)(4) 1 A TJ Operating junction temperature(4) –40 +150 °C (1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For compliant specifications, see Electrical Characteristics table. (2) Under no conditions can the output voltage be allowed to fall below zero volts. (3) Maximum continuous DC current can be derated when operating with high switching frequency or high ambient temperature. See Application section for details. (4) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 150℃. LMR51610 SLUSEY1 – JUNE 2023 www.ti.com ADVANCE INFORMATION

4 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: LMR51610

7.4 Thermal Information

THERMAL METRIC(1) LMR516xx UNITDBV(SOT-23-6)

6 PINS

RθJA Junction-to-ambient thermal resistance 173 °C/W RθJC(top) Junction-to-case (top) thermal resistance 116 °C/W RθJB Junction-to-board thermal resistance 31 °C/W ψJT Junction-to-top characterization parameter 20 °C/W ψJB Junction-to-board characterization parameter 30 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

Limits apply over operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following s apply: VIN = 4.5 V to 65 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IQ(VIN) VIN quiescent current VEN = 3 V, PWM Operation 420 µA IQ(VIN) VIN quiescent current (non-switching) (2) VEN = 3 V, PFM Variant Only 26.5 40 µA ISD(VIN) VIN shutdown supply current VEN = 0 V 0.9 3 µA UVLO VINUVLO(R) VIN UVLO rising threshold VIN rising 3.8 4 V VINUVLO(F) VIN UVLO falling threshold VIN falling 3.6 V VINUVLO(H) VIN UVLO hysteresis 0.2 V ENABLE VEN(R) EN voltage rising threshold EN rising, enable switching 1.1 1.227 1.36 V VEN(F) EN voltage falling threshold EN falling, disable switching 0.85 1.0 1.15 V IEN(P2) EN pin sourcing current post EN rising threshold VEN = 3 V 10 50 nA REFERENCE VOLTAGE Vfb Reference voltage 0.788 0.8 0.812 V IFB(LKG) FB input leakage current VFB = 0.8 V 0.2 nA SWITCHING FREQUENCY fSW1(CCM) Switching frequency, CCM operation 340 400 460 KHz STARTUP tSS Internal fixed soft-start time Time from first SW pulse to VREF at 90% 2 ms POWER STAGE RDSON(HS) High-side MOSFET on-resistance VIN = 12 V, TJ = 25°C 0.7 Ω RDSON(LS) Low-side MOSFET on-resistance VIN = 12 V, TJ = 25°C 0.36 Ω tON(min) Minimum ON pulse width VIN = 24 V, IOUT = 1 A 80 ns tON(max) Maximum ON pulse width VIN = 12 V, IOUT = 0.5 A 5 µs tOFF(min) Minimum OFF pulse width VIN = 5 V 200 ns OVERCURRENT PROTECTION IHS_PK(OC) High-side peak current limit (3) LMR51606 0.8 1.1 1.4 A IHS_PK(OC) High-side peak current limit (3) LMR51610 1.25 1.6 1.95 A www.ti.com LMR51610 SLUSEY1 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LMR51610

7.5 Electrical Characteristics (continued)

Limits apply over operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated. Minimum and Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following s apply: VIN = 4.5 V to 65 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ILS_V(OC) Low-side valley current limit (3) LMR51606 0.62 0.8 0.98 A ILS_V(OC) Low-side valley current limit (3) LMR51610 0.9 1.1 1.3 A ILS(NOC) Low-side negative current limit LMR51606 FPWM Only –0.33 A ILS(NOC) Low-side negative current limit LMR51610 FPWM Only –0.66 A IZC Zero-cross detection current threshold 0 A THERMAL SHUTDOWN TJ(SD) Thermal shutdown threshold (1) Temperature rising 165 °C TJ(HYS) Thermal shutdown hysteresis (1) 20 °C (1) MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). (2) This current is the current used by the device open loop. This current does not represent the total input current of the system when in regulation. (3) The current limit values in this table are tested, open loop, in production. The current limit values can differ from those found in a closed loop application

7.6 System Characteristics

The following specifications apply to a typical application circuit with nominal component values. Specifications in the typical (TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case of typical components over the temperature range of TJ = -40°C to 150°C. These specifications are not ensured by production testing. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Operating input voltage range 4 65 V VOUT Adjustable output voltage regulation(1) PFM operation –1.5% 2.5% ISUPPLY Input supply current when in regulation VIN = 24 V, VOUT = 5 V, IOUT = 0 A, RFBT = 22.1kΩ, PFM variant 38 µA DMAX Maximum switch duty cycle(2) 98% VHC FB pin voltage required to trip short- circuit hiccup mode 0.32 V tD Switch voltage dead time 5 ns (1) Deviation in VOUT from nominal output voltage value at VIN = 24 V, IOUT = 0 A to full load (2) In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: FMIN = 1 / (tON-MAX + tOFF-MIN). DMAX = tON-MAX /(tON-MAX + tOFF-MIN). LMR51610 SLUSEY1 – JUNE 2023 www.ti.com ADVANCE INFORMATION

6 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: LMR51610

7.7 Typical Characteristics

VIN = 24 V, fSW = 400 kHz, TA = 25°C, unless otherwise specified IOUT Efficiency(%) 100 V IN = 12V V IN = 24V V IN = 36V V IN = 48V V IN = 65V fSW = 400 kHz VOUT = 3.3 V LMR51610X Figure 7-1. 3.3-V PFM Efficiency Versus Load Current IOUT Efficiency(%) 100 V IN = 12V V IN = 24V V IN = 36V V IN = 48V V IN = 65V fSW =400 kHz VOUT = 3.3V LMR51610XF Figure 7-2. 3.3-V FPWM Efficiency Versus Load Current fSW = 400 kHz VOUT = 5 V LMR51610X Figure 7-3. 5-V PFM Efficiency Versus Load Current I OUT (A) Efficiency(%) 100 V IN = 12V V IN = 24V V IN = 36V V IN = 48V V IN = 65V fSW = 400KHz VOUT = 5 V LMR51610XF Figure 7-4. 5-V FPWM Efficiency Versus Load Current I OUT (A) Efficiency(%) 100 V IN = 24V V IN = 36V V IN = 48V V IN = 65V fSW = 400 kHz VOUT = 12 V LMR51610X Figure 7-5. 12-V PFM Efficiency Versus Load Current I OUT Efficiency(%) 100 V IN = 24V V IN = 36V V IN = 48V V IN = 65V fSW = 400 kHz VOUT = 12V LMR51610XF Figure 7-6. 12-V FPWM Efficiency Versus Load Current www.ti.com LMR51610 SLUSEY1 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LMR51610

7.7 Typical Characteristics (continued)

VIN = 24 V, fSW = 400 kHz, TA = 25°C, unless otherwise specified fSW = 400kHz VOUT = 3.3 V LMR51610X Figure 7-7. 3.3-V Load Regulation fSW = 400 kHz VOUT = 5 V LMR51610X Figure 7-8. 5-V Load Regulation Figure 7-9. IQ Versus Temperature Temperature(  C) V IN UVLO(V) -50 -25 0 25 50 75 100 125 150 175 3.5 3.6 3.7 3.8 3.9 UVLO_TURN ON UVLO_TURN OFF Figure 7-10. VIN UVLO Versus Temperature Figure 7-11. Reference Voltage Versus Temperature Temperature(  C) Current Limit(A) -50 -25 0 25 50 75 100 125 150 175 1.2 1.4 1.6 1.8 HS Current Limit LS Current Limit Figure 7-12. HS and LS Current Limit Versus Temperature LMR51610 SLUSEY1 – JUNE 2023 www.ti.com ADVANCE INFORMATION

8 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: LMR51610

8 Detailed Description

8.1 Overview

The LMR516xx converter is an easy-to-use, synchronous, step-down DC/DC converter operating from a 4-V to 65-V supply voltage. The LMR51610 is capable of delivering up to 1-A DC load current in a very small solution size while the LMR51606 is capable of delivering up to 0.6-A load current. The family has multiple versions applicable to various applications. See Device Comparison Table for detailed information. The LMR516xx employs fixed-frequency peak-current mode control. The PFM version enters PFM mode at light load to achieve high efficiency. A FPWM version is provided to achieve low output voltage ripple, tight output voltage regulation, and constant switching frequency at light load. The device is internally compensated, which reduces design time and requires few external components. Additional features, such as precision enable and internal soft start, provide a flexible and easy-to-use solution for a wide range of applications. Protection features include the following:

• Thermal shutdown
• VIN undervoltage lockout
• Cycle-by-cycle current limit
• Hiccup mode short-circuit protection This family of devices requires very few external components and has a pinout designed for simple, optimal PCB layout. www.ti.com LMR51610 SLUSEY1 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LMR51610

8.2 Functional Block Diagram

Ton_min/Toff_min Detector

8.3 Feature Description

8.3.1 Fixed Frequency Peak Current Mode Control

The following operating description of the LMR516xx refers to Functional Block Diagram and to the waveforms in Figure 8-1. The LMR516xx is a step-down synchronous buck converter with integrated high-side (HS) and low-side (LS) switches (synchronous rectifier). The LMR516xx supplies a regulated output voltage by turning on the high-side and low-side NMOS switches with controlled duty cycle. During high-side switch ON time, the SW pin voltage swings up to approximately V IN, and the inductor current, i L, increases with a linear slope of (V IN – VOUT) / L. When the high-side switch is turned off by the control logic, the low-side switch is turned on after an anti-shoot-through dead time. Inductor current discharges through the low-side switch with a slope of –V OUT / L. The control parameter of a buck converter is defined as Duty Cycle D = t ON / T SW, where t ON is the high-side switch ON time and T SW is the switching period. The converter control loop maintains a constant output voltage by adjusting the duty cycle D. In an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = VOUT / VIN. LMR51610 SLUSEY1 – JUNE 2023 www.ti.com ADVANCE INFORMATION

10 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: LMR51610

VIN D = tON/ TSW tON tOFF TSW t SW Voltage iL IOUT Inductor Current ILPK ¨LL Figure 8-1. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM) The LMR516xx employs fixed-frequency peak-current mode control. A voltage feedback loop is used to get accurate DC voltage regulation by adjusting the peak-current command based on voltage offset. The peak inductor current is sensed from the high-side switch and compared to the peak current threshold to control the ON time of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer external components, making designing easy and providing stable operation when using a variety of output capacitors. The converter operates with fixed switching frequency at normal load conditions. During light-load condition, the LMR516xx operates in PFM mode to maintain high efficiency (PFM version) or in FPWM mode for low output voltage ripple, tight output voltage regulation, and constant switching frequency (FPWM version). www.ti.com LMR51610 SLUSEY1 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LMR51610

8.3.2 Adjustable Output Voltage

A precision 0.8-V reference voltage (V REF) is used to maintain a tightly regulated output voltage over the entire operating temperature range. The output voltage is set by a resistor divider from V OUT to the FB pin. TI recommends to use 1% tolerance resistors with a low temperature coefficient for the FB divider. Select the bottom-side resistor, RFBB, for the desired divider current and use Equation 1 to calculate the top-side resistor, RFBT. The recommended range for R FBT is 10 k Ω to 100 k Ω. A lower R FBT value can be used if pre-loading is desired to reduce the V OUT offset in PFM operation. Lower R FBT values reduce efficiency at very light load. Less static current goes through a larger R FBT value and can be more desirable when light-load efficiency is critical. However, TI does not recommend R FBT values larger than 1 M Ω because they make the feedback path more susceptible to noise. Larger R FBT values require a more carefully designed feedback path trace from the feedback resistors to the feedback pin of the device. The tolerance and temperature variation of the resistor divider network affect the output voltage regulation. VOUT FB RFBT RFBB Figure 8-2. Output Voltage Setting R FBT = V OUT − V REF V REF × R FBB (1)

8.3.3 Enable

The voltage on the EN pin controls the ON/OFF operation of the LMR516xx. A voltage of less than 0.85 V shuts down the device, while a voltage of greater than 1.36 V is required to start the converter. The EN pin is an input and cannot be left open or floating. The simplest way to enable the operation of the LMR516xx is to connect EN to VIN. This connection allows self-start-up of the LMR516xx when VIN is within the operating range. Many applications benefit from the employment of an enable divider, R ENT and RENB (Figure 8-3) to establish a precision system UVLO level for the converter. A system UVLO can be used for supplies operating from utility power as well as battery power. A system UVLO can be used for sequencing, ensuring reliable operation, or supplying protection, such as a battery discharge level. An external logic signal can also be used to drive the EN input for system sequencing and protection. Note The EN pin voltage must not to be greater than V IN + 0.3 V. TI does not recommend to apply EN voltage when VIN is 0 V. RENT EN VIN RENB Figure 8-3. System UVLO by Enable Divider LMR51610 SLUSEY1 – JUNE 2023 www.ti.com ADVANCE INFORMATION

12 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: LMR51610

8.3.4 Minimum ON Time, Minimum OFF Time, and Frequency Foldback

The minimum ON time (T ON_MIN) is the shortest duration of time that the high-side switch can be turned on. TON_MIN is typically 80 ns for the LMR516xx. The minimum OFF time (T OFF_MIN) is the shortest duration of time that the high-side switch can be off. T OFF_MIN is typically 200 ns. In CCM operation, T ON_MIN and T OFF_MIN limit the voltage conversion range without switching frequency foldback. The minimum duty cycle without frequency foldback allowed is: D MIN = T O N _ MI N × f SW (2) The maximum duty cycle without frequency foldback allowed is: D MAX = 1 − T OFF _ M IN × f SW (3) Given a required output voltage, the maximum VIN without frequency foldback can be found by: V IN _ MAX = V OUT f S W × T ON _ MIN (4) The minimum VIN without frequency foldback can be calculated by: V IN _ MIN = V O UT 1 − f SW × T OFF _ M IN (5) In the LMR516xx, a frequency foldback scheme is employed once the T ON_MIN or T OFF_MIN is triggered, which can extend the maximum duty cycle or lower the minimum duty cycle. The on time decreases while V IN voltage increases. After the on time decreases to T ON_MIN, the switching frequency starts to decrease while V IN continues to go up, which lowers the duty cycle further to keep V OUT in regulation according to Equation 4. The frequency foldback scheme also works once larger duty cycle is needed under a low V IN condition. The frequency decreases after the device hits its T OFF_MIN, which extends the maximum duty cycle according to Equation 5. In such condition, the frequency can be as low as approximately 200 kHz. A wide range of frequency foldback allows for the LMR516xx output voltage to stay in regulation with a much lower supply voltage V IN, which leads to a lower effective dropout. With frequency foldback while maintaining a regulated output voltage, V IN_MAX is raised and V IN_MIN is lowered by decreased fSW.

8.3.5 Bootstrap Voltage

The LMR516xx provides an integrated bootstrap voltage converter. A small capacitor between the CB and SW pins provides the gate drive voltage for the high-side MOSFET. The bootstrap capacitor is refreshed when the high-side MOSFET is off and the low-side switch is on. The recommended value of the bootstrap capacitor is 0.1 µF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16 V or higher is recommended for stable performance over temperature and voltage.

8.3.6 Overcurrent and Short-Circuit Protection

The LMR516xx incorporates both peak and valley inductor current limit to provide protection to the device from overloads and short circuits and limit the maximum output current. Valley current limit prevents inductor current runaway during short circuits on the output, while both peak and valley limits work together to limit the maximum output current of the converter. Cycle-by-cycle current limit is used for overloads, while hiccup mode is used for sustained short circuits. High-side MOSFET overcurrent protection is implemented by the nature of the peak current mode control. The high-side switch current is sensed when the high-side is turned on after a set blanking time. The high-side switch current is compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle. www.ti.com LMR51610 SLUSEY1 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LMR51610

See Functional Block Diagram for more details. The peak current of high-side switch is limited by a clamped maximum peak current threshold Isc (see Electrical Characteristics), which is constant. The current going through the low-side MOSFET is also sensed and monitored. When the low-side switch turns on, the inductor current begins to ramp down. The low-side switch is not turned OFF at the end of a switching cycle if its current is above the low-side current limit, I LS_LIMIT (see Electrical Characteristics ). The low-side switch is kept ON so that inductor current keeps ramping down until the inductor current ramps below I LS_LIMIT. Then, the low-side switch is turned OFF and the high-side switch is turned on after a dead time. After I LS_LIMIT is achieved, peak and valley current limit controls the maximum current delivered and it can be calculated using Equation 6. I O UT _ MAX = I LS _ L I MIT + I SC 2 (6) If the feedback voltage is lower than 40% of the V REF, the current of the low-side switch triggers I LS_LIMIT for 256 consecutive cycles and hiccup current protection mode is activated. In hiccup mode, the converter shuts down and keeps off for a period of hiccup, T HICCUP (150 ms typical) before the LMR516xx tries to start again. If overcurrent or a short-circuit fault condition still exists, hiccup repeats until the fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions, preventing overheating and potential damage to the device. For the FPWM version, the inductor current is allowed to go negative. When this current exceeds the low-side negative current limit, I LS_NEG, the low-side switch is turned off and high-side switch is turned on immediately. This event is used to protect the low-side switch from excessive negative current.

8.3.7 Soft Start

The integrated soft-start circuit prevents input inrush current impacting the LMR516xx and the input power supply. Soft start is achieved by slowly ramping up the internal reference voltage when the device is first enabled or powered up. The typical soft-start time is 2 ms. The LMR516xx also employs overcurrent protection blanking time, T OCP_BLK (33-ms typical), at the beginning of power up. Without this feature, in applications with a large amount of output capacitors and high VOUT, the inrush current is large enough to trigger the current-limit protection, which can cause a false start as the device enters into hiccup mode. This event results in a continuous recycling of soft start without raising up to the programmed output voltage. The LMR516xx is able to charge the output capacitor to the programmed V OUT by controlling the average inductor current during the start-up sequence in the blanking time, TOCP_BLK.

8.3.8 Thermal Shutdown

The LMR516xx provides an internal thermal shutdown to protect the device when the junction temperature exceeds 170°C. Both high-side and low-side FETs stop switching in thermal shutdown. After the die temperature falls below 158°C, the device reinitiates the power-up sequence controlled by the internal soft-start circuitry. LMR51610 SLUSEY1 – JUNE 2023 www.ti.com ADVANCE INFORMATION

14 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: LMR51610

8.4 Device Functional Modes

8.4.1 Shutdown Mode

The EN pin provides electrical ON and OFF control for the LMR516xx. When V EN is below 1 V, the device is in shutdown mode. The LMR516xx also employs V IN undervoltage lockout protection (UVLO). If V IN voltage is below the UVLO threshold of 3.6 V, the converter turns off.

8.4.2 Active Mode

The LMR516xx is in active mode when both V EN and V IN are above their respective operating threshold. The simplest way to enable the LMR516xx is to connect the EN pin to VIN pin. This action allows self-start-up when the input voltage is in the operating range of 4.0 V to 65 V. See Enable for details on setting these operating levels. In active mode, depending on the load current, the LMR516xx is in one of four modes: 1. Continuous conduction mode (CCM) with fixed switching frequency when load current is greater than half of the peak-to-peak inductor current ripple (for both PFM and FPWM versions) 2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is less than half of the peak-to-peak inductor current ripple(only for PFM version) 3. Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load (only for PFM version) 4. Forced pulse width modulation mode (FPWM) with fixed switching frequency even at light load (only for FPWM version)

8.4.3 CCM Mode

Continuous conduction mode (CCM) operation is employed in the LMR516xx when the load current is greater than half of the peak-to-peak inductor current. In CCM operation, the frequency of operation is fixed, output voltage ripple is at a minimum in this mode and the maximum output current of 1 A or 0.6 A can be supplied by the LMR51610 or LMR51606, respectively.

8.4.4 Light Load Operation (PFM Version)

For PFM version, when the load current is lower than half of the peak-to-peak inductor current in CCM, the LMR516xx operates in discontinuous conduction mode (DCM), also known as diode emulation mode (DEM). In DCM operation, the low-side switch is turned off when the inductor current drops to I LS_ZC (20-mA typical) to improve efficiency. Both switching losses and conduction losses are reduced in DCM, compared to forced PWM operation at light load. During light load operation, pulse frequency modulation (PFM) mode is activated to maintain high efficiency operation. When either the minimum high-side switch ON time t ON_MIN or the minimum peak inductor current IPEAK_MIN (300-mA typical) is reached, the switching frequency decreases to maintain regulation. In PFM mode, switching frequency is decreased by the control loop to maintain output voltage regulation when load current reduces. Switching loss is further reduced in PFM operation due to a significant drop in effective switching frequency.

8.4.5 Light-Load Operation (FPWM Version)

For FPWM version, LMR516xx is locked in PWM mode at full load range. This operation is maintained, even in no-load condition, by allowing the inductor current to reverse its normal direction. This mode trades off reduced light load efficiency for low output voltage ripple, tight output voltage regulation, and constant switching frequency. www.ti.com LMR51610 SLUSEY1 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LMR51610

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The LMR516xx is a step-down DC-to-DC converter. The LMR51610 is typically used to convert a higher input voltage to a lower output DC voltage with a maximum output current of 1 A. The LMR51606 is typically used to convert a higher input voltage to a lower output DC voltage with a maximum output current of 0.6 A. The following design procedure can be used to select components for the LMR516xx.

9.2 Typical Application

The LMR51610 only requires a few external components to convert from a wide voltage range supply to a fixed output voltage. Figure 9-1 shows a basic schematic. CB SW Lout 33µH CBOOT 0.1 µF FB VIN VIN 24 V COUT 22 µF EN CIN 2.2 µF GND VOUT 5 V RFBT 118 kΩ RFBB 22.1 kΩ Figure 9-1. Application Circuit The external components have to fulfill the needs of the application and the stability criteria of the control loop of the device. Table 9-1 can be used to simplify the output filter component selection. Table 9-1. L and COUT Typical Values fSW (kHz) VOUT (V) L (µH) COUT (µF) (1) RFBT (kΩ) RFBB (kΩ) 400 3.3 22 22 µF / 16 V 69.8 22.1 5 33 22 µF / 25 V 118 22.1 12 68 2 × 22 µF / 25 V 309 22.1 (1) Ceramic capacitor is used in this table. LMR51610 SLUSEY1 – JUNE 2023 www.ti.com ADVANCE INFORMATION

16 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: LMR51610

9.2.1 Design Requirements

The detailed design procedure is described based on a design example. For this design example, use the parameters listed in Table 9-2 as the input parameters. Table 9-2. Design Example Parameters PARAMETER VALUE Input voltage, VIN 5-V typical, range from 6 V to 65 V Output voltage, VOUT 5 V ±3% Maximum output current, IOUT_MAX 1 A Output overshoot, undershoot (0.25 A to 0.75 A) ±5% Output voltage ripple 0.5% Operating frequency 400 kHz

9.2.2 Detailed Design Procedure

9.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR516xx device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.2.2 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR51610 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.2.3 Output Voltage Set-Point

The output voltage of the LMR51610 device is externally adjustable using a resistor divider network. The divider network is comprised of a top feedback resistor R FBT and bottom feedback resistor R FBB. Equation 7 is used to determine the output voltage of the converter: www.ti.com LMR51610 SLUSEY1 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LMR51610

R FBT = V OUT − V REF V REF × R FBB (7) Choose the value of R FBB to be 22.1 k Ω. With the desired output voltage set to 5 V and the V REF = 0.8 V, the RFBT value can then be calculated using Equation 7. The formula yields to a value 116 k Ω, a standard value of 115 kΩ is selected.

9.2.2.4 Switching Frequency

The higher switching frequency allows for lower value inductors and smaller output capacitors, which results in smaller solution size and lower component cost. However, higher switching frequency brings more switching loss, making the solution less efficient and produce more heat. The switching frequency is also limited by the minimum on time of the integrated power switch, the input voltage, the output voltage, and the frequency shift limitation as mentioned in Minimum ON Time, Minimum OFF Time, and Frequency Foldback . For this example, a switching frequency of 400 kHz is selected.

9.2.2.5 Inductor Selection

The most critical parameters for the inductor are the inductance, saturation current, and the RMS current. The inductance is based on the desired peak-to-peak ripple current ΔiL. Because the ripple current increases with the input voltage, the maximum input voltage is always used to calculate the minimum inductance L MIN. Use Equation 9 to calculate the minimum value of the output inductor. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current of the device. A reasonable value of K IND must be 20% to 60% of maximum I OUT supported by converter. During an instantaneous overcurrent operation event, the RMS and peak inductor current can be high. The inductor saturation current must be higher than peak current limit level. ∆ i L = V O U T × V IN _ MAX − V OUT V IN _ MAX × L × f SW (8) L MIN = V IN _ MAX − V OUT I OUT × K IND × V OUT V IN _ M AX × f SW (9) In general, choose lower inductance in switching power supplies because it usually corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. Too low of an inductance can generate too large of an inductor current ripple such that overcurrent protection at the full load can be falsely triggered. Too low of an inductance also generates more inductor core loss because the current ripple is larger. Larger inductor current ripple also implies larger output voltage ripple with the same output capacitors. With peak current mode control, TI recommends to have adequate amount of inductor ripple current. A larger inductor ripple current improves the comparator signal-to-noise ratio. For this design example, choose K IND = 0.3. The minimum inductor value is calculated to be 32.9 µH. Choose the nearest standard 33-µH ferrite inductor with a capability of 1.5-A RMS current and 2.5-A saturation current.

9.2.2.6 Output Capacitor Selection

The device is designed to be used with a wide variety of LC filters. Minimize the output capacitance to keep cost and size down. The output capacitor or capacitors, C OUT, must be chosen with care because it directly affects the steady state output voltage ripple, loop stability, and output voltage overshoot and undershoot during load current transient. The output voltage ripple is essentially composed of two parts. One part is caused by the inductor ripple current flowing through the Equivalent Series Resistance (ESR) of the output capacitors: ∆ V O UT _ ESR = ∆ i L × E SR = K IND × I OUT × E SR (10) The other part is caused by the inductor current ripple charging and discharging the output capacitors: The two components of the voltage ripple are not in-phase, therefore, the actual peak-to-peak ripple is less than the sum of the two peaks. LMR51610 SLUSEY1 – JUNE 2023 www.ti.com ADVANCE INFORMATION

18 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: LMR51610

∆ V O UT _ C = ∆ i L 8 × f S W × C OUT = K I N D × I OUT 8 × f SW × C OUT (11) Output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation with presence of large current steps and fast slew rates. When a large load step occurs, output capacitors provide the required charge before the inductor current can slew to an appropriate level. The control loop of the converter usually requires eight or more clock cycles to regulate the inductor current equal to the new load level during this time. The output capacitance must be large enough to supply the current difference for eight clock cycles to maintain the output voltage within the specified range. Equation 12 shows the minimum output capacitance needed for a specified VOUT overshoot and undershoot. C O UT > 1 2 × 6 × I OH − I OL f SW × ∆ V OUT _ SH O OT (12) where

• KIND = Ripple ratio of the inductor current (ΔiL / IOUT)
• IOL = Low level output current during load transient
• IOH = High level output current during load transient
• VOUT_SHOOT = Target output voltage overshoot or undershoot For this design example, the target output ripple is 25 mV. Assuming ΔVOUT_ESR = Δ VOUT_C = 15 mV, choose KIND = 0.3. Equation 10 yields ESR no larger than 50 m Ω and Equation 11 yields COUT no smaller than 6.25 µF. For the target overshoot and undershoot limitation of this design, ΔVOUT_SHOOT = 5% × VOUT = 250 mV. The COUT can be calculated to be no less than 20 µF by Equation 12. In summary, the most stringent criteria for the output capacitor is 20 µF. Considering derating, one 22-µF, 25-V, X7R ceramic capacitor with 5-mΩ ESR is used.

9.2.2.7 Input Capacitor Selection

The LMR51610 device requires a high frequency input decoupling capacitor or capacitor. The typical recommended value for the high frequency decoupling capacitor is 2.2 µF or higher. A high-quality ceramic type X5R or X7R with sufficiency voltage rating is recommended. The voltage rating must be greater than the maximum input voltage. To compensate the derating of ceramic capacitors, TI recommends a voltage rating of twice the maximum input voltage. For this design, one 2.2-µF, X7R dielectric capacitor rated for 100 V is used for the input decoupling capacitor. The equivalent series resistance (ESR) is approximately 10 m Ω, and the current rating is 1 A. Include a capacitor with a value of 0.1 µF for high-frequency filtering and place it as close as possible to the device pins.

9.2.2.8 Bootstrap Capacitor

Every LMR51610 design requires a bootstrap capacitor, C BOOT. The recommended bootstrap capacitor is 0.1 µF and rated at 16 V or higher. The bootstrap capacitor is located between the SW pin and the CB pin. The bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature stability.

9.2.2.9 Undervoltage Lockout Set-Point

The system undervoltage lockout (UVLO) is adjusted using the external voltage divider network of R ENT and RENB. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. Equation 13 can be used to determine the VIN UVLO level. V IN _ RISING = V E N H × R EBT + R E N B R EN B (13) The EN rising threshold (VENH) for LMR51610 is set to be 1.23 V (typical). Choose a value of 200 k Ω for RENB to minimize input current from the supply. If the desired V IN UVLO level is at 6.0 V, then the value of R ENT can be calculated using Equation 14: www.ti.com LMR51610 SLUSEY1 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LMR51610

R ENT = V IN _ RISING V ENH − 1 × R EN B (14) The above equation yields a value of 775.6 k Ω, a standard value of 768 k Ω is selected. The resulting falling UVLO threshold, equal to 5.3 V, can be calculated by Equation 15 where EN hysteresis voltage, VEN_HYS, is 0.13 V (typical). V IN _ F ALLIN G = V ENH − V ENH _ H Y S × R EBT + R EN B R EN B (15)

9.2.2.10 Replacing Non Sync Converter

The LMR516xx can also be used to replace asynchronous converters, which need a rectifying diode in the application circuit. The design works fine with or without a rectifying diode connected to the switch node of the LMR516xx as shown in Figure 9-2. CB SW Lout 33µH CBOOT 0.1 µF FB VIN VIN 24 V COUT 22 µF EN CIN 2.2 µF GND VOUT 5 V RFBT 118 k RFBB 22.1 k Design works with or without rectifying diode Figure 9-2. Replacing Non Sync Converter LMR51610 SLUSEY1 – JUNE 2023 www.ti.com ADVANCE INFORMATION

20 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: LMR51610

9.2.3 Application Curves

Unless otherwise specified the following conditions apply: V IN = 24 V, V OUT = 5 V, f SW = 400 kHz, L = 33 µH, COUT = 22 µF, TA = 25°C. IL[500mA/div] Vsw[10V/div] Vout(AC)[20mV/div] Time[8ms/div] Figure 9-3. Ripple at No Load IL[500mA/div] Vsw[10V/div] Vout(AC)[10mV/div] Time[4us/div] Figure 9-4. Ripple at Full Load IL[500mA/div] Vout[2V/div] Time[800us/div] Vin[10V/div] Figure 9-5. Start-Up by VIN IL[500mA/div] Vout[2V/div] Time[800us/div] Ven[2V/div] Figure 9-6. Start-Up by EN IL[500mA/div] Time[800us/div] Vout(AC)[200mV/div] Figure 9-7. Load Transient (0.25 A – 0.75 A) IL[500mA/div] Time[400us/div] Vout(AC)[500mV/div] Figure 9-8. Load Transient (0 A – 1 A) www.ti.com LMR51610 SLUSEY1 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LMR51610

IL[500mA/div] Vout[2V/div] Time[200ms/div] Figure 9-9. Short Protection and Recovery

9.3 Power Supply Recommendations

The LMR516xx is designed to operate from an input voltage supply range between 4.0 V and 65 V. This input supply must be well-regulated and able to withstand maximum input current and maintain a stable voltage. The resistance of the input supply rail must be low enough that an input current transient does not cause a high enough drop at the LMR516xx supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply is located more than a few inches from the LMR516xx additional bulk capacitance can be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 10-µF or 22-µF electrolytic capacitor is a typical choice.

9.4 Layout

9.4.1 Layout Guidelines

Layout is a critical portion of good power supply design. The following guidelines help users design a PCB with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.

• Place the input bypass capacitor CIN as close as possible to the VIN and GND pins. Grounding for both the input and output capacitors must consist of localized top side planes that connect to the GND pin.
• Minimize trace length to the FB pin net. Both feedback resistors, RFBT and RFBB, must be located close to the FB pin. If VOUT accuracy at the load is important, make sure VOUT sense is made at the load. Route VOUT sense path away from noisy nodes and preferably through a layer on the other side of a shielded layer.
• Use ground plane in one of the middle layers as noise shielding and heat dissipation path if possible.
• Make VIN, VOUT, and ground bus connections as wide as possible. This action reduces any voltage drops on the input or output paths of the converter and maximizes efficiency.
• Provide adequate device heat-sinking. GND, VIN, and SW pins provide the main heat dissipation path, make the GND, VIN, and SW plane area as large as possible. Use an array of heat-sinking vias to connect the top side ground plane to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be connected to inner layer heat-spreading ground planes. Make sure enough copper area is used for heat-sinking to keep the junction temperature below 125°C.

9.4.1.1 Compact Layout for EMI Reduction

Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger area covered by the path of a pulsing current, the more EMI is generated. High frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing a ceramic bypass capacitor or capacitors as close as possible to the VIN and GND pins is the key to EMI reduction. The SW pin connecting to the inductor must be as short as possible, and just wide enough to carry the load current without excessive heating. Short, thick traces or copper pours (shapes) must be used for high current conduction path to minimize parasitic resistance. The output capacitors must be placed close to the V OUT end of the inductor and closely grounded to GND pin. LMR51610 SLUSEY1 – JUNE 2023 www.ti.com ADVANCE INFORMATION

22 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: LMR51610

9.4.1.2 Feedback Resistors

To reduce noise sensitivity of the output voltage feedback path, place the resistor divider close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high impedance node and very sensitive to noise. Placing the resistor divider closer to the FB pin reduces the trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace from V OUT to the resistor divider can be long if short path is not available. If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects for voltage drops along the traces and provides the best output accuracy. The voltage sense trace from the load to the feedback resistor divider must be routed away from the SW node path and the inductor to avoid contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most important when high value resistors are used to set the output voltage. TI recommends to route the voltage sense trace and place the resistor divider on a different layer than the inductor and SW node path, such that there is a ground plane in between the feedback trace and inductor/SW node polygon. This action provides further shielding for the voltage feedback path from EMI noises. www.ti.com LMR51610 SLUSEY1 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LMR51610

9.4.2 Layout Example

VIA (Connect to GND Plane) Output Inductor Output Voltage Set Resistors VIN GND GND VOUT Notes: 1. BOOT capacitor must be close to CB and SW pins. 2. SW area must be small. 3. Output voltage set resistors must be close to FB pin. 4. Input bypass capacitor must be close to VIN and GND pins. 5. Use ground plane to keep a low GND impedance. Figure 9-10. Layout LMR51610 SLUSEY1 – JUNE 2023 www.ti.com ADVANCE INFORMATION

24 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: LMR51610

10 Device and Documentation Support

10.1 Device Support

10.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

10.1.2 Development Support

10.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR516xx device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

10.2 Documentation Support

10.2.1 Related Documentation

For related documentation see the following: Texas Instruments, AN-1149 Layout Guidelines for Switching Power Supplies application report

10.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.5 Trademarks

TI E2E™ is a trademark of Texas Instruments. SIMPLE SWITCHER® is a registered trademark of Texas Instruments. All trademarks are the property of their respective owners.

10.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. www.ti.com LMR51610 SLUSEY1 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: LMR51610

10.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

11.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant LMR51610 SLUSEY1 – JUNE 2023 www.ti.com ADVANCE INFORMATION

26 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: LMR51610

TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMR51610XDBVR SOT-23 DBV 6 3000 210.0 185.0 35.0 LMR51610XFDBVR SOT-23 DBV 6 3000 210.0 185.0 35.0 www.ti.com LMR51610 SLUSEY1 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: LMR51610

www.ti.com PACKAGE OUTLINE C 0.220.08 TYP0.25 3.02.6 2X 0.951.45 MAX 0.150.00 TYP6X 0.500.25

0.60.3 TYP80 TYP

1.9 A3.052.75B1.751.45 (1.1) SOT-23 - 1.45 mm max heightDBV0006ASMALL OUTLINE TRANSISTOR 0.2C A B 3 452INDEX AREAPIN 16 GAGE PLANESEATING PLANE 0.1 C SCALE 4.000 LMR51610 SLUSEY1 – JUNE 2023 www.ti.com ADVANCE INFORMATION

28 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: LMR51610

www.ti.com EXAMPLE BOARD LAYOUT 0.07 MAXARROUND0.07 MINARROUND 6X (1.1)6X (0.6) 4214840/C 06/2021 SOT-23 - 1.45 mm max heightDBV0006ASMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE:15X PKG1 3 452 6 SOLDER MASKOPENINGMETAL UNDERSOLDER MASK SOLDER MASKDEFINEDEXPOSED METALMETALSOLDER MASKOPENING NON SOLDER MASKDEFINED(PREFERRED)SOLDER MASK DETAILS EXPOSED METAL www.ti.com LMR51610 SLUSEY1 – JUNE 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: LMR51610

www.ti.com EXAMPLE STENCIL DESIGN (2.6)2X(0.95) 6X (1.1)6X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0006ASMALL OUTLINE TRANSISTOR SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCILSCALE:15X SYMMPKG1 3 452 6 LMR51610 SLUSEY1 – JUNE 2023 www.ti.com ADVANCE INFORMATION

30 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: LMR51610

www.ti.com 23-Jun-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PLMR51610XDBVR ACTIVE SOT-23 DBV 6 3000 TBD Call TI Call TI -40 to 150 Samples PLMR51610XFDBVR ACTIVE SOT-23 DBV 6 3000 TBD Call TI Call TI -40 to 150 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 23-Jun-2023 Addendum-Page 2

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.25 3.0 2.6 2X 0.95

1.45 MAX

0.15

0.00 TYP

6X 0.50 0.25 0.6

0.3 TYP

0 TYP

1.9 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR 4214840/C 06/2021 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side. 4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation. 5. Refernce JEDEC MO-178.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

6X (1.1) 6X (0.6) (2.6) 2X (0.95) (R0.05) TYP 4214840/C 06/2021 SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 2X(0.95) 6X (1.1) 6X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0006A SMALL OUTLINE TRANSISTOR 4214840/C 06/2021 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated