PLMR23615DRRR

Texas Instruments

SIMPLE SWITCHER 36-V, 1.5-A Synchronous Step-Down Converter

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ADVANCE□INFORMATION IOUT (A) Efficiency (%) 1E-5 0.0001 0.001 0.01 0.1 1 10 100 LMR2 VOUT = 5 V VOUT = 3.3 V BOOT SW LC BOOT FB VIN VIN up to 36 V PGND C OUT EN/SYNC C IN VCC AGND VOUT C VCC R FBT R FBB Copyright © 2017, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. LMR23615 SNVSAV8 –JUNE 2017 LMR23615SIMPLESWITCHER®36-V,1.5-ASynchronousStep-DownConverter

1 Features

1• 4-V to 36-V Input Range

1.5-A Continuous Output Current
Integrated Synchronous Rectification
Current-Mode Control with internal compensation
Minimum Switch ON Time: 60 ns
Adjustable Switching Frequency
PFM Mode at Light Load
Frequency Synchronization to External Clock
75-µA Quiescent Current
Soft-Start into a Pre-Biased Load
High-Duty-Cycle Operation Supported
Output Short-Circuit Protection With Hiccup Mode
Thermal Protection
12-Pin WSON Wettable Flanks Package With PowerPAD™

2 Applications

Programmable Logic Controller Power Supply
Multi-Function Printers
HVAC Systems
Industrial Power Supplies
GSM, GPRS Modules for Fleet Management, Smart Grids, and Security space

3 Description

The LMR23615 SIMPLE SWITCHER® is an easy-to- use 36-V, 1.5-A synchronous step-down regulator. With a wide input range from 4 V to 36 V, the device is suitable for various industrial applications for power conditioning from unregulated sources. Peak current mode control is employed to achieve simple control- loop compensation and cycle-by-cycle current limiting. A quiescent current of 75 µA makes the device suitable for battery-powered systems. An ultra- low 2-µA shutdown current can further prolong battery life. Internal loop compensation means that the user is free from the tedious task of loop- compensation design and also minimizes the external components needed. An extended family is available in 2.5-A (LMR23625) and 3-A (LMR23630) load- current options in pin-to-pin compatible packages, allowing simple, optimum PCB layout. A precision enable input allows simplification of regulator control and system power sequencing. Protection features include cycle-by-cycle current limit, hiccup-mode short-circuit protection, and thermal shutdown due to excessive power dissipation. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LMR23615 WSON (12) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic Efficiency vs Load, VIN = 12 V

11.1 Receiving Notification of Documentation Updates 26

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES June 2017 * Initial release

ADVANCE□INFORMATION SW SW BOOT VCC FB RT PGND NC VIN VIN EN/ SYNC AGND PAD LMR23615 www.ti.com SNVSAV8 –JUNE 2017 Product Folder Links: LMR23615 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated

5 Pin Configuration and Functions

12-Pin WSON With Thermal Pad Top View Pin Functions PIN I/O DESCRIPTION NUMBER NAME 1, 2 SW P Switching output of the regulator. Internally connected to both power MOSFETs. Connect to power inductor. 3 BOOT P Boot-strap capacitor connection for high-side driver. Connect a high-quality 100-nF capacitor from BOOT to SW. 4 VCC P Internal bias supply output for bypassing. Connect bypass capacitor from this pin to AGND. Do not connect external loading to this pin. Never short this pin to ground during operation. 5 FB A Feedback input to regulator, connect the feedback resistor divider tap to this pin. 6 RT A Connect a resistor RT from this pin to AGND to program switching frequency. Leave floating for 400-kHz default switching frequency. 7 AGND G Analog ground pin. Ground reference for internal references and logic. Connect to system ground.

8 EN/SYNC A

Enable input to regulator. High=On, Low=Off. Can be connected to VIN. Do not float. Adjust the input under voltage lockout with two resistors. The internal oscillator can be synchronized to an external clock by coupling a positive pulse into this pin through a small coupling capacitor. See Enable/Sync for detail. 9, 10 VIN P Input supply voltage. 11 NC N/A Not for use. Leave this pin floating. 12 PGND G Power ground pin, connected internally to the low side power FET. Connect to system ground, PAD, AGND, ground pins of CIN and COUT. Path to CIN must be as short as possible. 13 PAD G Low impedance connection to AGND. Connect to PGND on PCB. Major heat dissipation path of the die. Must be used for heat sinking to ground plane on PCB.

ADVANCE□INFORMATION LMR23615 SNVSAV8 –JUNE 2017 www.ti.com Product Folder Links: LMR23615 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) In shutdown mode, the VCC to AGND maximum value is 5.25 V.

6 Specifications

6.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of –40°C to 125°C (unless otherwise noted)(1) PARAMETER MIN MAX UNIT Input voltages VIN to PGND –0.3 42 V EN/SYNC to AGND –5.5 42 FB to AGND –0.3 4.5 RT to AGND –0.3 4.5 AGND to PGND –0.3 0.3 Output voltages SW to PGND –1 VIN + 0.3 V SW to PGND less than 10-ns transients –5 42 BOOT to SW –0.3 5.5 VCC to AGND –0.3 4.5(2) TJ Junction temperature –40 150 °C Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM)(1) ±2500 V Charged-device model (CDM)(2) ±1000 (1) Recommended Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see Electrical Characteristics.

6.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40 °C to 125 °C (unless otherwise noted)(1) MIN MAX UNIT Input voltage VIN 4 36 VEN/SYNC –5 36 FB –0.3 1.2 Output voltage VOUT 1 28 V Output current IOUT 0 1.5 A Temperature Operating junction temperature, TJ –40 125 °C

ADVANCE□INFORMATION LMR23615 www.ti.com SNVSAV8 –JUNE 2017 Product Folder Links: LMR23615 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) Determine power rating at a specific ambient temperature TA with a maximum junction temperature (TJ) of 125°C (see Recommended Operating Conditions ).

6.4 Thermal Information

THERMAL METRIC(1)(2) LMR23615 UNITDRR (WSON) (12 PINS) RθJA Junction-to-ambient thermal resistance 41.5 °C/W ψJT Junction-to-top characterization parameter 0.3 °C/W ψJB Junction-to-board characterization parameter 16.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 39.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 3.4 °C/W RθJB Junction-to-board thermal resistance 16.3 °C/W

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY (VIN PIN) VIN Operation input voltage 4 36 V VIN_UVLO Undervoltage lockout thresholds Rising threshold 3.3 3.6 3.9 V Falling threshold 3 3.3 3.5 ISHDN Shutdown supply current VEN = 0 V, VIN = 12 V, TJ = –40 °C to 125°C 2 4 μA IQ Operating quiescent current (non- switching) VIN =12 V, VFB = 1.2 V, TJ = –40 °C to 125°C, PFM mode 75 μA ENABLE (EN PIN) VEN_H Enable rising threshold voltage 1.4 1.55 1.7 V VEN_HYS Enable hysteresis voltage 0.4 V VWAKE Wake-up threshold 0.4 V IEN Input leakage current at EN pin VIN = 4 V to 36 V, VEN= 2 V 10 100 nA VIN = 4 V to 36 V, VEN= 36 V 1 μA VOLTAGE REFERENCE (FB PIN) VREF Reference voltage VIN = 4 V to 36 V, TJ = 25 °C 0.985 1 1.015 V VIN = 4 V to 36 V, TJ = –40 °C to 125°C 0.980 1 1.020 ILKG_FB Input leakage current at FB pin VFB= 1 V 10 nA INTERNAL LDO (VCC PIN) VCC Internal LDO output voltage 4.1 V VCC_UVLO VCC undervoltage lockout thresholds Rising threshold 2.8 3.2 3.6 V Falling threshold 2.4 2.8 3.2 CURRENT LIMIT IHS_LIMIT Peak inductor current limit 2.9 3.9 4.9 A ILS_LIMIT Valley inductor current limit 1.9 2.5 3.2 A IL_ZC Zero cross current limit –0.04 A INTEGRATED MOSFETS RDS_ON_HS High-side MOSFET ON- resistance VIN = 12 V, IOUT = 1 A 160 mΩ RDS_ON_LS Low-side MOSFET ON- resistance VIN = 12 V, IOUT = 1 A 95 mΩ

ADVANCE□INFORMATION LMR23615 SNVSAV8 –JUNE 2017 www.ti.com Product Folder Links: LMR23615 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT THERMAL SHUTDOWN TSHDN Thermal shutdown threshold 162 170 178 °C THYS Hysteresis 15 °C (1) Specified by design.

6.6 Timing Characteristics

Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted) MIN NOM MAX UNIT HICCUP MODE NOC(1) Number of cycles that LS current limit is tripped to enter hiccup mode 64 Cycles TOC Hiccup retry delay time 10 ms SOFT START TSS Internal soft-start time. The time of internal reference to increase from 0 V to 1 V 6 ms (1) Ensured by design.

6.7 Switching Characteristics

Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SW (SW PIN) TON_MIN Minimum turnon time 60 90 ns TOFF_MIN (1) Minimum turnoff time 100 ns SYNC (EN/SYNC PIN) fSW_DEFAULT Oscillator default frequency RT pin open circuit 340 400 460 kHz FADJ Minimum adjustable frequency RT = 198 kΩ with 1% accuracy 150 200 250 kHz Maximum adjustable frequency RT = 17.8 kΩ with 1% accuracy 1750 2150 2425 kHz fSYNC SYNC frequency range 200 2200 kHz VSYNC Amplitude of SYNC clock AC signal (measured at SYNC pin) 2.8 5.5 V TSYNC_MIN Minimum sync clock ON and OFF time 100 ns

6.8 Typical Characteristics

Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 1600 kHz, L = 4.7 µH, COUT = 47 µF, TA = 25 °C. Figure 1. Efficiency vs Load Current Figure 2. Efficiency vs Load Current Figure 3. Efficiency vs Load Current Figure 4. Efficiency vs Load Current Figure 5. Load Regulation Figure 6. Line Regulation

ADVANCE□INFORMATION EA REF EN/SYNC SW CBOOT VCC Internal SS OV/UV Detector Oscillator Precision Enable LDO PFM Detector Slope Comp PWM CONTROL LOGIC UVLOTSD Freq Foldback Zero Cross HICCUP Detector VIN Rc Cc PGND FB LS I Sense HS I Sense FB VCC Enable SYNC Detector SYNC Signal SYNC Signal AGND RT Copyright © 2017, Texas Instruments Incorporated LMR23615 www.ti.com SNVSAV8 –JUNE 2017 Product Folder Links: LMR23615 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The LMR23615 SIMPLE SWITCHER® regulator is an easy-to-use synchronous step-down DC-DC converter operating from a 4-V to 36-V supply voltage. It is capable of delivering up to 1.5-A DC load current with good thermal performance in a small solution size. An extended family is available in multiple current options from 1.5 A to 3 A in pin-to-pin compatible packages. The LMR23615 employs constant frequency peak-current-mode control. The device enters PFM mode at light load to achieve high efficiency. The device is internally compensated, which reduces design time, and requires few external components. The switching frequency is adjustable from 200 kHz to 2.2 MHz, leaving the RT pin open for 400-kHz default switching frequency. The LMR23615 is also capable of synchronization to an external clock within the range of 200 kHz to 2.2 MHz. Additional features such as precision enable and internal soft start provide a flexible and easy-to-use solution for a wide range of applications. Protection features include thermal shutdown, VIN and VCC undervoltage lockout, cycle-by-cycle current limit, and hiccup-mode short-circuit protection. The LMR236xx family requires very few external components and has a pinout designed for simple, optimum PCB layout.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Fixed Frequency Peak Current Mode Control

proportional to the input voltage: D = VOUT / VIN. Figure 13. SW Node and Inductor Current Waveforms in condition, the LMR23615 operates in PFM mode to maintain high efficiency.

7.3.2 Adjustable Frequency

switching frequency ( fSW ).

Figure 14. RT vs Frequency Curve Table 1. Typical Frequency Setting RT Resistance

7.3.3 Adjustable Output Voltage

static current goes through a larger RFBT and might be more desirable when light load efficiency is critical. temperature variation of the resistor dividers affect the output voltage regulation. Figure 15. Output Voltage Setting

7.3.4 Enable/Sync

Figure 16. System UVLO by Enable Divider synchronized to an external system clock. Figure 17. Synchronizing to External Clock

Figure 18. Synchronizing in PWM Mode Figure 19. Synchronizing in PFM Mode

7.3.5 VCC, UVLO

ground during operation. Shorting VCC to ground during operation may cause damage to the LMR23615 device.

7.3.6 Minimum ON Time, Minimum OFF Time, and Frequency Foldback at Dropout Conditions

ns in the LMR23615. Minimum OFF time, TOFF_MIN, is the smallest duration that the HS switch can be off. conversion range given a selected switching frequency. lower supply voltage VIN. This leads to a lower effective drop-out voltage. calculated in Equation 5. With frequency foldback, VIN_MIN is lowered by decreased fSW.

Figure 20. Frequency Foldback at Dropout (VOUT = 5 V, fSW = 1600 kHz)

7.3.7 Internal Compensation and CFF

designed such that the loop response is stable over the entire operating frequency and output voltage range. Depending on the output voltage, the compensation loop phase margin can be low with all ceramic capacitors. for optimum transient performance. Figure 21. Feedforward Capacitor for Loop Compensation CFF such that (CFF × RFBT) is unchanged and adjust RFBB such that (RFBT / RFBB) is unchanged. different equivalent series resistance (ESR). Ceramic capacitors have the smallest ESR and need the most CFF.

ADVANCE□INFORMATION IN OUT OUT OUT _MAX LS _LIMIT SW IN V V VI I 2 f L V u u u Z _ESR OUT 1f 2 C ESR Su u LMR23615 www.ti.com SNVSAV8 –JUNE 2017 Product Folder Links: LMR23615 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated (9) The CFF creates a time constant with RFBT that couples in the attenuate output voltage ripple to the FB node. If the CFF value is too large, it can couple too much ripple to the FB and affect VOUT regulation. Therefore, calculate CFF based on output capacitors used in the system. At cold temperatures, the value of CFF might change based on the tolerance of the chosen component. This may reduce its impedance and ease noise coupling on the FB node. To avoid this, more capacitance can be added to the output or the value of CFF can be reduced.

7.3.8 Bootstrap Voltage (BOOT)

The LMR23615 device provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and SW pins provides the gate-drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the high-side MOSFET is off and the low-side switch conducts. The recommended value of the BOOT capacitor is 0.1 μF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16 V or higher for stable performance over temperature and voltage.

7.3.9 Overcurrent and Short-Circuit Protection

The LMR23615 is protected from overcurrent conditions by cycle-by-cycle current limit on both the peak and valley of the inductor current. Hiccup mode is activated if a fault condition persists to prevent overheating. High-side MOSFET overcurrent protection is implemented by the nature of the peak-current-mode control. The HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is compared to the output of the error amplifier (EA) minus slope compensation every switching cycle. See Functional Block Diagram for more details. The peak current of HS switch is limited by a clamped maximum peak current threshold IHS_LIMIT, which is constant. Thus the peak current limit of the high-side switch is not affected by the slope compensation and remains constant over the full duty-cycle range. The current going through LS MOSFET is also sensed and monitored. When the LS switch turns on, the inductor current begins to ramp down. The LS switch does not turn OFF at the end of a switching cycle if its current is above the LS current limit ILS_LIMIT. The LS switch is kept ON so that inductor current keeps ramping down, until the inductor current ramps below the LS current limit ILS_LIMIT. Then the LS switch turns OFF, and the HS switches on, after a dead time. This is somewhat different than the more typical peak-current limit and results in Equation 10 for the maximum load current. (10) If the current of the LS switch is higher than the LS current limit for 64 consecutive cycles, hiccup-current- protection mode is activated. In hiccup mode, the regulator is shut down and kept off for 5 ms, typically, before the LMR23615 tries to start again. If an overcurrent or short-circuit fault condition still exist, hiccup repeats until the fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions, prevents over-heating and potential damage to the device.

7.3.10 Thermal Shutdown

The LMR23615 provides an internal thermal shutdown to protect the device when the junction temperature exceeds 170°C (typical). The device is turned off when thermal shutdown activates. Once the die temperature falls below 155°C (typical), the device reinitiates the power up sequence controlled by the internal soft-start circuitry.

7.4 Device Functional Modes

7.4.1 Shutdown Mode

The EN pin provides electrical on- and off-control for the LMR23615. When VEN is below 1 V (typical), the device is in shutdown mode. The LMR23615 also employs VIN and VCC UVLO protection. If VIN or VCC voltage is below their respective UVLO level, the regulator is turned off.

7.4.2 Active Mode

The LMR23615 is in active mode when VEN is above the precision enable threshold, and VIN and VCC are above their respective UVLO level. The simplest way to enable the LMR23615 is to connect the EN pin to VIN pin. This allows self start-up when the input voltage is in the operating range: 4 V to 36 V. See VCC, UVLO and Enable/Sync for details on setting these operating levels. In active mode, depending on the load current, the LMR23615 will be in one of three modes: 1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the peak-to-peak inductor current ripple. 2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of the peak-to-peak inductor current ripple in CCM operation. 3. Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load.

7.4.3 CCM Mode

CCM operation is employed in the LMR23615 device when the load current is higher than half of the peak-to- peak inductor current. In CCM operation, the frequency of operation is fixed, output voltage ripple is at a minimum in this mode, and the maximum output current of 1.5 A can be supplied by the device.

7.4.4 Light Load Operation

When the load current is lower than half of the peak-to-peak inductor current in CCM, the LMR23615 operate in DCM , also known as diode emulation mode (DEM). In DCM, the LS switch is turned off when the inductor current drops to IL_ZC (–40 mA typical). Both switching losses and conduction losses are reduced in DCM, compared to forced PWM operation at light load. At even lighter current loads, PFM is activated to maintain high efficiency operation. When either the minimum HS switch ON time (tON_MIN ) or the minimum peak inductor current IPEAK_MIN (300 mA typical) is reached, the switching frequency decreasse to maintain regulation. In PFM, switching frequency is decreased by the control loop when load current reduces to maintain output voltage regulation. Switching loss is further reduced in PFM operation due to less frequent switching actions. The external clock synchronizing is not valid when the LMR23615 device enters into PFM mode.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

comprehensive databases of components. See ti.com for more details.

8.2 Typical Applications

output voltage. Figure 22 shows a basic schematic. Figure 22. Application Circuit control loop. Table 2 can be used to simplify the output filter component selection.

(1) High ESR COUT gives enough phase boost and CFF not needed. Table 2. L, COUT, and CFF Typical Values

8.2.1 Design Requirements

parameters listed in Table 3 as the input parameters. Table 3. Design Example Parameters

8.2.2 Detailed Design Procedure

8.2.2.1 Output Voltage Setpoint

the RFBB value is calculated using Equation 11. The formula yields to a value 88.7 kΩ.

8.2.2.2 Switching Frequency

to Enable/Sync for more details. frequency approximate to 1600 kHz.

ADVANCE□INFORMATION IND OUTL OUT _ C SW OUT SW OUT K I iV 8 f C 8 f C u'' u u u u OUT_ESR L IND OUTV i ESR K I ESR' ' u u u IN_MAX OUT OUT MIN OUT IND IN_MAX SW V V VL I K V f u u u OUT IN_MAX OUT L IN_MAX SW V V V i V L f u ' u u LMR23615 www.ti.com SNVSAV8 –JUNE 2017 Product Folder Links: LMR23615 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated

8.2.2.3 Inductor Selection

The most critical parameters for the inductor are the inductance, saturation current, and the rated current. The inductance is based on the desired peak-to-peak ripple current ΔiL. Because the ripple current increases with the input voltage, the maximum input voltage is always used to calculate the minimum inductance LMIN. Use Equation 13 to calculate the minimum value of the output inductor. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current of the device. A reasonable value of KIND would be 20% to 40%. During an instantaneous short or overcurrent operation event, the RMS and peak inductor current can be high. The inductor current rating must be higher than the current limit of the device. (12) (13) In general, it is preferable to choose lower inductance in switching power supplies, because lower inductance usually corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But inductance that is too low can generate too large of an inductor current ripple such that overcurrent protection at the full load could be falsely triggered. It also generates more conduction loss and inductor core loss. Larger inductor current ripple also implies larger output voltage ripple with same output capacitors. With peak-current- mode control, TI does not recommend having an inductor current ripple that is too small. A larger peak-current ripple improves the comparator signal-to-noise ratio. For this design example, choose KIND = 0.4, the minimum inductor value is calculated to be 4.3 µH. Choose the nearest standard 4.7-μH ferrite inductor with a capability of 2-A RMS current and 4-A saturation current.

8.2.2.4 Output Capacitor Selection

Choose the output capacitor(s), COUT with care because it directly affects the steady-state output-voltage ripple, loop stability, and the voltage over/undershoot during load current transients. The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going through the ESR of the output capacitors: (14) The other is caused by the inductor current ripple charging and discharging the output capacitors: where

KIND = Ripple ratio of the inductor ripple current (ΔiL / IOUT) (15) The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the sum of two peaks.

ADVANCE□INFORMATION FF X FBT 1C 4 f R Su u X OUT OUT 8.32f V C u 2 2 OH OL OUT 2 2 OUT OS OUT I I C L V V V ! u OH OL OUT SW US

4 I IC f V

u ! u LMR23615 SNVSAV8 –JUNE 2017 www.ti.com Product Folder Links: LMR23615 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation with presence of large current steps and fast slew rate. When a fast large load increase happens, output capacitors provide the required charge before the inductor current can slew up to the appropriate level. The control loop of the regulator usually needs four or more clock cycles to respond to the output voltage droop. The output capacitance must be large enough to supply the current difference for four clock cycles to maintain the output voltage within the specified range. Equation 16 shows the minimum output capacitance needed for specified output undershoot. When a sudden large load decrease happens, the output capacitors absorb energy stored in the inductor, which causes an output voltage overshoot. Equation 17 calculates the minimum capacitance required to keep the voltage overshoot within a specified range. (16) where

IOL = Low level output current during load transient
IOH = High level output current during load transient
VUS = Target output voltage undershoot
VOS = Target output voltage overshoot (17) For this design example, the target output ripple is 50 mV. Presuppose ΔVOUT_ESR = ΔVOUT_C = 50 mV, and choose KIND = 0.4. Equation 14 yields ESR no larger than 83.3 mΩ, and Equation 15 yields COUT no smaller than 0.9 μF. For the target over/undershoot range of this design, VUS = VOS = 5% × VOUT = 250 mV. The COUT can be calculated to be no smaller than 14 μF and 4.1 μF by Equation 16 and Equation 17, respectively. Taking into account the derating factor of ceramic capacitor over temperature and voltage, one 33-μF, 16-V ceramic capacitor with 5-mΩ ESR is selected.

8.2.2.5 Feed-Forward Capacitor

The LMR23615 device is internally compensated. Depending on the VOUT and frequency fSW, if the output capacitor COUT is dominated by low ESR (ceramic types) capacitors, it could result in low phase margin. To improve the phase boost an external feed-forward capacitor CFF can be added in parallel with RFBT. CFF is chosen such that phase margin is boosted at the crossover frequency without CFF. A simple estimation for the crossover frequency (fX) without CFF is shown in Equation 18, assuming COUT has very small ESR, and COUT value is after derating. (18) Equation 19 for CFF was tested: (19) For designs with higher ESR, CFF is not needed when COUT has very high ESR, and CFF calculated from Equation 19 should be reduced with medium ESR. Table 2 can be used as a quick starting point. For the application in this design example, a 18-pF, 50-V, COG capacitor is selected.

8.2.2.6 Input Capacitor Selection

The LMR23615 device requires high-frequency input decoupling capacitor(s) and a bulk input capacitor, depending on the application. The typical recommended value for the high-frequency decoupling capacitor is 4.7 μF to 10 μF. TI recommends a high-quality ceramic capacitor type X5R or X7R with sufficiency voltage rating. To compensate the derating of ceramic capacitors, a voltage rating twice the maximum input voltage is recommended. Additionally, some bulk capacitance can be required, especially if the LMR23615 circuit is not located within approximately 5 cm from the input voltage source. This capacitor is used to provide damping to the voltage spike due to the lead inductance of the cable or the trace. For this design, two 4.7-μF, 50-V, X7R ceramic capacitors are used. A 0.1-μF for high-frequency filtering and place it as close as possible to the device pins.

8.2.2.7 Bootstrap Capacitor Selection

capacitor must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.

8.2.2.8 VCC Capacitor Selection

minimum of 2.2-μF, 16-V, X7R capacitor from this pin to ground.

8.2.2.9 Undervoltage Lockout Setpoint

or brownouts when the input voltage is falling. Equation 20 can be used to determine the VIN UVLO level. Equation 22, where EN hysteresis (VEN_HYS) is 0.4 V (typica).

8.2.3 Application Curves

Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 1600 kHz, L = 4.7 µH, COUT = 47 µF, TA = 25 °C. Figure 23. CCM Mode Figure 24. PFM Mode

9 Power Supply Recommendations

The LMR23615 is designed to operate from an input voltage supply range between 4 V and 36 V. This input supply must be able to withstand the maximum input current and maintain a stable voltage. The resistance of the input supply rail must be low enough that an input current transient does not cause a high enough drop at the LMR23615 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply is located more than a few inches from the LMR23615, additional bulk capacitance may be required in addition to the ceramic input capacitors. The amount of bulk capacitance is not critical, but a 47-μF or 100-μF electrolytic capacitor is a typical choice.

10 Layout

10.1 Layout Guidelines

Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB with the best power-conversion performance, thermal performance, and minimized generation of unwanted EMI. 1. The input bypass capacitor CIN must be placed as close as possible to the VIN and PGND pins. Grounding for both the input and output capacitors should consist of localized top side planes that connect to the PGND pin and PAD. 2. Place bypass capacitors for VCC close to the VCC pin and ground the bypass capacitor to device ground. 3. Minimize trace length to the FB pin net. Both feedback resistors, RFBT and RFBB must be located close to the FB pin. Place CFF directly in parallel with RFBT. If VOUT accuracy at the load is important, ensure that the VOUT sense is made at the load. Route VOUT sense path away from noisy nodes and preferably through a layer on the other side of a shielded layer. 4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path. 5. Have a single point ground connection to the plane. Route the ground connections for the feedback and enable components to the ground plane. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. 6. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the input or output paths of the converter and maximizes efficiency. 7. Provide adequate device heat sinking. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat sinking to keep the junction temperature below 125°C.

10.1.1 Compact Layout for EMI Reduction

Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger area covered by the path of a pulsing current, the more EMI is generated. High frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing ceramic bypass capacitor(s) as close as possible to the VIN and PGND pins is the key to EMI reduction. The SW pin connecting to the inductor must be as short as possible, and just wide enough to carry the load current without excessive heating. Use short, thick traces or copper pours (shapes) for high-current conduction path to minimize parasitic resistance. The output capacitors must be placed close to the VOUT end of the inductor and closely grounded to PGND pin and exposed PAD. Place the bypass capacitors on VCC as close as possible to the pin and closely grounded to PGND and the exposed PAD.

10.1.2 Ground Plane and Thermal Considerations

TI recommends using one of the middle layers as a solid ground plane. Ground plane provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. Connect the AGND and PGND pins to the ground plane using vias right next to the bypass capacitors. PGND pin is connected to the source of the internal LS switch. They must be connected directly to the grounds of the input and output capacitors. The PGND net contains noise at switching frequency and may bounce due to load variations. PGND trace, as well as VIN and SW traces, must be constrained to one side of the ground plane. The other side of the ground plane contains much less noise and should be used for sensitive routes. TI recommends providing adequate device heat sinking by utilizing the PAD of the device as the primary thermal path. Use a minimum 4 by 2 array of 12 mil thermal vias to connect the PAD to the system ground plane heat sink. The vias should be evenly distributed under the PAD. Use as much copper as possible, for system ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top of, 2 oz / 1 oz / 1 oz / 2 oz. Four-layer boards with enough copper thickness provides low current conduction impedance, proper shielding, and lower thermal resistance. The thermal characteristics of the LMR23615 are specified using the parameter RθJA, which characterize the junction temperature of silicon to the ambient temperature in a specific system. Although the value of RθJA is dependent on many variables, it still can be used to approximate the operating junction temperature of the device. To obtain an estimate of the device junction temperature, one may use the following relationship: TJ = PD × RθJA + TA (23) PD = VIN x IIN × (1 – Efficiency) – 1.1 × IOUT 2 × DCR in watt where

TJ = junction temperature in °C
PD = device power dissipation in watt
RθJA = junction-to-ambient thermal resistance of the device in °C/W
TA = ambient temperature in °C
DCR = inductor DC parasitic resistance in ohm (24) The recommended operating junction temperature of the LMR23615 is 125°C. RθJA is highly related to PCB size and layout, as well as environmental factors such as heat sinking and air flow.

10.1.3 Feedback Resistors

To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and CFF close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high impedance node and very sensitive to noise. Placing the resistor divider and CFF closer to the FB pin reduces the trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace from VOUT to the resistor divider can be long if short path is not available. If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects for voltage drops along the traces and provide the best output accuracy. Route the voltage sense trace from the load to the feedback resistor divider away from the SW node path and the inductor to avoid contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most important when high-value resistors are used to set the output voltage. TI recommends routing the voltage sense trace and place the resistor divider on a different layer than the inductor and SW node path, such that there is a ground plane in between the feedback trace and inductor/SW node polygon. This provides further shielding for the voltage feedback path from EMI noises.

10.2 Layout Example

Figure 31. LMR23615 Layout

11 Device and Documentation Support

11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.3 Trademarks

PowerPAD, E2E are trademarks of Texas Instruments. SIMPLE SWITCHER is a registered trademark of Texas Instruments.

11.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 11-Jul-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PLMR23615DRRR ACTIVE SON DRR 12 3000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com PACKAGE OUTLINE C 12X 0.3 0.2 2.5 0.1 2.5 1.7 0.1 10X 0.5

0.8 MAX

12X 0.38 0.28 0.05 0.00 A 3.1 2.9 B 3.1 2.9 (0.2) TYP (0.08) (0.05) WSON - 0.8 mm max heightDRR0012D PLASTIC SMALL OUTLINE - NO LEAD 4223146/B 05/2017 PIN 1 INDEX AREA SEATING PLANE 0.08 C 6 7 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 C THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 4.000 SCALE 30.000 SECTION A-A SECTION A-A TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

12X (0.25) (2.5) (2.87) 10X (0.5) (1.7) ( 0.2) VIA TYP (0.6) (1) 12X (0.53) (R0.05) TYP WSON - 0.8 mm max heightDRR0012D PLASTIC SMALL OUTLINE - NO LEAD 4223146/B 05/2017 SYMM 6 7 LAND PATTERN EXAMPLE SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SYMM SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP 12X (0.25) 12X (0.53) (0.74) (1.15) (2.87) (0.675) 10X (0.5) (0.47) WSON - 0.8 mm max heightDRR0012D PLASTIC SMALL OUTLINE - NO LEAD 4223146/B 05/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 80.1% PRINTED SOLDER COVERAGE BY AREA SCALE:25X SYMM 6 7 METAL TYP SYMM

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Product Information

PLMR23615DRRR specifications and overview.

Summary

SIMPLE SWITCHER 36-V, 1.5-A Synchronous Step-Down Converter

Description

SIMPLE SWITCHER 36-V, 1.5-A Synchronous Step-Down Converter

Source title PLMR23615DRRR Datasheet(PDF) - Texas Instruments

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