PLMP7704HBH/EM

LMP7704-SP TI | Alldatasheet

Document overview

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Technical content

LMP7704-SP Radiation Hardness Assured (RHA), Precision, Low Input Bias, RRIO, Wide Supply Range Amplifiers

1 Features

• QML Class V (QMLV), RHA, SMD 5962-19206
• Radiation performance – RHA up to TID = 100 krad(Si) – ELDRS-free up to TID = 100 krad(Si) – SEL immune to LET = 85 MeV·cm 2/mg – SEE characterized to LET = 85 MeV·cm 2/mg
• Ultra-low input bias current: ±200 fA
• Input offset voltage: ±37 µV
• Unity-gain bandwidth: 2.5 MHz
• Supply voltage range: 2.7 V to 12 V
• Rail-to-rail input and output
• Military temperature range: −55°C to +125°C
• Available in 14-lead CFP with industry-standard quad amp pinout

2 Applications

• Satellite health monitoring and telemetry
• Scientific exploration payload
• Altitude and orbit control system (AOCS)
• Satellite electrical power system (EPS)
• Communications payload
• Radar imaging payload

3 Description

The LMP7704-SP is a precision amplifier with low input bias, low offset voltage, 2.5-MHz gain bandwidth product, and a wide supply voltage. The device is radiation hardened and operates in the military temperature range of −55°C to +125°C. The high dc precision of this amplifier, specifically the low offset voltage of ±37 µV and ultra-low input bias of ±200 fA, make this device an excellent choice for interfacing with precision sensors with high output impedances. This amplifier can be configured for transducer, bridge, strain gauge, and transduce amplification. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) 5962-1920601VXC, Flight Model (QMLV) CFP (14) 9.73 mm x 6.47 mm 5962R1920601VXC, Flight Model (QMLV), RHA to 100-krad LMP7704HBH/EM, Engineering Model(2) (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) These units are intended for engineering evaluation only. They are processed to a noncompliant flow (that is, no burn- in, and so forth) and are tested to a temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing, or flight use. Parts are not warranted for performance over the full MIL specified temperature range of –55°C to +125°C or operating life. For more information about engineering models, see the Texas Instruments Engineering Evaluation Units versus MIL‑PRF‑38535 QML Class V Processing overview. RS Z LOAD R R R R I = (V2 ± V1) RS Typical Application Schematic www.ti.com LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 1 Product Folder Links: LMP7704-SP LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

11.1 Receiving Notification of Documentation Updates..27

12 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Revision * (December 2020) to Revision A (January 2021) Page LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 www.ti.com ADVANCE INFORMATION

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5 Pin Configuration and Functions

Figure 5-1. HBH Package, 14-Pin CFP, Top View Table 5-1. Pin Functions PIN I/O DESCRIPTION NAME NO. IN A+ 3 I Noninverting input for amplifier A IN A– 2 I Inverting input for amplifier A IN B+ 5 I Noninverting input for amplifier B IN B– 6 I Inverting input for amplifier B IN C+ 10 I Noninverting input for amplifier C IN C– 9 I Inverting input for amplifier C IN D+ 12 I Noninverting input for amplifier D IN D– 13 I Inverting input for amplifier D OUT A 1 O Output for amplifier A OUT B 7 O Output for amplifier B OUT C 8 O Output for amplifier C OUT D 14 O Output for amplifier D V+ 4 P Positive supply V– 11 P Negative supply LID — — The metal lid is internally connected to V– www.ti.com LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LMP7704-SP

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VS Supply voltage, VS = (V+) – (V–) 13.2 V Voltage Common-mode (V–) – 0.3 (V+) + 0.3 V Differential (V+) – (V–) + 0.3 Current ±10 mA Output short circuit(2) Continuous Continuous TA Operating temperature –55 150 °C TJ Junction temperature 150 °C TSTG Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VS Supply voltage, VS = (V+) – (V–) 2.7 12 V TA Specified temperature –55 125 °C

6.4 Thermal Information

THERMAL METRIC(1) LMP7704-SP UNITHBH (CFP)

14 PINS

RθJA Junction-to-ambient thermal resistance 37.5 ºC/W RθJC(top) Junction-to-case(top) thermal resistance 20.6 ºC/W RθJB Junction-to-board thermal resistance 21.3 ºC/W ψJT Junction-to-top characterization parameter 12.9 ºC/W ψJB Junction-to-board characterization parameter 21.0 ºC/W RθJC(bot) Junction-to-case(bottom) thermal resistance 10.8 N/A (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 www.ti.com ADVANCE INFORMATION

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6.5 Electrical Characteristics: VS = 5 V

at TA = +25°C, VS = (V+) – (V–) = 5 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage ±32 TBD µV TA = –55°C to +125°C TBD dVOS/dT Input offset voltage drift TA = –55°C to +125°C ±1 ±5 µV/°C PSRR Power-supply rejection ratio 2.7 V < VS < 12 V 86 100 dB TA = –55°C to +125°C 82 dB INPUT BIAS CURRENT IB Input bias current ±0.2 TBD pA TA = –55°C to +125°C TBD pA IOS Input offset current ±40 fA NOISE en Input voltage noise density f = 1 kHz 9 nV/√Hz in Input current noise density f = 100 kHz 1 fA/√Hz INPUT VOLTAGE VCM Common-mode voltage range TA = –55°C to +125°C (V–) – 0.2 (V+) + 0.2 V CMRR Common-mode rejection ratio (V–) < VCM < (V+) 86 130 dB TA = –55°C to +125°C 81 OPEN-LOOP GAIN AOL Open-loop voltage gain (V–) + 0.3 V < VOUT < (V+) – 0.3 V, RL = 2 kΩ 100 119 dB TA = –55°C to +125°C 94 (V–) + 0.2 V < VOUT < (V+) – 0.2 V, RL = 10 kΩ 100 130 TA = –55°C to +125°C 96 FREQUENCY RESPONSE GBW Gain bandwidth TBD 2.5 MHz SR Slew rate G = 1, 4-V step 10% to 90% rising 1 V/µs THD+N Total harmonic distortion + noise G = 1, f = 1 kHz, RL = 10 kΩ 0.02% www.ti.com LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LMP7704-SP

6.5 Electrical Characteristics: VS = 5 V (continued)

at TA = +25°C, VS = (V+) – (V–) = 5 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT VO Voltage output swing from rail Positive rail RL = 2 kΩ to VS / 2 60 120 mV RL = 2 kΩ to VS / 2, TA = –55°C to +125°C 200 RL = 10 kΩ to VS / 2 40 60 RL = 10 kΩ to VS / 2, TA = –55°C to +125°C 120 Negative rail RL = 2 kΩ to VS / 2 50 120 RL = 2 kΩ to VS / 2, TA = –55°C to +125°C 190 RL = 10 kΩ to VS / 2 30 50 RL = 10 kΩ to VS / 2, TA = –55°C to +125°C 100 ISC Short-circuit current VOUT = VS / 2, VIN = ±100 mV +66 / –76 mA POWER SUPPLY IQ Total quiescent current IO = 0 A 2.9 3.7 mA TA = –55°C to +125°C 4.6 LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 www.ti.com ADVANCE INFORMATION

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6.6 Electrical Characteristics: VS = 10 V

at TA = +25°C, VS = (V+) – (V–) = 10 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage ±37 TBD µV TA = –55°C to +125°C TBD dVOS/dT Input offset voltage drift TA = –55°C to +125°C ±1 ±5 µV/°C PSRR Power-supply rejection ratio 2.7 V < VS < 12 V 86 100 dB TA = –55°C to +125°C 82 dB INPUT BIAS CURRENT IB Input bias current ±0.2 TBD pA TA = –55°C to +125°C TBD pA IOS Input offset current ±40 fA NOISE en Input voltage noise density f = 1 kHz 9 nV/√Hz in Input current noise density f = 100 kHz 1 fA/√Hz INPUT VOLTAGE VCM Common-mode voltage range (V–) – 0.2 (V+) + 0.2 V CMRR Common-mode rejection ratio (V–) < VCM < (V+) 90 130 dB TA = –55°C to +125°C 86 OPEN-LOOP GAIN AOL Open-loop voltage gain (V–) + 0.3 V < VOUT < (V+) – 0.3 V, RL = 2 kΩ 100 121 dB TA = –55°C to +125°C 94 (V–) + 0.2 V < VOUT < (V+) – 0.2 V, RL = 10 kΩ 100 134 TA = –55°C to +125°C 97 FREQUENCY RESPONSE GBW Gain bandwidth TBD 2.5 TBD MHz SR Slew rate G = 1, 9-V step 10% to 90% rising 1.1 V/µs THD+N Total harmonic distortion + noise G = 1, f = 1 kHz, RL = 10 kΩ 0.02% www.ti.com LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LMP7704-SP

6.6 Electrical Characteristics: VS = 10 V (continued)

at TA = +25°C, VS = (V+) – (V–) = 10 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT VO Voltage output swing from rail Positive rail RL = 2 kΩ to VS / 2 60 120 mV RL = 2 kΩ to VS / 2, TA = –55°C to +125°C 200 RL = 10 kΩ to VS / 2 40 60 RL = 10 kΩ to VS / 2, TA = –55°C to +125°C 120 Negative rail RL = 2 kΩ to VS / 2 50 120 RL = 2 kΩ to VS / 2, TA = –55°C to +125°C 190 RL = 10 kΩ to VS / 2 30 50 RL = 10 kΩ to VS / 2, TA = –55°C to +125°C 100 ISC Short-circuit current VOUT = VS / 2, VIN = ±100 mV +86 / –84 mA POWER SUPPLY IQ Total quiescent current IO = 0 A 3.2 4.2 mA TA = –55°C to +125°C 5 LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 www.ti.com ADVANCE INFORMATION

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6.7 Typical Characteristics

TA = 25°C, VCM = VS/2, RL > 10 kΩ (unless otherwise noted) -200 -100 0 100 200 PERCENTAGE (%) OFFSET VOLTAGE (PV) VS = 3V TA = 25°C Figure 6-1. Figure 1. Offset Voltage Distribution TCVOS (PV/°C) -3 -2 -1 0 1 2 3 PERCENTAGE (%) VS = 3V -40°C dTAd125°C Figure 6-2. TCVOS Distribution -200 -100 0 100 200 PERCENTAGE (%) OFFSET VOLTAGE (PV) VS = 5V TA = 25°C Figure 6-3. Offset Voltage Distribution TCVOS (PV/°C) -3 -2 -1 0 1 2 3 PERCENTAGE (%) VS = 5V -40°C dTAd125°C Figure 6-4. TCVOS Distribution -200 -100 0 100 200 PERCENTAGE (%) OFFSET VOLTAGE (PV) VS = 10V TA = 25°C Figure 6-5. Offset Voltage Distribution TCVOS (PV/°C) -3 -2 -1 0 1 2 3 PERCENTAGE (%) VS = 10V -40°C dTAd125°C Figure 6-6. TCVOS Distribution www.ti.com LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LMP7704-SP

6.7 Typical Characteristics (continued)

TA = 25°C, VCM = VS/2, RL > 10 kΩ (unless otherwise noted) -40 -20 0 20 40 60 80 100 120125 -200 -150 -100 -50 200 OFFSET VOLTAGE ( PV) TEMPERATURE (°C) 100 150 VS = 3V VS = 5V VS = 10V Figure 6-7. Offset Voltage vs Temperature 10 1k 1M FREQUENCY (Hz) -140 -100 -60 CMRR (dB) 100k10k100 -20 -80 -120 -40 VS = 5V VS = 3V VS = 10V Figure 6-8. CMRR vs Frequency 2 4 6 8 10 12 -200 -150 -100 -50 100 150 200 OFFSET VOLTAGE ( PV) SUPPLY VOLTAGE (V) -40°C 25°C 125°C Figure 6-9. Offset Voltage vs Supply Voltage VCM (V) -200 -150 -100 -50 100 150 200 OFFSET VOLTAGE ( PV) VS = 3V 25°C 125°C -40°C Figure 6-10. Offset Voltage vs VCM -1 0 1 2 3 4 5 6 -200 -150 -100 -50 100 150 200 OFFSET VOLTAGE ( PV) VCM (V) VS = 5V -40°C 25°C 125°C Figure 6-11. Offset Voltage vs VCM -1 0 1 2 7 8 9 10 11 VCM (V) -200 -150 -100 -50 100 150 200 OFFSET VOLTAGE ( PV) 3 4 5 6 -40°C 125°C 25°C VS = 10V Figure 6-12. Offset Voltage vs VCM LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 www.ti.com ADVANCE INFORMATION

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TA = 25°C, VCM = VS/2, RL > 10 kΩ (unless otherwise noted) 0 0.5 1 1.5 2 2.5 3 VCM (V) -200 -100 100 200 IBIAS (fA) VS = 3V -40°C 25°C Figure 6-13. Input Bias Current vs VCM 0 1 2 3 VCM (V) -300 -200 200 300 IBIAS (pA) VS = 3V 0.5 1.5 2.5 100 -100 85°C 125°C Figure 6-14. Input Bias Current vs VCM 0 1 2 3 4 5 -300 -200 -100 100 200 300 IBIAS (fA) VCM (V) VS = 5V -40°C 25°C Figure 6-15. Input Bias Current vs VCM 0 1 2 3 VCM (V) -300 -200 200 300 IBIAS (pA) 100 -100 85°C 125°C 4 5 VS = 5V Figure 6-16. Input Bias Current vs VCM 0 2 4 6 8 10 -500 -250 250 500 IBIAS (fA) VCM (V) VS = 10V -40°C 25°C Figure 6-17. Input Bias Current vs VCM 0 2 4 6 8 10 -300 -200 -100 100 200 300 IBIAS (pA) VCM (V) VS = 10V 85°C 125°C Figure 6-18. Input Bias Current vs VCM www.ti.com LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LMP7704-SP

TA = 25°C, VCM = VS/2, RL > 10 kΩ (unless otherwise noted) 10 1k 1M FREQUENCY (Hz) 120 PSRR (dB) 100k10k100 100 -PSRR +PSRR VS = 10V VS = 5V VS = 3V VS = 10V VS = 5V VS = 3V Figure 6-19. PSRR vs Frequency 2 4 6 8 10 12 0.2 0.4 0.6 0.8 1.2 SUPPLY CURRENT (mA) SUPPLY VOLTAGE (V) 125°C -40°C 25°C Figure 6-20. Supply Current vs Supply Voltage (Per Channel) 2 4 6 8 10 12 100 120 ISINK (mA) SUPPLY VOLTAGE (V) 125°C -40°C 25°C Figure 6-21. Sinking Current vs Supply Voltage 2 4 6 8 10 12 100 120 ISOURCE (mA) SUPPLY VOLTAGE (V) 125°C -40°C 25°C Figure 6-22. Sourcing Current vs Supply Voltage 0 20 40 60 80 100 (V+) -2 (V+) -1 VOUT FROM RAIL (V) OUTPUT CURRENT (mA) | | VS = 3V, 5V, 10V Figure 6-23. Output Voltage vs Output Current 2 4 6 8 10 12 0.5 0.6 0.7 0.8 0.9 1.1 1.2 1.3 1.4 1.5 SLEW RATE (V/ Ps) SUPPLY VOLTAGE (V) FALLING EDGE RISING EDGE AV = +1 VIN = 2 VPP RL = 10 k: CL = 10 pF Figure 6-24. Slew Rate vs Supply Voltage LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 www.ti.com ADVANCE INFORMATION

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TA = 25°C, VCM = VS/2, RL > 10 kΩ (unless otherwise noted) 100 100 10k 1M 100M FREQUENCY (Hz) -60 -20 GAIN (dB) 10M100k1k -40 GAIN PHASE VS = 5V CL = 20 pF RL = 10 k: 225 -135 -45 180 135 -90 PHASE (°) 125°C -40°C 25°C 125°C -40°C 25°C Figure 6-25. Open-Loop Frequency Response 100 100 10k 1M 100M FREQUENCY (Hz) -60 -20 GAIN (dB) 10M100k1k -40 GAIN PHASE VS = 10V CL = 20 pF VS = 3V CL = 100 pF VS = 3V, 5V, 10V CL = 20 pF, 50 pF, 100 pF RL = 10 k: 225 -135 -45 180 135 -90 PHASE (°) Figure 6-26. Open-Loop Frequency Response 500 mV/DIV

10 Ps/DIV

VS = 5V f = 10 kHz AV = +1 VIN = 2 VPP RL = 10 k: CL = 10 pF Figure 6-27. Large Signal Step Response 20 mV/DIV VS = 5V f = 10 kHz AV = +1 VIN = 100 mVPP RL = 10 k: CL = 10 pF Figure 6-28. Small Signal Step Response 1V/DIV VS = 5V f = 10 kHz AV = +10 VIN = 400 mVPP RL = 10 k: CL = 10 pF Figure 6-29. Large Signal Step Response 200 mV/DIV VS = 5V f = 10 kHz AV = +10 VIN = 100 mVPP RL = 10 k: CL = 10 pF Figure 6-30. Small Signal Step Response www.ti.com LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LMP7704-SP

TA = 25°C, VCM = VS/2, RL > 10 kΩ (unless otherwise noted) 1 100 100k FREQUENCY (Hz) 120 10k1k10 100 VS = 3V VS = 5V VS = 10VINPUT REFERRED VOLTAGE NOISE (nV/ Hz) Figure 6-31. Input Voltage Noise vs Frequency 500 400 300 200 100 0 100 110 120 130 140 150 OPEN LOOP GAIN (dB) OUTPUT SWING FROM RAIL (mV) RL = 2 k: RL = 10 k: VS = 3V VS = 10V VS = 5V Figure 6-32. Open Loop Gain vs Output Voltage Swing 2 4 6 8 10 120 VOUT FROM RAIL (mV) SUPPLY VOLTAGE (V) 125°C 25°C -40°C RL = 10 k: Figure 6-33. Output Swing High vs Supply Voltage 2 4 6 8 10 12 VOUT FROM RAIL (mV) SUPPLY VOLTAGE (V) 125°C 25°C -40°C RL = 10 k: Figure 6-34. Output Swing Low vs Supply Voltage 2 4 6 8 10 12 100 VOUT FROM RAIL (mV) SUPPLY VOLTAGE (V) 125°C 25°C -40°C RL = 2 k: Figure 6-35. Output Swing High vs Supply Voltage 2 4 6 8 10 12 100 VOUT FROM RAIL (mV) SUPPLY VOLTAGE (V) 125°C 25°C -40°C RL = 2 k: Figure 6-36. Output Swing Low vs Supply Voltage LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 www.ti.com ADVANCE INFORMATION

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TA = 25°C, VCM = VS/2, RL > 10 kΩ (unless otherwise noted) 10 100 1k 10k 100k FREQUENCY (Hz) 0.001 0.01 0.1 THD+N (%) AV = +1 AV = +10 VS = 5V VO = 4.5 VPP RL = 100 k: Figure 6-37. THD+N vs Frequency 0.001 0.01 0.1 1 10 VOUT (V) 0.001 0.01 0.1 THD+N (%) AV = +1 AV = +10 VS = 5V f = 1 kHz RL = 100 k: Figure 6-38. THD+N vs Output Voltage 100 1k 10k 100k 1M FREQUENCY (Hz) 100 120 140 CROSSTALK REJECTION (dB) VS = 3V VS = 5V VS = 12V Figure 6-39. Crosstalk Rejection Ratio vs Frequency (LMP7702/LMP7704) www.ti.com LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LMP7704-SP

7 Detailed Description

7.1 Overview

The LMP7704-SP is a radiation-hardened, quad, low offset voltage, rail-to-rail input and output precision amplifier with a CMOS input stage and wide supply voltage range of 2.7 V to 12 V. The LMP7704-SP has a very low input bias current of only ±200 fA at room temperature. The wide supply voltage range of 2.7 V to 12 V over the extensive temperature range of −55°C to +125°C makes the LMP7704-SP excellent choices for low-voltage precision applications with extensive temperature requirements. The LMP7704-SP have only ±37 μV of typical input-referred offset voltage. This minimal offset voltage allows more accurate signal detection and amplification in precision applications. The low input bias current of only ±200 fA along with the low input-referred voltage noise of 9 nV/ √Hz gives the LMP7704-SP superiority for use in sensor applications. Lower levels of noise from the LMP7704-SP mean better signal fidelity and a higher signal-to-noise ratio.

7.2 Functional Block Diagram

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7.3 Feature Description

7.3.1 Radiation Hardened Performance

Total Ionizing Dose (TID) —The LMP7704-SP is a radiation-hardness-assured (RHA) QML class V (QMLV) product, and as such it has a total ionizing dose (TID) level specified in the Device Information table on the front page. Testing and qualification of these products is done on a wafer level according to MIL-STD-883, Test Method 1019. Radiation lot acceptance testing (RLAT) is performed at the 30-krad, 50-krad, and 100-krad TID levels. Group E TID RLAT data are available with lot shipments as part of the QCI summary reports; for information on finding QCI summary reports, see QML Flow, Its Importance, and Obtaining Lot Information. Neutron Displacement Damage (NDD)—The LMP7704-SP was irradiated up to 1 × 10 12 n/cm2. A sample size of 15 units was exposed to radiation testing per MILSTD-883, Method 1017 for Neutron Irradiation. Single-Event Effects (SEE)—One-time SEE characterization was performed according to EIA/JEDEC standard, EIA/JEDEC57 to linear energy transfer (LET) = 85 MeV ⋅cm2/mg. During testing, no single-event latch-up (SEL) was observed.

7.3.2 Engineering Model (Devices With /EM Suffix)

Engineering evaluation or engineering model (EM) devices are available for order and are identified by the /EM in the orderable device name (see the Ordering Information table on the front page of the data sheet). These devices meet the performance specifications of the data sheet at room temperature only and have not received the full space production flow or testing. Engineering samples may be QCI rejects that failed tests that would not impact the performance at room temperature, such as radiation or reliability testing.

7.3.3 Capacitive Load

The LMP7704-SP can each be connected as a non-inverting unity gain follower. This configuration is the most sensitive to capacitive loading. The combination of a capacitive load placed on the output of an amplifier along with the amplifier's output impedance creates a phase lag which in turn reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the response will be either underdamped or it will oscillate. To drive heavier capacitive loads, an isolation resistor, RISO, in Figure 7-1 should be used. By using this isolation resistor, the capacitive load is isolated from the amplifier's output, and hence, the pole caused by C L is no longer in the feedback loop. The larger the value of R ISO, the more stable the output voltage will be. If values of R ISO are sufficiently large, the feedback loop will be stable, independent of the value of C L. However, larger values of RISO result in reduced output swing and reduced output current drive. Figure 7-1. Isolating Capacitive Load www.ti.com LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LMP7704-SP

7.3.4 Input Capacitance

CMOS input stages inherently have low input bias current and higher input-referred voltage noise. The LMP7704-SP enhances this performance by having the low input bias current of only ±200 fA, as well as, a very low input referred voltage noise of 9 nV/ √Hz. To achieve these specifications, a larger input stage has been used. This larger input stage increases the input capacitance of the LMP7704-SP. The typical value of this input capacitance, CIN, for the LMP7704-SP is 25 pF. The input capacitance interacts with other impedances, such as gain and feedback resistors, which are seen on the inputs of the amplifier, to form a pole. This pole has little or no effect on the output of the amplifier at low frequencies and dc conditions, but plays a bigger role as the frequency increases. At higher frequencies, the presence of this pole decreases phase margin and also causes gain peaking. To compensate for the input capacitance, care must be taken in choosing the feedback resistors. In addition to being selective in picking values for the feedback resistor, a capacitor can be added to the feedback path to increase stability. The dc gain of the circuit shown in Figure 7-2 is simply –R2/R1. CIN VOUT VIN VOUT VIN AV = - = - CF Figure 7-2. Compensating for Input Capacitance For the time being, ignore CF. The ac gain of the circuit in Figure 7-2 can be calculated as follows: -R2/R1 1 + s + s2 CIN R2¨ §VOUT VIN (s) = A0 R1 R1 + R2 (1) This equation is rearranged to find the location of the two poles: + ¨ 2CIN P1,2 = 1 r 1

4 A0CIN

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As shown in Equation 2, as values of R 1 and R2 are increased, the magnitude of the poles is reduced, which in turn decreases the bandwidth of the amplifier. Whenever possible, best practice is to choose smaller feedback resistors. Figure 7-3 shows the effect of the feedback resistor on the bandwidth of the LMP7704-SP. 1k 10k 100k 1M 10M FREQUENCY (Hz) -10 NORMALIZED GAIN (dB) VS = 5V CF = 0 pF AV = -1 R1 = R2 = 100 k: R1 = R2 = 30 k: R1 = R2 = 10 k: R1 = R2 = 1 k: Figure 7-3. Closed-Loop Gain vs Frequency Equation 2 has two poles. In most cases, it is the presence of pairs of poles that causes gain peaking. To eliminate this effect, the poles should be placed in Butterworth position, because poles in Butterworth position do not cause gain peaking. To achieve a Butterworth pair, the quantity under the square root in Equation 2 should be set to equal −1. Using this fact and the relation between R 1 and R2, R2 = −AV R1, the optimum value for R 1 can be found. This is shown in Equation 3. If R1 is chosen to be larger than this optimum value, gain peaking will occur. (1 - AV)2 2A0AVCIN <R1 (3) www.ti.com LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LMP7704-SP

In Figure 7-2, CF is added to compensate for input capacitance and to increase stability. Additionally, CF reduces or eliminates the gain peaking that can be caused by having a larger feedback resistor. Figure 7-4 shows how CF reduces gain peaking. 1k 10k 100k 1M 10M FREQUENCY (Hz) -10 NORMALIZED GAIN (dB)VS = 5V R1 = R2 = 100 k: AV = -1 CF = 5 pF CF = 3 pF CF = 1 pF CF = 0 pF Figure 7-4. Closed-Loop Gain vs Frequency With Compensation

7.3.5 Diodes Between the Inputs

The LMP7704-SP have a set of anti-parallel diodes between the input pins, as shown in Figure 7-5 . These diodes are present to protect the input stage of the amplifier. At the same time, they limit the amount of differential input voltage that is allowed on the input pins. A differential signal larger than one diode voltage drop might damage the diodes. The differential signal between the inputs needs to be limited to ±300 mV or the input current needs to be limited to ±10 mA. ESD R1 IN+ ESD ESD IN- ESD V- V- Figure 7-5. Input of LMP7704-SP LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 www.ti.com ADVANCE INFORMATION

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7.4 Device Functional Modes

7.4.1 Precision Current Source

The LMP7704-SP can each be used as a precision current source in many different applications. Figure 7-6 shows a typical precision current source. This circuit implements a precision voltage controlled current source. Amplifier A1 is a differential amplifier that uses the voltage drop across RS as the feedback signal. Amplifier A2 is a buffer that eliminates the error current from the load side of the R S resistor that would flow in the feedback resistor if it were connected to the load side of the R S resistor. In general, the circuit is stable as long as the closed loop bandwidth of amplifier A2 is greater then the closed loop bandwidth of amplifier A1. If A1 and A2 are the same type of amplifiers, then the feedback around A1 will reduce its bandwidth compared to A2. RS Z LOAD R R R R I = (V2 ± V1) RS Figure 7-6. Precision Current Source The equation for output current can be derived as shown in Equation 4. V2R R + R (V0 ± IRS)R V1R V 0R + = + R + R R + R R + R (4) Solving for the current I results in the Equation 5. I = V2 ± V1 RS (5) www.ti.com LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LMP7704-SP

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Low Input Voltage Noise

The LMP7704-SP have the very low input voltage noise of 9 nV/ √Hz. This input voltage noise can be further reduced by placing N amplifiers in parallel as shown in Figure 8-1. The total voltage noise on the output of this circuit is divided by the square root of the number of amplifiers used in this parallel combination. This is because each individual amplifier acts as an independent noise source, and the average noise of independent sources is the quadrature sum of the independent sources divided by the number of sources. For N identical amplifiers, this means: REDUCED INPUT VOLTAGE NOISE = en1+en2+ 2 2 +enN N N Nen = N N en = 1 en N (6) Figure 8-1 shows a schematic of this input voltage noise reduction circuit. Typical resistor values are: RG = 10 Ω, RF = 1 kΩ, and RO = 1 kΩ. VOUT RO RG VIN RF RO RG RF RO RG RF RO RG RF Figure 8-1. Noise Reduction Circuit LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 www.ti.com ADVANCE INFORMATION

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8.1.2 Total Noise Contribution

The LMP7704-SP have very low input bias current, very low input current noise, and very low input voltage noise. As a result, these amplifiers are excellent choices for circuits with high impedance sensor applications. Figure 8-2 shows the typical input noise of the LMP7704-SP as a function of source resistance where:

• e n denotes the input referred voltage noise.
• e i is the voltage drop across source resistance due to input referred current noise or ei = RS * in.
• e t shows the thermal noise of the source resistance.
• e ni shows the total noise on the input, where: eni = e n +2 ei +2 et The input current noise of the LMP7704-SP is so low that this noise does not become the dominant factor in the total noise unless the source resistance exceeds 300 MΩ, which is an unrealistically high value. As is evident in Figure 8-2, at lower RS values, total noise is dominated by the amplifier input voltage noise. After RS is larger than a few kilo-ohms, then the dominant noise factor becomes the thermal noise of R S. As mentioned previously, the current noise will not be the dominant noise factor for any practical application. 10 1k 100k 10M RS (:) 0.1 1000 1M10k100 100 VOLTAGE NOISE DENSITY (nV/ Hz) eni en ei et Figure 8-2. Total Input Noise www.ti.com LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LMP7704-SP

8.2 Typical Application

-5 V 5 V 10 M GND Vin = ±0.1 V GND Vout Signal Source with high output impedance Figure 8-3. LMP7704-SP Configured for 25x Gain With High Signal Source Impedance

8.2.1 Design Requirements

Many precision, analog sensors such as temperature or pressure (bridge) sensors, require a high precision amplifier with low input bias to condition the signal before the analog-to-digital converter. The LMP7704-SP is an excellent amplifier choice for a voltage gain stage thanks to its low offset voltage, offset voltage drift and ultra- low input bias current.

8.2.2 Detailed Design Procedure

Many sensors have high source impedances that may range up to 10 M Ω. The output signal of sensors often needs to be amplified or otherwise conditioned by means of an amplifier. The input bias current of this amplifier can load the sensor output and cause a voltage drop across the source resistance, as shown in Figure 8-4 , where VIN+ = VS – IBIAS * RS. SENSOR RS IB VIN+ VS + Figure 8-4. Offset Error Due to IBIAS The last term, I BIAS * R S, shows the voltage drop across R S. To prevent errors introduced to the system due to this voltage, an op amp with very low input bias current must be used with high impedance sensors. An amplifier with low input bias also has low input current noise, further improving the accuracy of systems with high source resistance. Figure 8-3 shows one channel of the LMP7704-SP configured for a gain of 10. A high source impedance is placed between the input signal and the noninverting input of the amplifier to represent the output impedance of the sensor. With the ultra-low input bias current of the LMP7704-SP, even with a signal source that has high output impedance the system output maintains very good linearity to the ideal output voltage (that is, the output of an ideal amplifier in the same configuration) as shown in Figure 8-6. LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 www.ti.com ADVANCE INFORMATION

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8.2.3 Application Curves

Figure 8-5. LMP7704-SP Output Voltage vs Input Voltage Figure 8-6. LMP7704-SP Ideal Output Voltage vs Input Voltage www.ti.com LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: LMP7704-SP

9 Power Supply Recommendations

For proper operation, the power supplies must be decoupled. For supply decoupling, TI recommends placing 10-nF to 1-µF capacitors as close as possible to the operational-amplifier power supply pins. For single supply configurations, place a capacitor between the V + and V– supply pins. For dual supply configurations, place one capacitor between V + and ground, and place a second capacitor between V – and ground. Bypass capacitors must have a low ESR of less than 0.1 Ω.

10 Layout

10.1 Layout Guidelines

Take care to minimize the loop area formed by the bypass capacitor connection between supply pins and ground. A ground plane underneath the device is recommended; any bypass components to ground should have a nearby via to the ground plane. The optimum bypass capacitor placement is closest to the corresponding supply pin. Use of thicker traces from the bypass capacitors to the corresponding supply pins will lower the power supply inductance and provide a more stable power supply. The feedback components should be placed as close to the device as possible to minimize stray parasitics.

10.2 Layout Example

+3.3V +3.3V +3.3V GND +3.3V +3.3V +3.3V GND 1 VOUT GND +3.3V +3.3V+3.3V VOUT GND GND GND VOUT VOUT V–GND GND Figure 10-1. LMP7704-SP Example Layout for a Single Channel LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 www.ti.com ADVANCE INFORMATION

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11 Device and Documentation Support

11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

11.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: LMP7704-SP

www.ti.com PACKAGE OUTLINE C

25 MAX

6X 1.27 2X 7.62 8X 0.482

0.3822.874 MAX

0.18 0.10

0.43 MAX

0.18 MIN

A 6.65 6.30 B 9.91 9.55 (4.45) (6.09) (9.27) 4X (R0.76) 4225069/A 06/2019 NOTES: CFP - 2.874 mm max heightHBH0014A CERAMIC FLATPACK 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermetically sealed with a metal lid. The lid is not connected to any lead. 4. The leads are gold plated.

0.2 C A B

SCALE 1.000 7 8 PIN 1 ID LMP7704-SP SNOSDB6A – DECEMBER 2020 – REVISED JANUARY 2021 www.ti.com ADVANCE INFORMATION

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www.ti.com 28-Jan-2021 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LMP7704HBH/EM PREVIEW CFP HBH 14 1 RoHS (In work) & Green (In work) Call TI Call TI -55 to 125 PLMP7704HBH/EM ACTIVE CFP HBH 14 1 RoHS (In work) & Green (In work) Call TI Call TI -55 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 28-Jan-2021 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LMP7704-SP :

• Catalog: LMP7704 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product

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