PLMKDB1108RKPT

LMKDB1120 TI | Alldatasheet

Document overview

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Technical content

LMKDB1120 and LMKDB1108 Ultra-Low Jitter PCIe Gen 1 to Gen 6 LP-HCSL Clock Buffers

1 Features

• LP-HCSL clock buffer that support: – PCIe Gen 1 to Gen 6 – CC (Common Clock) and IR (Independent Reference) PCIe architectures – Input clock with or without SSC
• DB2000QL compliant: – All devices meet DB2000QL specifications – LMKDB1120 is pin-compatible to DB2000QL
• Extremely low additive jitter: – 31 fs maximum 12 kHz to 20 MHz RMS additive jitter at 156.25 MHz – 13 fs maximum additive jitter for PCIe Gen 4 – 5 fs maximum additive jitter for PCIe Gen 5 – 3 fs maximum additive jitter for PCIe Gen 6
• Fail-safe input
• Flexible power-up sequence
• Automatic output disable
• Individual output enable
• SBI (Side Band Interface) for high-speed output enable or disable
• LOS (Loss of Signal) input detection
• 85 Ω or 100 Ω output impedance
• 1.8 V / 3.3 V ± 10% power supply
• –40°C to 105°C ambient temperature

2 Applications

• High Performance Computing
• Server Motherboard
• NIC/SmartNIC
• Hardware Accelerator

3 Description

LMKDB1120 and LMKDB1108 are extremely-low-jitter LP-HCSL buffers that support PCIe Gen 1 to Gen 6 and are DB2000QL compliant. The devices provide flexible power-up sequence, fail-safe inputs, individual output enable and disable pins, loss of input signal (LOS) detection and automatic output disable features, as well as excellent power supply noise rejection performance. Both 1.8-V and 3.3-V supply voltages are supported. For LMKDB1120, 1.8-V power supply saves 250 mW power compared to 3.3 V.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) LMKDB1120 NPP (TLGA, 80) 6 mm × 6 mm LMKDB1108 RKP (VQFN, 40) 5 mm × 5 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. PCIe Clock Source #1 LMKDB family PCIe Clock Buffer or MUX SMBus Control OE# Control PCIe PHYPCIe PHYPCIe PHYPCIe PHY LP-HCSL PCIe PHYPCIe PHYPCIe Device Side-Band Interface Control Interface PCIe Clock Source #2 MUX only, optional Typical Application ADVANCE INFORMATION LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

10.2 Receiving Notification of Documentation Updates..29

14 Mechanical, Packaging, and Orderable

LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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4 Device Comparison

Table 4-1. Device Comparison PART NUMBER DESCRIPTION LMKDB1120Z85 1 input, 20 outputs, 85-Ω output impedance LMKDB1120Z100 1 input, 20 outputs, 100-Ω output impedance LMKDB1108Z85 1 input, 8 outputs, 85-Ω output impedance LMKDB1108Z100 1 input, 8 outputs, 100-Ω output impedance LMKDB1104Z85(1) 1 input, 4 outputs, 85-Ω output impedance LMKDB1104Z100(1) 1 input, 4 outputs, 100-Ω output impedance LMKDB1204(1) 2 inputs, 4 outputs, 85-Ω or 100-Ω output impedance LMKDB1202(1) 2 inputs, 4 outputs, 85-Ω or 100-Ω output impedance LMKDB1102(1) 2 inputs, 4 outputs, 85-Ω or 100-Ω output impedance (1) This device is in preview only. www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LMKDB1120 LMKDB1108

5 Pin Configuration and Functions

CLK17_P CLK17_N CLK18_P CLK18_N CLK19_P CLK19_N CLKIN_P CLKIN_N CLK0_P CLK0_N CLK1_P CLK1_N CLK16_N CLK16_P CLK15_N CLK15_P CLK14_N CLK14_P CLK13_N CLK13_P CLK12_N CLK12_P CLK11_N VDD vOE13#/NC vOE12# VDD CLK11_P SBI_OUT/ NC vOE17#/NC vSBI_EN NC NC VDD vOE0#/NC vOE1#/NC VDD CLK2_P CLK10_N CLK10_P vOE9# CLK9_N CLK9_P CLK8_N CLK8_P CLK7_N CLK7_P vOE16#/NC CLK6_N ^vSADR0 _tri vOE15#/NC VDD vOE14#/NC ^vSADR1 _tri vOE2#/NC SMB_DATA SMB_CLK vOE3#/NC NC vOE5#/ SBI_IN vOE4#/NC vOE6#/ SBI_CLK VDD CLK2_N CLK3_P CLK3_N vPWRGD/ PWRDN# CLK4_P CLK4_N CLK5_P CLK5_N CLK6_P vOE11# vOE18#/NC vOE10#/ SHFT_LD# NC LOS#/NC vOE8# vOE19#/NC vOE7# DAP (GND) A B C D E F G H J K L M A B C D E F G H J K L M 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 Figure 5-1. LMKDB1120 6 x 6 mm 80-pin TLGA Table 5-1. LMKDB1120 Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. CLKIN_P G1 I Differential clock input CLKIN_N H1 I Differential clock input CLK0_P J1 O LP-HCSL differential clock output 0. No connect if unused. CLK0_N K1 O LP-HCSL differential clock output 0. No connect if unused. CLK1_P L1 O LP-HCSL differential clock output 1. No connect if unused. LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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Table 5-1. LMKDB1120 Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. CLK1_N M1 O LP-HCSL differential clock output 1. No connect if unused. CLK2_P M2 O LP-HCSL differential clock output 2. No connect if unused. CLK2_N M3 O LP-HCSL differential clock output 2. No connect if unused. CLK3_P M4 O LP-HCSL differential clock output 3. No connect if unused. CLK3_N M5 O LP-HCSL differential clock output 3. No connect if unused. CLK4_P M7 O LP-HCSL differential clock output 4. No connect if unused. CLK4_N M8 O LP-HCSL differential clock output 4. No connect if unused. CLK5_P M9 O LP-HCSL differential clock output 5. No connect if unused. CLK5_N M10 O LP-HCSL differential clock output 5. No connect if unused. CLK6_P M11 O LP-HCSL differential clock output 6. No connect if unused. CLK6_N M12 O LP-HCSL differential clock output 6. No connect if unused. CLK7_P L12 O LP-HCSL differential clock output 7. No connect if unused. CLK7_N K12 O LP-HCSL differential clock output 7. No connect if unused. CLK8_P J12 O LP-HCSL differential clock output 8. No connect if unused. CLK8_N H12 O LP-HCSL differential clock output 8. No connect if unused. CLK9_P G12 O LP-HCSL differential clock output 9. No connect if unused. CLK9_N F12 O LP-HCSL differential clock output 9. No connect if unused. CLK10_P D12 O LP-HCSL differential clock output 10. No connect if unused. CLK10_N C12 O LP-HCSL differential clock output 10. No connect if unused. CLK11_P B12 O LP-HCSL differential clock output 11. No connect if unused. CLK11_N A12 O LP-HCSL differential clock output 11. No connect if unused. CLK12_P A11 O LP-HCSL differential clock output 12. No connect if unused. CLK12_N A10 O LP-HCSL differential clock output 12. No connect if unused. CLK13_P A9 O LP-HCSL differential clock output 13. No connect if unused. CLK13_N A8 O LP-HCSL differential clock output 13. No connect if unused. CLK14_P A7 O LP-HCSL differential clock output 14. No connect if unused. CLK14_N A6 O LP-HCSL differential clock output 14. No connect if unused. CLK15_P A5, O LP-HCSL differential clock output15. No connect if unused. CLK15_N A4 O LP-HCSL differential clock output15. No connect if unused. CLK16_P A3 O LP-HCSL differential clock output 16. No connect if unused. CLK16_N A2 O LP-HCSL differential clock output 16. No connect if unused. CLK17_P A1 O LP-HCSL differential clock output 17. No connect if unused. CLK17_N B1 O LP-HCSL differential clock output 17. No connect if unused. CLK18_P C1 O LP-HCSL differential clock output 18. No connect if unused. CLK18_N D1 O LP-HCSL differential clock output 18. No connect if unused. CLK19_P E1 O LP-HCSL differential clock output 19. No connect if unused. CLK19_P F1 O LP-HCSL differential clock output 19. No connect if unused. vPWRGD/PWRDN# M6 I Power Good/Power Down Active Low. Multifunctional input pin. Internal pull-down resistor.

• On the first low-to-high transition, functions as Power Good pin which starts up the device
• On the subsequent low/high transitions, functions as Power Down Active Low pin which controls the device to enter or exit power-down mode. – Low = power-down mode – High = normal operation mode www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LMKDB1120 LMKDB1108

Table 5-1. LMKDB1120 Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. vOE0#/NC J2, I Output Enable for CLK0 Active Low/No Connect. Internal pull-down resistor. This pin can be left no connect to match with DB2000QL pinout. vOE1#/NC K2 I Output Enable for CLK1 Active Low/No Connect. Internal pull-down resistor. This pin can be left no connect to match with DB2000QL pinout. vOE2#/NC L3 I Output Enable for CLK2 Active Low/No Connect. Internal pull-down resistor. This pin can be left no connect to match with DB2000QL pinout. vOE3#/NC L6 I Output Enable for CLK3 Active Low/No Connect. Internal pull-down resistor. This pin can be left no connect to match with DB2000QL pinout. vOE4#/NC L9 I Output Enable for CLK4 Active Low/No Connect. Internal pull-down resistor. This pin can be left no connect to match with DB2000QL pinout. vOE5#/SBI_IN L8 I Output Enable for CLK5 Active Low/SBI Data Input. Internal pull-down resistor. Functionality is decided by the state of pin E2 (SBI_EN) at power-up. No connect if unused. vOE6#/SBI_CLK L10 I Output Enable for CLK6 Active Low/SBI Clock. Internal pull-down resistor. Functionality is decided by the state of pin E2 (SBI_EN) at power-up. Internal pull-down resistor. No connect if unused. vOE7# K11 I Output Enable for CLK7 Active Low. Internal pull-down resistor. No connect if unused. vOE8# H11 I Output Enable for CLK8 Active Low. Internal pull-down resistor. No connect if unused. vOE9# E12 I Output Enable for CLK9 Active Low. Internal pull-down resistor. No connect if unused. vOE10#/SHFT_LD# E11 I Output Enable for CLK10 Active Low/SBI Shift Register Load Active Low. Internal pull- down resistor. Functionality is decided by the state of pin E2 (SBI_EN) at power-up. No connect if unused. vOE11# C11 I Output Enable for CLK11 Active Low. Internal pull-down resistor. No connect if unused. vOE12# B10 I Output Enable for CLK12 Active Low. Internal pull-down resistor. No connect if unused. vOE13#/NC B9 I Output Enable for CLK13 Active Low/No Connect. Internal pull-down resistor. This pin can be left no connect to match with DB2000QL pinout. vOE14#/NC B7 I Output Enable for CLK14 Active Low/No Connect. Internal pull-down resistor. This pin can be left no connect to match with DB2000QL pinout. vOE15#/NC B5 I Output Enable for CLK15 Active Low/No Connect. Internal pull-down resistor. This pin can be left no connect to match with DB2000QL pinout. vOE16#/NC B3 I Output Enable for CLK16 Active Low/No Connect. Internal pull-down resistor. This pin can be left no connect to match with DB2000QL pinout. vOE17#/NC D2 I Output Enable for CLK17 Active Low/No Connect. Internal pull-down resistor. This pin can be left no connect to match with DB2000QL pinout. vOE18#/NC D11 I Output Enable for CLK18 Active Low/No Connect. Internal pull-down resistor. This pin can be left no connect to match with DB2000QL pinout. vOE19#/NC J11 I Output Enable for CLK19 Active Low/No Connect. Internal pull-down resistor. This pin can be left no connect to match with DB2000QL pinout. vSBI_EN E2 I SBI Enable. Internal pull-down resistor. Do not change the state of this pin after power-up.

• Low at power-up = SBI interface disabled. Pin L8, L10, E11 function as OE pins.
• High at power-up = SBI interface enabled. Pin L8, L10, E11 function as SBI interface pins. SMBus and other OE pins remain functional. SBI_OUT/NC C2 O SBI Data Output/No Connect. This pin can be left no connect to match with DB2000QL pinout. SMB_DATA L4 I/O SMBus Data. Requires external pull-up resistor. No connect if unused. SMB_CLK L5 I SMBus Clock. Requires external pull-up resistor. No connect if unused. ^vSADR1_tri B8 I SMBus Address 3-level input pins. These two pins select 1 out of 9 SMBus addresses. ^vSADR0_tri B4 I SMBus Address 3-level input pins. These two pins select 1 out of 9 SMBus addresses. LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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Table 5-1. LMKDB1120 Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. LOS#/NC G11 O Loss of Input Clock Signal Active Low/No Connect. Open drain. Requires external pull-up resistor. This pin can be left no connect to match with DB2000QL pinout.

• Low = Invalid input clock.
• High = Valid input clock. VDD B2, B6, B11, H2, L2, L11 P Power supply. DAP GND G Ground. NC F2, F11, G2, L7 NC No Connect (1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LMKDB1120 LMKDB1108

DAP (GND) 1 30 10 21 4011 3120 LOS# ^SLEWRATE_SEL ^vSADR1_tri SMB_DATA CLKIN_P CLKIN_N VDD ^vSADR0_tri SMB_CLK VDD vOE4#/SBI_CLK CLK4_N CLK4_P VDD CLK2_N CLK2_P CLK3_P vOE3# CLK3_N vOE2# vOE7# CLK7_N CLK7_P CLK6_N vOE5# CLK5_N vOE6#/SBI_OUT VDD CLK6_P CLK5_P vSBI_EN vPWRGD/PWRDN# VDD CLK0_P CLK1_N vOE1#/SBI_IN CLK1_P vOE0#/SHFT_LD# CLK0_N VDD Figure 5-2. LMKDB1108 5 x 5 mm 40-pin QFN Table 5-2. LMKDB1108 Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. CLKIN_P 8 I Differential clock input CLKIN_N 9 I Differential clock input CLK0_P 15 O LP-HCSL differential clock output 0 CLK0_N 16 O LP-HCSL differential clock output 0 CLK1_P 17 O LP-HCSL differential clock output 1 CLK1_N 18 O LP-HCSL differential clock output 1 CLK2_P 22 O LP-HCSL differential clock output 2 CLK2_N 23 O LP-HCSL differential clock output 2 CLK3_P 24 O LP-HCSL differential clock output 3 CLK3_N 25 O LP-HCSL differential clock output 3 CLK4_P 28 O LP-HCSL differential clock output 4 CLK4_N 29 O LP-HCSL differential clock output 4 CLK5_P 31 O LP-HCSL differential clock output 5 CLK5_N 32 O LP-HCSL differential clock output 5 CLK6_P 35 O LP-HCSL differential clock output 6 CLK6_N 36 O LP-HCSL differential clock output 6 CLK7_P 38 O LP-HCSL differential clock output 7 CLK7_N 39 O LP-HCSL differential clock output 7 LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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Table 5-2. LMKDB1108 Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. vPWRGD/PWRDN# 12 I Power Good/Power Down Active Low. Multifunctional input pin. Internal pull-down resistor.

• On the first low-to-high transition, functions as Power Good pin which starts up the device
• On the subsequent low/high transitions, functions as Power Down Active Low pin which controls the device to enter or exit power-down mode. – Low = power-down mode – High = normal operation mode vOE0#/SHFT_LD# 14 I Output Enable for CLK0 Active Low/SBI Shift Register Load Active Low. Internal pull-down resistor. Functionality is decided by the state of pin 11 (SBI_EN) at power-up. No connect if unused. vOE1#/SBI_IN 19 I Output Enable for CLK1 Active Low/SBI Data Input. Internal pull-down resistor. Functionality is decided by the state of pin 11 (SBI_EN) at power-up. No connect if unused. vOE2# 21 I Output Enable for CLK2 Active Low. Internal pull-down resistor. No connect if unused. vOE3# 27 I Output Enable for CLK3 Active Low. Internal pull-down resistor. No connect if unused. vOE4#/SBI_CLK 30 I Output Enable for CLK4 Active Low/SBI Clock. Internal pull-down resistor. Functionality is decided by the state of pin 11 (SBI_EN) at power-up. Internal pull-down resistor. No connect if unused. vOE5# 33 I Output Enable for CLK5 Active Low. Internal pull-down resistor. No connect if unused. vOE6#/SBI_OUT 34 I or O Output Enable for CLK6 Active Low/SBI Data Output. Functionality is decided by the state of pin 11 (SBI_EN) at power-up. Internal pull-down resistor. No connect if unused. vOE7# 40 I Output Enable for CLK7 Active Low. Internal pull-down resistor. No connect if unused. vSBI_EN 11 I SBI Enable. Internal pull-down resistor. Do not change the state of this pin after power-up.
• Low at power-up = SBI interface disabled. Pin 14, 19, 30, 34 function as OE pins.
• High at power-up = SBI interface enabled. Pin 14, 19, 30, 34 function as SBI interface pins. SMBus and other OE pins remain functional. SMB_DATA 5 I/O SMBus Data. Requires external pull-up resistor. No connect if unused. SMB_CLK 6 I SMBus Clock. Requires external pull-up resistor. No connect if unused. ^vSADR1_tri 3 I SMBus Address 3-level input pins. These two pins select 1 out of 9 SMBus addresses. ^vSADR1_tri 4 I SMBus Address 3-level input pins. These two pins select 1 out of 9 SMBus addresses. ^SLEWRATE_SEL 2 I Slew Rate Select for output clocks. Internal pull-up resistor.
• Low = Slow slew rate
• High = Fast slew rate LOS# 1 O Loss of Input Clock Signal Active Low. Open drain. Requires external pull-up resistor.
• Low = Invalid input clock.
• High = Valid input clock. VDD 7 P Power supply. VDD 10 P Power supply. VDD 13 P Power supply. VDD 20 P Power supply. VDD 26 P Power supply. VDD 37 P Power supply. DAP GND G Ground. (1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LMKDB1120 LMKDB1108

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDDx Supply voltage on any VDD pin –0.3 3.63 V VIN Input voltage on CLKIN_x and digital input pins –0.3 3.63 V IOUT Output current - continuous (CLKOUT) 30 mA Output current - continuous (SMB_DATA, SBI_OUT) 25 mA Output current - surge (CLKOUT) 60 mA Output current - surge (SMB_DATA, SBI_OUT) 50 mA TJ Junction temperature 125 ℃ TS Storage temperature –65 150 ℃ (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001 (1) ±2000 V Charged-device model (CDM), per ANSI/ESDA/ JEDEC JS-002 (2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT TJ Junction temperature 125 °C TA Ambient temperature –40 105 °C VDD Power supply voltage 2.97 3.6 V 1.71 1.89 V tramp Power ramping time 0.05 5 ms

6.4 Thermal Information

THERMAL METRIC(1) NPP (TLGA) RKP (VQFN) REX (VQFN) REY (VQFN) UNIT

80 PINS 40 PINS 28 PINS 20 PINS

RθJA Junction-to-ambient thermal resistance TBD TBD TBD TBD °C/W RθJC(top) Junction-to-case (top) thermal resistance TBD TBD TBD TBD °C/W RθJB Junction-to-board thermal resistance TBD TBD TBD TBD °C/W ΨJT Junction-to-top characterization parameter TBD TBD TBD TBD °C/W ΨJB Junction-to-board characterization parameter TBD TBD TBD TBD °C/W LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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THERMAL METRIC(1) NPP (TLGA) RKP (VQFN) REX (VQFN) REY (VQFN) UNIT RθJC(bot) Junction-to-case (bottom) thermal resistance TBD TBD TBD TBD °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CLOCK INPUT REQUIREMENTS VIN, cross Clock input crossing point voltage 100 1400 mV DCIN Clock input duty cycle 45 55 % VIN Differential clock input amplitude (half of differential peak-peak voltage) f0 ≤ 300 MHz 200 2000 mV

300 MHz < f0 ≤ 400 MHz 250 2000 mV

dVIN/dt Clock input slew rate Measured from -150 mV to +150 mV on the differential waveform 0.6 V/ns CLOCK OUTPUT CHARACTERISTICS - 100 MHz 85 Ω PCIe VOH,AC Output voltage high DB2000QL AC test load(6) 660 850 mV VOL,AC Output voltage low –150 150 mV Vmax,AC Output max voltage (including overshoot) 660 1150 mV Vmin,AC Output min voltage (including undershoot) –300 150 mV VOH,DC Output voltage high with DC test load DB2000QL DC test load(2) 225 270 mV VOL,DC Output voltage low with DC test load 10 150 mV Vovs,DC Output overshoot voltage with DC test load 75 mV Vuds,DC Output undershoot voltage with DC test load –75 mV Zdiff Differential output impedance Measured at VOL/VOH, VDD = 3.3 V 80.75 85 89.25 Ω Measured at VOL/VOH, VDD = 1.8 V 81 90 Ω Zdiff- crossing Differential output impedance - crossing Measured during transition 68 85 102 Ω dV/dt Output slew rate Measured from -150 mV to +150 mV on the differential waveform. Slew rate control register = 0b00(6) 2.1 2.9 V/ns Measured from -150 mV to +150 mV on the differential waveform. Slew rate control register = 0b01(6) 2.6 3.1 V/ns Measured from -150 mV to +150 mV on the differential waveform. Slew rate control register = 0b10 (default)(6) 3.4 4 V/ns Measured from -150 mV to +150 mV on the differential waveform. Slew rate control register = 0b11(6) 5.9 6.9 V/ns ∆dV/dt Rising edge rate to falling edge rate matching DB2000QL AC test load(6) 20 % DCD Duty cycle distortion Measured on the differential waveform. Input duty cycle = 50%(6) –1 1 % Vcross,AC Absolute crossing point voltage DB2000QL AC test load(6) 250 550 mV Vcross,DC Absolute crossing point voltage DB2000QL DC test load(2) 130 200 mV ∆Vcross,A C Variation of Vcross over all clock edges DB2000QL AC test load(6) 140 mV www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LMKDB1120 LMKDB1108

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ∆Vcross- DC Variation of Vcross over all clock edges DB2000QL DC test load(2) 35 mV |VRB| Absolute value of ring back voltage as defined in PCIe DB2000QL AC test load(6) 100 mV tstable Time before VRB is allowed DB2000QL AC test load(6) 500 ps CLOCK OUTPUT CHARACTERISTICS - 100 MHz 100 Ω PCIe Vmax Output voltage high including overshoot PCIe AC test load(1) 660 1150 mV Vmin Output voltage low including undershoot PCIe AC test load(1) –300 150 mV VOH Output voltage high PCIe AC test load(1) 660 850 mV VOL Output voltage low PCIe AC test load(1) –150 150 mV Zdiff Differential output DC impedance VDD = 3.3 V 95 100 105 Ω VDD = 1.8 V 95 100 105 Ω dV/dt Output slew rate Measured from -150 mV to +150 mV on the differential waveform. Slew rate control register = 0b00(1) 1.9 2.2 V/ns Measured from -150 mV to +150 mV on the differential waveform. Slew rate control register = 0b01(1) 2.3 2.6 V/ns Measured from -150 mV to +150 mV on the differential waveform. Slew rate control register = 0b10 (default)(1) 2.7 3.1 V/ns Measured from -150 mV to +150 mV on the differential waveform. Slew rate control register = 0b11(1) 4.4 4.9 V/ns ∆dV/dt Rising edge rate to falling edge rate matching PCIe AC test load(1) 20 % DCD Duty cycle distortion Measured on the differential waveform. Input duty cycle = 50%(1) –1 1 % Vcross Absolute crossing point voltage PCIe AC test load(1) 250 550 mV ∆Vcross Variation of Vcross over all clock edges PCIe AC test load(1) 140 mV |VRB| Absolute value of ring back voltage as defined in PCIe PCIe AC test load(1) 100 mV tstable Time before VRB is allowed PCIe AC test load(1) 500 ps CLOCK OUTPUT CHARACTERISTICS - non-PCIe VOH Output voltage high Output swing programmed to 800 mV. f0 = 156.25 MHz or 312.5 MHz 680 920 mV VOL Output voltage low –150 150 mV VOH Output voltage high Output swing programmed to 900 mV. f0 = 156.25 MHz or 312.5 MHz 765 1035 mV VOL Output voltage low –150 150 mV tR, tF Rise/fall time on single-ended waveform, 20% to 80% Output swing programmed to 800 mV. Fastest slew rate. f0 = 156.25 MHz or

312.5 MHz

Output swing programmed to 900 mV. Fastest slew rate. f0 = 156.25 MHz or DCD Duty cycle distortion Input duty cycle = 50% –1 1 % SKEW AND DELAY CHARACTERISTICS tskew Output-to-output skew Same bank 50 ps Regardless of banks 50 ps Part-to-part skew 300 ps tPD Input-to-output delay 0.9 ns LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ΔtPD Input-to-output delay variation Single device over temperature and voltage 2 ps/℃ FREQUENCY AND TIMING CHARACTERISTICS f0 Operating frequency Automatic Output Disable functionality is disabled 1 400 MHz Automatic Output Disable functionality is enabled 25 400 MHz tstartup Startup time Cold start. Measured from VDD valid (90% of final VDD) to output clock stable(3). Input clock is provided before VDD is valid. PWRGD_PWRDN# pin is tied to VDD. f0 ≥ 100 MHz 0.4 ms Cold start. Measured from VDD valid (90% of final VDD) to output clock stable(3). Input clock is provided before VDD is valid. PWRGD_PWRDN# pin is tied to VDD. f0 < 100 MHz 0.8 ms tstable Clock stabilization time VDD is stable. Measured from PWRGD assertion(4) to output clock stable. f0 ≥ 100 MHz(3) 0.4 ms VDD is stable. Measured from PWRGD assertion(4) to output clock stable. f0 <

100 MHz(3)

0.8 ms tPD# Powerdown deassertion time Measured from PWRDN# deassertion(4) to output clock stable. f0 ≥ 100 MHz(3) 0.3 ms Measured from PWRDN# deassertion(4) to output clock stable. f0 < 100 MHz(3) 0.5 ms tOE Output enable/disable time Time elapsed from OE assertion/ deassertion(4) to output clock starts/stops 4 10 clk tLOS-assert LOS# assertion time Time elapsed from loss of input clock to LOS# assertion. f0 < 100 MHz 120 ns Time elapsed from loss of input clock to LOS# assertion. f0 ≥ 100 MHz 116 ns tLOS- deassert LOS# deassertion time Time elapsed from return of input clock to LOS# deassertion. f0 < 100 MHz 340 ns Time elapsed from return of input clock to LOS# deassertion. f0 ≥ 100 MHz 94 ns tAOD Automatic output disable time Time elapsed from LOS# assertion to output disable (both outputs are low/ low). f0 < 100 MHz 0.07 ns Time elapsed from LOS# assertion to output disable (both outputs are low/low), f0 ≥ 100 MHz 0.07 ns tAOE Automatic output enable time Time elapsed from LOS# deassertion to output clock stable. f0 < 100 MHz(3) 115 ns Time elapsed from LOS# deassertion to output clock stable, f0 ≥ 100 MHz(3) 22 ns JITTER CHARACTERISTICS www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LMKDB1120 LMKDB1108

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT JPCIe1-CC PCIe Gen 1 CC jitter Only one input has running clock. Input slew rate ≥ 3.5 V/ns. Differential input swing ≥ 1600 mV 450 fs JPCIe2-CC PCIe Gen 2 CC jitter 40 fs JPCIe3-CC PCIe Gen 3 CC jitter 13 fs JPCIe4-CC PCIe Gen 4 CC jitter 13 fs JPCIe5-CC PCIe Gen 5 CC jitter 5 fs JPCIe6-CC PCIe Gen 6 CC jitter 3 fs JPCIe2-IR PCIe Gen 2 IR jitter 35 fs JPCIe3-IR PCIe Gen 3 IR jitter 14.5 fs JPCIe4-IR PCIe Gen 4 IR jitter 14.5 fs JPCIe5-IR PCIe Gen 5 IR jitter 4 fs JPCIe6-IR PCIe Gen 6 IR jitter 3 fs JPCIe1-CC PCIe Gen 1 CC jitter Only one input has running clock. Input slew rate ≥ 1.5 V/ns. Differential input swing ≥ 800 mV 600 fs JPCIe2-CC PCIe Gen 2 CC jitter 55 fs JPCIe3-CC PCIe Gen 3 CC jitter 16 fs JPCIe4-CC PCIe Gen 4 CC jitter 16 fs JPCIe5-CC PCIe Gen 5 CC jitter 6.5 fs JPCIe6-CC PCIe Gen 6 CC jitter 4 fs JPCIe2-IR PCIe Gen 2 IR jitter 45 fs JPCIe3-IR PCIe Gen 3 IR jitter 19 fs JPCIe4-IR PCIe Gen 4 IR jitter 19 fs JPCIe5-IR PCIe Gen 5 IR jitter 5.5 fs JPCIe6-IR PCIe Gen 6 IR jitter 4 fs JDB2000QL DB2000QL filter Input slew rate ≥ 1.5 V/ns. Differential input swing ≥ 800 mV(6) 11.5 fs Input slew rate ≥ 3.5 V/ns. Differential input swing ≥ 1600 mV(6) 9 fs JRMS- additive Additive 12 kHz to 20 MHz RMS jitter f = 100 MHz, slew rate ≥ 3.5 V/ns 38 fs f = 100 MHz, slew rate ≥ 1.5 V/ns 49 fs Additive 12 kHz to 20 MHz RMS jitter f = 156.25 MHz, slew rate ≥ 3.5 V/ns 22 31 fs f = 156.25 MHz, slew rate ≥ 1.5 V/ns 38.5 fs Additive 12 kHz to 70 MHz RMS jitter f = 156.25 MHz, slew rate ≥ 3.5 V/ns 48.5 fs f = 156.25 MHz, slew rate ≥ 1.5 V/ns 60.5 fs Additive 12 kHz to 20 MHz RMS jitter f = 312.5 MHz, slew rate ≥ 3.5 V/ns 28 fs f = 312.5 MHz, slew rate ≥ 1.5 V/ns 40 fs Additive 12 kHz to 70 MHz RMS jitter f = 312.5 MHz, slew rate ≥ 3.5 V/ns 41.5 fs f = 312.5 MHz, slew rate ≥ 1.5 V/ns 58 fs SUPPLY CURRENT CHARACTERISTICS IDD,total LMKDB1104 total supply current All outputs running, f0 = 100 MHz 57.6 mA LMKDB1108 total supply current 87.4 mA LMKDB1120 total supply current 165.9 mA LMKDB1202 total supply current mA LMKDB1204 total supply current mA LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IDD,core LMKDB1104 core supply current Pin PWRGD/PWRDN# = high, all outputs disabled 32 mA LMKDB1108 core supply current 36.2 mA LMKDB1120 core supply current 37.9 mA LMKDB1202 core supply current Pin PWRGD/PWRDN# = high, all outputs disabled, 1 input enabled mA Pin PWRGD/PWRDN# = high, all outputs disabled, 2 inputs enabled mA LMKDB1204 core supply current Pin PWRGD/PWRDN# = high, all outputs disabled, 1 input enabled mA Pin PWRGD/PWRDN# = high, all outputs disabled, 2 inputs enabled mA IDDO Output supply current per output f0 = 100 MHz 6.4 mA f0 = 400 MHz 9.2 mA IPD LMKDB1104/08/20 power down current Pin PWRGD/PWRDN# = low 5.6 mA LMKDB1202/1204 power down current mA PSNR CHARACTERISTICS PSNR Power Supply Noise Rejection, VDD =

3.3 V(5)

10 kHz noise ripple –90 dBc 50 kHz noise ripple –87 dBc 100 kHz noise ripple –88 dBc 500 kHz noise ripple –79 dBc

1 MHz noise ripple –71 dBc

5 MHz noise ripple –55 dBc

10 MHz noise ripple –51 dBc

PSNR Power Supply Noise Rejection, VDD =

1.8 V(5)

10 kHz noise ripple –87 dBc 50 kHz noise ripple –86 dBc 100 kHz noise ripple –84 dBc 500 kHz noise ripple –73 dBc

1 MHz noise ripple –66 dBc

5 MHz noise ripple –52 dBc

10 MHz noise ripple –49 dBc

2-level logic input, VDD = 3.3 V ± 10%

2 VDD +

0.3 V VIL Input voltage low –0.3 0.8 V VIH Input voltage high 3-level logic input, VDD = 3.3 V ± 10%

2.4 VDD +

0.3 V VIM Input voltage mid 1.2 1.8 V VIL Input voltage low –0.3 0.8 V VIH Input voltage high 2-level logic input, VDD = 1.8 V ± 5% V VIL Input voltage low V VIH Input voltage high 3-level logic input, VDD = 1.8 V ± 5% V VIM Input voltage mid V VIL Input voltage low V VOH Output high voltage SBI_OUT, IOH = -2 mA 2.4 VDD + 0.3 V VOL Output low voltage SBI_OUT, IOL = 2 mA 0.4 V www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LMKDB1120 LMKDB1108

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IIN Input leakage current CLKINx_P –40 40 µA CLKINx_N –40 40 µA single-ended inputs with internal pulldown –30 30 µA single-ended inputs without internal pulldown –5 5 µA 3-level logic input –30 30 µA CIN,GPIO GPIO pins input capacitance 4.5 pF COUT,GPI O GPIO pins output capacitance 4.5 pF Rup,down Internal pullup/pulldown resistor for single-ended inputs 120 kΩ SMBUS ELECTRICAL CHARACTERISTICS VIH SMB_CLK, SMB_DATA input high voltage 0.8 × VDD V VIL SMB_CLK, SMB_DATA input low voltage 0.3 × VDD V VHYS Hysteresis of Schmitt Trigger Inputs 0.05 × VDD V VOL SMB_DATA output low voltage IOL = 4 mA 0.4 V ILEAK SMB_CLK, SMB_DATA input leakage –10 10 µA CPIN SMB_CLK, SMB_DATA pin capacitance 10 pF (1) PCIe AC test load (2) DB2000QL DC test load (3) First clock edge is used for timing measurements. Clock outputs are muted until stabilized. (4) For input pins, assertion or deassertion starts when the input voltage reaches the minimum voltage required for a "high" level, or the maximum voltage required for a "low" level (5) All power supply pins are tied together. 0.1 uF capacitor placed close to each power supply pin. Apply 50 mVpp ripple and measure the spur level at the clock output (6) DB2000QL AC test load

6.6 SMBus Timing Requirements

100-kHz CLASS 400-kHz CLASS UNIT MIN MAX MIN MAX fSMB SMBus Operating Frequency 10 100 10 400 kHz fBUF Bus free time between STOP and START condition 4.7 – 1.3 – μs tHD:STA Hold time after (REPEATED) START condition 4.0 – 0.6 – μs tSU:STA REPEATED START condition setup time 4.7 – 0.6 – μs tSU:STO STOP condition setup time 4.0 – 0.6 – μs tHD:DAT Data hold time 0 – 0 – ns tSU:DAT Data setup time 250 – 100 – ns tTIMEOUT Detect clock low timeout 25 35 25 35 ms tLOW Clock low period 4.7 – 1.3 – μs tHIGH Clock high period 4.0 50 0.6 50 μs tLOW:SEXT Cumulative clock low extend time (secondary device) – 25 – 25 ms tLOW:PEXT Cumulative clock low extend time (primary device) – 10 – 10 ms tF Clock/Data Fall Time – 300 – 300 ns tR Clock/Data Rise Time – 1000 – 300 ns LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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100-kHz CLASS 400-kHz CLASS UNIT MIN MAX MIN MAX tSPIKE Noise spike suppression time – – 0 50 ns tPOR Time in which a device must be operational after power-on reset 500 500 ms

6.7 SBI Timing Requirements

tPERIOD Clock period 40 – ns tSETUP SHFT setup to SBI_CLK rising edge 10 – ns tDSU SBI_IN data setup to SBI_CLK rising edge 5 – ns tDHOLD SBI_IN data hold after SBI_CLK rising edge 2 – ns tDOUT SBI_CLK rising edge to SBI_OUT data valid 2 – ns tLD CLK rising edge to LD# falling edge 10 – ns tOE Delay from LD# falling edge to output enable/disable taking effect 4 10 clocks tSLEW SBI_CLK 20% to 80% slew rate 0.7 4 V/ns www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LMKDB1120 LMKDB1108

7 Parameter Measurement Information

ZDiff = 100 ± 10% High impedance differential probe Figure 7-1. PCIe AC Test Load DUT 2 pF 2 pF 25.4 cm Differential PCB trace, ZDiff = 85 High impedance differential probe Figure 7-2. DB2000QL AC Test Load DUT R1 = 47 0.75 V R2 = 147 SMA R1 = 47 0.75 V R2 = 147 SMA 42.5 85 50 Figure 7-3. DB2000QL DC Test Load LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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8 Detailed Description

8.1 Overview

LMKDB clock buffer and clock MUX family distributes LP-HCSL clocks with ultra-low additive jitter.

8.2 Functional Block Diagram

CLK0_P CLK0_N CLKx_P LOS# Input Detection Digital Control (Side Band Interface, SMBus, Glitchless Output Enable/Disable) OE[x:0]# SBI_IN SBI_CLK SHFT_LD# SBI_EN# SADR[1:0]_tri SMB_DATA SMB_CLK ... ... PWRGD/PWRDN# CLKx_N SBI_OUT CLKIN_P CLKIN_N Figure 8-1. LMKDB1120 or LMKDB1108 Block Diagram

8.3 Feature Description

8.3.1 Input Features

8.3.1.1 Running Input Clocks When Device is Powered Off

The device supports running input clocks when power is off. This is different than the fail-safe feature where the input can be pulled to static VDD when device power is off. This is useful if clock inputs are available before power is provided to the clock buffer.

8.3.1.2 Fail-Safe Inputs

All clock input pins and digital input pins support fail-safe. Fail-safe means a pin can be driven to VDD when device power is off, without causing any leakage or reliability problem. For example, an OE# pin can be driven to VDD before device power is up so that the output stays muted until the OE# pin goes low, sometime after power-up.

8.3.1.3 Internal Termination for Clock Inputs

There is an option to enable 50- Ω internal termination for differential clock input. For LP-HCSL input, disable the internal termination. For HCSL input, enable internal termination if external termination is not provided. The internal termination is disabled by default.

8.3.1.4 AC-Coupled or DC-Coupled Clock Inputs

Input clocks can be either AC coupled or DC coupled.

8.3.1.5 Unused Clock Inputs

For MUX devices, unused clock inputs can be left floating. No external termination is required.

8.3.2 Flexible Power Sequence

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8.3.2.1 PWRDN# Assertion and Deassertion

In normal operation mode, PWRDN# is asserted while input clocks are valid. In this case, when PWRDN# pin is sampled low by two consecutive rising edges of input clock, all clock outputs are muted to low/low (OUTx_P = Low, OUTx_N = Low) without a glitch. If PWRDN# is asserted while input is invalid (this is uncommon), then there is no impact. The outputs stay low/low (outputs are automatically parked to low/low once input becomes invalid) and nothing happens. The PWRDN# pin functions normally after the input is valid again.

8.3.2.2 OE# Assertion and Deassertion

OE# pins can be asserted and deasserted at anytime, whether:

• Device power supply is on or off
• PWRGD/PWRDN# pin is pulled high or low
• Clock input is valid or invalid The OE# pins only take effect if all below conditions are met: 1. The clock input is valid 2. The PWRGD/PWRDN# pin is high 3. The device power is up Otherwise outputs are always muted and OE# assertion and deassertion has no impact. If OE# pins become low in any of the below conditions: 1. Input clock is invalid 2. PWRGD/PWRDN# pin is low 3. Device power is off Then when all below conditions are met: 1. The clock input is valid 2. The PWRGD/PWRDN# pin is high 3. The device power is up Outputs are enabled without any glitch (assuming register OE and SBI OE are active).

8.3.2.3 PWRGD Assertion

The first low-to-high transition of the PWRGD pin after device power is on can occur while input clock is running, floating, low/low or pulled to VDD. The power-up sequence only starts if the PWRGD pin is pulled from low to high while input clock is valid. If the PWRGD pin is pulled from low to high while input clock is invalid, then the power-up sequence is not initiated and the outputs stay low/low. When this happens, pulling the PWRGD pin back from high to low has no impact and this low-to-high transition on PWRGD pin is not considered a valid Power Good signal. The device is powered up next time when the PWRGD pin is pulled high while input clock is valid. In other words, there is only one valid Power Good signal for every power cycle.

8.3.2.4 Clock Input and PWRGD/PWRDN# Behaviors When Device Power is Off

Input clocks can be running, floating, low/low or pulled to VDD when device power is off, regardless of PWRGD/ PWRDN# pin states (low, high, low-to-high transition and high-to-low transition)

8.3.3 LOS and OE

8.3.3.1 Additional OE# Pins for LMKDB1120 and Backward Compatibility

The DB2000QL specification only defines 8 OE# pins. In the LMKDB1120, 12 additional OE# pins are added so that each of the 20 outputs has a dedicated OE# pin. This provides additional design flexibility. The LMKDB1120 is backward pin-compatible with DB2000QL because all OE# pins have internal pulldown resistor. When left floating, these additional OE# pins have no impact (OE# pins are active low), because the three types of OE controls follow the AND logic. LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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8.3.3.2 Synchronous OE

Outputs are enabled and disabled synchronously. Synchronous OE means when an output is enabled or disabled, there is no glitch or runt pulse at the output.

8.3.3.3 OE Control

OE (Output Enable) can enable or disable a certain output. Three types of OE controls are supported: OE pin, OE register bit through SMBus, and OE control through SBI. The three controls follow the AND logic. An output is enabled only if all three controls enable that output. If any control disables that output, that output is disabled.

8.3.3.4 Automatic Output Disable

When input clock becomes invalid and LOS# is active, output clocks are muted to low/low (OUTx_P = Low, OUTx_N = Low). Before LOS# is active and after input clock becomes invalid (because LOS detection takes time), output clocks stay at a steady state following the last input state. For example, if the input clock stopped at low/high, then output clocks first stay at low/high, then muted to low/low once LOS# is active.

8.3.3.5 LOS Detection

LOS (Loss Of input Signal) detects whether the clock input is valid or not. When input clock is valid, LOS# register bit = 1 and LOS# pin = high. When input clock is invalid, LOS register bit = 0 and LOS# pin = low. At power-up, the LOS# pin is kept low until input is detected valid. Therefore, the LOS# pin can be used for the timing of OE# insertion and other operations. The LOS# signal is only effective if PWRGD/PWRDN# pin is high. If this pin is low, then LOS# is low regardless of input validness

8.3.4 Output Features

8.3.4.1 Double Termination

For regular PCIe applications, LP-HCSL outputs do not require external termination, but the LMKDB family does support double termination (this is uncommon). In that case, an external 50- Ω termination is placed and the swing is halved

8.3.4.2 Programmable Output Slew Rate

The LMKDB family support programmable output slew rate for each output individually.

8.3.4.3 Accurate Output Impedance

The LMKDB family supports both 100- Ω LP-HCSL and 85- Ω LP-HCSL. The output impedance is accurately trimmed to ±5%. This helps improve impedance matching and clock signal integrity.

8.4 Device Functional Modes

8.4.1 SMBus Mode

In SMBus mode, SMBus registers can be written and read through SMBus pins. Pin SADR1 and SADR0 set the SMBus address. SADR1 SADR0 8-Bit SMBus Address (R/W Bit = 0) Low Low 0xD8 Low Float 0xDA Low High 0xDE Float Low 0xC2 Float Float 0xC4 Float High 0xC6 High Low 0xCA www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LMKDB1120 LMKDB1108

SADR1 SADR0 8-Bit SMBus Address (R/W Bit = 0) High Float 0xCC High High 0xCE

8.4.2 SBI Mode

SBI is used for faster OE control compared to SMBus, especially when the device is just powered up and SMBus controller is not ready. SBI registers can be accessed while PWRGD/PWRDN# pin is low. Enabling SBI mode does not disable SMBus.

8.4.3 Pin Mode

If SMBus and SBI are not needed, the related pins can be left floating. LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The LMKDB devices are a family of ultra-low additive jitter LP-HCSL clock buffers and clock MUX. The device can be controlled through SMBus registers, Side Band Interface, and OE# pins.

9.2 Typical Application

This example shows PCIe and Ethernet clock distribution. Provide multiple copies of PCIe clocks (100 MHz) or Ethernet clocks (156.25 MHz) based on the given source. PCIe Clock Source #1 LMKDB family PCIe Clock Buffer or MUX SMBus Control OE# Control PCIe PHYPCIe PHYPCIe PHYPCIe PHY LP-HCSL PCIe PHYPCIe PHYPCIe Device Side-Band Interface Control Interface PCIe Clock Source #2 MUX only, optional Figure 9-1. Typical Application

9.2.1 Design Requirements

Find two buffers for PCIe clock fan-out and Ethernet clock fan-out separately. Jitter requirements must be met and space must be minimized. Table 9-1. Design Parameters PARAMETER VALUE Number of PCIe clocks 15 Number of 156.25 MHz Ethernet clocks 7 PCIe architecture CC (Common Clock) PCIe reference clock slew rate ≥3.5 V/ns PCIe Gen 5 reference clock jitter 45 fs maximum PCIe Gen 5 total jitter 50 fs maximum 156.25-MHz reference clock slew rate ≥3.5 V/ns 156.25-MHz reference clock jitter (12 kHz to 20 MHz) 90 fs maximum 156.25-MHz total jitter (12 kHz to 20 MHz) 100 fs maximum

9.2.2 Detailed Design Procedure

First of all, calculate the jitter budget for the clock buffer using RMS addition. The maximum allowed additive jitter for the clock buffer is square root of the difference between square of reference clock jitter and square of total clock jitter. www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LMKDB1120 LMKDB1108

The maximum PCIe Gen 5 additive jitter allowed for the buffer is sqrt(50 2 – 45 2) = 21 fs. According to the Electrical Characteristics table, the additive PCIe Gen 5 jitter under Common Clock and ≥3.5 V/ns input slew rate test condition is 13 fs maximum, well below 21 fs requirement. Therefore, the LMKDB1120 (20 outputs) can be used for PCIe Gen 5 clock distribution. Similarly, the maximum 12 kHz to 20 MHz additive jitter allowed at 156.25 MHz is sqrt(100 2 – 90 2) = 43 fs. According to the Electrical Characteristics table, the 12 kHz to 20 MHz additive jitter at 156.25 MHz is 31 fs maximum, well below the 43 fs requirement. Therefore, the LMKDB1108 (8 outputs) can be used for Ethernet clock distribution.

9.2.3 Application Curves

Below are example phase noise plots before and after clock buffer at 156.25 MHz. The LMKDB clock buffer adds 22 fs (typical) jitter from 12 kHz to 20 MHz. Figure 9-2. Reference Clock Phase Noise LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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Figure 9-3. Reference Clock + Buffer Phase Noise

9.3 Power Supply Recommendations

Place a 0.1-μF capacitor close to every power supply pin. All supply pins can be grouped onto one power rail. A Ferrite Bead is recommended for the entire chip. If both inputs are used for a MUX device and the two inputs have different frequencies (including PCIe SSC and PCIe No SSC), then isolate the inputs and corresponding output banks by adding more Ferrite Beads.

9.4 Layout

9.4.1 Layout Guidelines

Use a low-inductance ground connection between the device DAP and the PCB. Match PCB trace impedance with device output impedance (85- Ω or 100- Ω differential impedance). Eliminate stubs and reduce discontinuity on the transmission lines. www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: LMKDB1120 LMKDB1108

9.4.2 Layout Example

Figure 9-4. Layout Example - Top Layer LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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Figure 9-5. Layout Example - GND Layer www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: LMKDB1120 LMKDB1108

100 nF decoupling capacitors must be within 25 mm of pin 100 nF decoupling capacitors must be within 25 mm of pin 100 nF decoupling capacitors must be within 25 mm of pin Figure 9-6. Layout Example - Bottom Layer LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

10.1 Documentation Support

10.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, LMKDB1120 Evaluation Module User's Guide
• Texas Instruments, LMKDB1108 Evaluation Module User's Guide

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

10.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: LMKDB1120 LMKDB1108

11 LMKDB1120 Registers

Table 11-1 lists the memory-mapped registers for the LMKDB1120 registers. All register offset addresses not listed in Table 11-1 should be considered as reserved locations and the register contents should not be modified. Table 11-1. LMKDB1120 Registers Offset Acronym Register Name Section 0h R0 Output Enable Control for CLK16 through CLK19 Section 11.1 1h R1 Output Enable Control for CLK0 through CLK7 Section 11.2 2h R2 Output Enable Control for CLK8 through CLK15 Section 11.3 3h R3 OE Pin Readback for CLK5 through CLK12 Section 11.4 4h R4 ACP Enable Control and SBI_EN Readback Section 11.5 5h R5 Device Info Section 11.6 6h R6 Device Info (cont.) Section 11.7 7h R7 SMBus Byte Counter Section 11.8 8h R8 SBI Mask for CLK0 through CLK7 Section 11.9 9h R9 SBI Mask for CLK8 and CLK15 Section 11.10 Ah R10 SBI Mask for CLK16 and CLK19 Section 11.11 Bh R11 Output Slew Rate Control for CLK0 through CLK7 Section 11.12 Ch R12 Output Slew Rate Control for CLK8 through CLK15 Section 11.13 Dh R13 Output Slew Rate Control for CLK16 through CLK18 Section 11.14 14h R20 Output Amplitude Section 11.15 15h R21 Input Configuration, Save Config in PD, SMB SDATA Monitoring, and LOS Readback Section 11.16 21h R33 SBI Mask Readback for CLK0 through CLK7 Section 11.17 22h R34 SBI Mask Readback for CLK8 through CLK15 Section 11.18 23h R35 SBI Mask Readback for CLK16 through CLK19 Section 11.19 26h R38 Non-clearable SMBUS Write Lock Section 11.20 27h R39 LOS Event Status and Clearable SMBus Write Lock Section 11.21 73h R115 Section 11.22 Complex bit access types are encoded to fit into small table cells. Table 11-2 shows the codes that are used for access types in this section. Table 11-2. LMKDB1120 Access Type Codes Access Type Code Description Read Type R R Read RC R C Read to Clear Write Type W W Write W1C W Write 1 to clear WSC W Write Reset or Default Value -n Value after reset or the default value LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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11.1 R0 Register (Offset = 0h) [Reset = 78h]

R0 is shown in Table 11-3. Return to the Summary Table. Table 11-3. R0 Register Field Descriptions Bit Field Type Reset Description

7 RESERVED R 0h Reserved

6 CLK_EN_19 R/W 1h Output Enable for CLK19

0h = Output Disabled (low/low) 1h = Output Enabled

5 CLK_EN_18 R/W 1h Output Enable for CLK18

0h = Output Disabled (low/low) 1h = Output Enabled

4 CLK_EN_17 R/W 1h Output Enable for CLK17

0h = Output Disabled (low/low) 1h = Output Enabled

3 CLK_EN_16 R/W 1h Output Enable for CLK16

0h = Output Disabled (low/low) 1h = Output Enabled 7-3 RESERVED R 0h Reserved 6-0 RESERVED R 0h Reserved 2-0 RESERVED R 0h Reserved

11.2 R1 Register (Offset = 1h) [Reset = FFh]

R1 is shown in Table 11-4. Return to the Summary Table. Table 11-4. R1 Register Field Descriptions Bit Field Type Reset Description

7 CLK_EN_7 R/W 1h Output Enable for CLK7

0h = Output Disabled (low/low) 1h = Output Enabled

6 CLK_EN_6 R/W 1h Output Enable for CLK6

0h = Output Disabled (low/low) 1h = Output Enabled

5 CLK_EN_5 R/W 1h Output Enable for CLK5

0h = Output Disabled (low/low) 1h = Output Enabled

4 CLK_EN_4 R/W 1h Output Enable for CLK4

0h = Output Disabled (low/low) 1h = Output Enabled

3 CLK_EN_3 R/W 1h Output Enable for CLK3

0h = Output Disabled (low/low) 1h = Output Enabled

2 CLK_EN_2 R/W 1h Output Enable for CLK2

0h = Output Disabled (low/low) 1h = Output Enabled 7-1 RESERVED R 0h Reserved

1 CLK_EN_1 R/W 1h Output Enable for CLK1

0h = Output Disabled (low/low) 1h = Output Enabled 6-0 RESERVED R 0h Reserved www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: LMKDB1120 LMKDB1108

Table 11-4. R1 Register Field Descriptions (continued) Bit Field Type Reset Description

0 CLK_EN_0 R/W 1h Output Enable for CLK0

0h = Output Disabled (low/low) 1h = Output Enabled

11.3 R2 Register (Offset = 2h) [Reset = FFh]

R2 is shown in Table 11-5. Return to the Summary Table. Table 11-5. R2 Register Field Descriptions Bit Field Type Reset Description

7 CLK_EN_15 R/W 1h Output Enable for CLK15

0h = Output Disabled (low/low) 1h = Output Enabled

6 CLK_EN_14 R/W 1h Output Enable for CLK14

0h = Output Disabled (low/low) 1h = Output Enabled

5 CLK_EN_13 R/W 1h Output Enable for CLK13

0h = Output Disabled (low/low) 1h = Output Enabled

4 CLK_EN_12 R/W 1h Output Enable for CLK12

0h = Output Disabled (low/low) 1h = Output Enabled

3 CLK_EN_11 R/W 1h Output Enable for CLK11

0h = Output Disabled (low/low) 1h = Output Enabled

2 CLK_EN_10 R/W 1h Output Enable for CLK10

0h = Output Disabled (low/low) 1h = Output Enabled

1 CLK_EN_9 R/W 1h Output Enable for CLK9

0h = Output Disabled (low/low) 1h = Output Enabled 7-1 RESERVED R 0h Reserved

0 CLK_EN_8 R/W 1h Output Enable for CLK8

0h = Output Disabled (low/low) 1h = Output Enabled 6-0 RESERVED R 0h Reserved

11.4 R3 Register (Offset = 3h) [Reset = 00h]

R3 is shown in Table 11-6. Return to the Summary Table. Table 11-6. R3 Register Field Descriptions Bit Field Type Reset Description

7 RB_OEb_12 R 0h Status of OEb12

6 RB_OEb_11 R 0h Status of OEb11

5 RB_OEb_10 R 0h Status of OEb10

4 RB_OEb_9 R 0h Status of OEb9

3 RB_OEb_8 R 0h Status of OEb8

2 RB_OEb_7 R 0h Status of OEb7

7-1 RESERVED R 0h Reserved LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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Table 11-6. R3 Register Field Descriptions (continued) Bit Field Type Reset Description

1 RB_OEb_6 R 0h Status of OEb6

6-0 RESERVED R 0h Reserved

0 RB_OEb_5 R 0h Status of OEb5

11.5 R4 Register (Offset = 4h) [Reset = 10h]

R4 is shown in Table 11-7. Return to the Summary Table. Table 11-7. R4 Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h Reserved

4 BANK1_ACP_ENABLE R/W 1h Enable Automatic Clock Parking to low/low when LOS event is

0h = Disabled 1h = Enabled 7-1 RESERVED R 0h Reserved 3-1 RESERVED R 0h Reserved

0 RB_SBI_ENQ R 0h Status of SBI_ENQ

4-0 RESERVED R 0h Reserved

11.6 R5 Register (Offset = 5h) [Reset = 0Ah]

R5 is shown in Table 11-8. Return to the Summary Table. Table 11-8. R5 Register Field Descriptions Bit Field Type Reset Description 7-4 REV_ID R 0h Silicon revision 7-4 RESERVED R 0h Reserved 3-0 VENDOR_ID R Ah Vendor ID 3-0 RESERVED R 0h Reserved

11.7 R6 Register (Offset = 6h) [Reset = C9h]

R6 is shown in Table 11-9. Return to the Summary Table. Table 11-9. R6 Register Field Descriptions Bit Field Type Reset Description 7-0 DEV_ID R C9h Device ID

11.8 R7 Register (Offset = 7h) [Reset = 07h]

R7 is shown in Table 11-10. Return to the Summary Table. www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: LMKDB1120 LMKDB1108

Table 11-10. R7 Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h Reserved 7-5 RESERVED R 0h Reserved 4-0 SMBUS_BC R/W 7h SMBus Block Read Byte Count 4-0 RESERVED R 0h Reserved

11.9 R8 Register (Offset = 8h) [Reset = 00h]

R8 is shown in Table 11-11. Return to the Summary Table. Table 11-11. R8 Register Field Descriptions Bit Field Type Reset Description

7 SBI_MASK_7 R/W 0h Mask off Side-Band Disable for CLK7

6 SBI_MASK_6 R/W 0h Mask off Side-Band Disable for CLK6

5 SBI_MASK_5 R/W 0h Mask off Side-Band Disable for CLK5

4 SBI_MASK_4 R/W 0h Mask off Side-Band Disable for CLK4

3 SBI_MASK_3 R/W 0h Mask off Side-Band Disable for CLK3

2 SBI_MASK_2 R/W 0h Mask off Side-Band Disable for CLK2

7-1 RESERVED R 0h Reserved

1 SBI_MASK_1 R/W 0h Mask off Side-Band Disable for CLK1

6-0 RESERVED R 0h Reserved

0 SBI_MASK_0 R/W 0h Mask off Side-Band Disable for CLK0

11.10 R9 Register (Offset = 9h) [Reset = 00h]

R9 is shown in Table 11-12. Return to the Summary Table. Table 11-12. R9 Register Field Descriptions Bit Field Type Reset Description

7 SBI_MASK_15 R/W 0h Mask off Side-Band Disable for CLK15

6 SBI_MASK_14 R/W 0h Mask off Side-Band Disable for CLK14

5 SBI_MASK_13 R/W 0h Mask off Side-Band Disable for CLK13

4 SBI_MASK_12 R/W 0h Mask off Side-Band Disable for CLK12

3 SBI_MASK_11 R/W 0h Mask off Side-Band Disable for CLK11

2 SBI_MASK_10 R/W 0h Mask off Side-Band Disable for CLK10

1 SBI_MASK_9 R/W 0h Mask off Side-Band Disable for CLK9

7-1 RESERVED R 0h Reserved

0 SBI_MASK_8 R/W 0h Mask off Side-Band Disable for CLK8

6-0 RESERVED R 0h Reserved

11.11 R10 Register (Offset = Ah) [Reset = 00h]

R10 is shown in Table 11-13. Return to the Summary Table. LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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Table 11-13. R10 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h Reserved

3 SBI_MASK_19 R/W 0h Mask off Side-Band Disable for CLK19

2 SBI_MASK_18 R/W 0h Mask off Side-Band Disable for CLK18

7-1 RESERVED R 0h Reserved

1 SBI_MASK_17 R/W 0h Mask off Side-Band Disable for CLK17

0 SBI_MASK_16 R/W 0h Mask off Side-Band Disable for CLK16

3-0 RESERVED R 0h Reserved

11.12 R11 Register (Offset = Bh) [Reset = FFh]

R11 is shown in Table 11-14. Return to the Summary Table. Table 11-14. R11 Register Field Descriptions Bit Field Type Reset Description

7 CLK_SLEWRATE_7 R/W 1h CLK7 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate

6 CLK_SLEWRATE_6 R/W 1h CLK6 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate

5 CLK_SLEWRATE_5 R/W 1h CLK5 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate

4 CLK_SLEWRATE_4 R/W 1h CLK4 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate

3 CLK_SLEWRATE_3 R/W 1h CLK3 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate

2 CLK_SLEWRATE_2 R/W 1h CLK2 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate

1 CLK_SLEWRATE_1 R/W 1h CLK1 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate 7-1 RESERVED R 0h Reserved

0 CLK_SLEWRATE_0 R/W 1h CLK0 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate 6-0 RESERVED R 0h Reserved

11.13 R12 Register (Offset = Ch) [Reset = FFh]

R12 is shown in Table 11-15. Return to the Summary Table. Table 11-15. R12 Register Field Descriptions Bit Field Type Reset Description

7 CLK_SLEWRATE_15 R/W 1h CLK15 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: LMKDB1120 LMKDB1108

Table 11-15. R12 Register Field Descriptions (continued) Bit Field Type Reset Description

6 CLK_SLEWRATE_14 R/W 1h CLK14 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate

5 CLK_SLEWRATE_13 R/W 1h CLK13 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate

4 CLK_SLEWRATE_12 R/W 1h CLK12 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate

3 CLK_SLEWRATE_11 R/W 1h CLK11 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate

2 CLK_SLEWRATE_10 R/W 1h CLK10 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate 7-1 RESERVED R 0h Reserved

1 CLK_SLEWRATE_9 R/W 1h CLK9 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate

0 CLK_SLEWRATE_8 R/W 1h CLK8 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate 6-0 RESERVED R 0h Reserved

11.14 R13 Register (Offset = Dh) [Reset = 0Fh]

R13 is shown in Table 11-16. Return to the Summary Table. Table 11-16. R13 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h Reserved

3 CLK_SLEWRATE_19 R/W 1h CLK19 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate

2 CLK_SLEWRATE_18 R/W 1h CLK18 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate 7-1 RESERVED R 0h Reserved

1 CLK_SLEWRATE_17 R/W 1h CLK17 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate

0 CLK_SLEWRATE_16 R/W 1h CLK16 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate 3-0 RESERVED R 0h Reserved

11.15 R20 Register (Offset = 14h) [Reset = 66h]

R20 is shown in Table 11-17. Return to the Summary Table. LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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Table 11-17. R20 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h Reserved 7-4 RESERVED R 0h Reserved 7-4 AMP_1 R/W 6h Global Differential output Control 0.6V~1V 25mV/step Default = 0.75V 0h = 600 mV 1h = 625 mV 2h = 650 mV 3h = 675 mV 4h = 700 mV 5h = 725 mV 6h = 750 mV 7h = 775 mV 8h = 800 mV 9h = 825 mV Ah = 850 mV Bh = 875 mV Ch = 900 mV Dh = 925 mV Eh = 950 mV Fh = 975 mV 3-0 RESERVED R 0h Reserved 3-0 RESERVED R 0h Reserved

11.16 R21 Register (Offset = 15h) [Reset = 0Ch]

R21 is shown in Table 11-18. Return to the Summary Table. Table 11-18. R21 Register Field Descriptions Bit Field Type Reset Description

7 RX1_EN_AC_INPUT R/W 0h Enable receiver bias when CLKIN is AC coupled

0h = DC Coupled Input 1h = AC Coupled Input

6 RX1_EN_RTERM_LSB R/W 0h Enable termination resistors on CLKIN1

0h = Input Termination R Disabled 1h = Input Termination R Enabled

4 RESERVED R 0h Reserved

3 PD_RESTOREB R/W 1h Save Configuration in Power Down 1'b0 : config cleared 1'b1: config

2 SDATA_TIMEOUT_EN R/W 1h Enable SMB SDATA time out monitoring

0h = Disable SDATA Time Out 1h = Enable SDATA Time Out 7-1 RESERVED R 0h Reserved

1 RESERVED R 0h Reserved

6-0 RESERVED R 0h Reserved

0 LOSb_RB R 0h Real time read back of loss detect block output

0h = LOS Event Detected 1h = LOS Event Not-Detected

11.17 R33 Register (Offset = 21h) [Reset = FFh]

R33 is shown in Table 11-19. Return to the Summary Table. www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: LMKDB1120 LMKDB1108

Table 11-19. R33 Register Field Descriptions Bit Field Type Reset Description

7 SBI_CLK_7 R 1h Readback of Side-Band Disable for CLK7

6 SBI_CLK_6 R 1h Readback of Side-Band Disable for CLK6

7-6 RESERVED R 0h Reserved

5 SBI_CLK_5 R 1h Readback of Side-Band Disable for CLK5

4 SBI_CLK_4 R 1h Readback of Side-Band Disable for CLK4

3 SBI_CLK_3 R 1h Readback of Side-Band Disable for CLK3

2 SBI_CLK_2 R 1h Readback of Side-Band Disable for CLK2

1 SBI_CLK_1 R 1h Readback of Side-Band Disable for CLK1

7-1 RESERVED R 0h Reserved

0 SBI_CLK_0 R 1h Readback of Side-Band Disable for CLK0

6-0 RESERVED R 0h Reserved

11.18 R34 Register (Offset = 22h) [Reset = FFh]

R34 is shown in Table 11-20. Return to the Summary Table. Table 11-20. R34 Register Field Descriptions Bit Field Type Reset Description

7 SBI_CLK_15 R 1h Readback of Side-Band Disable for CLK15

6 SBI_CLK_14 R 1h Readback of Side-Band Disable for CLK14

5 SBI_CLK_13 R 1h Readback of Side-Band Disable for CLK13

4 SBI_CLK_12 R 1h Readback of Side-Band Disable for CLK12

3 SBI_CLK_11 R 1h Readback of Side-Band Disable for CLK11

2 SBI_CLK_10 R 1h Readback of Side-Band Disable for CLK10

7-1 RESERVED R 0h Reserved

1 SBI_CLK_9 R 1h Readback of Side-Band Disable for CLK9

0 SBI_CLK_8 R 1h Readback of Side-Band Disable for CLK8

6-0 RESERVED R 0h Reserved

11.19 R35 Register (Offset = 23h) [Reset = 0Fh]

R35 is shown in Table 11-21. Return to the Summary Table. Table 11-21. R35 Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R 0h Reserved

3 SBI_CLK_19 R 1h Readback of Side-Band Disable for CLK19

2 SBI_CLK_18 R 1h Readback of Side-Band Disable for CLK18

1 SBI_CLK_17 R 1h Readback of Side-Band Disable for CLK17

7-1 RESERVED R 0h Reserved 3-0 RESERVED R 0h Reserved

0 SBI_CLK_16 R 1h Readback of Side-Band Disable for CLK16

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11.20 R38 Register (Offset = 26h) [Reset = 00h]

R38 is shown in Table 11-22. Return to the Summary Table. Table 11-22. R38 Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R 0h Reserved 7-1 RESERVED R 0h Reserved 0 WRITE_LOCK W1C 0h Non-clearable SMBus Write Lock bit. When written to one, the SMBus control registers cannot be written to. This bit can only be cleared by recycling power. 0h = SMBus Not locked for Writing 1h = SMBus Locked for Writing

0 RESERVED R 0h Reserved

11.21 R39 Register (Offset = 27h) [Reset = 00h]

R39 is shown in Table 11-23. Return to the Summary Table. Table 11-23. R39 Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h Reserved

1 LOS_EVT R/WSC 0h LOS Event Status When high, indicates that a LOS event was

detected. Can be cleared by writing a 1 to it. 0h = LOS Event Not-Detected 1h = LOS Event Detected 7-1 RESERVED R 0h Reserved 1-0 RESERVED R 0h Reserved 0 WRITE_LOCK_RW1C R/W 0h Clearable SMBus Write Lock bit. When written to one, the SMBus control registers cannot be written to. This bit can be cleared by writing a 1 to it. 0h = SMBus Not Locked for Writing 1h = SMBus locked for writing

11.22 R115 Register (Offset = 73h) [Reset = 00h]

R115 is shown in Table 11-24. Return to the Summary Table. Table 11-24. R115 Register Field Descriptions Bit Field Type Reset Description 3-1 RESERVED R 0h Reserved 7-1 RESERVED R 0h Reserved 1-0 RESERVED R 0h Reserved www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: LMKDB1120 LMKDB1108

12 LMKDB1108 Registers

Table 12-1 lists the memory-mapped registers for the LMKDB1108 registers. All register offset addresses not listed in Table 12-1 should be considered as reserved locations and the register contents should not be modified. Table 12-1. LMKDB1108 Registers Offset Acronym Register Name Section 0h R0 Output Enable Control for CLK2 through CLK7 Section 12.1 1h R1 Output Enable Control for CLK0 and CLK1 Section 12.2 2h R2 OE Pin Readback for CLK2 through CLK7 Section 12.3 3h R3 OE Pin Readback for CLK0 and CLK1 Section 12.4 4h R4 ACP Enable Control and SBI_EN Readback Section 12.5 5h R5 Device Info Section 12.6 6h R6 Device Info (cont.) Section 12.7 7h R7 SMBus Byte Counter Section 12.8 8h R8 SBI Mask for CLK2 through CLK7 Section 12.9 9h R9 SBI Mask for CLK0 and CLK1 Section 12.10 Bh R11 SBI Mask Readback for CLK0 through CLK5 Section 12.11 Ch R12 SBI Mask Readback for CLK6 and CLK7 Section 12.12 11h R17 Output Amplitude Section 12.13 12h R18 Input Configuration, Save Config in PD, SMB SDATA Monitoring, and LOS Readback Section 12.14 14h R20 Output Slew Rate Control for CLK2 through CLK7 Section 12.15 15h R21 Output Slew Rate Control for CLK0 and CLK1 Section 12.16 26h R38 Non-clearable SMBUS Write Lock Section 12.17 27h R39 LOS Event Status and Clearable SMBus Write Lock Section 12.18 73h R115 Section 12.19 Complex bit access types are encoded to fit into small table cells. Table 12-2 shows the codes that are used for access types in this section. Table 12-2. LMKDB1108 Access Type Codes Access Type Code Description Read Type R R Read RC R C Read to Clear Write Type W W Write W1C W Write 1 to clear WSC W Write Reset or Default Value -n Value after reset or the default value

12.1 R0 Register (Offset = 0h) [Reset = EEh]

R0 is shown in Table 12-3. Return to the Summary Table. LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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Table 12-3. R0 Register Field Descriptions Bit Field Type Reset Description

7 CLK_EN_2 R/W 1h Output Enable for CLK2

0h = Output Disabled (low/low) 1h = Output Enabled

6 CLK_EN_3 R/W 1h Output Enable for CLK3

0h = Output Disabled (low/low) 1h = Output Enabled

5 CLK_EN_4 R/W 1h Output Enable for CLK4

0h = Output Disabled (low/low) 1h = Output Enabled

3 CLK_EN_5 R/W 1h Output Enable for CLK5

0h = Output Disabled (low/low) 1h = Output Enabled

2 CLK_EN_6 R/W 1h Output Enable for CLK6

0h = Output Disabled (low/low) 1h = Output Enabled 7-1 RESERVED R 0h Reserved

1 CLK_EN_7 R/W 1h Output Enable for CLK7

0h = Output Disabled (low/low) 1h = Output Enabled 6-0 RESERVED R 0h Reserved

12.2 R1 Register (Offset = 1h) [Reset = 24h]

R1 is shown in Table 12-4. Return to the Summary Table. Table 12-4. R1 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 0h Reserved

5 CLK_EN_0 R/W 1h Output Enable for CLK0

0h = Output Disabled (low/low) 1h = Output Enabled 4-3 RESERVED R 0h Reserved

2 CLK_EN_1 R/W 1h Output Enable for CLK1

0h = Output Disabled (low/low) 1h = Output Enabled 7-2 RESERVED R 0h Reserved 5-0 RESERVED R 0h Reserved 1-0 RESERVED R 0h Reserved

12.3 R2 Register (Offset = 2h) [Reset = 00h]

R2 is shown in Table 12-5. Return to the Summary Table. Table 12-5. R2 Register Field Descriptions Bit Field Type Reset Description

7 RB_OEb_2 R 0h Status of OEb2

6 RB_OEb_3 R 0h Status of OEb3

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Table 12-5. R2 Register Field Descriptions (continued) Bit Field Type Reset Description

5 RB_OEb_4 R 0h Status of OEb4

3 RB_OEb_5 R 0h Status of OEb5

2 RB_OEb_6 R 0h Status of OEb6

7-1 RESERVED R 0h Reserved

1 RB_OEb_7 R 0h Status of OEb7

6-0 RESERVED R 0h Reserved

12.4 R3 Register (Offset = 3h) [Reset = 00h]

R3 is shown in Table 12-6. Return to the Summary Table. Table 12-6. R3 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 0h Reserved

5 RB_OEb_0 R 0h Status of OEb0

4-3 RESERVED R 0h Reserved

2 RB_OEb_1 R 0h Status of OEb1

7-2 RESERVED R 0h Reserved 5-0 RESERVED R 0h Reserved 1-0 RESERVED R 0h Reserved

12.5 R4 Register (Offset = 4h) [Reset = 10h]

R4 is shown in Table 12-7. Return to the Summary Table. Table 12-7. R4 Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h Reserved

4 ACP_ENABLE R/W 1h Enable Automatic Clock Parking to low/low when LOS event is

detected. 0h = Disabled (DC Coupled) 1h = Enabled (AC Coupled) 3-1 RESERVED R 0h Reserved 7-1 RESERVED R 0h Reserved 4-0 RESERVED R 0h Reserved

12.6 R5 Register (Offset = 5h) [Reset = 0Ah]

R5 is shown in Table 12-8. Return to the Summary Table. LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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Table 12-8. R5 Register Field Descriptions Bit Field Type Reset Description 7-4 REV_ID R 0h Silicon revision 7-4 RESERVED R 0h Reserved 3-0 VENDOR_ID R Ah Vendor ID 3-0 RESERVED R 0h Reserved

12.7 R6 Register (Offset = 6h) [Reset = 08h]

R6 is shown in Table 12-9. Return to the Summary Table. Table 12-9. R6 Register Field Descriptions Bit Field Type Reset Description 7-0 DEV_ID R 8h Device ID

12.8 R7 Register (Offset = 7h) [Reset = 07h]

R7 is shown in Table 12-10. Return to the Summary Table. Table 12-10. R7 Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 0h Reserved 7-5 RESERVED R 0h Reserved 4-0 SMBUS_BC R/W 7h SMBUS Block Read Byte Count 4-0 RESERVED R 0h Reserved

12.9 R8 Register (Offset = 8h) [Reset = 00h]

R8 is shown in Table 12-11. Return to the Summary Table. Table 12-11. R8 Register Field Descriptions Bit Field Type Reset Description

7 SBI_MASK_2 R/W 0h Mask off Side-Band Disable for CLK2

6 SBI_MASK_3 R/W 0h Mask off Side-Band Disable for CLK3

5 SBI_MASK_4 R/W 0h Mask off Side-Band Disable for CLK4

3 SBI_MASK_5 R/W 0h Mask off Side-Band Disable for CLK5

2 SBI_MASK_6 R/W 0h Mask off Side-Band Disable for CLK6

7-1 RESERVED R 0h Reserved

1 SBI_MASK_7 R/W 0h Mask off Side-Band Disable for CLK7

6-0 RESERVED R 0h Reserved www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: LMKDB1120 LMKDB1108

12.10 R9 Register (Offset = 9h) [Reset = 00h]

R9 is shown in Table 12-12. Return to the Summary Table. Table 12-12. R9 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 0h Reserved

5 SBI_MASK_0 R/W 0h Mask off Side-Band Disable for CLK0

4-3 RESERVED R 0h Reserved

2 SBI_MASK_1 R/W 0h Mask off Side-Band Disable for CLK1

7-2 RESERVED R 0h Reserved 5-0 RESERVED R 0h Reserved 1-0 RESERVED R 0h Reserved

12.11 R11 Register (Offset = Bh) [Reset = EEh]

R11 is shown in Table 12-13. Return to the Summary Table. Table 12-13. R11 Register Field Descriptions Bit Field Type Reset Description

7 SBI_CLK_2 R 1h Readback of Side-Band Disable for CLK5

6 SBI_CLK_3 R 1h Readback of Side-Band Disable for CLK4

5 SBI_CLK_4 R 1h Readback of Side-Band Disable for CLK3

3 SBI_CLK_5 R 1h Readback of Side-Band Disable for CLK2

2 SBI_CLK_6 R 1h Readback of Side-Band Disable for CLK1

1 SBI_CLK_7 R 1h Readback of Side-Band Disable for CLK0

7-1 RESERVED R 0h Reserved 6-0 RESERVED R 0h Reserved

12.12 R12 Register (Offset = Ch) [Reset = 24h]

R12 is shown in Table 12-14. Return to the Summary Table. Table 12-14. R12 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 0h Reserved

5 SBI_CLK_0 R 1h Readback of Side-Band Disable for CLK7

4-3 RESERVED R 0h Reserved

2 SBI_CLK_1 R 1h Readback of Side-Band Disable for CLK6

7-2 RESERVED R 0h Reserved 5-0 RESERVED R 0h Reserved 1-0 RESERVED R 0h Reserved LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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12.13 R17 Register (Offset = 11h) [Reset = 66h]

R17 is shown in Table 12-15. Return to the Summary Table. Table 12-15. R17 Register Field Descriptions Bit Field Type Reset Description 7-4 AMP R/W 6h Global Differential output Control 0.6V~1V 25mV/step Default = 0.8V 0h = 600 mV 1h = 625 mV 2h = 650 mV 3h = 675 mV 4h = 700 mV 5h = 725 mV 6h = 750 mV 7h = 775 mV 8h = 800 mV 9h = 825 mV Ah = 850 mV Bh = 875 mV Ch = 900 mV Dh = 925 mV Eh = 950 mV Fh = 975 mV 7-4 RESERVED R 0h Reserved 7-4 RESERVED R 0h Reserved 3-0 RESERVED R 0h Reserved 3-0 RESERVED R 0h Reserved

12.14 R18 Register (Offset = 12h) [Reset = 08h]

R18 is shown in Table 12-16. Return to the Summary Table. Table 12-16. R18 Register Field Descriptions Bit Field Type Reset Description

7 RX_EN_AC_INPUT R/W 0h Enable receiver bias when CLKIN is AC coupled

0h = DC Coupled Input 1h = AC Coupled Input

6 RX_EN_RTERM_LSB R/W 0h Enable/Disables termination resistors on CLKIN1

0h = Disabled 1h = Enabled

3 PD_RESTOREB R/W 1h Save Configuration in Power Down

0h = Config Cleared 1h = Config Saved 7-1 RESERVED R 0h Reserved 2-1 RESERVED R 0h Reserved 6-0 RESERVED R 0h Reserved 0h = LOS Event Detected 1h = LOS Event Not-Detected

12.15 R20 Register (Offset = 14h) [Reset = EEh]

R20 is shown in Table 12-17. www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: LMKDB1120 LMKDB1108

Return to the Summary Table. Table 12-17. R20 Register Field Descriptions Bit Field Type Reset Description

7 CLK_SLEWRATE_2 R/W 1h CLK3 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate

6 CLK_SLEWRATE_3 R/W 1h CLK4 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate

5 CLK_SLEWRATE_4 R/W 1h CLK4 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate

3 CLK_SLEWRATE_5 R/W 1h CLK5 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate

2 CLK_SLEWRATE_6 R/W 1h CLK6 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate

1 CLK_SLEWRATE_7 R/W 1h CLK7 Slew Rate Control:

0h = Low Slew Rate 1h = High Slew Rate 7-1 RESERVED R 0h Reserved 6-0 RESERVED R 0h Reserved

12.16 R21 Register (Offset = 15h) [Reset = 24h]

R21 is shown in Table 12-18. Return to the Summary Table. Table 12-18. R21 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 0h Reserved

5 CLK_SLEWRATE_0 R/W 1h CLK2 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate 4-3 RESERVED R 0h Reserved 7-2 RESERVED R 0h Reserved

2 CLK_SLEWRATE_1 R/W 1h CLK2 Slew Rate Control

0h = Low Slew Rate 1h = High Slew Rate 5-0 RESERVED R 0h Reserved 1-0 RESERVED R 0h Reserved

12.17 R38 Register (Offset = 26h) [Reset = 00h]

R38 is shown in Table 12-19. Return to the Summary Table. Table 12-19. R38 Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R 0h Reserved LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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Table 12-19. R38 Register Field Descriptions (continued) Bit Field Type Reset Description 7-1 RESERVED R 0h Reserved 0 WRITE_LOCK R 0h Non-clearable SMBus Write Lock bit. When written to one, the SMBus control registers cannot be written to. This bit can only be cleared by recycling power. 0h = SMBus Not Locked for Writing 1h = SMBus Locked for Writing

12.18 R39 Register (Offset = 27h) [Reset = 00h]

R39 is shown in Table 12-20. Return to the Summary Table. Table 12-20. R39 Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R 0h Reserved

1 LOS_EVT R/W 0h LOS Event Status When high, indicates that a LOS event was

detected. Can be cleared by writing a 1 to it. 0h = Not LOS Event Detected 1h = LOS Event Detected 7-1 RESERVED R 0h Reserved 0 WRITE_LOCK_RW1C R 0h Clearable SMBus Write Lock bit. When written to one, the SMBus control registers cannot be written to. This bit can be cleared by writing a 1 to it. 0h = SMBus Not Locked for Writing 1h = SMBus Locked for Writing 1-0 RESERVED R 0h Reserved

12.19 R115 Register (Offset = 73h) [Reset = 00h]

R115 is shown in Table 12-21. Return to the Summary Table. Table 12-21. R115 Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R 0h Reserved 1-0 RESERVED R 0h Reserved www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: LMKDB1120 LMKDB1108

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES November 2023 * Initial Release

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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14.1 Package Option Addendum

Device Status(1) Package type Package Drawing Pins Package Qty Eco Plan(2) Lead finish/ Ball material(6) MSL Peak Temp(3) Op Temp (°C) Device marking(4) (5) LMKDB1120Z1 00NPPR ACTIVE TLGA NPP 80 3000 RoHS & Green NIPDAU Level-3-260C-

168 HR -40 to 105 LMKDB

5NPPR ACTIVE TLGA NPP 80 3000 RoHS & Green NIPDAU Level-3-260C- 00NPPT ACTIVE TLGA NPP 80 250 RoHS & Green NIPDAU Level-3-260C- 5NPPT ACTIVE TLGA NPP 80 250 RoHS & Green NIPDAU Level-3-260C- 00RKPR ACTIVE VQFN RKP 40 3000 RoHS & Green NIPDAU Level-1-260C- 5RKPR ACTIVE VQFN RKP 40 3000 RoHS & Green NIPDAU Level-1-260C- 00RKPT ACTIVE VQFN RKP 40 250 RoHS & Green NIPDAU Level-1-260C- 5RKPT ACTIVE VQFN RKP 40 250 RoHS & Green NIPDAU Level-1-260C- 00REXR PREVIEW VQFN REX 28 3000 RoHS & Green NIPDAU Level-1-260C- 5REXR PREVIEW VQFN REX 28 3000 RoHS & Green NIPDAU Level-1-260C- 00REXT PREVIEW VQFN REX 28 250 RoHS & Green NIPDAU Level-1-260C- 5REXT PREVIEW VQFN REX 28 250 RoHS & Green NIPDAU Level-1-260C- EXR PREVIEW VQFN REX 28 3000 RoHS & Green NIPDAU Level-1-260C-

168 HR -40 to 105 LMKDB 1204

EXT PREVIEW VQFN REX 28 250 RoHS & Green NIPDAU Level-1-260C- EYR PREVIEW VQFN REY 20 3000 RoHS & Green NIPDAU Level-1-260C-

168 HR -40 to 105 LMKDB 1202

EYT PREVIEW VQFN REY 20 250 RoHS & Green NIPDAU Level-1-260C- EYR PREVIEW VQFN REY 20 3000 RoHS & Green NIPDAU Level-1-260C-

168 HR -40 to 105 LMKDB 1102

EYT PREVIEW VQFN REY 20 250 RoHS & Green NIPDAU Level-1-260C- (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: LMKDB1120 LMKDB1108

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

14.2 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin 1 Quadrant LMKDB11 20Z100NP PR LMKDB11 20Z85NP PR LMKDB11 20Z100NP PT LMKDB11 20Z85NP PT LMKDB11 08Z100RK PR LMKDB11 08Z85RK PR LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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(mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin 1 Quadrant LMKDB11 08Z100RK PT LMKDB11 08Z85RK PT LMKDB11 04Z100RE XR LMKDB11 04Z85RE XR LMKDB11 04Z100RE XT LMKDB11 04Z85RE XT LMKDB12 LMKDB12 LMKDB12 LMKDB12 LMKDB11 LMKDB11 www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: LMKDB1120 LMKDB1108

14.3 Mechanical Data

www.ti.com PACKAGE OUTLINE

5.5 TYP

B 6.15.9A 6.15.9 (0.725)(0.725) (0.125)(0.125) 4224877/A 03/2019 TLGA - 0.9 mm max heightNPP0080ATHIN LAND GRID ARRAY CORNERPIN A1 SEATING PLANE0.08 C A123 0.1C A B0.05C456789101112 SYMM SYMM BCDEFGHJKLM PIN 1 ID(45 X 0.35) SCALE 2.500 LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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www.ti.com EXAMPLE BOARD LAYOUT 0.05 MIN0.05 MAX 80X (0.25)(0.5) TYP(0.5) TYP (0.25)SOLDER MASKOPENING(0.25)METAL ( 2.8)(0.2) VIATYP (1.15) (1.15) 4224877/A 03/2019 TLGA - 0.9 mm max heightNPP0080ATHIN LAND GRID ARRAY SOLDER MASK DETAILSNOT TO SCALE SYMM SYMM C123456789101112ABDEFGHJKLMEXPOSED METAL SHOWNLAND PATTERN EXAMPLESCALE: 15X NON-SOLDER MASKDEFINED(PREFERRED)EXPOSEDMETALSOLDER MASKOPENINGSOLDER MASKDEFINEDMETAL UNDERSOLDER MASKEXPOSEDMETAL www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: LMKDB1120 LMKDB1108

www.ti.com EXAMPLE STENCIL DESIGN (0.715)4X ( 1.23) 4224877/A 03/2019 TLGA - 0.9 mm max heightNPP0080ATHIN LAND GRID ARRAY NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM 123456789101112CABDEFGHJKLMBASED ON 0.1 mm THICK STENCILSOLDER PASTE EXAMPLESCALE: 15X METALTYP EXPOSED METALTYP LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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www.ti.com PACKAGE OUTLINE5.14.9 5.14.9 1.00.80.050.00 2X 3.636X 0.4 2X 3.6 40X 0.50.340X 0.250.15 3.60.1 (0.2) TYP VQFN - 1 mm max heightRKP0040APLASTIC QUAD FLATPACK - NO LEAD 4229293/A 12/2022 0.08 C PIN 1 INDEX AREA SEATING PLANE PIN 1 ID(45X 0.35) SYMMEXPOSEDTHERMAL PADSYMM1 1011 2021 303140 SCALE 2.800 AB C www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: LMKDB1120 LMKDB1108

www.ti.com EXAMPLE BOARD LAYOUT 36X (0.4) (R0.05) TYP 0.05 MAXALL AROUND0.05 MINALL AROUND 40X (0.6)40X (0.2) (4.8) (4.8)(3.6) (3.6) (0.2) TYPVIA (0.615)(0.935) (0.615)(0.935) VQFN - 1 mm max heightRKP0040APLASTIC QUAD FLATPACK - NO LEAD SYMM SYMM LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE: 18X SEE SOLDER MASKDETAIL1 1011 2021 303140 METAL EDGESOLDER MASKOPENINGEXPOSED METALMETAL UNDERSOLDER MASKSOLDER MASKOPENINGEXPOSEDMETALNON SOLDER MASKDEFINED(PREFERRED)SOLDER MASK DEFINEDSOLDER MASK DETAILS LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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www.ti.com EXAMPLE STENCIL DESIGN (4.8) (4.8)(1.23) 9X (1.03) 9X (1.03)(R0.05) TYP (1.23)VQFN - 1 mm max heightRKP0040APLASTIC QUAD FLATPACK - NO LEAD 4229293/A 12/2022NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLEBASED ON 0.125 MM THICK STENCILSCALE: 18X EXPOSED PAD 4174% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SYMM SYMM411 1011 2021 303140 www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: LMKDB1120 LMKDB1108

www.ti.com PACKAGE OUTLINE4.13.94.13.9 1.00.80.050.00 2X 2.424X 0.4 2X 2.4 28X 0.50.3 2.60.128X 0.250.15 (0.1) TYP VQFN - 1 mm max heightREX0028APLASTIC QUAD FLATPACK - NO LEAD 4229744/A 06/2023 0.08 C PIN 1 INDEX AREA SEATING PLANE PIN 1 ID(45X 0.3) SYMMEXPOSEDTHERMAL PADSYMM1 78 141521222829 0.1C A B0.05C SCALE 3.000 AB C LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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www.ti.com EXAMPLE BOARD LAYOUT 24X (0.4)(1.05) (1.05)(R0.05) TYP 0.05 MAXALL AROUND0.05 MINALL AROUND 28X (0.6)28X (0.2) (3.8) (3.8) ( 2.6) (0.2) TYPVIA VQFN - 1 mm max heightREX0028APLASTIC QUAD FLATPACK - NO LEAD SYMM SYMM LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE: 20X SEE SOLDER MASKDETAIL1 78 1415 212228 METAL EDGESOLDER MASKOPENINGEXPOSED METALMETAL UNDERSOLDER MASKSOLDER MASKOPENINGEXPOSEDMETALNON SOLDER MASKDEFINED(PREFERRED)SOLDER MASK DEFINEDSOLDER MASK DETAILS www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: LMKDB1120 LMKDB1108

www.ti.com EXAMPLE STENCIL DESIGN (3.8) (3.8) (0.675) TYP 4X (1.15)(R0.05) TYP VQFN - 1 mm max heightREX0028APLASTIC QUAD FLATPACK - NO LEAD 4229744/A 06/2023NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLEBASED ON 0.1 MM THICK STENCILSCALE: 20X EXPOSED PAD 2978% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SYMM SYMM1 78 1415 212228 LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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www.ti.com PACKAGE OUTLINE C SEE TERMINALDETAIL20X 0.250.15 1.70.05 20X 0.50.3 A 3.12.9B VQFN - 1 mm max heightREY0020BPLASTIC QUAD FLATPACK - NO LEAD 4229745/A 06/2023 OPTION 01 (0.1)DIMENSION AOPTION 02 (0.2) PIN 1 INDEX AREA

0.08 CSEATING PLANE

2016X0.3)(45PIN 1 ID0.1C A B0.05C EXPOSEDTHERMAL PAD21SYMM SCALE 4.000 DETAILOPTIONAL TERMINALTYPICAL www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: LMKDB1120 LMKDB1108

www.ti.com EXAMPLE BOARD LAYOUT 0.05 MINALL AROUND0.05 MAXALL AROUND 20X (0.2)20X (0.6) (0.2) TYPVIA16X (0.4)(2.8) (2.8) (0.6) (1.7) (R0.05)TYP(0.6) VQFN - 1 mm max heightREY0020BPLASTIC QUAD FLATPACK - NO LEAD 4229745/A 06/2023 SYMM1 56 1011 151620 SYMM LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE:20X SOLDER MASKOPENINGMETAL UNDERSOLDER MASKSOLDER MASKDEFINEDMETALSOLDER MASKOPENINGNON SOLDER MASKSOLDER MASK DETAILSDEFINED(PREFERRED) LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 www.ti.com ADVANCE INFORMATION

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Product Folder Links: LMKDB1120 LMKDB1108

www.ti.com EXAMPLE STENCIL DESIGN (2.8) (2.8) 4X (0.75) (0.47) (0.47) TYP (R0.05) TYP VQFN - 1 mm max heightREY0020BPLASTIC QUAD FLATPACK - NO LEAD 4229745/A 06/2023NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM TYPMETAL BASED ON 0.1 mm THICK STENCILSOLDER PASTE EXAMPLE EXPOSED PAD 21:78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGESCALE:20X SYMM1 56 1011 151620 www.ti.com LMKDB1120, LMKDB1108 SNAS855 – NOVEMBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 63 Product Folder Links: LMKDB1120 LMKDB1108

www.ti.com 19-Nov-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PLMKDB1108RKPT ACTIVE VQFN RKP 40 250 TBD Call TI Call TI -40 to 85 Samples PLMKDB1120NPPT ACTIVE TLGA NPP 80 250 TBD Call TI Call TI -40 to 85 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 19-Nov-2023 Addendum-Page 2

www.ti.com PACKAGE OUTLINE C0.9 0.8 0.05 0.00 5.5 TYP 0.5 TYP

0.5 TYP

80X 0.3 0.2 2.8 0.1 B 6.1 5.9 A 6.1 5.9 (0.725) (0.725) (0.125) (0.125) 4224877/A 03/2019 TLGA - 0.9 mm max heightNPP0080A THIN LAND GRID ARRAY NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. CORNER PIN A1 SEATING PLANE 0.08 C A 1 2 3

0.1 C A B

0.05 C4 5 6 7 8 9 10 11 12

B C D E F G H J K L M PIN 1 ID (45 X 0.35) SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT 0.05 MIN0.05 MAX 80X ( 0.25) (0.5) TYP (0.5) TYP ( 0.25) SOLDER MASK OPENING ( 0.25) METAL ( 2.8) ( 0.2) VIA TYP (1.15) (1.15) 4224877/A 03/2019 TLGA - 0.9 mm max heightNPP0080A THIN LAND GRID ARRAY NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK DETAILS NOT TO SCALE SYMM SYMM C 1 2 3 4 5 6 7 8 9 10 11 12 A B D E F G H J K L M LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X NON-SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL SOLDER MASK OPENING SOLDER MASK DEFINED METAL UNDER SOLDER MASK EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (0.715) 4X ( 1.23) (0.5) TYP (0.5) TYP 4224877/A 03/2019 TLGA - 0.9 mm max heightNPP0080A THIN LAND GRID ARRAY NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM 1 2 3 4 5 6 7 8 9 10 11 12 C A B D E F G H J K L M SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE: 15X METAL TYP EXPOSED METAL TYP

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRKP 40 PLASTIC QUAD FLATPACK - NO LEAD5 x 5, 0.4 mm pitch 4229305/A

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