PLMK6CE02400CDLET

Texas Instruments

LMK6x Low Jitter, High-Performance BAW Oscillator REVISED FEBRUARY 2023

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Technical content

LMK6x Low Jitter, High-Performance BAW Oscillator

1 Features

High-performance differential and single-ended output Oscillator, supporting any fixed frequency within the below range: – LMK6D: 1 to 400 MHz, LVDS output – LMK6H: 1 to 400 MHz, HCSL output – LMK6P: 1 to 400 MHz, LVPECL output – LMK6C: 1 to 200 MHz, LVCMOS output
Ultra-low jitter: – LMK6D/LMK6H/LMK6P: 100-fs typical / 125-fs maximum RMS jitter at 156.25 MHz (12 kHz to

20 MHz)

– LMK6C: 350-fs typical / 500-fs maximum RMS jitter at 100 MHz (12 kHz to 20 MHz) – LMK6H: PCIe Gen 1 to Gen 6 compliant

±25 ppm total frequency stability inclusive of 10 years aging and all other factors
Smallest industry standard DLE and DLF packages
Support extended industrial temperature grade: – LMK6P/LMK6D/LMK6H: –40°C to 85°C – LMK6C: –40°C to 105°C
Integrated LDO for robust supply noise immunity: – –72 dBc PSRR at 500 kHz ripple
Start-up time: < 5 ms
Standard frequencies: 33.333, 40, 50, 60, 65.53, 74.25, 100, 125 and 156.25 – Differential (MHz): 51.84, 100, 122.88, 125, 148.5, 155.52, 156.25, 161.1328125, 200 and 312.5
Device can support any frequency between 1 MHz to 400 MHz. Contact TI representative for any frequency and samples needed

2 Applications

56G/112G PAM4 clocking
100G/200G/400G/800G Optical Transport Network and Coherent Optics
Network equipment, switches, routers, line cards, SAN, data centers and baseband units (BBU)
PCIe Gen 1 to Gen 6 compliant reference clock
Industrial applications
Test and measurement
ASIC, FPGA, MCU reference clocking
High-performance crystal oscillator replacement

3 Description

Texas Instruments' Bulk-Acoustic Wave ( BAW) is a micro-resonator technology that enables integration of high-precision BAW resonator directly into packages with ultra-low jitter clock circuitry. BAW is fully designed and manufactured at TI factories like other silicon-based fabrication processes. The LMK6x device is an ultra-low jitter, fixed- frequency oscillator which incorporates the BAW as the resonator source. The device is factory- programmed per specific operation mode, including frequency, voltage, output type, and function pin. With a high-performance fractional frequency divider, the LMK6x is capable of producing any frequency within the specified range providing a single device family for all frequency needs. The high-performance clocking, mechanical stability, flexibility, and small package options for this device are designed for reference and core clocks in high- speed SERDES used in telecommunications, data and enterprise network, and industrial applications.

Package Information

TYPE PACKAGE(1) BODY SIZE (NOM) LMK6C LVCMOS VSON (DLE-4) 3.20 mm × 2.50 mm LMK6C VSON (DLF-4) 2.50 mm × 2.00 mm LMK6D LMK6H LMK6P LVDS, HCSL, LVPECL VSON (DLE-6) 3.20 mm × 2.50 mm LMK6D LMK6H LMK6P VSON (DLF-6) 2.50 mm × 2.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. BAWVDD CLK Fractional Output Divider OE / ST / NC GND Power Conditioning Output driver Temp Sensor Frequency Control Logic Output/Chip Control Logic LMK6C Simplified Block Diagram LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11.2 Receiving Notification of Documentation Updates.. 36

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (December 2022) to Revision D (February 2023) Page Changes from Revision B (November 2022) to Revision C (December 2022) Page LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

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Product Folder Links: LMK6C LMK6D LMK6H LMK6P

5 Device Ordering Information

Use Figure 5-1 and Figure 5-2 to understand the device nomenclature of the LMK6x orderable options. PLMK6 156250 TA Output Type D: LVDS H: HCSL P: LVPECL Sub-Family Options E: Pin 1 – Output Enable (Active High or NC) F: Pin 2 – Output Enable (Active High or NC) A: Pin 1 – Stand By (Active Low) B: Pin 2 – Stand By (Active Low) Note: Contact TI for other options for Output Enable and Stand By. Frequency Options 156250 = 156.250 MHz 050000 = 50.000 MHz 008192 = 8.192 MHz XXX.XXX = Custom Frequency Code; Note: Contact TI for custom number of digits after decimal point A Voltage/Temperature Rating DLF Package Size DLE: 3.2 mm x 2.5 mm DLF: 2.5 mm x 2.0 mm Packaging Method T: Small Reel R: Large Reel Product Family Figure 5-1. Part Number Guide: LMK6D, LMK6H, and LMK6P Note: Contact a TI representative to pre-order specific devices. Email: ti_osc_customer_requirement@list.ti.com www.ti.com LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LMK6C LMK6D LMK6H LMK6P

C: LVCMOS Sub-Family Options E: Pin 1 – Output Enable (Active High or NC) A: Pin 1 – Stand By (Active Low) Note: Contact TI for other options for Output Enable and Stand By. Frequency Options 125000 = 125.000 MHz 033333 = 33.333 MHz 008192 = 8.192 MHz XXX.XXX = Custom Frequency Code Note: Contact TI for custom number of digits after decimal point C Voltage/Temperature Rating DLF Package Size DLE: 3.2 mm x 2.5 mm DLF: 2.5 mm x 2.0 mm Packaging Method T: Small Reel R: Large Reel Product Family Figure 5-2. Part Number Guide: LMK6C Note: Contact a TI representative to pre-order specific devices. Email: ti_osc_customer_requirement@list.ti.com LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

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Product Folder Links: LMK6C LMK6D LMK6H LMK6P

6 Pin Configuration and Functions

Figure 6-1. LMK6P, LMK6D, or LMK6H 6-Pin VSON (Top View) Table 6-1. LMK6P, LMK6D, or LMK6H Pin Functions PIN I/O(1) DESCRIPTION NAME DLE/DLF OE / ST / NC 1 I / NC Output Enable (OE) or Standby (ST) pin or No Connect (NC). See Table 9-1 for more details. OE / ST / NC 2 NC / I Output Enable (OE) or Standby (ST) pin or No Connect (NC). See Table 9-1 for more details. GND 3 G Device ground OUTP 4 O Positive differential output clock OUTN 5 O Negative differential output clock VDD 6 P Device power supply (1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect (can be left floating). 1OE / ST / NC 2GND VDD OUT Figure 6-2. LMK6C 4-Pin VSON (Top View) Table 6-2. LMK6C Pin Functions PIN I/O(1) DESCRIPTION NAME DLE/DLF OE / ST / NC 1 I / NC Output Enable (OE) or Standby (ST) pin or No Connect (NC). See Table 9-2 for more details. GND 2 G Device ground OUT 3 O LVCMOS output clock VDD 4 P Device power supply (1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect (can be left floating). www.ti.com LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LMK6C LMK6D LMK6H LMK6P

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDD Device Supply Voltage(2) –0.3 3.63 V Device Supply Voltage(3) –0.3 1.98 V EN Logic Input Voltage –0.3 VDD + 0.3 V OUTP, OUTN Clock Output Voltage(4) –0.3 VDD + 0.3 V OUT Clock Output Voltage(5) –0.3 VDD + 0.3 V TJ Junction Temperature 125 ℃ TSTG Storage Temperature 150 ℃ (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) For all devices with Recommended Operating Voltage of 2.5 V +/- 5% and 3.3 V +/- 5% (3) For all devices with Recommended Operating Voltage of 1.8 V +/- 5% (4) For all differential outputs - LMK6D, LMK6H, and LMK6P. (5) For single ended outputs - LMK6C.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), per ANSI/ESDA/ JEDEC JS-002, all pins(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Environmental Compliance

Mechanical Shock Resistance MIL-STD-883F, Method 2002, Condition A 1500 g Mechanical Vibration Resistance MIL-STD-883F, Method 2026, Condition C 10 g MIL-STD-883F, Method 2007, Condition A 20 g Moisture Sensitivity Level (MSL) MSL1

7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Device Supply Voltage(1) 1.7 1.8 1.9 V Device Supply Voltage(2) 2.37 2.5, 3.3 3.5 V TA Ambient temperature(3) –40 85 °C Ambient temperature(4) –40 105 °C TJ Junction temperature 125 °C tRAMP VDD power-up ramp time(1) (2) 0.1 100 ms (1) For all devices with Recommended Operating Voltage of 1.8V +/- 5% (2) For all devices with Recommended Operating Voltage of 2.5V +/- 5% and 3.3V +/- 5% (3) For all differential outputs - LMK6D, LMK6H and LMK6P. (4) For single-ended output - LMK6C. LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

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Product Folder Links: LMK6C LMK6D LMK6H LMK6P

7.5 Thermal Information

THERMAL METRIC(1) LMK6D/H/P UNITDLE (VSON) DLF (VSON)

6 PINS 6 PINS

RθJA Junction-to-ambient thermal resistance 101.2 107.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 58.6 70.1 °C/W RθJB Junction-to-board thermal resistance 31.3 39.4 °C/W ΨJT Junction-to-top characterization parameter 2.7 2.3 °C/W ΨJB Junction-to-board characterization parameter 31.1 39.2 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.6 Thermal Information

THERMAL METRIC(1) LMK6C UNITDLE (VSON) DLF (VSON)

4 PINS 4 PINS

RθJA Junction-to-ambient thermal resistance 124.8 128.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 61.2 73.2 °C/W RθJB Junction-to-board thermal resistance 42.5 39.8 °C/W ΨJT Junction-to-top characterization parameter 2.8 2.4 °C/W ΨJB Junction-to-board characterization parameter 42.3 39.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LMK6C LMK6D LMK6H LMK6P

7.7 Electrical Characteristics

over recommended operating conditions, typical temperature = 25°C, frequency output = 156.25 MHz, VDD = 3.3 V, LVCMOS output capacitor load = 2.2 pF (unless otherwise specified)(4) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Current Consumption Characteristics IDD Device power consumption (LVPECL,VDD = 2.5 V/3.3 V, excluding load current)

100 MHz 65 82 mA

156.25 MHz 69 87 mA

200 MHz 67 85 mA

312.5 MHz 76 95 mA

400 MHz 88 108 mA

(LVPECL,VDD = 1.8 V, excluding load current)

100 MHz 61 79 mA

156.25 MHz 66 83 mA

200 MHz 64 82 mA

312.5 MHz 73 91 mA

400 MHz 84 104 mA

(HCSL,VDD = 2.5 V/3.3 V, excluding load current)

200 MHz 67 86 mA

312.5 MHz 76 96 mA

(HCSL,VDD = 1.8 V, excluding load current)

100 MHz 58 75 mA

156.25 MHz 62 80 mA

200 MHz 60 78 mA

312.5 MHz 69 88 mA

400 MHz 77 97 mA

(LVDS,VDD = 2.5 V/3.3 V, excluding load current)

100 MHz 54 71 mA

156.25 MHz 58 75 mA

200 MHz 56 74 mA

312.5 MHz 65 84 mA

400 MHz 76 96 mA

(LVDS,VDD = 1.8 V, excluding load current)

100 MHz 52 68 mA

156.25 MHz 56 72 mA

200 MHz 54 71 mA

312.5 MHz 63 80 mA

400 MHz 74 92 mA

(LVCMOS,VDD = 2.5 V / 3.3 V, with load)

100 MHz 45 62 mA

156.25 MHz 55 71 mA

200 MHz 61 77 mA

(LVCMOS,VDD = 1.8 V, with load)

100 MHz 44 59 mA

156.25 MHz 50 65 mA

200 MHz 56 72 mA

IDD-STBY Device standby current ST (Standby) = GND 6 13 mA IDD-PD Device current with output disabled (100 MHz) OE = GND, LVPECL mode, VDD = 3.3 V 48 67 mA OE = GND, HCSL mode, VDD = 3.3 V 49 67 mA OE = GND, LVDS mode, VDD = 3.3 V 49 66 mA OE = GND, LVCMOS mode, VDD = 3.3 V 40 56 mA LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

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over recommended operating conditions, typical temperature = 25°C, frequency output = 156.25 MHz, VDD = 3.3 V, LVCMOS output capacitor load = 2.2 pF (unless otherwise specified)(4) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVPECL Output Characteristics Fout Output frequency 1 400 MHz VOD Output voltage swing (VOH – VOL) AC coupled, VDD = 3.3 V 525 645 765 mV AC coupled, VDD = 2.5 V 450 555 660 mV AC coupled, VDD = 1.8 V 280 375 470 mV DC coupled, VDD = 2.5 V/ 3.3 V(1) 650 800 950 mV DC coupled, VDD = 1.8 V(1) 450 600 750 mV VOD,DIFF Differential output peak-peak swing 2 × |VOD| Vpp VOS Output common-mode voltage VDD = 3.3 V(1) 1.5 1.6 1.7 V VDD = 2.5 V(1) 0.825 0.9 0.975 V VDD = 1.8 V(1) 0.45 0.5 0.55 V tR/tF Output rise/fall time 20% to 80% of VOD,DIFF, VDD = 2.5 V/ 3.3 V 120 200 ps 20% to 80% of VOD,DIFF, VDD = 1.8 V 120 200 ps ODC Output duty cycle VDD = 2.5 V/ 3.3 V, measured between 50% points on the waveform 45 50 55 % VDD = 1.8 V, measured between 50% points on the waveform 45 50 55 % LVDS Output Characteristics Fout Output frequency 1 400 MHz VOD Output voltage swing (VOH – VOL) Under LVDS load condition 250 350 450 mV VOD,DIFF Differential output peak-peak swing 2 × |VOD| Vpp VOS Output common-mode voltage VDD = 1.8 V 0.80 0.9 1.0 V tR/tF Output rise/fall time 20% to 80% of VOD,DIFF, VDD = 2.5 V/3.3 V 150 250 ps 20% to 80% of VOD,DIFF, VDD = 1.8 V 150 250 ps ODC Output duty cycle VDD = 2.5 V/3.3 V, measured between 50% points on the waveform 45 50 55 % VDD = 1.8 V, measured between 50% points on the waveform 45 50 55 % HCSL Output Characteristics Fout Output frequency 1 400 MHz VOH Output high voltage DC coupled, 50 Ω to ground, VDD = 2.5 V/ 3.3 V 650 750 850 mV DC coupled, 50 Ω to ground, VDD = 1.8 V 460 560 660 mV VOL Output low voltage DC coupled, 50 Ω to ground, VDD = 2.5 V/ 3.3 V –150 0 150 mV DC coupled, 50 Ω to ground, VDD = 1.8 V –150 0 150 mV VOD,DIFF Differential output peak-peak swing 2 × |VOH – VOL| V Vcross Absolute crossing point voltage VDD = 1.8 V, fout = 100 MHz 0.15 0.275 0.40 Vpp Vcross- delta Absolute crossing point voltage variation VDD = 3.3 V / 2.5 V / 1.8 V, fout = 100 MHz 0.14 V dV/dt Output slew rate 50 Ω to ground; DC coupled load; measured slew rate in ±150 mV from center. 2 12 V/ns www.ti.com LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LMK6C LMK6D LMK6H LMK6P

over recommended operating conditions, typical temperature = 25°C, frequency output = 156.25 MHz, VDD = 3.3 V, LVCMOS output capacitor load = 2.2 pF (unless otherwise specified)(4) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ΔdV/dt Output slew rate variation 20 % ODC Output duty cycle 45 50 55 % LVCMOS Output Characteristics Fout Output frequency 1 200 MHz VOL Output low voltage IOL = 3.6 mA, VDD = 1.8 V 0.36 V IOL = 5.0 mA, VDD = 2.5 V 0.5 V IOL = 6.6 mA, VDD = 3.3 V 0.66 V VOH Output high voltage IOH = 3.6 mA, VDD = 1.8 V 1.44 V IOH = 5.0 mA, VDD = 2.5 V 2 V IOH = 6.6 mA, VDD = 3.3 V 2.64 V tR/tF Output rise/fall time 20% to 80% of VOH – VOL, CL = 2 pF 0.5 1 ns ODC Output duty cycle 45 50 55 % Rout Output impedance OE = HIGH 40 50 60 Ω CL Maximum capacitive load Fout > 50 MHz(3) 15 pF Fout < 50 MHz(3) 30 pF Function Pin Input Characteristics (OE/ST Pin) VIL Input low voltage 0.6 V VIH Input high voltage 1.3 V IIL Input low current OE = GND –40 µA IIH Input high current OE = VDD 40 µA CIN Input capacitance 2 pF LVDS, HCSL and LVPECL Frequency Tolerance FT Total frequency stability Inclusive of: solder shift, initial tolerance, variation over –40℃ to 85℃, variation over rated supply voltage range, and 10 year aging at 25℃. –25 25 ppm Inclusive of: solder shift, initial tolerance, variation over –40℃ to 85℃, variation over supply voltage range. –20 20 ppm LVCMOS Frequency Tolerance FT Total frequency stability Inclusive of: solder shift, initial tolerance, variation over –40℃ to 105℃, variation over rated supply voltage range, and 10 year aging at 25℃. –25 25 ppm Inclusive of: solder shift, initial tolerance, variation over –40℃ to 105℃, variation over rated supply voltage range. –20 20 ppm Differential Output PSRR Characteristics PSRR Spur induced by 50 mV power supply ripple at 156.25 MHz output, VDD = 2.5 V/3.3 V, No power supply decoupling capacitor Sine wave at 50 kHz –71 dBc Sine wave at 100 kHz –71 dBc Sine wave at 500 kHz –72 dBc Sine wave at 1 MHz –70 dBc PSRR Spur induced by 50 mV power supply ripple at 156.25 MHz output, VDD = 1.8 V, no power supply decoupling capacitor Sine wave at 50 kHz –64 dBc Sine wave at 100 kHz –64 dBc Sine wave at 500 kHz –67 dBc Sine wave at 1 MHz –68 dBc PSRR Jitter sensitivity to power supply ripple 100 kHz sine wave ripple, 3.3 V supply(2) 4 fs/mV LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

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over recommended operating conditions, typical temperature = 25°C, frequency output = 156.25 MHz, VDD = 3.3 V, LVCMOS output capacitor load = 2.2 pF (unless otherwise specified)(4) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVCMOS PSRR Characteristics PSRR Spur induced by 50 mV power supply ripple at 50 MHz output, VDD = 2.5 V/3.3 V, no power supply decoupling capacitor Sine wave at 50 kHz –72 dBc Sine wave at 100 kHz –71 dBc Sine wave at 500 kHz –70 dBc Sine wave at 1 MHz –69 dBc PSRR Spur induced by 50 mV power supply ripple at 50 MHz output, VDD = 1.8 V, no power supply decoupling capacitor Sine wave at 50 kHz –50 dBc Sine wave at 100 kHz –50 dBc Sine wave at 500 kHz –52 dBc Sine wave at 1 MHz –55 dBc PSRR Jitter sensitivity to power supply ripple; 100 kHz sine wave ripple, 3.3 V supply(2) 10 fs/mV Power-On Characteristics tSTART_UP Start-up Time Time elapsed from 0.95 x VDD until output is enabled and output is within specification 5 ms tOE-EN Output enable time Time elapsed from OE = VIH until output is enabled and output is within specification, Fout > 10 MHz 25 µs tOE-DIS Output disable time Time elapsed from OE = VIL until output is disabled, Fout > 10 MHz 1 µs LVPECL - Clock Output Jitter RJ RMS jitter (integration BW: 12 kHz to 20 MHz) Fout = 156.25 MHz 100 125 fs PN1k Phase noise at 1 kHz offset Fout = 156.25 MHz. –95 dBc/Hz PN10k Phase noise at 10 kHz offset –127 dBc/Hz PN100k Phase noise at 100 kHz offset –146 dBc/Hz PN1M Phase Noise at 1 MHz offset –156 dBc/Hz PN10M Phase Noise at 10 MHz offset –158 dBc/Hz RJ RMS jitter (integration BW: 12 kHz to 20 MHz) Fout = 312.5 MHz 100 125 fs PN1k Phase noise at 1 kHz offset Fout = 312.5 MHz. –89 dBc/Hz PN10k Phase noise at 10 kHz offset –121 dBc/Hz PN100k Phase noise at 100 kHz offset –140 dBc/Hz PN1M Phase noise at 1 MHz offset –150 dBc/Hz PN10M Phase noise at 10 MHz offset –154 dBc/Hz RJ RMS jitter (integration BW: 12 kHz to 20 MHz) Fout = 100 MHz 125 170 fs Fout = 125 MHz 100 125 fs Fout = 155.52 MHz 100 125 fs Fout = 161.1328125 MHz 110 150 fs Fout = 200 MHz 120 150 fs Fout = 400 MHz 100 135 fs RPeriodJITT ,RMS RMS period jitter Fout ≥ 25 MHz 1.7 ps RJITT,PK- PK Peak-peak period jitter Fout ≥ 25 MHz 13 ps LVDS - Clock Output Jitter RJ RMS jitter (integration BW: 12 kHz to 20 MHz) Fout = 156.25 MHz 100 125 fs www.ti.com LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LMK6C LMK6D LMK6H LMK6P

over recommended operating conditions, typical temperature = 25°C, frequency output = 156.25 MHz, VDD = 3.3 V, LVCMOS output capacitor load = 2.2 pF (unless otherwise specified)(4) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PN1k Phase noise at 1 kHz offset Fout = 156.25 MHz –95 dBc/Hz PN10k Phase noise at 10 kHz offset –128 dBc/Hz PN100k Phase noise at 100 kHz offset –146 dBc/Hz PN1M Phase noise at 1 MHz offset –156 dBc/Hz PN10M Phase noise at 10 MHz offset –156.5 dBc/Hz RJ RMS jitter (integration BW: 12 kHz to 20 MHz) Fout = 312.5 MHz 100 125 fs PN1k Phase noise at 1 kHz offset Fout = 312.5 MHz. –89 dBc/Hz PN10k Phase noise at 10 kHz offset –122 dBc/Hz PN100k Phase noise at 100 kHz offset –139 dBc/Hz PN1M Phase noise at 1 MHz offset –150 dBc/Hz PN10M Phase noise at 10 MHz offset –153.5 dBc/Hz RJ RMS jitter (integration BW: 12 kHz to 20 MHz) Fout = 100 MHz 140 170 fs Fout = 125 MHz 110 125 fs Fout = 155.52 MHz 105 140 fs Fout = 161.1328125 MHz 125 160 fs Fout = 200 MHz 125 150 fs Fout = 400 MHz 100 135 fs RPeriodJIT T,RMS RMS period jitter Fout ≥ 25 MHz 1.6 ps RJITT,PK- PK Peak-peak period jitter Fout ≥ 25 MHz 13 ps HCSL - Clock Output Jitter JPCIe1-cc PCIe Gen 1 common clock jitter (jitter limit = 86 ps) Fout = 100 MHz 0.146 6.4 ps JPCIe1- SRNS PCIe Gen 1 SRNS jitter 0.447 6.99 ps JPCIe2-cc PCIe Gen 2 common clock jitter (jitter limit = 3 ps) 0.103 0.554 ps JPCIe2- SRNS PCIe Gen 2 SRNS jitter 0.135 0.56 ps JPCIe3-cc PCIe Gen 3 common clock jitter (jitter limit = 1 ps) 0.029 0.164 ps JPCIe3- SRNS PCIe Gen 3 SRNS jitter 0.033 0.180 ps JPCIe4-cc PCIe Gen 4 common clock jitter (jitter limit = 500 fs) 0.029 0.164 ps JPCIe4- SRNS PCIe Gen 4 SRNS jitter 0.033 0.180 ps JPCIe5-cc PCIe Gen 5 common clock jitter (jitter limit = 150 fs) 0.007 0.070 ps JPCIe5- SRNS PCIe Gen 5 SRNS jitter 0.007 0.074 ps JPCIe6-cc PCIe Gen 6 common clock jitter (jitter limit = 100 fs) 0.007 0.042 ps JPCIe6- SRNS PCIe Gen 6 SRNS jitter 0.009 0.052 ps RJ RMS jitter (integration BW: 12 kHz to 20 MHz) Fout = 156.25 MHz 100 125 fs LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

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over recommended operating conditions, typical temperature = 25°C, frequency output = 156.25 MHz, VDD = 3.3 V, LVCMOS output capacitor load = 2.2 pF (unless otherwise specified)(4) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PN1k Phase noise at 1 kHz offset Fout = 156.25 MHz. –95 dBc/Hz PN10k Phase noise at 10 kHz offset –127 dBc/Hz PN100k Phase noise at 100 kHz offset –146 dBc/Hz PN1M Phase noise at 1 MHz offset –156 dBc/Hz PN10M Phase noise at 10 MHz offset –158 dBc/Hz RJ RMS jitter (integration BW: 12 kHz to 20 MHz) Fout = 312.5 MHz 100 125 fs PN1k Phase noise at 1 kHz offset Fout = 312.5 MHz. –89 dBc/Hz PN10k Phase noise at 10 kHz offset –121 dBc/Hz PN100k Phase noise at 100 kHz offset –140 dBc/Hz PN1M Phase noise at 1 MHz offset –150 dBc/Hz PN10M Phase noise at 10 MHz offset –154 dBc/Hz RJ RMS jitter (integration BW: 12 kHz to 20 MHz) Fout = 100 MHz 125 170 fs Fout = 125 MHz 100 125 fs Fout = 155.52 MHz 100 125 fs Fout = 161.1328125 MHz 110 150 fs Fout = 200 MHz 120 150 fs Fout = 400 MHz 100 135 fs RPeriodJIT T,RMS RMS period jitter Fout ≥ 25 MHz 1.7 ps RJITT,PK- PK Peak-peak period jitter Fout ≥ 25 MHz 13 ps www.ti.com LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LMK6C LMK6D LMK6H LMK6P

over recommended operating conditions, typical temperature = 25°C, frequency output = 156.25 MHz, VDD = 3.3 V, LVCMOS output capacitor load = 2.2 pF (unless otherwise specified)(4) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVCMOS - Clock Output Jitter RJ RMS jitter (integration BW: 12 kHz to 20 MHz) Fout = 156.25 MHz 0.25 0.5 ps PN1k Phase noise at 1 kHz offset Fout = 156.25 MHz –100 dBc/Hz PN10k Phase noise at 10 kHz offset –128 dBc/Hz PN100k Phase noise at 100 kHz offset –143 dBc/Hz PN1M Phase noise at 1 MHz offset –150 dBc/Hz PN10M Phase noise at 10 MHz offset –152 dBc/Hz RJ RMS jitter (integration BW: 12 kHz to 5 MHz) Fout = 24 MHz 0.25 .5 ps Fout = 25 MHz 0.25 .5 ps Fout = 33.33 MHz 0.25 1 ps RMS jitter (integration BW: 12 kHz to 20 MHz) Fout = 40 MHz 0.5 1 ps Fout = 50 MHz 0.4 1 ps Fout = 66.66 MHz 0.5 1 ps Fout = 74.25 MHz 0.3 0.5 ps Fout = 78 MHz 0.35 0.5 ps Fout = 100 MHz 0.35 0.5 ps Fout = 125 MHz 0.35 0.5 ps RPeriodJIT T,RMS RMS period jitter Fout ≥ 25 MHz 1.5 ps RJITT,PK- PK Peak-peak period jitter Fout ≥ 25 MHz 13 ps (1) DC Load condition (2) Measured using TI LMK6x Evaluation Module; (3) Refer to the Application Curves section for Rise time and fall time details for different capacitor load values. (4) The Jitter specifications are based on design and characterization

7.8 Timing Diagrams

VOD = VOH - VOL OUTx_N OUTx_P VOUT-DIFF = 2 × VOD0 V 20% 80% tR tF VOH VOL Figure 7-1. Differential Output Voltage and Rise/Fall Time LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

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VOUT,SE tR tF OUT_REFx/2 20% 80% Figure 7-2. Single-Ended Output Voltage and Rise/Fall Time

7.9 Typical Characteristics

Frequency (MHz) Current Consumption (mA) 20 40 60 80 100 120 140 160 32.5 37.5 42.5 47.5 VDD = 1.8V Output Format = LVCMOS -40 o C o C 105 o C Figure 7-3. Current Consumption vs Frequency (LVCMOS, 1.8 V) Frequency (MHz) Current Consumption (mA) 20 40 60 80 100 120 140 160 VDD = 2.5 V OUTPUT FORMAT = LVCMOS -40 o C o C 105 o C Figure 7-4. Current Consumption vs Frequency (LVCMOS, 2.5 V) Frequency (MHz) Current Consumption (mA) 20 40 60 80 100 120 140 160 VDD = 3.3V OUTPUT FORMAT = LVCMOS -40 o C o C 105 o C Figure 7-5. Current Consumption vs Frequency (LVCMOS, 3.3 V) Frequency (MHz) Current Consumption (mA) 100 125 150 175 200 225 250 275 300 325 350 375 400 100 VDD = 1.8 V OUTPUT FORMAT = HCSL -40 o C o C o C Figure 7-6. Current Consumption vs Frequency (HCSL, 1.8 V) www.ti.com LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LMK6C LMK6D LMK6H LMK6P

7.9 Typical Characteristics (continued)

Figure 7-7. Current Consumption vs Frequency (HCSL, 2.5 V) Frequency (MHz) Current Consumption (mA) 100 125 150 175 200 225 250 275 300 325 350 375 400 100 VDD = 3.3 V OUTPUT FORMAT = HCSL -40 o C o C o C Figure 7-8. Current Consumption vs Frequency (HCSL, 3.3 V) Frequency (MHz) Current Consumption (mA) 50 100 150 200 250 300 350 400 100 VDD = 1.8 V OUTPUT FORMAT = LVPECL -40 o C o C o C Figure 7-9. Current Consumption vs Frequency (LVPECL, 1.8 V) Frequency (MHz) Current Consumption (mA) 100 125 150 175 200 225 250 275 300 325 350 375 400 100 VDD = 2.5 V OUTPUT FORMAT = LVPECL -40 o C o C o C Figure 7-10. Current Consumption vs Frequency (LVPECL, 2.5 V) Frequency (MHz) Current Consumption (mA) 100 125 150 175 200 225 250 275 300 325 350 375 400 100 VDD = 3.3 V OUTPUT FORMAT = LVPECL -40 o C o C o C Figure 7-11. Current Consumption vs Frequency (LVPECL, 3.3 V) Frequency (MHz) Current Consumption (mA) 100 125 150 175 200 225 250 275 300 325 350 375 400 100 VDD = 1.8 V OUTPUT FORMAT = LVDS -40 o C o C o C Figure 7-12. Current Consumption vs Frequency (LVDS, 1.8 V) LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

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Frequency (MHz) Current Consumption (mA) 100 125 150 175 200 225 250 275 300 325 350 375 400 100 VDD = 2.5 V OUTPUT FORMAT = LVDS -40 o C o C o C Figure 7-13. Current Consumption vs Frequency (LVDS, 2.5 V) Frequency (MHz) Current Consumption (mA) 100 125 150 175 200 225 250 275 300 325 350 375 400 100 VDD = 3.3 V OUTPUT FORMAT = LVDS -40 o C o C o C Figure 7-14. Current Consumption vs Frequency (LVDS, 3.3 V) Frequency (MHz) RMS Jitter (fs) 100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 175 180 185 190 195 200 100 105 110 115 120 125 130 135 140 145 150 155 160 Figure 7-15. RMS Jitter vs Frequency (100 MHz to 200 MHz) for LVPECL, HCSL; TYPICAL 3.3 V, 25°C Frequency (MHz) RMS Jitter (fs) 100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 175 180 185 190 195 200 100 105 110 115 120 125 130 135 140 145 150 155 160 Figure 7-16. RMS Jitter vs Frequency (100 MHz to 200 MHz) for LVDS; TYPICAL 3.3 V, 25°C Figure 7-17. RMS Jitter vs Frequency (200 MHz to 300 MHz) for LVPECL, HCSL; TYPICAL 3.3 V, 25°C Frequency (MHz) RMS Jitter (fs) 200 205 210 215 220 225 230 235 240 245 250 255 260 265 270 275 280 285 290 295 300 100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 Figure 7-18. RMS Jitter vs Frequency (200 MHz to 300 MHz) for LVDS; TYPICAL 3.3 V, 25°C Frequency (MHz) RMS Jitter (fs) 300 305 310 315 320 325 330 335 340 345 350 355 360 365 370 375 380 385 390 395 400 100 105 110 115 120 125 130 135 140 145 150 155 160 Figure 7-19. RMS Jitter vs Frequency (300 MHz to 400 MHz) for LVPECL, HCSL; TYPICAL 3.3 V, 25°C Frequency (MHz) RMS Jitter (fs) 300 305 310 315 320 325 330 335 340 345 350 355 360 365 370 375 380 385 390 395 400 100 105 110 115 120 125 130 135 140 145 150 155 160 Figure 7-20. RMS Jitter vs Frequency (300 MHz to 400 MHz) for LVDS; TYPICAL 3.3 V, 25°C www.ti.com LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LMK6C LMK6D LMK6H LMK6P

Frequency (MHz) RMS Jitter (fs) 40 45 50 55 60 65 70 75 80 85 90 95 100 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 Figure 7-21. RMS Jitter vs Frequency (Below 100 MHz) for LVPECL, HCSL; TYPICAL 3.3 V, 25°C Frequency (MHz) RMS Jitter (fs) 40 45 50 55 60 65 70 75 80 85 90 95 100 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 Figure 7-22. RMS Jitter vs Frequency (Below 100 MHz) for LVDS; TYPICAL 3.3 V, 25°C Frequency (MHz) RMS Jitter (fs) 100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 175 180 185 190 195 200 200 220 240 260 280 300 320 340 360 380 400 Figure 7-23. RMS Jitter vs Frequency ( 100 MHz - 200 MHz) for LVCMOS; TYPICAL 3.3 V, 25°C Frequency (MHz) RMS Jitter (fs) 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 Figure 7-24. RMS Jitter vs Frequency ( 10 MHz - 100 MHz) for LVCMOS; TYPICAL 3.3 V, 25°C Frequency (MHz) Duty Cycle (%) 25 50 75 100 125 150 175 200 1.8 V 2.5 V 3.3 V Figure 7-25. Duty Cycle (%) vs Frequency vs Power Supply; 25°C Temperature ( o Duty Cycle (%) -40 -20 0 20 40 60 80 100 1.8 V 2.5 V 3.3 V Figure 7-26. Duty Cycle (%) vs Temperature vs Power Supply; 50-MHz Frequency LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

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Frequency (MHz ) Duty Cycle (%) 25 50 75 100 125 150 175 200 47.5 52.5 57.5 -40 o C o C 105 o C Figure 7-27. Duty Cycle (%) vs Frequency Over Temperature Range for LVCMOS; 3.3 V www.ti.com LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LMK6C LMK6D LMK6H LMK6P

8 Parameter Measurement Information

8.1 Device Output Configurations

Figure 8-1. LMK6C Output Test Configuration LMK6C Device Phase Noise Analyzer Figure 8-2. LMK6C Output Phase Noise Test Configuration LMK6D Device Oscilloscope (50- inputs) Figure 8-3. LMK6D Output Test Configuration LMK6D Device Balun Phase Noise Analyzer Figure 8-4. LMK6D Output Phase Noise Configuration Rp Rp LMK6P Device Oscilloscope (50- inputs) Figure 8-5. LMK6P Output Test Configuration LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

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9 Detailed Description

9.1 Overview

The LMK6x is a fixed-frequency BAW based oscillator that can provide ultra-low jitter for both differential and single-ended output types.

9.2 Functional Block Diagram

VDD CLK_P GND Power Conditioning CLK_N OE / ST / NC Temp Sensor Frequency Control LogicOutput/Chip Control Logic BAW Fractional Output Divider Output driver

9.3 Feature Description

9.3.1 Bulk Acoustic Wave (BAW)

TI’s BAW resonator technology uses piezoelectric transduction to generate high-Q resonance at 2.5 GHz. The resonator is defined by the quadrilateral area overlaid by top and bottom electrodes. Alternating high- and low-acoustic impedance layers form acoustic mirrors beneath the resonant body to prevent acoustic energy leakage into the substrate. Furthermore, these acoustic mirrors are also placed on top of the resonator stack to protect the device from contamination and minimize energy leakage into the package materials. This unique dual-Bragg acoustic resonator (DBAR) allows efficient excitation without the need of costly vacuum cavities around the resonator. As a result, TI’s BAW resonator is immune to frequency drift caused by adsorption of surface contaminants and can be directly placed in a non-hermetic plastic package with the oscillator IC in small standard oscillator footprints. Refer to BAW for more details on BAW technology.

9.3.2 Device Block-Level Description

The device contains a BAW oscillator, a Fractional Output Divider (FOD), and output driver, which together generates a pre-programmed output frequency. Temperature variations of oscillation frequency are continuously monitored by internal precision temperature sensor and provided as input to the frequency control logic block. Using this frequency control logic block, frequency corrections are performed internally for maintaining the output frequency within ±25 ppm across temperature range and aging. The output driver is capable of providing both single-ended LVCMOS and differential LVPECL, LVDS, and HCSL output formats. The device contains an internal LDO which reduces the power supply noise, resulting in low noise clock output.

9.3.3 Function Pin(s)

Pin 1 on the LMK6C and pin 1 or pin 2 on the LMK6P, LMK6D, and LMK6H are the function pins which have multiple functions based on the orderable part number. The function can be used as Output Enable (OE), Stand By (ST) or No Connect (NC). Options for both Active High and Active Low are available for OE and ST. Contact TI for Active Low options. Table 9-1 lists the functions of pin 1 and pin 2 for differential output 6-pin packages and Table 9-2 lists the functions of pin 1 for single-ended outputs. LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

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Table 9-1. Function Pin Descriptions for 6-Pin Packages (LMK6D, LMK6H, LMK6P) ORDERABLE OPTION PIN DESCRIPTION OUTPUT FUNCTION OTHER FUNCTIONAL PIN CONFIGURATION E (Pin 1) Output Enable (Active High / NC) HIGH or No Connect : Output active at Specified Frequency LOW : Output disabled, high impedance; current consumption is given by IDD-PD Pin 2 can be left floating or grounded F (Pin 2) Output Enable (Active High / NC) HIGH or No Connect : Output active at Specified Frequency LOW : Output disabled, high impedance; current consumption is given by IDD-PD Pin 1 can be left floating or grounded A (Pin 1) Standby (Active Low) LOW : High Impedance; standby mode; current consumption is given by standby current IDD-STBY HIGH or No Connect : Output active at Specified Frequency Pin 2 can be left open or grounded B (Pin 2) Standby (Active Low) LOW : High Impedance; standby mode; current consumption is given by standby current IDD-STBY HIGH or No Connect : Output active at Specified Frequency Pin 1 can be left open or grounded Table 9-2. Function Pin Descriptions for 4-Pin Packages (LMK6C) ORDERABLE OPTION PIN DESCRIPTION OUTPUT FUNCTION E (Pin 1) Output Enable (Active High / NC) HIGH or No Connect : Output active at Specified Frequency LOW : Output disabled, high impedance; current consumption is given by IDD-PD A (Pin 1) Standby (Active Low) LOW : High Impedance; standby mode; current consumption is given by standby current IDD-STBY HIGH or No Connect : Output active at Specified Frequency In standby mode, all blocks are powered down to provide a maximum current consumption savings equivalent to the standby current provided in the Current Consumption Characteristics portion of the Electrical Characteristics table. The return to the output clock active time corresponds to same as the initial start-up time. The Function Pin is driven internally with resistance >100 kΩ.

9.3.4 Clock Output Interfacing and Termination

These figures show the recommended output interfacing and termination circuits. LMK6C Device LVCMOS Receiver Figure 9-1. LMK6C Output to LVCMOS Receiver www.ti.com LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LMK6C LMK6D LMK6H LMK6P

100 ΩLMK6D Device LVDS Receiver Figure 9-2. LMK6D Output DC-Coupled to LVDS Receiver With Internal Termination/Biasing LMK6D Device 100 Ω LVDS Receiver Figure 9-3. LMK6D Output AC Coupled to LVDS Receiver With Internal Termination/Biasing LMK6P Device LVPECL Receiver Vdd R1 R1 R2 R2 Figure 9-4. LMK6P Output DC-Coupled to LVPECL Receiver With External Termination/Biasing (T-Network) Table 9-3. LMK6P T-Network DC-Coupled Resistor Values SUPPLY (V) R1 (Ω) R2 (Ω) 3.3 133 82 2.5 250 62.5 1.8 450 56.5 LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

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Figure 9-7. LMK6P Output AC-Coupled to LVPECL Receiver With External Termination/Biasing (Y-Network) Table 9-6. LMK6P Y-Network AC-Coupled Resistor Values SUPPLY (V) Rp (Ω) R1 (Ω) R2 (Ω) 3.3 207.5 50 78.8 2.5 112.5 50 31.3 1.8 83.3 50 16.7 LMK6H Device HCSL Receiver 50Ω50Ω Figure 9-8. LMK6H Output to HCSL Receiver With External Termination LMK6H Device HCSL Receiver 50Ω50Ω Figure 9-9. LMK6H Output AC-Coupled to HCSL Receiver With External Termination

9.3.5 Temperature Stability

Figure 9-10 shows the frequency variation of the LMK6x differential output oscillator over the temperature range of –40°C to 85°C for total of 60 units. Figure 9-11 shows the frequency variation of the LMK6C single-ended output oscillator over the operating temperature range of –40°C to 105°C. These plots represent the typical temperature stability of the device, remaining below ±10 ppm. The devices are soldered onto the evaluation LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

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board as per the standard soldering profile and frequency variation measurements are carried out. The output frequency is 156.25 MHz for these tests. Temperature ( o Frequency Variation (PPM) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 -25 -20 -15 -10 Figure 9-10. Frequency Change Over Temperature (LMK6x Differential Output Device) Temperature ( O C) Frequency Variation (PPM) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 -25 -20 -15 -10 Figure 9-11. Frequency Change Over Temperature (LMK6C Single-Ended Output Device)

9.3.6 Mechanical Robustness

For reference oscillators, vibration and shock are common causes for increased phase noise and jitter, frequency shift and spikes, or even physical damages to the resonator and the package. Compared to quartz crystals, the BAW resonator is more immune to vibration and shock due to its orders of magnitude, smaller mass, and higher frequency, which means force applied to the device from acceleration is much smaller due to smaller mass. Figure 9-12 shows the LMK6x BAW oscillator vibration performance. In this test, the LMK6x oscillator mounted on an EVM is subject to 10g acceleration force, ranging from 50 Hz to 2 kHz in x, y, and z-axis. Phase noise trace with spur due to vibration is captured using Keysight E5052B and frequency deviation is calculated from the spur power. Then the frequency deviation is converted to ppb by noting the carrier frequency and normalized to ppb/g. Finally, the RMS sum of ppb/g along all three axes is reported as the Vibration sensitivity in ppb/g. LMK6x performance under vibration is approximately 2 ppb/g while most quartz oscillators best case is 3 ppb/g and worse can be above 10 ppb/g. www.ti.com LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: LMK6C LMK6D LMK6H LMK6P

Vibration Frequency (Hz) Vibration Sensitivity (ppb/g) 50 60 70 80 90 100 200 300 400 500 600 700 800 1000 2000 Figure 9-12. LMK6X BAW Oscillator Vibration Performance

9.4 Device Functional Modes

The LMK6x BAW Oscillator is a fixed output frequency device and does not require any programming. The device pin 1 (and pin 2 for a 6-pin device) has different functions. See the Function Pin(s) section for more information on the function pins. LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

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Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

10.1 Application Information

The LMK6x is high-performance, fixed-frequency oscillator that can be used as a reference clock. The product family supports any output frequency between 1 MHz to 400 MHz for differential LMK6D, LMK6H, LMK6P or 1 MHz to 200 MHz for singled-ended LVCMOS clock output types, and 1.8-V or 2.5-V through 3.3-V supply rails.

10.2 Typical Application

For reference schematic implementation for LMK6x family of oscillators, refer to the LMK6EVM User's Guide for bypass capacitor and AC-coupling capacitor value recommendations. Refer to the Clock Output Interfacing and Termination section for output clock required termination and biasing. Figure 10-1 shows a typical application example. The LMK6D differential oscillator is used as an input to the LVDS buffer input in this example. LMK6D Differential Oscillator - 156.25 MHz 100 ASIC / FPGA / PHY VDD Power Conditioning Output/Chip Control Logic 1 μF OE Output driver GND CLK_ P CLK_ N Figure 10-1. Application Example

10.2.1 Design Requirements

The LMK6x is a fixed-frequency oscillator with no programming needed. Make sure to follow the recommended termination options as described in the Clock Output Interfacing and Termination section closely. Refer to the Function Pin(s) section to understand the pin 1 and pin 2 functions, and order the part number as per your requirements for Output Enable (OE), Standby (ST) options.

10.2.2 Detailed Design Procedure

The LMK6x has three different options for differential output which are LVDS, LVPECL, HCSL type and one LVCMOS single-ended output type. For designing with the any of the oscillator output type in actual system, use the proper AC or DC termination based on the application requirement. Refer to the Clock Output Interfacing and Termination section for the details of all the AC and DC termination schemes and use the appropriate option. The figures in this section have all the AC and DC coupling options with the termination resistor values. The LMK6x has an integrated LDO and has excellent PSRR performance as shown in the Electrical Characteristics table. Refer to the LMK6EVM for the reference layout recommendation while designing the LMK6x BAW oscillator. For the Function Pin 1 of LMK6C, connect typical 10-kΩ or less resistor to VDD for driving the OE pin High. Note this pin can be left open if you do not want to use pullup resistor as the device has > 100-k Ω internal pullup resistor. For driving the OE pin to Low, use the typical 10 k Ω or less resistor as a pulldown resistor. For the Function Pin 1 or Functional Pin 2 for LMK6D, LMK6H, LMK6P, you can use the similar approach described for LMK6C. www.ti.com LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: LMK6C LMK6D LMK6H LMK6P

10.2.3 Application Curves

The LMK6C LVCMOS output connects to different load capacitances based on the actual application use case in a system. With the different load capacitance, the rise time / fall time varies for the specific output frequency. The following graphs shows the Rise / Fall time for load capacitance of 2.2 pF, 4.7 pF, 10 pF, 15 pF and 22 pF for temperature range from –40°C to 105°C. Temperature ( o Rise / Fall time (ps) -40 -20 0 20 40 60 80 100 300 600 900 1200 1500 1800 2100 2400 2700 3000 0 pF 2.2 pF 4.7 pF 10 pF 15 pF 22 pF Figure 10-2. Rise / Fall time (ps) vs Temperature for 25-MHz Output Frequency, 3.3-V Supply Temperature ( o Rise / Fall time (ps) -40 -20 0 20 40 60 80 100 300 600 900 1200 1500 1800 2100 2400 2700 3000 0 pF 2.2 pF 4.7 pF 10 pF 15 pF 22 pF Figure 10-3. Rise / Fall time (ps) vs Temperature for 50-MHz Output Frequency, 3.3-V Supply LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

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Supply Voltage (V) Rise / Fall time (ps) 300 600 900 1200 1500 1800 2100 2400 2700 3000 Temp = 25 o C Frequency = 50 MHz 0 pF 2.2 pF 4.7 pF 10 pF 15 pF 22 pF Figure 10-6. Rise / Fall time (ps) vs Supply Voltage vs Load Capacitance

10.3 Power Supply Recommendations

For the best electrical performance of the LMK6x, TI recommends use 1 µF capacitor on the device power supply bypass network. TI also recommends using component side mounting of the power-supply bypass capacitors, and best to use 0201 or 0402 body size capacitors to facilitate signal routing. Keep the connections between the bypass capacitors and the power supply on the device as short as possible. Ground the other side of the capacitor using a low impedance connection to the ground plane.

10.4 Layout

10.4.1 Layout Guidelines

The following sections provide recommendations for board layout, solder reflow profile and power-supply bypassing when using the LMK6x to ensure good thermal and electrical performance and signal integrity of the entire system.

10.4.1.1 Ensuring Thermal Reliability

The LMK6x is a high-performance device. Therefore, pay careful attention to device configuration and printed circuit board (PCB) layout with respect to power consumption. The ground pin must be connected to the ground plane of the PCB through three vias or more to maximize thermal dissipation out of the package. The equation below describes the relationship between the PCB temperature around the LMK6x and its junction temperature. TB = TJ – ΨJB × P (1) where

TB: PCB temperature around the LMK6x
TJ: Junction temperature of LMK6x
ΨJB: Junction-to-board thermal resistance parameter of LMK6x (refer to the Thermal Information tables in the Specifications section for this information)
P: On-chip power dissipation of LMK6x LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

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10.4.1.2 Recommended Solder Reflow Profile

TI recommends following the solder paste supplier's recommendations to optimize flux activity and to achieve proper melting temperatures of the alloy within the guidelines of J-STD-20. It is preferable for the LMK6x to be processed with the lowest peak temperature possible while also remaining below the components peak temperature rating as listed on the MSL label. The exact temperature profile would depend on several factors including maximum peak temperature for the component as rated on the MSL label, Board thickness, PCB material type, PCB geometries, component locations, sizes, densities within PCB, as well solder manufactures recommended profile, and capability of the reflow equipment to as confirmed by the SMT assembly operation. www.ti.com LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: LMK6C LMK6D LMK6H LMK6P

10.4.2 Layout

Refer to the LMK6EVM User's Guide for printed circuit board layout examples for LMK6D, LMK6H, LMK6P and LMK6C devices. The figured below show the PCB layout example as done on the evaluation module for the LMK6x EVM. Figure 10-7. PCB Layout Example From LMK6 EVM - Top Layer Figure 10-8. PCB Layout Example From LMK6 EVM - GND Layer 1 LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

Product Folder Links: LMK6C LMK6D LMK6H LMK6P

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation, see the following:

Texas Instruments, LMK6EVM User's Guide
Texas Instruments, Standalone BAW Oscillators Advantages Over Quartz Oscillators application note
Texas Instruments, BAW oscillator solutions for Building Automation application note
Texas Instruments, BAW oscillator solutions for Factory Automation application note
Texas Instruments, BAW oscillator solutions for Grid Infrastructure application note
Texas Instruments, BAW oscillator solutions for Optical Modules application note

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

11.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

Product Folder Links: LMK6C LMK6D LMK6H LMK6P

0.1 C A B

0.05 C B SYMM SYMM 2.6 2.4 3.3 3.1 PIN 1 INDEX AREA 1.0 0.8 0.05 0.00 (0.1) TYP SEATING PLANE C 1.7 1.9 4X 0.95 6X 0.7 0.5 4X 0.75 0.65 2X 0.55 0.45 0.05 C PIN 1 ID (OPTIONAL) 3 4 www.ti.com LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: LMK6C LMK6D LMK6H LMK6P

NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . EXAMPLE BOARD LAYOUT 4224885/B 10/2020 www.ti.com VSON - 1 mm max heightDLE0006A PLASTIC QUAD FLAT PACK-NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X SOLDER MASK DETAILS NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED EXPOSED METAL

0.07 MAX

0.07 MIN

(1.7) (0.95) (1.9) 6X (0.6) 4X (0.7) 2X (0.5) (R0.05) TYP 3 4 LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

Product Folder Links: LMK6C LMK6D LMK6H LMK6P

NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4224885/B 10/2020 www.ti.com VSON - 1 mm max heightDLE0006A PLASTIC QUAD FLAT PACK-NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE: 20X SYMM SYMM (1.7) (0.95) (1.9) 6X (0.6) 4X (0.65) 2X (0.5) (R0.05) TYP 3 4 www.ti.com LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: LMK6C LMK6D LMK6H LMK6P

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. PACKAGE OUTLINE 4225945/B 10/2020 www.ti.com VSON - 1 mm max height PLASTIC QUAD FLAT PACK-NO LEAD DLE0004A A 0.08 C 0.05 C B SYMM SYMM 2.6 2.4 3.3 3.1 PIN 1 INDEX AREA 1.0 0.8 0.05 0.00 (0.1) TYP SEATING PLANE C 1.6 2.1 4X 0.7 0.5 4X 0.75 0.65 PIN 1 ID (OPTIONAL) 2 3 1.05 LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

Product Folder Links: LMK6C LMK6D LMK6H LMK6P

NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . EXAMPLE BOARD LAYOUT 4225945/B 10/2020 www.ti.com VSON - 1 mm max heightDLE0004A PLASTIC QUAD FLAT PACK-NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X SOLDER MASK DETAILS NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED EXPOSED METAL (1.6) (1.05) TYP (2.1) 4X (0.6) 4X (0.7) (R0.05) TYP 2 3 www.ti.com LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: LMK6C LMK6D LMK6H LMK6P

NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4225945/B 10/2020 www.ti.com VSON - 1 mm max heightDLE0004A PLASTIC QUAD FLAT PACK-NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE ALL PADS: 93% SCALE: 20X SYMM SYMM (1.6) (1.05) TYP (2.1) 4X (0.6) 4X (0.65) (R0.05) TYP 2 3 LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

Product Folder Links: LMK6C LMK6D LMK6H LMK6P

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. PACKAGE OUTLINE 4224884/B 10/2020 www.ti.com VSON - 1 mm max height PLASTIC QUAD FLAT PACK-NO LEAD DLF0006A A 0.08 C 0.05 C B SYMM SYMM 2.1 1.9 2.6 2.4 PIN 1 INDEX AREA 1.0 0.8 0.05 0.00 (0.1) TYP SEATING PLANE C 1.3 1.65 4X 0.825 6X 0.8 0.6 4X 0.7 0.6 2X 0.3 0.2 0.05 C PIN 1 ID (OPTIONAL) 3 4 www.ti.com LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: LMK6C LMK6D LMK6H LMK6P

NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . EXAMPLE BOARD LAYOUT 4224884/B 10/2020 www.ti.com VSON - 1 mm max heightDLF0006A PLASTIC QUAD FLAT PACK-NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X SOLDER MASK DETAILS NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED EXPOSED METAL (1.5) (0.825) (1.65) 6X (0.9) 4X (0.65) 2X (0.25) (R0.05) TYP 3 4 LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

Product Folder Links: LMK6C LMK6D LMK6H LMK6P

NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4224884/B 10/2020 www.ti.com VSON - 1 mm max heightDLF0006A PLASTIC QUAD FLAT PACK-NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE: 20X SYMM SYMM (1.5) (0.825) (1.65) 6X (0.9) 4X (0.6) 2X (0.25) (R0.05) TYP 3 4 www.ti.com LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: LMK6C LMK6D LMK6H LMK6P

www.ti.com VSON - 1 mm max heightPLASTIC QUAD FLAT PACK-NO LEADDLF0004AA 0.08C 0.1CAB0.05C B SYMMSYMM 2.11.92.62.4PIN 1 INDEX AREA 1.650.825 6X 0.80.64X 0.70.6PIN 1 ID(OPTIONAL)1 2 3 LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

Product Folder Links: LMK6C LMK6D LMK6H LMK6P

NOTES: (continued)3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). EXAMPLE BOARD LAYOUT 4225946/C 12/2022 www.ti.com VSON - 1 mm max heightDLF0004APLASTIC QUAD FLAT PACK-NO LEAD SYMMSYMM LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE: 20X SOLDER MASK DETAILSNON- SOLDER MASKDEFINED(PREFERRED)SOLDER MASKDEFINEDEXPOSED METAL0.07 MAXALL AROUNDMETALSOLDER MASKOPENING0.07 MINALL AROUNDEXPOSED METALMETAL UNDERSOLDER MASKSOLDER MASKOPENING 2 3 www.ti.com LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: LMK6C LMK6D LMK6H LMK6P

NOTES: (continued)4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternatedesign recommendations. EXAMPLE STENCIL DESIGN 4225946/C 12/2022 www.ti.com VSON - 1 mm max heightDLF0004APLASTIC QUAD FLAT PACK-NO LEAD SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCILPRINTED SOLDER COVERAGE BY AREA UNDER PACKAGEPADS 1,3,4 & 6: 92%SCALE: 20X 2 3 LMK6C, LMK6D, LMK6H, LMK6P SNAS826D – APRIL 2022 – REVISED FEBRUARY 2023 www.ti.com

Product Folder Links: LMK6C LMK6D LMK6H LMK6P

www.ti.com 28-Oct-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LMK6CE012288CDLFR ACTIVE VSON DLF 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LCBJ Samples LMK6CE012288CDLFT ACTIVE VSON DLF 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LCBJ Samples LMK6CE02500CDLFR ACTIVE VSON DLF 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LCBG Samples LMK6CE02500CDLFT ACTIVE VSON DLF 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LCBG Samples LMK6CE02500DDLFR ACTIVE VSON DLF 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LC1G Samples LMK6CE02500DDLFT ACTIVE VSON DLF 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LC1G Samples LMK6CE03333CDLER ACTIVE VSON DLE 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 HCB8 Samples LMK6CE03333CDLET ACTIVE VSON DLE 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 HCB8 Samples LMK6CE04000CDLFR ACTIVE VSON DLF 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 HCB6 Samples LMK6CE04000CDLFT ACTIVE VSON DLF 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 HCB6 Samples LMK6CE04800DDLFR ACTIVE VSON DLF 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LC1C Samples LMK6CE04800DDLFT ACTIVE VSON DLF 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LC1C Samples LMK6CE05000CDLFR ACTIVE VSON DLF 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LCCB Samples LMK6CE05000CDLFT ACTIVE VSON DLF 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LCCB Samples LMK6CE07425DDLFR ACTIVE VSON DLF 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LC19 Samples LMK6CE07425DDLFT ACTIVE VSON DLF 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LC19 Samples LMK6CE12500CDLER ACTIVE VSON DLE 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LCB6 Samples LMK6CE12500CDLET ACTIVE VSON DLE 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LCB6 Samples LMK6CE15625DDLFR ACTIVE VSON DLF 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LC12 Samples LMK6CE15625DDLFT ACTIVE VSON DLF 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 LC12 Samples Addendum-Page 1

www.ti.com 28-Oct-2023 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LMK6DA05184ADLER ACTIVE VSON DLE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 105 HDAH Samples LMK6DA05184ADLET ACTIVE VSON DLE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM HDAH Samples LMK6DA12288ADLER ACTIVE VSON DLE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HDA4 Samples LMK6DA12288ADLET ACTIVE VSON DLE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HDA4 Samples LMK6DA12500ADLFR ACTIVE VSON DLF 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LDA6 Samples LMK6DA12500ADLFT ACTIVE VSON DLF 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LDA6 Samples LMK6DA15552ADLER ACTIVE VSON DLE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HDA3 Samples LMK6DA15552ADLET ACTIVE VSON DLE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HDA3 Samples LMK6DA20000ADLER ACTIVE VSON DLE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HDA1 Samples LMK6DA20000ADLET ACTIVE VSON DLE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HDA1 Samples LMK6HA10000ADLER ACTIVE VSON DLE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LHA8 Samples LMK6HA10000ADLET ACTIVE VSON DLE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LHA8 Samples LMK6HA10000ADLFR ACTIVE VSON DLF 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LHA8 Samples LMK6HA10000ADLFT ACTIVE VSON DLF 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LHA8 Samples LMK6HA10000BDLFR ACTIVE VSON DLF 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LH18 Samples LMK6HA10000BDLFT ACTIVE VSON DLF 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LH18 Samples LMK6HA15625ADLER ACTIVE VSON DLE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LHA2 Samples LMK6HA15625ADLET ACTIVE VSON DLE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LHA2 Samples LMK6PA15625ADLER ACTIVE VSON DLE 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LPA2 Samples LMK6PA15625ADLET ACTIVE VSON DLE 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LPA2 Samples LMK6PA15625ADLFR ACTIVE VSON DLF 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LPA2 Samples Addendum-Page 2

www.ti.com 28-Oct-2023 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LMK6PA15625ADLFT ACTIVE VSON DLF 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LPA2 Samples PLMK6CE01920CDLFT ACTIVE VSON DLF 4 250 TBD Call TI Call TI -40 to 105 Samples PLMK6CE02400CDLET ACTIVE VSON DLE 4 250 TBD Call TI Call TI -40 to 105 Samples PLMK6CE02500CDLET ACTIVE VSON DLE 4 250 TBD Call TI Call TI -40 to 105 Samples PLMK6CE04000CDLFT ACTIVE VSON DLF 4 250 TBD Call TI Call TI -40 to 105 Samples PLMK6CE15625CDLFT ACTIVE VSON DLF 4 250 TBD Call TI Call TI -40 to 105 PCEC Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 3

www.ti.com 28-Oct-2023 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 4-Nov-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 4-Nov-2023 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 4-Nov-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMK6CE012288CDLFR VSON DLF 4 3000 182.0 182.0 20.0 LMK6CE012288CDLFT VSON DLF 4 250 182.0 182.0 20.0 LMK6CE02500CDLFR VSON DLF 4 3000 210.0 185.0 35.0 LMK6CE02500CDLFT VSON DLF 4 250 210.0 185.0 35.0 LMK6CE02500DDLFR VSON DLF 4 3000 182.0 182.0 20.0 LMK6CE02500DDLFT VSON DLF 4 250 182.0 182.0 20.0 LMK6CE03333CDLER VSON DLE 4 3000 346.0 346.0 33.0 LMK6CE03333CDLET VSON DLE 4 250 182.0 182.0 20.0 LMK6CE04000CDLFR VSON DLF 4 3000 210.0 185.0 35.0 LMK6CE04000CDLFT VSON DLF 4 250 210.0 185.0 35.0 LMK6CE04800DDLFR VSON DLF 4 3000 182.0 182.0 20.0 LMK6CE04800DDLFT VSON DLF 4 250 182.0 182.0 20.0 LMK6CE05000CDLFR VSON DLF 4 3000 182.0 182.0 20.0 LMK6CE05000CDLFT VSON DLF 4 250 182.0 182.0 20.0 LMK6CE07425DDLFR VSON DLF 4 3000 182.0 182.0 20.0 LMK6CE07425DDLFT VSON DLF 4 250 182.0 182.0 20.0 LMK6CE12500CDLER VSON DLE 4 3000 346.0 346.0 33.0 LMK6CE12500CDLET VSON DLE 4 250 182.0 182.0 20.0 Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 4-Nov-2023 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMK6CE15625DDLFR VSON DLF 4 3000 210.0 185.0 35.0 LMK6CE15625DDLFT VSON DLF 4 250 210.0 185.0 35.0 LMK6DA05184ADLER VSON DLE 6 3000 346.0 346.0 33.0 LMK6DA05184ADLET VSON DLE 6 250 182.0 182.0 20.0 LMK6DA12288ADLER VSON DLE 6 3000 346.0 346.0 33.0 LMK6DA12288ADLET VSON DLE 6 250 210.0 185.0 35.0 LMK6DA12500ADLFR VSON DLF 6 3000 210.0 185.0 35.0 LMK6DA12500ADLFT VSON DLF 6 250 210.0 185.0 35.0 LMK6DA15552ADLER VSON DLE 6 3000 346.0 346.0 33.0 LMK6DA15552ADLET VSON DLE 6 250 210.0 185.0 35.0 LMK6DA20000ADLER VSON DLE 6 3000 346.0 346.0 33.0 LMK6DA20000ADLET VSON DLE 6 250 210.0 185.0 35.0 LMK6HA10000ADLER VSON DLE 6 3000 346.0 346.0 33.0 LMK6HA10000ADLET VSON DLE 6 250 210.0 185.0 35.0 LMK6HA10000ADLFR VSON DLF 6 3000 210.0 185.0 35.0 LMK6HA10000ADLFT VSON DLF 6 250 210.0 185.0 35.0 LMK6HA10000BDLFR VSON DLF 6 3000 182.0 182.0 20.0 LMK6HA10000BDLFT VSON DLF 6 250 182.0 182.0 20.0 LMK6HA15625ADLET VSON DLE 6 250 182.0 182.0 20.0 LMK6PA15625ADLER VSON DLE 6 3000 346.0 346.0 33.0 LMK6PA15625ADLET VSON DLE 6 250 182.0 182.0 20.0 LMK6PA15625ADLFR VSON DLF 6 3000 210.0 185.0 35.0 LMK6PA15625ADLFT VSON DLF 6 250 210.0 185.0 35.0 Pack Materials-Page 4

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VSON - 1 mm max heightDLF 6 PLASTIC SMALL OUTLINE - NO LEAD2 x 2.5, multiple pitch 4229715/A

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. PACKAGE OUTLINE 4224884/B 10/2020 www.ti.com VSON - 1 mm max height PLASTIC QUAD FLAT PACK-NO LEAD DLF0006A A 0.08 C 0.05 C B SYMM SYMM 2.1 1.9 2.6 2.4PIN 1 INDEX AREA 1.0 0.8 0.05 0.00 (0.1) TYP SEATING PLANE C 1.3 1.65 4X 0.825 6X 0.8 0.6 4X 0.7 0.6 2X 0.3 0.2 0.05 C PIN 1 ID (OPTIONAL) 3 4

NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4224884/B 10/2020 www.ti.com VSON - 1 mm max heightDLF0006A PLASTIC QUAD FLAT PACK-NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE: 20X SYMM SYMM (1.5) (0.825) (1.65) 6X (0.9) 4X (0.6) 2X (0.25) (R0.05) TYP 3 4

NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4225945/B 10/2020 www.ti.com VSON - 1 mm max heightDLE0004A PLASTIC QUAD FLAT PACK-NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE ALL PADS: 93% SCALE: 20X SYMM SYMM (1.6) (1.05) TYP (2.1) 4X (0.6) 4X (0.65) (R0.05) TYP 2 3

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VSON - 1 mm max heightDLE 6 PLASTIC SMALL OUTLINE - NO LEAD2.5 x 3.2, multiple pitch 4229714/A

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. PACKAGE OUTLINE 4224885/B 10/2020 www.ti.com VSON - 1 mm max height PLASTIC QUAD FLAT PACK-NO LEAD DLE0006A A 0.08 C 0.05 C B SYMM SYMM 2.6 2.4 3.3 3.1 PIN 1 INDEX AREA 1.0 0.8 0.05 0.00 (0.1) TYP SEATING PLANE C 1.7 1.9 4X 0.95 6X 0.7 0.5 4X 0.75 0.65 2X 0.55 0.45 0.05 C PIN 1 ID (OPTIONAL) 3 4

NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4224885/B 10/2020 www.ti.com VSON - 1 mm max heightDLE0006A PLASTIC QUAD FLAT PACK-NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE: 20X SYMM SYMM (1.7) (0.95) (1.9) 6X (0.6) 4X (0.65) 2X (0.5) (R0.05) TYP 3 4

NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . EXAMPLE BOARD LAYOUT 4225946/D 03/2023 www.ti.com VSON - 1 mm max heightDLF0004A PLASTIC QUAD FLAT PACK-NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X SOLDER MASK DETAILS NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED EXPOSED METAL (1.5) (0.825) (1.65) 4X (0.9) 4X (0.65) (R0.05) TYP 2 3

NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4225946/D 03/2023 www.ti.com VSON - 1 mm max heightDLF0004A PLASTIC QUAD FLAT PACK-NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE: 20X SYMM SYMM (1.5) (0.825) (1.65) 4X (0.9) 4X (0.6) (R0.05) TYP 2 3

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Product Information

PLMK6CE02400CDLET specifications and overview.

Summary

LMK6x Low Jitter, High-Performance BAW Oscillator REVISED FEBRUARY 2023

Description

LMK6x Low Jitter, High-Performance BAW Oscillator REVISED FEBRUARY 2023

Source title PLMK6CE02400CDLET Datasheet(PDF) - Texas Instruments

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