PLMK00804BQWRGTTQ1

LMK00804B-Q1 TI1 | Alldatasheet

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Technical content

ADVANCE□INFORMATION PD PD PU/ PD LVCMOS _CLK CLK_P CLK_N CLK_EN PU D Q CLK_SEL PU Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. LMK00804B-Q1 SNAS784 – MARCH 2019 LMK00804B-Q11.5-Vto3.3-V,1-to-4high-performanceLVCMOSfan-outbufferandlevel translator

1 Features

1• AEC-Q100 qualified with the following results: – Device temperature grade 1: –40°C to +125°C, TA

Four LVCMOS/LVTTL outputs supporting 1.5-V to 3.3-V levels – Additive jitter: 0.1-ps RMS (typical) at 40 MHz – Noise floor: –168 dBc/Hz (typical) at 40 MHz – Output frequency: 350 MHz (maximum) – Output skew: 35 ps (maximum) – Part-to-part skew: 700 ps (maximum)
Two selectable inputs – CLK_P, CLK_N pair accepts LVPECL, LVDS, HCSL, SSTL, LVHSTL, or LVCMOS/LVTTL – LVCMOS_CLK accepts LVCMOS/LVTTL
Synchronous clock enable
Core/output power supplies: – 3.3 V/3.3 V – 3.3 V/2.5 V – 3.3 V/1.8 V – 3.3 V/1.5 V
Package: 16-pin VQFN

2 Applications

Advanced Driver Assistance Systems (ADAS) – Front long range radar – Medium/short range radar – Ultra short range radar

3 Description

The LMK00804B-Q1 is a high-performance clock fan- out buffer and level translator that can distribute up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5-V levels) from one of two selectable inputs that can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable terminal is asserted or de-asserted. The outputs are held in logic low state when the clock is disabled. The LMK00804B-Q1 enables the distribution of low-jitter clock to up to four transceivers and improves the overall target detection and resolution in a cascaded mmWave radar system. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LMK00804B-Q1 VQFN (16) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic (1) PU = 51-kΩ pullup, PD = 51-kΩ pulldown. See Figure 12.

12.1 Receiving Notification of Documentation Updates 23

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES February 2019 * Initial release.

ADVANCE□INFORMATION LMK00804B-Q1 www.ti.com SNAS784 – MARCH 2019 Product Folder Links: LMK00804B-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) See Recommendations for Unused Input and Output Pins, if applicable. (2) The definitions below define the functionality of the I/O cells for each pin. TYPE: (a) G = Ground, (b) I = Input, (c) O = Output, (d) P = Power, (e) PU = 51-kΩ pullup, (f) PD = 51-kΩ pulldown. (g) NC = No connect

5 Pin Configuration and Functions

Pin Functions(1) PIN TYPE(2) DESCRIPTION NAME NO. CLK_EN 4 I, PU Synchronous clock enable input. Typically connected to VDD with a 1-kΩ pullup. When unused, leave floating. 0 = Outputs are forced to logic low state 1 = Outputs are enabled with LVCMOS/LVTTL levels CLK_N 6 I, PD, PU Inverting differential clock input 0. Typically connected to the inverting clock input. When unused, leave floating. Internally biased to VDD/2 when left floating. CLK_P 5 I, PD Noninverting differential clock input 0. Typically connected to the noninverting clock input. A single-ended clock input can also be connected to CLK_P. When unused, leave floating. CLK_SEL 7 I, PU Clock select input. Typically connected to VDD with a 1-kΩ pullup. When unused, leave floating. 0 = Select LVCMOS_CLK (pin 8) 1 = Select CLK_P, CLK_N (pins 5, 6) GND 1, 9, 13 G Power supply ground. LVCMOS_CLK 8 I, PD Single-ended clock input. Typically connected to a single-ended clock input. When unused, leave floating. Accepts LVCMOS/LVTTL levels. NC 2 NC No connect pin. Typically left floating. Do not connect to ground. Q0 16 O Single-ended clock outputs with LVCMOS/LVTTL levels, 7-Ω output impedance. Typically connected to a receiver with a 43-Ω series termination. When unused, leave floating. Q1 14 Q2 12 Q3 10

ADVANCE□INFORMATION LMK00804B-Q1 SNAS784 – MARCH 2019 www.ti.com Product Folder Links: LMK00804B-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Pin Functions(1) (continued) PIN TYPE(2) DESCRIPTION NAME NO. VDD 3 P Power supply terminal. Typically connected to a 3.3-V supply. VDDO 11, 15 P Output supply terminals. Typically connected to a 3.3-V, 2.5-V, 1.8-V, or 1.5-V supply.

ADVANCE□INFORMATION LMK00804B-Q1 www.ti.com SNAS784 – MARCH 2019 Product Folder Links: LMK00804B-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and specifications.

6 Specifications

6.1 Absolute Maximum Ratings(1)(2)

Over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VDD Supply input voltage –0.3 3.6 V VDDO Supply output voltage –0.3 3.6 V VI Input voltage –0.3 VDD + 0.3 V TJ Junction temperature 150 °C Tstg Storage temperature –65 150 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) HBM ESD Classification Level 2 1000 V Charged-device model (CDM), per AEC Q100-011 CDM ESD Classification Level C6 250 (1) There is no minimum input / output frequency provided the input slew rate is sufficiently fast. Refer to Input Slew Rate Considerations. (2) These AC parameters are specified by characterization. Not tested in production.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply input voltage 3.135 3.3 3.465 V VDDO Supply output voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 1.65 1.8 1.95 1.425 1.5 1.575 TA Ambient temperature –40 125 °C TJ Junction temperature 135 °C fOUT Maximum output frequency(1)(2) 350 MHz

ADVANCE□INFORMATION LMK00804B-Q1 SNAS784 – MARCH 2019 www.ti.com Product Folder Links: LMK00804B-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953). (2) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-K board).

6.4 Thermal Information

THERMAL METRIC(1)(2) LMK00804B-Q1 UNITRGT (VQFN)

16 PINS

RθJA Junction-to-ambient thermal resistance 48.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 58.6 °C/W RθJB Junction-to-board thermal resistance 22.6 °C/W ψJT Junction-to-top characterization parameter 2.1 °C/W ψJB Junction-to-board characterization parameter 22.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.5 °C/W

6.5 Power Supply Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. PARAMETER MIN TYP MAX UNIT IDD Power supply current through VDD 21 mA IDDO Power supply current through VDDO 5 mA (1) Outputs terminated with 50 Ω to VDDO/2.

6.6 LVCMOS / LVTTL DC Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH Input high voltage CLK_EN, CLK_SEL 2 VDD + 0.3 V LVCMOS_CLK 2 VDD + 0.3 V VIL Input low voltage CLK_EN, CLK_SEL –0.3 0.8 V LVCMOS_CLK –0.3 1.3 IIH Input high current CLK_EN, CLK_SEL VDD = 3.465 V, VIN = 3.465 V 5 µA LVCMOS_CLK VDD = 3.465 V, VIN = 3.465 V 150 IIL Input low current CLK_EN, CLK_SEL VDD = 3.465 V, VIN = 0 V –150 µA LVCMOS_CLK VDD = 3.465 V, VIN = 0 V –5 VOH Output high voltage(1) VDDO = 3.3 V ± 5% 2.6 V VDDO = 2.5 V ± 5% 1.8 VDDO = 1.8 V ± 0.15 V 1.5 VDDO = 1.5 V ± 5% VDDO – 0.3 VOL Output low voltage(1) VDDO = 3.3 V ± 5% 0.5 V VDDO = 2.5 V ± 5% 0.5 VDDO = 1.8 V ± 0.15 V 0.4 VDDO = 1.5 V ± 5% 0.35 IOZL Output Hi-Z current low –5 µA IOZH Output Hi-Z current high 5

ADVANCE□INFORMATION LMK00804B-Q1 www.ti.com SNAS784 – MARCH 2019 Product Folder Links: LMK00804B-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) VIL should not be less than –0.3 V. (2) Input common-mode voltage is defined as VIH. (3) For IIH and IIL measurements on CLK_Por CLK_N, one must comply with VID and VIC specifications by using the appropriate bias on CLK_N or CLK.

6.7 Differential Input DC Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VID Differential input voltage swing, (VIH – VIL)(1) 0.15 1.3 V VIC Input common-mode voltage(1)(2) 0.5 VDD – 0.85 V IIH Input high current(3) CLK_N VDD = 3.465 V, VIN = 3.465 V 150 µA CLK VDD = 3.465 V, VIN = 3.465 V 150 IIL Input low current(3) CLK_N VDD = 3.465 V , VIN = 0 V –150 µA CLK VDD = 3.465 V, VIN = 0 V –5 (1) These AC parameters are specified by design. Not tested in production (2) Measured from the VDD/2 of the input to the VDDO/2 of the output. (3) Measured from the differential input crossing point to VDDO/2 of the output. (4) These AC parameters are specified by characterization. Not tested in production. (5) Defined as skew between outputs at the same supply voltage and with equal loading conditions. Measured at VDDO/2 of the output. (6) Parameter is defined in accordance with JEDEC Standard 65. (7) Calculation for part-to-part skew is the difference between the fastest and slowest tPD across multiple devices, operating at the same supply voltage, same frequency, same temperature, with equal load conditions, and using the same type of inputs on each device. (8) Buffer additive jitter: tJIT = SQRT(tJIT_SYS2 – tJIT_SOURCE2), where t JIT_SYS is the RMS jitter of the system output (source+buffer) and tJIT_SOURCE is the RMS jitter of the input source, and system output noise is not correlated to the input source noise. Additive jitter should be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PNFLOOR). This is usually the case for high-quality ultra-low-noise oscillators. Refer to System-Level Phase Noise and Additive Jitter Measurement for input source and measurement details. 6.8 Timing Characteristics (VDDO = 3.3 V ± 5%) Over recommended operating free-air temperature range (unless otherwise noted), VDD = VDDO = 3.3 V ± 5%, All AC parameters measured at ≤ 350 MHz unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPDLH Propagation delay, Low-to-high(1) LVCMOS_CLK(2), CLK_P/CLK_N(3) 0°C to 70°C TBD TBD ns –40°C to 85°C TBD TBD ns tSK(O) Output skew(4)(5)(6) Measured on rising edge TBD ps tSK(PP) Part-to-part skew(1)(6)(7) TBD ps tR/tF Output rise/fall time(1) 20% to 80% TBD TBD ps tJIT Additive jitter(8) f = 40 MHz, Input slew rate ≥ 3 V/ns, 12-kHz to 20-MHz integration band TBD ps RMS

ADVANCE□INFORMATION LMK00804B-Q1 SNAS784 – MARCH 2019 www.ti.com Product Folder Links: LMK00804B-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Timing Characteristics (VDDO = 3.3 V ± 5%) (continued) Over recommended operating free-air temperature range (unless otherwise noted), VDD = VDDO = 3.3 V ± 5%, All AC parameters measured at ≤ 350 MHz unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (9) Buffer phase noise floor: PNFLOOR (dBc/Hz) = 10 × log10[10^(PNSYSTEM/10) – 10^(PNSOURCE/10)], where PNSYSTEM is the phase noise floor of the system output (source+buffer) and PNSOURCE is the phase noise floor of the input source. Buffer Phase Noise Floor should be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PNFLOOR). This is usually the case for high-quality ultra-low-noise oscillators. Refer to System-Level Phase Noise and Additive Jitter Measurement for input source and measurement details. (10) 50% Input duty cycle PNFLOOR Phase noise floor(9) f = 40 MHz, Input slew rate ≥ 3 V/ns TBD dBc/Hz 10-kHz offset –155 100-kHz offset –162 1-MHz offset –166 10-MHz offset –166 20-MHz offset –166 DO Output duty cycle(1)(10) REF = CLK_P/CLK_N 45% 55% REF = LVCMOS_CLK, f ≤ 300 MHz 45% 55% tDIS Output disable time 5 ns (1) These AC parameters are specified by design. Not tested in production. (2) Measured from the VDD/2 of the input to the VDDO/2 of the output. (3) Measured from the differential input crossing point to VDDO/2 of the output. (4) These AC parameters are specified by characterization. Not tested in production. (5) Defined as skew between outputs at the same supply voltage and with equal loading conditions. Measured at VDDO/2 of the output. (6) Parameter is defined in accordance with JEDEC Standard 65. (7) Calculation for part-to-part skew is the difference between the fastest and slowest tPD across multiple devices, operating at the same supply voltage, same frequency, same temperature, with equal load conditions, and using the same type of inputs on each device. (8) Buffer additive jitter: tJIT = SQRT(tJIT_SYS 2 – tJIT_SOURCE 2), where JSYS is the RMS jitter of the system output (source+buffer) and tJIT_SOURCE is the RMS jitter of the input source, and system output noise is not correlated to the input source noise. Additive jitter should be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PNFLOOR). This is usually the case for high-quality ultra-low-noise oscillators. Refer to System-Level Phase Noise and Additive Jitter Measurement for input source and measurement details. (9) 50% Input Duty Cycle 6.9 Timing Characteristics (VDDO = 2.5 V ± 5%) Over recommended operating free-air temperature range (unless otherwise noted), VDD = 3.3 V ± 5%, VDDO = 2.5 V ± 5%, All AC parameters measured at ≤ 350 MHz unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPDLH Propagation delay, Low-to-high(1) LVCMOS_CLK(2), CLK_P/CLK_N(3) 0°C to 70°C TBD TBD ns –40°C to 85°C TBD TBD tSK(O) Output skew(4)(5)(6) Measured on rising edge TBD ps tSK(PP) Part-to-part skew(1)(6)(7) TBD ps tR/tF Output rise/fall time(1) 20% to 80% TBD TBD ps tJIT Additive jitter(8) f = 40 MHz, Input slew rate ≥ 3 V/ns, 12-kHz to 20-MHz integration band TBD ps RMS DO Output duty cycle(1)(9) REF = CLK_P/CLK_N 45% 55% REF = LVCMOS_CLK, f ≤ 300 MHz 45% 55% tDIS Output disable time 5 ns

ADVANCE□INFORMATION LMK00804B-Q1 www.ti.com SNAS784 – MARCH 2019 Product Folder Links: LMK00804B-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) These AC parameters are specified by design. Not tested in production. (2) Measured from the VDD/2 of the input to the VDDO/2 of the output. (3) Measured from the differential input crossing point to VDDO/2 of the output. (4) These AC parameters are specified by characterization. Not tested in production. (5) Defined as skew between outputs at the same supply voltage and with equal loading conditions. Measured at VDDO/2 of the output. (6) Parameter is defined in accordance with JEDEC Standard 65. (7) Calculation for part-to-part skew is the difference between the fastest and slowest tPD across multiple devices, operating at the same supply voltage, same frequency, same temperature, with equal load conditions, and using the same type of inputs on each device. (8) Buffer additive jitter: tJIT = SQRT(tJIT_SYS 2 – tJIT_SOURCE 2), where JSYS is the RMS jitter of the system output (source+buffer) and tJIT_SOURCE is the RMS jitter of the input source, and system output noise is not correlated to the input source noise. Additive jitter should be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PNFLOOR). This is usually the case for high-quality ultra-low-noise oscillators. Refer to System-Level Phase Noise and Additive Jitter Measurement for input source and measurement details. (9) 50% Input Duty Cycle 6.10 Timing Characteristics (VDDO = 1.8 V ± 0.15 V) Over recommended operating free-air temperature range (unless otherwise noted), VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 0.15 V. All AC parameters measured at ≤ 350 MHz unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPDLH Propagation delay, Low-to-high(1) LVCMOS_CLK(2), CLK_P/CLK_N(3) 0°C to 70°C TBD TBD ns –40°C to 85°C TBD TBD ns tSK(O) Output skew(4)(5)(6) Measured on rising edge TBD ps tSK(PP) Part-to-part skew(1)(6)(7) TBD ps tR/tF Output rise/fall time(1) 20% to 80% TBD TBD ps tJIT Additive jitter(8) f = 40 MHz, Input slew rate ≥ 3 V/ns, 12-kHz to 20-MHz integration band TBD ps RMS DO Output duty cycle(1)(9) REF = CLK_P/CLK_N 45% 55% REF = LVCMOS_CLK, f ≤ 300 MHz 45% 55% tDIS Output disable time 5 ns

ADVANCE□INFORMATION LMK00804B-Q1 SNAS784 – MARCH 2019 www.ti.com Product Folder Links: LMK00804B-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) These AC parameters are specified by design. Not tested in production. (2) Measured from the VDD/2 of the input to the VDDO/2 of the output. (3) Measured from the differential input crossing point to VDDO/2 of the output. (4) These AC parameters are specified by characterization. Not tested in production. (5) Defined as skew between outputs at the same supply voltage and with equal loading conditions. Measured at VDDO/2 of the output. (6) Parameter is defined in accordance with JEDEC Standard 65. (7) Calculation for part-to-part skew is the difference between the fastest and slowest tPD across multiple devices, operating at the same supply voltage, same frequency, same temperature, with equal load conditions, and using the same type of inputs on each device. (8) Buffer additive jitter: tJIT = SQRT(tJIT_SYS 2 – tJIT_SOURCE 2), where tJIT_SYS is the RMS jitter of the system output (source+buffer) and tJIT_SOURCE is the RMS jitter of the input source, and system output noise is not correlated to the input source noise. Additive jitter should be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PNFLOOR). This is usually the case for high-quality ultra-low-noise oscillators. Refer to System-Level Phase Noise and Additive Jitter Measurement for input source and measurement details. (9) 50% Input Duty Cycle 6.11 Timing Characteristics (VDDO = 1.5 V ± 5%) Over recommended operating free-air temperature range (unless otherwise noted), VDD = 3.3 V ± 5%, VDDO = 1.5 V ± 5%, All AC parameters measured at ≤ 350 MHz unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPDLH Propagation delay, Low-to-high(1) LVCMOS_CLK(2), CLK_P/CLK_N(3) 0°C to 70°C TBD TBD ns –40°C to 85°C TBD TBD ns tSK(O) Output skew(4)(5)(6) Measured on rising edge TBD ps tSK(PP) Part-to-part skew(4)(6)(7) TBD ns tR/tF Output rise/fall time(1) 20% to 80% TBD TBD ps tJIT Additive Jitter(8) f = 40 MHz, Input slew rate ≥ 3 V/ns, 12-kHz to 20-MHz integration band TBD ps RMS DO Output duty cycle(1)(9) f ≤ 166 MHz 45% 55% tDIS Output disable time 5 ns

6.12 Pin Characteristics

RPU Input pullup resistance 51 kΩ RPD Input pulldown resistance 51 kΩ CPD Power dissipation capacitance (per output) 2 pF ROUT Output impedance 7 Ω

100 MHz

125 MHz

250 MHz

350 MHz

6.13 Typical Characteristics

Figure 1. Additive Jitter vs Input Slew Rate Figure 2. Additive Jitter vs VDDO Supply and Temperature Figure 3. Phase Noise Floor vs Input Slew Rate Figure 4. Phase Noise Floor vs VDDO Supply and

7 Parameter Measurement Information

Figure 5. Differential Input Level Figure 6. Output Voltage, and Rise and Fall Times Figure 7. Output Skew and Propagation Delay

ADVANCE□INFORMATION PD PD PU/ PD LVCMOS _CLK CLK_P CLK_N CLK_EN PU D Q CLK_SEL PU LMK00804B-Q1 www.ti.com SNAS784 – MARCH 2019 Product Folder Links: LMK00804B-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The LMK00804B-Q1 is a clock fan-out buffer with two selectable clock inputs and four LVCMOS outputs. The LVCMOS_CLK input accepts a single-ended clock input, and the CLK_P/CLK_N input accepts a differential or single-ended clock input. The LMK00804B-Q1 has a synchronous clock enable feature allows the device to drive the outputs to a logic low using the CLK_EN pin.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Clock Enable Timing

Figure 8. Clock Enable Timing Diagram

8.4 Device Functional Modes

9 Applications and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

to match the driver impedance and series resistance to the trace impedance.

9.2 Typical Applications

Refer to the following sections for output clock and input clock interface circuits.

9.2.1 Output Clock Interface Circuit

Figure 9. LVCMOS Output Configuration

9.2.1.1 Design Requirements

the input source and the measurement equipment. trace shows the input source phase noise, and the dark blue trace shows the system output phase noise.

9.2.1.2 Detailed Design Procedure

PNSYSTEM is the phase noise of the system output (source+buffer)
PNSOURCE is the phase noise of the input source (1) Use Equation 2 to calculate the additive jitter of the buffer (tJIT): tJIT = SQRT(tJIT_SYS 2 – tJIT_SOURCE where:
tJIT_SYS is the RMS jitter of the system output (source+buffer), integrated from 10 kHz to 20 MHz
tJIT_SOURCE is the RMS jitter of the input source, integrated from 10 kHz to 20 MHz (2)

9.2.1.3 Application Curves

9.2.1.3.1 System-Level Phase Noise and Additive Jitter Measurement

Figure 10. 125-MHz Input Phase Noise (57 fs rms, Light Blue),

9.2.2 Input Detail

Figure 11. Clock Input Components

9.2.3 Input Clock Interface Circuits

Figure 12. LVCMOS_CLK Input Configuration –60-mV offset voltage (VCLK_N – VCLK_P) . Ensure a logic low state if the LVCMOS driver enters a tri-state condition. Figure 13. Single-Ended/LVCMOS Input DC Configuration

9.3 Do's and Don'ts

9.3.1 Power Considerations

Power used by the device as it switches states
Power required to charge any output load The output load can be capacitive-only or capacitive and resistive. Use Equation 3 through Equation 5 to calculate the power consumption of the device: PDev = Pstat + Pdyn + PCload (3) Pstat = (IDD × VDD) + (IDDO × VDDO) (4) Pdyn + PCload = (IDDO,dyn + IDDO,Cload) × VDDO where:
IDDO,dyn = CPD × VDDO × f × n [mA]
IDDO,Cload = Cload × VDDO × f × n [mA] (5) Example for power consumption of the LMK00804B-Q1: 4 outputs are switching, f = 100 MHz, VDD = VDDO = 3.465 V and assuming Cload = 5 pF per output: PDev = 90 mW + 34 mW = 124 mW (6)

ADVANCE□INFORMATION LMK00804B-Q1 SNAS784 – MARCH 2019 www.ti.com Product Folder Links: LMK00804B-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Do's and Don'ts (continued) Pstat = (21 mA × 3.465 V) + (5 mA × 3.465 V) = 90 mW (7) Pdyn + PCload = (2.8 mA + 6.9 mA) × 3.465 V = 34 mW (8) IDD,dyn = 2 pF × 3.465 V × 100 MHz × 4 = 2.8 mA (9) IDD,Cload = 5 pF × 3.465 V × 100 MHz × 4 = 6.9 mA (10) NOTE For dimensioning the power supply, consider the total power consumption. The total power consumption is the sum of device power consumption and the power consumption of the load.

9.3.2 Recommendations for Unused Input and Output Pins

CLK_SEL and CLK_EN: CLK_EN must be held low until a valid reference clock is provided before the engineer can use the pin to enable the outputs. These inputs both have an internal pullup (PU) according to

Table 1. Table 1 shows the default floating state of these inputs: Table 1. Input Floating Default States

CLK_P/CLK_N Inputs: See Figure 11 for the internal connections. When using single-ended input, take note of the internal pullup and pulldown to make sure the unused input is properly biased. To interface a single- ended input to the CLK_P/CLK_N input, the configuration shown in Figure 13 is recommended.
LVCMOS_CLK Input: See Figure 11 for the internal connection. The internal pulldown (PD) resistor ensures a low state when this input is left floating.
Outputs: Connect the outputs to the receivers with a 43-Ω series resistor. Any unused output must be left floating.

9.3.3 Input Slew Rate Considerations

Figure 2. Also, using an input signal with a slow input slew rate less than 0.05 V/ns can cause output switching input in single-ended fashion with a very slow slew rate, such as a sine-wave input signal.

10 Power Supply Recommendations

10.1 Power Supply Considerations

input voltage (VDD) before the supply output voltage (VDDO).

10.1.1 Power-Supply Filtering

jitter or phase noise is critical to applications. high-frequency switching noises generated by the clock driver. This would prevent leakage into the board supply. supply terminals that is greater than the minimum voltage required for proper operation. Figure 14. Power-Supply Decoupling

10.1.2 Thermal Management

estimate, TA (ambient temperature) plus device power consumption times RθJA should not exceed 125°C.

Use multi-layer boards
Specify a higher copper thickness for the board
Increase the number of vias from the top level ground plane under and around the device to internal layers and to the bottom layer with as much copper area flow on each level as possible
Apply air flow
Leave unused outputs floating

11 Layout

11.1 Layout Guidelines

11.1.1 Ground Planes

Solid ground planes are recommended as they provide a low-impedance return paths between the device and bypass capacitors and the clock source and destination devices. Avoid return paths of other system circuitry (for example, high-speed/digital logic, switching power supplies, and so forth) from passing through the local ground of the device to minimize noise coupling, which could induce added jitter and spurious noise.

11.1.2 Power Supply Pins

Follow the power supply schematic and layout example described in Power-Supply Filtering.

11.1.3 Differential Input Termination

Place input termination or biasing resistors as close to the CLK_P/CLK_N pins as possible.
Avoid or minimize vias in the 50-Ω input traces to minimize impedance discontinuities. Intra-pair skew should be also be minimized on the differential input traces.
If not used, CLK_P/CLK_N inputs may be left as no connect.

11.1.4 LVCMOS Input Termination

Input termination is not necessary when the LVCMOS_CLK input is driven from a LVCMOS driver that is series-terminated to match the characteristic impedance of the trace. Otherwise, place the input termination resistor as close to the LVCMOS_CLK input as possible.
Avoid or minimize vias in the 50-Ω input trace to minimize impedance discontinuities.
If not used, LVCMOS_CLK input may be left as no connect.

11.1.5 Output Termination

Place 43-Ω series termination resistors close to the Qx outputs at the launch of the 50-Ω traces.
Avoid or minimize vias in the 50-Ω input traces to minimize impedance discontinuities.
If not used, any Qx output should be left as no connect.

11.2 Layout Example

Figure 15 shows the recommended PCB design for good electrical and thermal performance. Figure 15. General PCB Ground Layout for Thermal Reliability

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 20-Mar-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PLMK00804BQWRGTTQ1 ACTIVE VQFN RGT 16 250 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LMK00804B-Q1 :

www.ti.com 20-Mar-2019 Addendum-Page 2

Catalog: LMK00804B NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2019, Texas Instruments Incorporated

Summary

1.5-V to 3.3-V, 1-to-4 high-performance LVCMOS fan-out buffer and level translator

Description