PLMH5485DGKSEP

LMH5485-SEP TI | Alldatasheet

Document overview

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Technical content

LMH5485-SEP Radiation Tolerant Negative Rail Input, Rail-to-Rail Output, Precision,

850 MHz Fully Differential Amplifier

1 Features

• Radiation tolerant – Radiation tolerant up to 30-krad (Si) total ionizing dose (TID) – Single event latch-up (SEL) immune to LET = 43 MeV-cm2 /mg – Qualified over the military temperature range:.. –55°C to 125°C
• Fully differential amplifier (FDA) architecture
• Bandwidth: 495 MHz (G = 2 V/V)
• Gain bandwidth product (GBWP): 850 MHz
• Slew rate: 1300 V/µs
• HD2, HD3: –90 dBc, –102 dBc (10 MHz, 2 VPP)
• Input voltage noise: 2.4 nV/ √Hz (f > 100 kHz)
• Input offset voltage, drift: ±100 µV, ±0.5 µV/°C
• Negative rail input (NRI), rail-to-rail output (RRO)
• Output common-mode control
• Power supply: – Supply voltage range: 2.7 V to 5.1 V – Quiescent current: 10.1 mA (5 V supply) – Power-down capability: 2 µA (typical)

2 Applications

• Low-power, high-performance ADC driver: – SAR, ΔΣ, and pipeline
• Differential DAC output driver
• Command and data handling
• Launch vehicle systems
• Space imaging systems: – Optical imaging payload – Radar imaging payload – Thermal imaging cameras

3 Description

The LMH5485-SEP is a radiation hardened tolerant, low-power, voltage-feedback, fully differential amplifier (FDA) with an input common-mode range below the negative rail, and rail-to-rail output. Designed for power sensitive data acquisition systems where high density is critical in a high-performance analog-to- digital converter (ADC) or digital-to-analog converter (DAC) interface designs. The LMH5485-SEP features the negative-rail input required when interfacing a DC-coupled, ground- centered, source signal. This negative-rail input, with rail-to-rail output, allows for easy interface between single-ended, ground-referenced, bipolar signal sources and a wide variety of successive approximation register (SAR), delta-sigma ( ΔΣ), or pipeline ADCs using only a single 2.7 V to 5.1 V power supply. LMH5485-SEP also offers excellent DC precision for such ADC driving applications and is characterized for operation over the wide temperature range of –55°C to +125°C. Device Information PART NUMBER(1) PACKAGE BODY SIZE (NOM) LMH5485-SEP VSSOP (8) 3.00 mm × 3.00 mm (1) For all available packages, see the package option addendum at the end of the data sheet. 100 nF Rf1 402 Rload 500 Rg1 191 100 nF Rg2 221 Rt 60.2 Output Measurement Point LMH5485 Wideband, Fully-Differential Amplifier50- Input Match, Gain of 2 V/V from Rt, Single-Ended Source to Differential Output Vocm Rf2 402 50- Source Vcc Vocm Vcc FDA PD Simplified Schematic Single to Differential Gain of 2, 100-mVPP Output ADVANCE INFORMATION LMH5485-SEP SBOSA87 – DECEMBER 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

7.10 Typical Characteristics: 3 V to 5 V Supply Range...12 12.2 Receiving Notification of Documentation Updates..29

13 Mechanical, Packaging, and Orderable

4 Revision History

December 2021 * Initial Release LMH5485-SEP SBOSA87 – DECEMBER 2021 www.ti.com ADVANCE INFORMATION

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5 Device Comparison Table

(MHz) IQ (mA) HD2 / HD3 (dBc)

2 VPP AT 10 MHz

(nV/√ Hz) RAIL-TO-RAIL LMH5485-SP 100 kRad TID 850 10.1 –79 / –97 2.4 NRI/Out LMH5485-SEP 30 kRad TID 850 10.1 –90 / –102 2.4 NRI/Out THS4513-SP 150 kRad TID 3000 37.7 –106 / –108 2.2 No LMH5401-SP 100 kRad TID 6500 60 –99 / –100 1.25 No

6 Pin Configuration and Functions

Figure 6-1. DGK Package 8-Pin VSSOP Top View Table 6-1. Pin Functions PIN TYPE(1) DESCRIPTIONNAME NO. IN+ 8 I Noninverting (positive) amplifier input IN– 1 I Inverting (negative) amplifier input OUT+ 4 O Noninverted (positive) amplifier output OUT– 5 O Inverted (negative) amplifier output PD 7 I Power down. PD = logic low = power off mode; PD = logic high = normal operation. Vocm 2 I Common-mode voltage input Vs+ 3 P Positive power-supply input Vs– 6 P Negative power-supply input (1) I = input, O = output, P = power www.ti.com LMH5485-SEP SBOSA87 – DECEMBER 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LMH5485-SEP

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage Supply voltage, (Vs+) – Vs– 5.25 V Input-output voltage range (Vs–) – 0.5 (Vs+) + 0.5 V Differential input voltage ±1 V Current Continuous input current ±20 mA Continuous output current ±80 mA Continuous power dissipation See Thermal Information table and Thermal Analysis section Temperature Maximum junction temperature 150 °C Operating free-air temperature range –55 125 °C Storage temperature, Tstg –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±TBD V Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±TBD (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Vs+ Single-supply voltage 2.7 5 5.1 V TA Ambient temperature –55 25 125 °C

7.4 Thermal Information

THERMAL METRIC(1) LMH5485-SEP UNITDGK (VSSOP)

8 PINS

RθJA Junction-to-ambient thermal resistance 171.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 63.4 °C/W RθJB Junction-to-board thermal resistance 93.4 °C/W ψJT Junction-to-top characterization parameter 9.2 °C/W ψJB Junction-to-board characterization parameter 91.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. LMH5485-SEP SBOSA87 – DECEMBER 2021 www.ti.com ADVANCE INFORMATION

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7.5 Electrical Characteristics: VS+ – VS– = 5 V

The specifications shown below correspond to the respectively identified subgroup temperature (see Section 7.7), unless otherwise noted. VOCM = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ω input match, G = 2 V/V, single-ended input, differential output, and PD = +Vs, unless otherwise noted. See Figure 8-1 for an AC-coupled gain of a 2-V/V test circuit, and Figure 8-3 for a DC-coupled gain of a 2-V/V test circuit. PARAMETER TEST CONDITIONS SUBGROUP(1) MIN TYP MAX UNIT AC PERFORMANCE Small-signal bandwidth Vout = 100 mVPP, G = 1 590 MHz Small-signal bandwidth Vout = 100 mVPP, G = 2 495 MHz Small-signal bandwidth Vout = 100 mVPP, G = 5 185 MHz Small-signal bandwidth Vout = 100 mVPP, G = 10 110 MHz GBWP Gain-bandwidth product Vout = 100 mVPP, G = 20 850 MHz Large-signal bandwidth Vout = 2 VPP 295 MHz Bandwidth for 0.1-dB flatness Vout = 2 VPP 125 MHz Slew rate(2) Vout = 2-VPP, FPBW 1300 V/µs Rise/fall time Vout = 2-V step, input ≤ 0.5 ns tr 1.3 ns Settling time Vout = 2-V step, tr = 2 ns To 1% 4 ns To 0.1% 8 ns Overshoot and undershoot Vout = 2-V step, input ≤ 0.3 ns tr 10% 100-kHz harmonic distortion Vout = 2 VPP HD2 –118 dBc HD3 –147 dBc 10-MHz harmonic distortion Vout = 2 VPP HD2 –90 dBc HD3 –102 dBc 2nd-order intermodulation distortion f = 10 MHz, 100-kHz tone spacing, Vout envelope = 2 VPP (1 VPP per tone) –90 dBc 3rd-order intermodulation distortion –85 dBc Input voltage noise f > 100 kHz 2.4 nV/√Hz Input current noise f > 1 MHz 1.9 pA/√Hz Overdrive recovery time 2x output overdrive, either polarity 20 ns Closed-loop output impedance f = 10 MHz (differential) 0.1 Ω DC PERFORMANCE AOL Open-loop voltage gain [1, 2, 3] 97 119 dB Input-referred offset voltage [1, 2, 3] –900 ±100 900 µV Input offset voltage drift(3) –2.5 ±0.5 2.5 µV/°C Input bias current Positive out of node [1, 2, 3] 1.7 10 15 µA Input bias current drift(3) 6 15 nA/°C Input offset current [1, 2, 3] –650 ±150 650 nA Input offset current drift(3) –1.5 ±0.3 1.5 nA/°C INPUT Common-mode input low < 3-dB degradation in CMRR from midsupply [1, 2, 3] (Vs–) – 0.2 Vs– V Common-mode input high < 3-dB degradation in CMRR from midsupply [1, 2, 3] (Vs+) – 1.3 (Vs+) –1.2 V Common-mode rejection ratio Input pins at midsupply [1, 2, 3] 82 100 dB Input impedance differential mode Input pins at midsupply 110 || 0.9 kΩ || pF www.ti.com LMH5485-SEP SBOSA87 – DECEMBER 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LMH5485-SEP

7.5 Electrical Characteristics: VS+ – VS– = 5 V (continued)

The specifications shown below correspond to the respectively identified subgroup temperature (see Section 7.7), unless otherwise noted. VOCM = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ω input match, G = 2 V/V, single-ended input, differential output, and PD = +Vs, unless otherwise noted. See Figure 8-1 for an AC-coupled gain of a 2-V/V test circuit, and Figure 8-3 for a DC-coupled gain of a 2-V/V test circuit. PARAMETER TEST CONDITIONS SUBGROUP(1) MIN TYP MAX UNIT OUTPUT Output voltage low [1, 2, 3] (Vs–) + 0.2 (Vs–) + 0.25 V Output voltage high [1, 2, 3] (Vs+) – 0.25 (Vs+) – 0.2 V Output current drive [1, 2, 3] ±75 ±100 mA POWER SUPPLY Specified operating voltage [1, 2, 3] 2.7 5 5.1 V Quiescent operating current [1, 2, 3] 9.2 10.1 11 mA ±PSRR Power-supply rejection ratio Either supply pin to differential Vout [1, 2, 3] 82 100 dB POWER DOWN Enable voltage threshold [1, 2, 3] (Vs–) + 1.7 V Disable voltage threshold [1, 2, 3] (Vs–) + 0.7 V Disable pin bias current PD = Vs– → Vs+ [1, 2, 3] 20 50 nA Power-down quiescent current PD = Vs– [1, 2, 3] 2 8 µA Turnon-time delay Time from PD = low to Vout = 90% of final value 100 ns Turnoff time delay Time from PD = low to Vout = 10% of final value 60 ns OUTPUT COMMON-MODE VOLTAGE CONTROL(4) Small-signal bandwidth Vocm = 100 mVPP 150 MHz Slew rate(2) Vocm = 2-V step 400 V/µs Gain [1, 2, 3] 0.975 0.982 0.995 V/V Input bias current Considered positive out of node [1, 2, 3] –0.8 0.1 0.8 µA Input impedance Vocm input driven to midsupply 47 || 1.2 kΩ || pF Default voltage offset from midsupply Vocm pin open [1, 2, 3] –45 ±8 45 mV CM Vos Common-mode offset voltage Vocm input driven to midsupply [1, 2, 3] –8 ±2 8 mV CM VOS drift(3) Vocm input driven to midsupply –20 ±4 +20 mV/°C Common-mode loop supply headroom to negative supply < ±15-mV shift from midsupply CM Vos [1, 2, 3] 0.94 V Common-mode loop supply headroom to positive supply < ±15-mV shift from midsupply CM Vos [1, 2, 3] 1.2 V (1) For subgroup definitions, please see Section 7.7 (2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VP / √2) · 2π · f–3dB. (3) Input offset voltage drift, input bias current drift, input offset current drift, and Vocm drift are average values calculated by taking data at the at the maximum-range ambient-temperature end-points, computing the difference, and dividing by the temperature range. (4) Specifications are from the input Vocm pin to the differential output average voltage. LMH5485-SEP SBOSA87 – DECEMBER 2021 www.ti.com ADVANCE INFORMATION

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7.6 Electrical Characteristics: VS+ – VS– = 3 V

The specifications shown below correspond to the respectively identified subgroup temperature (see Section 7.7), unless otherwise noted. Vocm = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ω input match, G = 2 V/V, single-ended input, differential output, and PD = +Vs, unless otherwise noted. See Figure 8-1 for an AC-coupled gain of a 2-V/V test circuit, and Figure 8-3 for a DC-coupled gain of a 2-V/V test circuit. PARAMETER TEST CONDITIONS SUBGROUP(1) MIN TYP MAX UNIT AC PERFORMANCE Small-signal bandwidth Vout = 100 mVPP, G = 1 585 MHz Vout = 100 mVPP, G = 2 490 MHz Vout = 100 mVPP, G = 5 180 MHz GBWP Gain-bandwidth product Vout = 100 mVPP, G = 20 850 MHz Large-signal bandwidth Vout = 2 VPP 275 MHz Bandwidth for 0.1-dB flatness Vout = 2 VPP 120 MHz Slew rate(2) Vout = 2-V step, FPBW 1200 V/µs Rise/fall time Vout = 2-V step, input ≤ 0.5 ns tr 1.6 ns Settling time Vout = 2-V step, tr = 2 ns To 1% 5 ns To 0.1% 8 ns Overshoot and undershoot Vout = 2-V step, input ≤ 0.3 ns tr 11% 100-kHz harmonic distortion Vout = 2 VPP HD2 –118 dBc HD3 –148 dBc 10-MHz harmonic distortion Vout = 2 VPP HD2 –101 dBc HD3 –129 dBc 2nd-order intermodulation distortion f = 10 MHz, 100-kHz tone spacing, Vout envelope = 2 VPP (1 VPP per tone) –89 dBc 3rd-order intermodulation distortion –87 dBc Input voltage noise f > 100 kHz 2.4 nV/√Hz Input current noise f > 1 MHz 1.9 pA/√Hz Overdrive recovery time 2X output overdrive, either polarity 20 ns Closed-loop output impedance f = 10 MHz (differential) 0.1 Ω DC PERFORMANCE AOL Open-loop voltage gain [1, 2, 3] 97 119 dB Input-referred offset voltage [1, 2, 3] –900 ±100 900 µV Input offset voltage drift(3) –2.5 ±0.5 2.5 µV/°C Input bias current Positive out of node [1, 2, 3] 1.7 9 15 µA Input bias current drift(3) 5 15 nA/°C Input offset current [1, 2, 3] –650 ±150 650 nA Input offset current drift(3) –1.5 ±0.3 1.5 nA/°C INPUT Common-mode input low < 3-dB degradation in CMRR from midsupply [1, 2, 3] (Vs–) – 0.2 Vs– V Common-mode input high < 3-dB degradation in CMRR from midsupply [1, 2, 3] (Vs+) – 1.3 (Vs+) –1.2 V Common-mode rejection ratio Input pins at midsupply [1, 2, 3] 82 100 dB Input impedance differential mode Input pins at midsupply 110 || 0.9 kΩ || pF www.ti.com LMH5485-SEP SBOSA87 – DECEMBER 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LMH5485-SEP

7.6 Electrical Characteristics: VS+ – VS– = 3 V (continued)

The specifications shown below correspond to the respectively identified subgroup temperature (see Section 7.7), unless otherwise noted. Vocm = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ω input match, G = 2 V/V, single-ended input, differential output, and PD = +Vs, unless otherwise noted. See Figure 8-1 for an AC-coupled gain of a 2-V/V test circuit, and Figure 8-3 for a DC-coupled gain of a 2-V/V test circuit. PARAMETER TEST CONDITIONS SUBGROUP(1) MIN TYP MAX UNIT OUTPUT Output voltage low [1, 2, 3] (Vs–) + 0.2 (Vs–) + 0.25 V Output voltage high [1, 2, 3] (Vs+) – 0.25 (Vs+) – 0.2 V Output current drive [1, 2, 3] ±55 ±60 mA POWER SUPPLY Specified operating voltage [1, 2, 3] 2.7 3 5.1 V Quiescent operating current [1, 2, 3] 9 9.7 10.6 mA ±PSRR Power-supply rejection ratio Either supply pin to differential Vout [1, 2, 3] 82 100 dB POWER DOWN Enable voltage threshold [1, 2, 3] (Vs–) + 1.7 V Disable voltage threshold [1, 2, 3] (Vs–) + 0.7 V Disable pin bias current PD = Vs– → Vs+ [1, 2, 3] 20 50 nA Power-down quiescent current PD = Vs– [1, 2, 3] 1 8 µA Turnon-time delay Time from PD = low to Vout = 90% of final value 100 ns Turnoff time delay Time from PD = low to Vout = 10% of final value 60 ns OUTPUT COMMON-MODE VOLTAGE CONTROL(4) Small-signal bandwidth Vocm = 100 mVPP 140 MHz Slew rate(2) Vocm = 1-V step 350 V/µs Gain [1, 2, 3] 0.975 0.987 0.990 V/V Input bias current Considered positive out of node [1, 2, 3] –0.7 0.1 0.7 µA Input impedance Vocm input driven to midsupply 47 || 1.2 kΩ || pF Default voltage offset from midsupply Vocm pin open [1, 2, 3] –45 ±10 45 mV CM Vos Common-mode offset voltage Vocm input driven to midsupply [1, 2, 3] –8 ±2 8 mV CM VOS drift(3) Vocm input driven to midsupply –20 ±4 20 mV/°C Common-mode loop supply headroom to negative supply < ±15-mV shift from midsupply CM Vos [1, 2, 3] 0.94 V Common-mode loop supply headroom to positive supply < ±15-mV shift from midsupply CM Vos [1, 2, 3] 1.2 V (1) For subgroup definitions, please see Section 7.7. (2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VP / √2) · 2π · f–3dB. (3) Input offset voltage drift, input bias current drift, input offset current drift, and Vocm drift are average values calculated by taking data at the at the maximum-range ambient-temperature end-points, computing the difference, and dividing by the temperature range. Maximum drift set by distribution of a large sampling of devices. Drift is not specified by test or QA sample test. (4) Specifications are from input Vocm pin to differential output average voltage. LMH5485-SEP SBOSA87 – DECEMBER 2021 www.ti.com ADVANCE INFORMATION

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7.7 Quality Conformance Inspection

SUBGROUP DESCRIPTION TEMPERATURE (℃)

1 Static tests at 25

2 Static tests at 125

3 Static tests at –55

4 Dynamic tests at 25

5 Dynamic tests at 125

6 Dynamic tests at –55

7 Functional tests at 25

8A Functional tests at 125 8B Functional tests at –55 www.ti.com LMH5485-SEP SBOSA87 – DECEMBER 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LMH5485-SEP

7.8 Typical Characteristics: 5 V Single Supply

at Vs+ = 5 V, Vs– = GND, RF= 402 Ω, Vocm is open, 50 Ω single-ended input to differential output, gain = 2 V/V, Rload = 500 Ω, and TA ≈ 25°C (unless otherwise noted) Frequency (MHz) Normalized Gain (dB) 10 100 1000 G=1 G=2 G=5 Vo = 100 mVpp, see Figure 8-1 and Table 9-1 for resistor values Figure 7-1. Small-Signal Frequency Response vs Gain Frequency (MHz) Normalized Gain (dB) 10 100 1000 VO = 2 Vpp, see Figure 8-1 and Table 9-1 for resistor values Figure 7-2. Large-Signal Frequency Response Time (ns) Differential Output (V) 0 2 4 6 8 10 12 14 16 18 20 22 24 -1.5 -0.5 0.5 1.5 50 MHz input, 0.5-ns input edge rate, single-ended to differential output, split supply, DC-coupled, see Figure 8-3 Figure 7-3. Large-Signal Step Response Frequency (MHz) Distortion (dBc) 0.01 0.1 1 10 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 HD2 HD3

2 VPP output, see Figure 8-1

Figure 7-4. Harmonic Distortion Over Frequency LMH5485-SEP SBOSA87 – DECEMBER 2021 www.ti.com ADVANCE INFORMATION

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7.9 Typical Characteristics: 3 V Single Supply

at Vs+ = 3 V, Vs– = GND, Vocm is open, 50 Ω single-ended input to differential output, gain = 2 V/V, Rload = 500 Ω, and TA ≈ 25°C (unless otherwise noted) Frequency (MHz) Normalized Gain (dB) 10 100 1000 G=1 G=2 G=5 Rf = 402 Ω, Vout = 100 mVPP, see Figure 8-1 and Table 9-1 for resistor values Figure 7-5. Small-Signal Frequency Response vs Gain Frequency (MHz) Normalized Gain (dB) 10 100 1000 Rf = 402 Ω, Vout = 2 VPP, see Figure 8-1 and Table 9-1 for resistor values Figure 7-6. Large-Signal Frequency Response Time (ns) Differential Output (V) 0 2 4 6 8 10 12 14 16 18 20 22 24 -1.5 -0.5 0.5 1.5 50 MHz input, 0.5-ns input edge rate, single-ended input to differential output, split supply, DC coupled, see Figure 8-3 Figure 7-7. Large-Signal Step Response Frequency (MHz) Distortion (dBc) 0.01 0.1 1 10 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 HD2 HD3 2 VPP output, see Figure 8-1 with Vs+ = 3 V, Vocm = 1.5 V Figure 7-8. Harmonic Distortion Over Frequency www.ti.com LMH5485-SEP SBOSA87 – DECEMBER 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LMH5485-SEP

7.10 Typical Characteristics: 3 V to 5 V Supply Range

at Vs+ = 3 V and 5 V, Vs– = GND, Vocm is open, 50 Ω single-ended input to differential output, gain = 2 V/V, Rload = 500 Ω, and TA ≈ 25°C (unless otherwise noted) Figure 7-9. Main Amplifier Differential Open-Loop Gain and Phase vs Frequency Frequency (Hz) Differential Output Impedance (:) 0.0001 0.001 0.01 0.1 1k 10k 100k 1M 10M 100M D038 Gain=2, +3 V Gain=2, +5 V Gain=5, +3 V Gain=5, +5 V Single-ended input to differential output, simulated differential output impedance, see Figure 8-1 Figure 7-10. Closed-Loop Output Impedance Frequency (Hz) Input Voltage Noise (nV/ Hz) and Current Noise (pA/ Hz) 1k 10k 100k 1M 10M +5 V E N +5 V I N +3 V E N +3 V I N Figure 7-11. Input Spot Noise Over Frequency Frequency (Hz) Output Balance Error (dB) -80 -75 -70 -65 -60 -55 -50 1k 10k 100k 1M 10M 100M D040 +3 V supply +5 V supply Single-ended input to differential output, gain of 2 (see Figure 8-1), simulated with 1% resistor, worst-case mismatch Figure 7-12. Output Balance Error Over Frequency Frequency (Hz) CMRR (dB) 100 110 1k 10k 100k 1M 10M 100M D041 Common-mode in to differential out, gain of 2 simulation Figure 7-13. CMRR Over Frequency Frequency (Hz) PSRR (dB) 10k 100k 1M 10M 100M D042 +3 V +Vs +5 V +Vs +3 V -Vs +5 V -Vs Single-ended to differential, gain of 2 (see Figure 8-1) PSRR simulated to differential output Figure 7-14. PSRR Over Frequency LMH5485-SEP SBOSA87 – DECEMBER 2021 www.ti.com ADVANCE INFORMATION

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7.10 Typical Characteristics: 3 V to 5 V Supply Range (continued)

at Vs+ = 3 V and 5 V, Vs– = GND, Vocm is open, 50 Ω single-ended input to differential output, gain = 2 V/V, Rload = 500 Ω, and TA ≈ 25°C (unless otherwise noted) Frequency (Hz) Output Spot Common Mode Noise (nV/—Hz) 100 1000 100 1k 10k 100k 1M 10M D045 +5 V Vocm driven +5 V Vocm floating +3 V Vocm driven +3 V Vocm floating Vocm input either driven to mid-supply by low impedance source, or allowed to float and default to mid-supply Figure 7-15. Output Common-Mode Noise Vocm Input Voltage (V) Output CM Voltage Offset (mV) -10 D046 +5 V supply +3 V supply Average Vocm output offset of 37 units, Standard deviation < 2.5 mV, see Figure 8-3 Figure 7-16. Vocm Offset vs Vocm Setting Vocm (V) Negative Supply PSRR (dB) 100 D047 +3 V supply +5 V supply Single-ended to differential gain of 2 (see Figure 8-1), PSRR for negative supply to differential output (1-kHz simulation) Figure 7-17. –PSRR vs Vocm Approaching Vs– Vocm (V) Positive Supply PSRR (dB) 100 D048 +3 V supply +5 V supply Single-ended to differential gain of 2 (see Figure 8-1), PSRR for positive supply to differential output (1-kHz simulation) Figure 7-18. +PSRR vs Vocm Approaching Vs+ Input Offset Voltage  V # of Units -350 -300 -250 -200 -150 -100 -50 100 150 200 250 300 350 +5 V Supply +3 V Supply Total of 225 units for each supply. For Vs = 5 V: μ = 5.1 μV, σ = 77.5 μV Figure 7-19. Input Offset Voltage Input Offset Current (nA) # of Units -300 -250 -200 -150 -100 -50 100 150 200 250 300 +5 V Supply +3 V Supply Total of 225 units for each supply. For Vs = 5 V: μ = -8.5 nA, σ = 59.2 nA Figure 7-20. Input Offset Current www.ti.com LMH5485-SEP SBOSA87 – DECEMBER 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LMH5485-SEP

at Vs+ = 3 V and 5 V, Vs– = GND, Vocm is open, 50 Ω single-ended input to differential output, gain = 2 V/V, Rload = 500 Ω, and TA ≈ 25°C (unless otherwise noted) Differential Load (:) Differential Vopp (V) 10 100 1000 D055

5 V supply

3 V supply

Maximum differential output swing, Vocm at mid-supply Figure 7-21. Maximum Vopp vs Rload Disable Pin Voltage (PD) Volts Supply Current (mA) 0 1 2 3 4 5 7.5 8.5 9.5 10.5 D056 Figure 7-22. Supply Current vs PD Voltage Vocm Offset Voltage (mV) # of Units -30 -25 -20 -15 -10 100 120 +5 V Supply +3 V Supply Vocm input floating. Total of 225 units for each supply. For Vs = 5 V: μ = 14.2 mV, σ = 3.7 mV Figure 7-23. Common-Mode Output Offset from Vs+ / 2 Default Value Vocm Offset Voltage (mV) # of Units +5 V Supply +3 V Supply Total of 225 units for each supply. For Vs = 5 V: μ = 0.53 mV, σ = 1.4 mV Figure 7-24. Common-Mode Output Offset from Driven Vocm Time (µs) Disable and Differential Output Voltage (V) D059 PD 3 V PD 5 V 5-V Supply 3-V Supply

10 MHz, 1 Vpp input single to differential gain of 2,

Figure 7-25. PD Turn On Waveform Time (µs) Disable and Differential Output Voltage (V) D060 PD 3 V Out 3 V Out 5 V PD 5 V Figure 7-26. PD Turn Off Waveform LMH5485-SEP SBOSA87 – DECEMBER 2021 www.ti.com ADVANCE INFORMATION

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8 Parameter Measurement Information

8.1 Example Characterization Circuits

The LMH5485-SEP offers the advantages of a fully differential amplifier (FDA) design, with the trimmed input offset voltage of a precision op amp. The FDA is an extremely flexible device that provides a purely differential output signal centered on a settable output common-mode level. The primary options revolve around the choices of single-ended or differential inputs, AC-coupled or DC-coupled signal paths, gain targets, and resistor Value selections. Differential sources can certainly be supported and are often simpler to both implement and analyze. Because most lab equipment is single-ended, the characterization circuits typically operate with a single-ended, matched, 50 Ω input termination to a differential output at the FDA output pins. That output is then translated back to single-ended through a variety of baluns (or transformers) depending on the test and frequency range. DC-coupled, step-response testing uses two 50 Ω scope inputs with trace math. The starting point for any single-ended-to-differential, AC-coupled characterization plot is shown in Figure 8-1. 100 nF Rf1 402 Rload 500 Rg1 191 100 nF Rg2 221 Rt 60.2 Output Measurement Point LMH5485 Wideband, Fully-Differential Amplifier50- Input Match, Gain of 2 V/V from Rt, Single-Ended Source to Differential Output Vocm Rf2 402 50- Source Vcc Vocm Vcc FDA PD Figure 8-1. AC-Coupled, Single-Ended Source to a Differential Gain of a 2 V/V Test Circuit Figure 8-1 shows how most characterization plots fix the R f (Rf1 = R f2) value at 402 Ω. This element value is completely flexible in application, but the 402 Ω provides a good compromise for the parasitic issues linked to this value, specifically:

• Added output loading. The FDA appears like an inverting op amp design with both feedback resistors as an added load across the outputs (approximate total differential load in Figure 8-1 is 500 Ω || 804 Ω = 308 Ω).
• Noise contributions because of the resistor values. The resistors contribute both a 4kTR term and provide gain for the input current noise.
• Parasitic feedback pole at the input summing nodes. This pole created by the feedback R value and the differential input capacitance (as well as any board layout parasitic) introduces a zero in the noise gain, decreasing the phase margin in most situations. This effect must be managed for best frequency response flatness or step response overshoot. The 402 Ω value selected does degrade the phase margin slightly over a lower value, but does not decrease the loading significantly from the nominal 500 Ω value across the output pins. www.ti.com LMH5485-SEP SBOSA87 – DECEMBER 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LMH5485-SEP

The frequency domain characterization curves start with the selections of Figure 8-1. Then, various elements are modified to show their impact over a range of design targets, specifically:

• Gain setting is changed by adjusting Rt and the 2 – Rg elements (holding a 50 Ω input match).
• Output loading, including both resistive and capacitive load testing.
• Power-supply settings. Most often, a single +5 V test uses a ±2.5 V supply, and a +3 V test uses ±1.5 V supplies.
• The disable control pin is tied to Vs+ for any active channel test. Because most network and spectrum analyzers are a single-ended input, the output network on the LMH5485- SEP characterization tests typically show the desired load connected through a balun to a single-ended, 50 Ω load, while presenting a 50 Ω source from the balun output back into the balun. For instance, Figure 8-2 shows a wideband MA/Com balun used for Figure 8-1 . This network shows a 500 Ω differential load to the LMH5485-SEP, but an AC-coupled, 50 Ω source to the network analyzer. Distortion testing typically uses a lower-frequency, DC-isolated balun (such as the TT1-6T) that is rotated 90° from the wider band interface of Figure 8-2. Ro1 237 100 nF Ro2 237 56.2 C10 100 nF 50- Load ETC1-1-13 500- Differential Load LMH5485 Output Figure 8-2. Example 500 Ω Load to a Single-Ended, Doubly-Terminated, AC-Coupled, 50 Ω Interface This approach allows a higher differential load, but with a wideband 50 Ω output match at the cost of considerable signal-path insertion loss. This loss is acceptable for characterization, and is normalized out to show the characterization curves. Figure 8-3 shows the circuit used as a starting point for time-domain or DC-coupled testing. Rf1 402 500 Rg1 68.1 Rg2 100 Rt 80.6 Output Measurement Point LMH5485 Wideband, Fully-Differential Amplifier Rf2 402 50- Input Match, Gain of 5 V/V from Rt, Single-Ended Source to Differential Step-Response Test 50- Source Vcc Vocm Vcc FDA PD Figure 8-3. DC-Coupled, Single-Ended-to-Differential, Basic Test Circuit Set for a Gain of 5 V/V LMH5485-SEP SBOSA87 – DECEMBER 2021 www.ti.com ADVANCE INFORMATION

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In this case, the input is DC-coupled, showing a 50 Ω input match to the source, gain of 5 V/V to a differential output, again driving a nominal 500 Ω load. Using a single supply, the Vocm control input can either be floated (defaulting to mid-supply) or be driven within the allowed range for the Vocm loop (see the headroom limits on Vocm in the Electrical Characteristics: VS+ −VS = 5 V tables). To use this circuit for step-response measurements, load each of the two outputs with a 250 Ω network, translating to a 50 Ω source impedance driving into two 50 Ω scope inputs. Then, difference the scope inputs to generate the step responses. Figure 8-4 shows the output interface circuit. This grounded interface pulls a DC load current from the output Vocm voltage for single-supply operation. Running this test with balanced bipolar power supplies eliminates this DC load current and gives similar waveform results. Ro1 221 Ro2 221 Rm1 64.9 LMH5485 Output Rm1 64.9 50- Scope 50- Scope Figure 8-4. Example 500 Ω Load to Differential, Doubly-Terminated, DC-Coupled 50 Ω Scope Interface

9 Detailed Description

9.1 Overview

The LMH5485-SEP is a voltage-feedback (VFA) based, fully-differential amplifier (FDA) offering greater than 495 MHz, small-signal bandwidth at a gain of 2 V/V with trimmed supply current and input offset voltage. The core differential amplifier is a slightly decompensated voltage-feedback design with a high slew-rate, precision input stage. This design gives the MHz gain of 2 V/V small-signal bandwidth shown in the characterization curves, with a V/µs slew rate, yielding approximately a MHz, 2 V PP, large-signal bandwidth in the same circuit configuration. The outputs offer near rail-to-rail output swing (0.2 V headroom to either supply), while the device inputs are negative rail inputs with approximately 1.2 V of headroom required to the positive supply. Figure 8-3 shows how this negative rail input directly supports a bipolar input around ground in a DC-coupled, single-supply design. Similar to all FDA devices, the output average voltage (common-mode) is controlled by a separate common-mode loop. The target for this output average is set by the Vocm input pin that can be either floated to default near mid-supply or driven to a desired output common-mode voltage. The Vocm range extends from a very low 0.91 V above the negative supply to 1.1 V below the positive supply, supporting a wide range of modern analog-to-digital converter (ADC) input common-mode requirements using a single 2.7 V to 5.1 V supply range for the LMH5485-SEP. A power-down pin ( PD) is included. Pull the PD pin voltage to the negative supply to turn the device off, putting the LMH5485-SEP into a very-low quiescent current state. For normal operation, the PD pin must be asserted high. When the device is disabled, remember that the signal path is still present through the passive external resistors. Input signals applied to a disabled LMH5485-SEP still appear at the outputs at some level through this passive resistor path as they would for any disabled FDA device. www.ti.com LMH5485-SEP SBOSA87 – DECEMBER 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LMH5485-SEP

9.1.1 Terminology and Application Assumptions

Like all widely-used devices, numerous common terms have developed that are unique to this type of device. These terms include:

• Fully differential amplifier (FDA)—In this document, this term is restricted to devices offering what appears similar to a differential inverting op amp design element that requires an input resistor (not high-impedance input) and includes a second internal control-loop setting the output average voltage (Vocm) to a default or set point. This second loop interacts with the differential loop in some configurations.
• The desired output signal at the two output pins is a differential signal swinging symmetrically around a common-mode voltage where that is the average voltage for the two outputs.
• Single-ended to differential—always use the outputs differentially in an FDA; however, the source signal can be either a single-ended source or differential, with a variety of implementation details for either. When the FDA operation is single-ended to differential, only one of the two input resistors receives the source signal with the other input resistor connected to a DC reference (often ground) or through a capacitor to ground. To simplify, several features in the application of the LMH5485-SEP are not explicitly stated, but are necessary for correct operation. These requirements include:
• Although not always stated, make sure to tie the power disable pin to the positive supply when only an enabled channel is desired.
• Virtually all AC characterization equipment expects a 50 Ω termination from the 50 Ω source, and a 50 Ω single-ended source impedance from the device outputs to the 50 Ω sensing termination. This termination is achieved in all characterizations (often with some insertion loss), but is not necessary for most applications. Matching impedance is most often required when transmitting over longer distances. Tight layouts from a source, through the LMH5485-SEP, and on to an ADC input do not require doubly-terminated lines or filter designs; the exception is if the source requires a defined termination impedance for correct operation (for example, a SAW filter source).
• External element values are normally assumed to be accurate and matched. In an FDA, match the feedback resistor values and also match the (DC and AC) impedance from the summing junctions to the source on one side and the reference or ground on the other side. Unbalancing these values introduces nonidealities in the signal path. For the signal path, imbalanced resistor ratios on the two sides create a common-mode to differential conversion. Also, mismatched Rf values and feedback ratios create some added differential output error terms from any common-mode DC, ac signal, or noise terms. Snapping to standard 1% resistor values is a typical approach and generally leads to some nominal feedback ratio mismatch. Mismatched resistors or ratios do not in themselves degrade harmonic distortion. If there is meaningful CM noise or distortion coming in, those errors are converted to a differential error through element or ratio mismatch. LMH5485-SEP SBOSA87 – DECEMBER 2021 www.ti.com ADVANCE INFORMATION

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9.2 Functional Block Diagram

IN– High-Aol Differential I/O Amplifier IN+ 100 k 2.5 k 2.5 k OUT+ OUT– Vcm Error Amplifier Vocm Vs+ 100 k PD CMOS Buffer Vs–

9.3 Feature Description

9.3.1 Differential I/O

The LMH5485-SEP combines a core differential I/O, high-gain block with an output common-mode sense that is compared to a reference voltage and then fed back into the main amplifier block to control the average output to that reference. The differential I/O block is a classic, high open-loop gain stage with a dominant pole at approximately 900 Hz. This voltage feedback structure projects a single-pole, unity-gain Aol at 850 MHz (gain bandwidth product). The high-speed differential outputs include an internal averaging resistor network to sense the output common-mode voltage. This voltage is compared by a separate Vcm error amplifier to the voltage on the Vocm pin. If floated, this reference is at half the total supply voltage across the device using two 100-kΩ resistors. This Vcm error amplifier transmits a correction signal into the main amplifier to force the output average voltage to meet the target voltage on the Vocm pin. The bandwidth of this error amplifier is approximately the same bandwidth as the main differential I/O amplifier. The differential outputs are collector outputs to obtain the rail-to-rail output swing. These outputs are relatively high-impedance, open-loop sources; however, closing the loop provides a very low output impedance for load driving. No output current limit or thermal shutdown features are provided in this lower-power device. The differential inputs are PNP inputs to provide a negative-rail input range. To operate the LMH5485-SEP connect the OUT– pin to the IN+ pin through an Rf, and the OUT+ pin to the IN– pin through the same value of Rf. Bring in the inputs through additional resistors to the IN+ and IN– pins. The differential I/O op amp operates similarly to an inverting op amp structure where the source must drive the input resistor and the gain is the ratio of the feedback to the input resistor.

9.3.2 Power-Down Control Pin (PD)

The LMH5485-SEP includes a power-down control pin, PD. This pin must be asserted high for correct amplifier operation. The PD pin cannot be floated because there is no internal pullup or pulldown resistor on this pin to reduce disabled power consumption. Asserting this pin low (within 0.7 V of the negative supply) puts the LMH5485-SEP into a very low quiescent state (approximately 2 µA). Switches in the default Vocm resistor string open to eliminate the fixed bias current (25 µA) across the supply in this 200-kΩ voltage divider to mid-supply. www.ti.com LMH5485-SEP SBOSA87 – DECEMBER 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LMH5485-SEP

9.3.2.1 Operating the Power Shutdown Feature

When the PD pin is asserted high, close to the positive supply, the device will be in normal active mode of operation. To disable the device for reduced power consumption, PD pin must be asserted low, close to the negative supply. Figure 7-22 shows the PD pin voltage and the corresponding quiescent current drawn. For applications that require the device to only be powered on when the supplies are present, tie the PD pin to the positive supply voltage. The disable operation is referenced from the negative supply (normally, ground). For split-supply operation, with the negative supply below ground, a disable control voltage below ground is required to turn the LMH5485 -SEP off when the negative supply exceeds –0.7 V. For single-supply operation, a minimum of 1.7 V above the negative supply (ground, in this case) is required to assure operation. This minimum logic-high level allows for direct operation from 1.8 V supply logic.

9.3.3 Input Overdrive Operation

The LMH5485-SEP input stage architecture is intrinsically robust to input overdrives with the series input resistor required by all applications. High input overdrives cause the outputs to limit into their maximum swings with the remaining input current through the Rg resistors absorbed by internal, back-to-back protection diodes across the two inputs. These diodes are normally off in application, and only turn on to absorb the currents that a large input overdrive might produce through the source impedance and or the series Rg elements required by all designs. The internal input diodes can safely absorb up to ±15 mA in an overdrive condition. For designs that require more current to be absorbed, consider adding an external protection diode such as BAV99.

9.4 Device Functional Modes

This wideband FDA requires external resistors for correct signal-path operation. When configured for the desired input impedance and gain setting with these external resistors, the amplifier can be either on with the PD pin asserted to a voltage greater than (Vs–) + 1.7 V or turned off by asserting PD low. Disabling the amplifier shuts off the quiescent current and stops the correct amplifier operation. The signal path is still present for the source signal through the external resistors. The Vocm control pin sets the output average voltage. Left open, Vocm defaults to an internal mid-supply value. Driving this high-impedance input with a voltage reference within its valid range sets a target for the internal Vcm error amplifier.

9.4.1 Operation from Single-Ended Sources to Differential Outputs

One of the most useful features supported by the FDA device is an easy conversion from a single-ended input to a differential output centered on a user-controlled, common-mode level. While the output side is relatively straightforward, the device input pins move in a common-mode sense with the input signal. This common-mode voltage at the input pins moving with the input signal acts to increase the apparent input impedance to be greater than the Rg value. This input active impedance issue applies to both AC- and DC-coupled designs, and requires somewhat more complex solutions for the resistors to account for this active impedance, as shown in the following subsections. LMH5485-SEP SBOSA87 – DECEMBER 2021 www.ti.com ADVANCE INFORMATION

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9.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion

When the signal path can be AC-coupled, the DC biasing for the LMH5485 -SEP becomes a relatively simple task. In all designs, start by defining the output common-mode voltage. The AC-coupling issue can be separated for the input and output sides of an FDA design. The input can be AC coupled and the output DC coupled, or the output can be AC coupled and the input DC coupled, or they can both be AC coupled. One situation where the output might be DC coupled (for an AC-coupled input), is when driving directly into an ADC where the Vocm control voltage uses the ADC common-mode reference to directly bias the FDA output common-mode to the required ADC input common-mode. In any case, the design starts by setting the desired Vocm. When an AC-coupled path follows the output pins, the best linearity is achieved by operating Vocm at mid-supply. The Vocm voltage must be within the linear range for the common-mode loop, as specified in the headroom specifications (approximately 0.91 V greater than the negative supply and 1.1 V less than the positive supply). If the output path is also AC coupled, simply letting the Vocm control pin float is usually preferred in order to get a mid-supply default Vocm bias with minimal elements. To limit noise, place a 0.1 µF decoupling capacitor on the Vocm pin to ground. After Vocm is defined, check the target output voltage swing to ensure that the Vocm plus the positive or negative output swing on each side does not clip into the supplies. If the desired output differential swing is defined as Vopp, divide by 4 to obtain the ±Vp swing around Vocm at each of the two output pins (each pin operates 180° out of phase with the other). Check that Vocm ±Vp does not exceed the absolute supply rails for this rail-to-rail output (RRO) device. Going to the device input pins side, because both the source and balancing resistor on the nonsignal input side are DC blocked (see Figure 8-1), no common-mode current flows from the output common-mode voltage, thus setting the input common-mode equal to the output common-mode voltage. This input headroom also sets a limit for higher Vocm voltages. Because the input Vicm is the output Vocm for AC-coupled sources, the 1.2 V minimum headroom for the input pins to the positive supply overrides the 1.1 V headroom limit for the output Vocm. Also, the input signal moves this input Vicm around the DC bias point, as described in the Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA section. www.ti.com LMH5485-SEP SBOSA87 – DECEMBER 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LMH5485-SEP

9.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion

The output considerations remain the same as for the AC-coupled design. Again, the input can be DC-coupled while the output is AC-coupled. A DC-coupled input with an AC-coupled output might have some advantages to move the input Vicm down if the source is ground referenced. Figure 8-3 shows how when the source is DC-coupled into the LMH5485 -SEP, both sides of the input circuit must be DC coupled to retain differential balance. Normally, the nonsignal input side has an Rg element biased to whatever the source midrange is expected to be. Providing this midscale reference gives a balanced differential swing around Vocm at the outputs. Often, Rg2 is simply grounded for DC-coupled, bipolar-input applications. This configuration gives a balanced differential output if the source is swinging around ground. If the source swings from ground to some positive voltage, grounding Rg2 gives a unipolar output differential swing from both outputs at Vocm (when the input is at ground) to one polarity of swing. Biasing Rg2 to an expected midpoint for the input signal creates a differential output swing around Vocm. One significant consideration for a DC-coupled input is that Vocm sets up a common-mode bias current from the output back through Rf and Rg to the source on both sides of the feedback. Without input balancing networks, the source must sink or source this DC current. After the input signal range and biasing on the other Rg element is set, check that the voltage divider from Vocm to Vin through Rf and Rg (and possibly Rs) establishes an input Vicm at the device input pins that is in range. If the average source is at ground, the negative rail input stage for the LMH5485-SEP is in range for applications using a single positive supply and a positive output Vocm setting because this DC current lifts the average FDA input summing junctions up off of ground to a positive voltage (the average of the V+ and V– input pin voltages on the FDA).

9.4.1.3 Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA

The design equations for setting the resistors around an FDA to convert from a single-ended input signal to differential output can be approached from several directions. Here, several critical assumptions are made to simplify the results:

• The feedback resistors are selected first and set equal on the two sides.
• The DC and AC impedances from the summing junctions back to the signal source and ground (or a bias voltage on the nonsignal input side) are set equal to retain feedback divider balance on each side of the FDA Both of these assumptions are typical and aimed to delivering the best dynamic range through the FDA signal path. Figure 8-1 and Figure 8-3 shows how after the feedback resistor values are chosen, the aim is to solve for the Rt (a termination resistor to ground on the signal input side), Rg1 (the input gain resistor for the signal path), and Rg2 (the matching gain resistor on the nonsignal input side). The same resistor solutions can be applied to either AC- or DC-coupled paths. Adding blocking capacitors in the input-signal chain is a simple option. Figure 8-1 shows how adding these blocking capacitors after the Rt element has the advantage of removing any DC currents in the feedback path from the output Vocm to ground. Earlier approaches to the solutions for Rt and Rg1 (when the input must be matched to a source impedance, Rs) follow an iterative approach. This complexity arises from the active input impedance at the Rg1 input. When the FDA is used to convert a single-ended signal to differential, the common-mode input voltage at the FDA inputs must move with the input signal to generate the inverted output signal as a current in the Rg2 element. Equation 1shows a more recent solution, where a quadratic in Rt can be solved for an exact required value. This quadratic emerges from the simultaneous solution for a matched input impedance and target gain. The only inputs required are the following: 1. The selected Rf value. 2. The target voltage gain (Av) from the input of Rt to the differential output voltage. 3. The desired input impedance at the junction of Rt and Rg1 to match Rs. As Equation 1 shows, solving this quadratic for Rt starts the solution sequence. LMH5485-SEP SBOSA87 – DECEMBER 2021 www.ti.com ADVANCE INFORMATION

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( ) ( ) Rs2 Rs 2 Rf Av 2 RfRs Av2Rt Rt 02 Rf 2 Av RsAv 4 Av 2 Rf 2 Av RsAv 4 Av § · ¨ ¸ © ¹ (1) Being a quadratic, there are limits to the range of solutions. Specifically, after Rf and Rs are chosen, there is physically a maximum gain beyond which Equation 1 starts to solve for negative Rt values (if input matching is a requirement). With Rf selected, use Equation 2 to verify that the maximum gain is greater than the desired gain. max ( ) 2 Rf4Rf RsAv 2 1 1 RfRs 2Rs ª º « » « » « » « » ¬ ¼ (2) If the achievable Av max is less than desired, increase the Rf value. After Rt is derived from Equation 1, the Rg1 element is given by Equation 3: Rf2 RsAvRg 1 Rs1 Rt (3) Then, the simplest approach is to use a single Rg2 = Rt || Rs + Rg1 on the nonsignal input side. Often, this approach is shown as the separate Rg1 and Rs elements. Using these separate elements provide a better divider match on the two feedback paths, but a single Rg2 is often acceptable. A direct solution for Rg2 is given as Equation 4: Rf2 AvRg2 Rs1 Rt (4) This design proceeds from a target input impedance matched to Rs, signal gain Av from the matched input to the differential output voltage, and a selected Rf value. The nominal Rf value chosen for the LMH5485 -SEP characterization is 402 Ω. As discussed previously, going lower improves noise and phase margin, but reduces the total output load impedance possibly degrading harmonic distortion. Going higher increases the output noise, and might reduce the loop-phase margin because of the feedback pole to the input capacitance, but reduces the total loading on the outputs. Using Equation 2 to Equation 4 to sweep the target gain from 1 to Av max < 14.3 V/V gives Table 9-1, which shows exact values for Rt, Rg1, and Rg2, where a 50 Ω source must be matched while setting the two feedback resistors to 402 Ω. One possible solution for 1% standard values is shown along with the resulting actual input impedance and gain with % errors to the targets in Table 9-1. www.ti.com LMH5485-SEP SBOSA87 – DECEMBER 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LMH5485-SEP

Table 9-1. Required Resistors for a Single-Ended to Differential FDA Design Stepping Gain from

1 V/V to 14 V/V

Av(1) Rt, EXACT (Ω) Rt 1% Rg1, EXACT (Ω) Rg1 1% Rg2, EXACT (Ω) Rg2 1% ACTUAL ZIN %ERR TO Rs ACTUAL GAIN %ERR TO Av (1) Rf = 402 Ω, Rs = 50 Ω, and AvMAX = 14.32 V/V. These equations and design flow apply to any FDA. Using the feedback resistor value as a starting point is particularly useful for current-feedback-based FDAs such as the LMH6554, where the value of these feedback resistors determines the frequency response flatness. Similar tables can be built using the equations provided here for other source impedances, Rf values, and gain ranges. Note the extremely low Rg1 values at the higher gains. For instance, at a gain of 14 V/V, that 7.32 Ω standard value is transformed by the action of the common-mode loop moving the input common-mode voltage to appear like a 50 Ω input match. This active input impedance provides an improved input-referred noise at higher gains. The TINA model correctly shows this actively-set input impedance in the single-ended to differential configuration, and is a good tool to validate the gains, input impedances, response shapes, and noise issues.

9.4.1.4 Input Impedance for the Single-Ended to Differential FDA Configuration

The designs so far have included a source impedance, Rs, that must be matched by Rt and Rg1. The total impedance at the junction of Rt and Rg1 for the circuit of Figure 8-3 is the parallel combination of Rt to ground, and the ZA (active impedance) presented by Rg1. The expression for ZA, assuming Rg2 is set to obtain the differential divider balance, is given by Equation 5: Rg 1 Rf1 1 Rg2 Rg 1ZA Rg 1 Rf2 Rg2 © ¹© ¹ (5) For designs that do not need impedance matching, but instead come from the low impedance output of another amplifier for instance, Rg1 = Rg2 is the single-to-differential design used without an Rt to ground. Setting Rg1 = Rg2 = Rg in Equation 5 gives the input impedance of a simple input FDA driving from a low-impedance, single-ended source to a differential output as shown in Equation 6: Rf1 RgZA 2Rg Rf2 Rg (6) LMH5485-SEP SBOSA87 – DECEMBER 2021 www.ti.com ADVANCE INFORMATION

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In this case, setting a target gain as Rf / Rg ≡ α, and then setting the desired input impedance, allows the Rg element to be resolved first, and then the required Rf to get the gain. For example, targeting an input impedance of 200 Ω with a gain of 4 V/V, Equation 7 gives the physical Rg element. Multiplying this required Rg value by a gain of 4 gives the Rf value and the design of Figure 9-1. 2Rg ZA 2 1 D D (7) Rf1 480 500 Rg1 120 Rg2 120 Output Measurement Point LMH5485 Wideband, Fully-Differential Amplifier Rf2 480 200- Input Impedance, Gain of 4 V/V Design – Vs Vcc Vocm Vcc FDA PD Figure 9-1. 200 Ω Input Impedance, Single-Ended to Differential DC-Coupled Design with Gain of 4 V/V After being designed, this circuit can also be AC-coupled by adding blocking caps in series with the two 120 Ω Rg resistors. This active input impedance has the advantage of increasing the apparent load to the prior stage using lower resistors values, leading to lower output noise for a given gain target.

9.4.2 Differential-Input to Differential-Output Operation

In many ways, this method is a much simpler way to operate the FDA from a design equations perspective. Again, assuming the two sides of the circuit are balanced with equal Rf and Rg elements, the differential input impedance is now just the sum of the two Rg elements to a differential inverting summing junction. In these designs, the input common-mode voltage at the summing junctions does not move with the signal, but must be DC biased in the allowable range for the input pins with consideration given to the voltage headroom required from each supply. Slightly different considerations apply to AC- or DC-coupled, differential-in to differential-out designs, as described in the following sections.

9.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues

There are two typical ways to use the LMH5485 -SEP with an AC-coupled differential source. In the first method, the source is differential and can be coupled in through two blocking capacitors. The second method uses either a single-ended or a differential source and couples in through a transformer (or balun). Figure 9-2 shows a typical blocking capacitor approach to a differential input. An optional input differential termination resistor (Rm) is included in this design. This Rm element allows the input Rg resistors to be scaled up while still delivering lower differential input impedance to the source. In this example, the Rg elements sum to show a 200 Ω differential impedance, while the Rm element combines in parallel to give a net 100 Ω, AC-coupled, differential impedance to the source. Again, the design proceeds ideally by selecting the Rf element values, then the Rg to set the differential gain, then an Rm element (if needed) to achieve a target input impedance. Alternatively, the Rm element can be eliminated, the Rg elements set to the desired input impedance, and Rf set to the get the differential gain (= Rf / Rg). www.ti.com LMH5485-SEP SBOSA87 – DECEMBER 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: LMH5485-SEP

LMH5485 Wideband, Fully-Differential Amplifier Rf2 402 100 nF 100 nF Downconverter Differential Output Rm 200 Vcc Vocm Vcc FDA PD Figure 9-2. Down-Converting Mixer Delivering an AC-Coupled Differential Signal to the LMH5485-SEP The DC biasing here is very simple. The output Vocm is set by the input control voltage. Because there is no DC current path for the output common-mode voltage, that DC bias also sets the input pins common-mode operating points. Transformer input coupling allows either a single-ended or differential source to be coupled into the LMH5485 - SEP, which also improves the input-referred noise figure. These designs assume a source impedance that must be matched in the balun interface. Figure 9-3 shows the simplest approach where an example 1:2 turns ratio step-up transformer is used from a 50 Ω source. Rf1 402 500 Rg1 100 Rg2 100 Output Measurement Point LMH5485 Wideband, Fully-Differential Amplifier Rf2 402 Pulse CX2047LNL 1:2 Turns Ratio Balun N1 N2VG1 90.4 H 100 nFRs Vcc Vocm Vcc FDA PD Figure 9-3. Input Balun Interface Delivers a Differential Input to the LMH5485-SEP In this example, this 1:2 turns ratio step-up transformer provides a source and load match from the 50 Ω source if the secondary is terminated in 200 Ω (turns-ratio squared is the impedance ratio across a balun). The two Rg elements provide that termination as they sum to the differential virtual ground at the FDA summing junctions. The input blocking cap (C1) is optional and included only to eliminate DC shorts to ground from the source. This solution often improves the input-referred noise figure more so than just the FDA using this passive (zero power dissipation) input balun. Defining a few ratios allows a noise figure expression to be written as Equation 8: ‡ ‡ ‡ ( ) ‡ ( ) nni 2 2 2 2 2 n i Rse 1 1 1 n 2 21 8 4NF 10 Log 1 k Rs E D E E E DE DE ¨ ¸ ¨ ¸© ¹ T (8) LMH5485-SEP SBOSA87 – DECEMBER 2021 www.ti.com ADVANCE INFORMATION

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• n ≡ turns ratio (the ohms ratio is then n2)
• α ≡ differential gain in the FDA = Rf / Rg
• β ≡ transformer insertion loss in V/V (from a dB insertion loss, convert to linear attenuation = β)
• kT = 4e-21J at 290 K (17°C) One way to use Equation 8 is to fix the input balun selection, and then sweep the FDA gain by stepping up the Rf value. The lowest-noise method uses just the two Rg elements for termination matching (no Rm element, such as in Figure 9-3) and sweep the Rf values up to assess the resulting input-referred noise figure. While this method can be used with all FDAs and a wide range of input baluns, relatively low-frequency input baluns are an appropriate choice here because the LMH5485 -SEP holds exceptional SFDR for less than 40 MHz applications. Two representative selections, with their typical measured spans and resulting model elements, are shown in Table 9-2. For these two selections, the critical inputs for the noise figures are the turns ratio and the insertion loss (the 0.2 dB for the CX2014LNL becomes a β = 0.977 in the NF expression). Table 9-2. Example Input Step-Up Baluns and Associated Parameters PART NUMBER Rs (Ω) –1-dB FREQUENCY (MHz) INSERTION LOSS (dB) MFR NO. OF DECADES –3-dB FREQUENCY (MHz) TURNS RATIO MODEL ELEMENTS MIN MAX –1-dB POINTS –3-dB POINTS MIN MAX L1 (µH) L2 (µH) k M (µH) Using the typical input referred noise terms for the LMH5485 -SEP (eni = 2.2 nV and i n = 1.9 pA) and sweeping the total gain from the input of the balun to the differential output over a 10-dB to 24-dB span, gives the input noise figure shown in Figure 9-4. Total Gain (dB) Noise Figure (dB) 10 12 14 16 18 20 22 24 ADT2-1T CX2047LNL Figure 9-4. Noise Figure vs Total Gain with the Two Input Baluns of Table 9-2 The 50 Ω referred noise figure estimates show a decreasing input-referred noise for either balun as the gain increases through 24 dB. The only elements changing in these sweeps are the feedback-resistor values, to achieve the total target gain after the step up from the input balun. The example of Figure 9-3 is a gain of 7.86 V/V, or a 17.9-dB gain where a 10.0-dB input noise figure is predicted from Figure 9-4. Another advantage for this method is that the effective noise gain (NG) is reduced by the source impedance appearing as part of the total Rg element in the design. The example of Figure 9-3 operates with a NG = 1 + 402 / (100 + 100) = 3 V/V, giving greater than 300 MHz SSBW in the LMH5485 -SEP portion of the design. Combining that with the 372 MHz in the balun itself gives greater than 200 MHz in this 18-dB gain stage; or an equivalent greater than 1.6-GHz gain bandwidth product in a low-power, high dynamic range interface. Added features and considerations for the balun input of Figure 9-3 include:
• Many of these baluns offer a secondary centertap. Leave the centertap unconnected for the best HD2 suppression and DC biasing (do not include a capacitor from this centertap to ground).
• With a floating secondary centertap, the input pins common-mode voltage again equals the output Vocm setting because there is no DC path for the output common-mode voltage to create a common-mode current (ICM). www.ti.com LMH5485-SEP SBOSA87 – DECEMBER 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: LMH5485-SEP

10 Power Supply Recommendations

The LMH5485-SEP is principally intended to operate with a nominal single-supply voltage of +3 V to +5 V. Supply decoupling is required, as described in the Layout Guidelines . The amplifier signal path is flexible for single or split-supply operation. Most applications are intended to be single supply, but any split-supply design can be used, as long as the total supply across the LMH5485-SEP is less than 5.25 V and the required input, output, and common-mode pin headrooms to each supply are observed. Left open, the Vocm pin defaults to near mid-supply for any combination of split or single supplies used. The disable pin is negative-rail referenced. Using a negative supply requires the disable pin to be pulled down to within 0.7 V of the negative supply to disable the amplifier.

11 Layout

11.1 Layout Guidelines

Similar to all high-speed devices, best system performance is achieved with a close attention to board layout. The LMH5485-SEP evaluation module (EVM) shows a good example of high frequency layout techniques as a reference. This EVM includes numerous extra elements and features for characterization purposes that may not apply to some applications. General high-speed, signal-path layout suggestions include the following:

• Continuous ground planes are preferred for signal routing with matched impedance traces for longer runs; however, ground and power planes around the capacitive sensitive input and output device pins should be open. After the signal is sent into a resistor, the parasitic capacitance becomes more of a band limiting issue and less of a stability issue.
• Use good, high-frequency decoupling capacitors (0.1 µF) on the ground plane at the device power pins. Higher value capacitors (2.2 µF) are required, but may be placed further from the device power pins and shared among devices. A supply decoupling capacitor across the two power supplies (for bipolar operation) should also be added. For best high-frequency decoupling, consider X2Y supply-decoupling capacitors that offer a much higher self-resonance frequency over standard capacitors.
• For each LMH5485-SEP, attach a separate 0.1 µF capacitor to a nearby ground plane. With cascaded or multiple parallel channels, including ferrite beads from the larger capacitor is often useful to the local high-frequency decoupling capacitor.
• When using differential signal routing over any appreciable distance, use microstrip layout techniques with matched impedance traces.
• The input summing junctions are very sensitive to parasitic capacitance. Connect any Rg elements into the summing junction with minimal trace length to the device pin side of the resistor. The other side of the Rg elements can have more trace length if needed to the source or to ground. LMH5485-SEP SBOSA87 – DECEMBER 2021 www.ti.com ADVANCE INFORMATION

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, Design for a Wideband, Differential Transimpedance DAC Output application report
• Texas Instruments, Extending Rail-to-Rail Output Range for Fully Differential Amplifiers to Include True Zero Volts reference guide
• Texas Instruments, LMH6554 2.8-GHz Ultra Linear Fully Differential Amplifier data sheet
• Texas Instruments, LMH5485-SP-EVM user guide
• Texas Instruments, Maximizing the dynamic range of analog front ends having a transimpedance amplifier technical brief

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com LMH5485-SEP SBOSA87 – DECEMBER 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: LMH5485-SEP

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13.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PLMH5485DGKSEP VSSOP DGK 8 80 180 12.4 5.3 3.4 1.4 8 12 Q1 www.ti.com LMH5485-SEP SBOSA87 – DECEMBER 2021 ADVANCE INFORMATION Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: LMH5485-SEP

TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PLMH5485DGKSEP VSSOP DGK 8 80 210 185 35 LMH5485-SEP SBOSA87 – DECEMBER 2021 www.ti.com ADVANCE INFORMATION

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www.ti.com 16-Feb-2022 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PLMH5485DGKSEP ACTIVE VSSOP DGK 8 80 TBD Call TI Call TI -55 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LMH5485-SEP :

www.ti.com 16-Feb-2022 Addendum-Page 2

• Space : LMH5485-SP NOTE: Qualified Version Definitions:
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

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