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Sample & Buy T echnical Documents Tools & Software Support & Community LMG5200 SNOSCY4B –MARCH 2015–REVISED JANUARY 2016 GaNTECHNOLOGYPREVIEW LMG520080-V,GaNHalf-BridgePowerStage
1 Features 3 Description
The LMG5200 device, a 80-V driver, GaN half-bridge 1• Input Voltage up to 80-V DC power stage, provides an integrated power stage• Integrated 80-V, 18-mΩ, GaN FETs solution using enhancement-mode Gallium Nitride
- Optimized Pinout for Easy PCB Layout (GaN) FETs. The device consists of two, 80-V GaN FETs driven by one high-frequency GaN FET driver• Internal Bootstrap Supply Voltage Clamping to in a half-bridge configuration.Prevent GaN FET Overdrive
- Supply Rail Undervoltage Lockout The TTL logic compatible inputs can withstand input voltages up to 14 V regardless of the VCC voltage.• Independent High-Side and Low-Side TTL Logic The proprietary bootstrap voltage clamping techniqueInputs ensures the gate voltages of the enhancement mode• Fast Propagation Times (29.5 ns Typical) GaN FETs are within a safe operating range. GaN
- Excellent Propagation Delay Matching (2 ns FETs provide significant advantages for power conversion as they have near zero reverse recoveryTypical) and very small input capacitance CISS. All the devices• Low Power Consumption are mounted on a completely bond-wire-free package platform with minimized package parasitic elements.2 Applications The LMG5200 device is available in a 6 mm x 8 mm
- Multi MHz Synchronous Buck Converters x 2 mm lead free package and can be easily mounted on PCBs.• Class D Amplifiers for Audio The device extends advantages of discrete GaN• 48-V Point-of-Load (POL) Converters for FETs by offering a more user-friendly interface. It isIndustrial, Computing and Telecom an ideal solution for applications requiring high- frequency, high-efficiency operation in a small form factor. It reduces the board requirements for maintaining clearance and creepage requirements for medium voltage GaN applications while minimizing the loop inductances to ensure fast switching. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LMG5200 QFN (9) 6.00 mm × 8.00 mm × 2.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Application An IMPORTANT NOTICE at the end of this document addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. GaN TECHNOLOGY PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice.
SNOSCY4B –MARCH 2015–REVISED JANUARY 2016 www.ti.com Table of Contents
4 Revision History
Changes from Revision A (March 2015) to Revision B Page Changes from Original (March 2015) to Revision A Page
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www.ti.com SNOSCY4B –MARCH 2015–REVISED JANUARY 2016
5 Pin Configuration and Functions
MOF (QFN) PACKAGE
9 PINS
(TOP VIEW) Pin Functions PIN I/O(1) DESCRIPTION NAME NO. AGND 7 G Analog ground. Ground of driver device. HB 2 P High-side gate driver bootstrap rail. HI 4 I High-side gate driver control input HS 3 P High-side GaN FET source connection LI 5 I Low-side driver control input PGND 9 G Power ground. Low-side GaN FET source. Electrically shorted to AGND pin. SW 8 P Switching node. Electrically shorted to HS pin. VCC 6 P 5-V positive gate drive supply VIN 1 P Input voltage pin. Electrically connected to high-side GaN FET drain. (1) I = Input, O = Output, G = Ground, P = Power Copyright © 2015–2016, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LMG5200
SNOSCY4B –MARCH 2015–REVISED JANUARY 2016 www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VIN (2) 0 90 HB(3) –0.3 96 HS(3) –5 90 Input voltage HI, LI(3) –0.3 15 V VCC(2), HB to HS –0.3 6 HB to VCC 0 90 SW (2) –5 90 Output current Pulsed current from SW pin (10-µs duration) 40 A Operating junction temperature, TJ –40 125 °C Storage temperature, Tstg –40 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) with respect to PGND (3) with respect to AGND
6.2 ESD Ratings
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000ElectrostaticV(ESD) Vdischarge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCC 4.75 5 5.25 V Input voltage range LI or HI Input 0 14 V HS, VIN, SW -5 80 V HB VHS+ 4 VHS+ 5.5 V Output voltage range HS, SW Slew rate 50 V/ns IOUT from SW pin 10 A Junction temperature, TJ -40 125 °C
6.4 Thermal Information
THERMAL METRIC(1)(2) QFN UNIT RθJA Junction-to-ambient thermal resistance 40 RθJC(top) Junction-to-case (top) thermal resistance 12 RθJB Junction-to-board thermal resistance 12 °C/W ψJT Junction-to-top characterization parameter 2.8 ψJB Junction-to-board characterization parameter 23 RθJC(bot) Junction-to-case (bottom) thermal resistance 12 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
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www.ti.com SNOSCY4B –MARCH 2015–REVISED JANUARY 2016
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENTS IVCC VCC quiescent current LI = HI = 0 V, VVCC = 5 V 0.07 0.1 mA ICCO VCC operating current f = 500 kHz 3.0 5.0 mA IHB Total HB quiescent current LI = HI = 0 V, VVCC = 5 V 0.09 0.120 mA f = 500 kHz, 50% Duty cycle,IHBO Total HB operating current 1.5 2 mAVDD = 5 V INPUT PINS VIH High-level input voltage Rising edge 1.89 2.06 2.18 V VIL Low-level input voltage Falling edge 1.48 1.66 1.76 V Hysteresis between rising and fallingVHYS 400 mVthreshold RI Input pull-down resistance 100 200 300 kΩ UNDERVOLTAGE PROTECTION VVCC VCC rising edge threshold Rising 3.2 3.8 4.5 V Hysteresis between falling and risingVVCC(hyst) 185 mVedge VHB HB rising edge threshold Rising 2.7 3.2 3.7 V HB hysteresis between rising edge 185 mVand falling edge BOOTSTRAP DIODE VDL Low-current forward voltage IVDD-HB = 100 µA 0.45 0.65 V VDH High-current forward voltage IVDD-HB = 100 mA 0.9 1.0 V RD Dynamic resistance 1.6 2.8 Ω HB-HS clamp Regulation voltage 4.7 5 5.3 V Bootstrap diode reverse recoverytBS IF = 100 mA, IR = 100 mA 40 nstime Bootstrap diode reverse recoveryQRR VVIN = 50 V 2 nCcharge POWER STAGE RDS(on)HS High-side GaN FET on-resistance IOUT = 5 A, VVCC = 5 V, TJ = 25ºC 14 18 mΩ RDS(on)LS Low-side GaN FET on-resistance IOUT = 5 A, VVCC = 5 V, TJ = 25ºC 14 18 mΩ ISD = 500 mA, VIN floating,VSD GaN 3rd quadrant conduction drop 2 VVVCC = 5 V, HI, LI low Leakage between VIN to SW when VIN = 80 V, (HI = LI = 0 V)IL-VIN-SW the high-side GaN FET and low-side 25 150 µAVVCC = 5 V, TJ = 25ºCGaN FET are off Leakage between SW and GND VSW = 80 V, HI , LI = 0 V, VVCC = 5 IL-SW-GND when the high-side GaN FET and V, 25 150 µA low-side GaN FET are off TJ = 25ºC Output capacitance of high-side VDS = 50 V, VGS = 0 VCOSS 225 280 pFGaN FET and low-side GaN FET (HI = LI = 0 V) QG Total gate charge VDS = 50 V, ID = 10 A, VGS = 5 V 3.8 nC QOSS Output charge VDS = 50 V, ID = 10 A 20 nC Source to drain reverse recovery Not including internal driverQRR 0 nCcharge bootstrap diode Copyright © 2015–2016, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LMG5200
SNOSCY4B –MARCH 2015–REVISED JANUARY 2016 www.ti.com Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC CHARACTERISTICS HI turning from low to high and SW tHIPLH node being pulled to VIN (LO is 29.5 47 ns low), VVIN = 50 V, VVCC = 5 V HI turning from high to low and SW tHIPHL node being tristated (LO is low), 29.5 47 ns VVIN = 50 V, VVCC = 5 V Propagation delay(1) LI turning from low to high and tLPLH switch node being pulled to PGND 29.5 47 ns (HI is low), VVIN = 50 V, VVCC = 5 V LI turning from high to low and tLPHL switch node being tristated (HI is 29.5 47 ns low), VVIN = 50 V, VVCC = 5 V Delay matching: LI high and HI lowtMON VVIN = 50 V, VVCC = 5 V 2 8.0 ns(2) Delay matching: LI low and HItMOFF VVIN = 50 V, VVCC = 5 V 2 8.0 nshigh(2) Minimum input pulse width thattPW 10 nschanges the output (1) See Propagation Delay and Mismatch Measurement section. (2) See Figure 6 through Figure 9.
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400 LFM
200 LFM
100 LFM
6.6 Typical Characteristics
0.062 inch (T) and 4 copper layers of 2 oz. area for different airflow conditions. Figure 2. Safe Operating AreaFigure 1. VDD Supply Current vs Switching Frequency .GaN third quadrant conduction. Figure 4. GaN FET On-Resistance vs Junction TemperatureFigure 3. Source-to-Drain Current vs Source-to-Drain
7 Parameter Measurement Information
7.1 Propagation Delay and Mismatch Measurement
turns ON and the high-side GaN FET turns OFF and vice versa to measure the tMON and tMOFF parameters. Figure 5. Propagation Delay and Propagation Mismatch Measurement
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Figure 6. High-Side Gate Driver Turn-On Figure 7. Low-Side Gate Driver Turn-On Figure 8. High-Side Gate Driver Turn-Off Figure 9. Low-Side Gate Driver Turn-Off
8 Detailed Description
8.1 Overview
optimized to ensure high voltage slew rates without causing any excessive ringing on the gate or power loop.
8.2 Functional Block Diagram
Figure 10. Functional Block Diagram
8.3 Feature Description
<10 ns. Co-packaging the GaN FET half-bridge with the driver ensures minimized common source inductance. This minimized inductance has a significant performance impact on hard-switched topologies. the device as possible to minimize parasitic inductance.
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/c61 /c180 /c180 /c180SW IN OUT SW TRP V I f t /c40 /c41/c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 /c230 /c246 /c230 /c246/c61 /c180 /c43 /c180/c231 /c247 /c231 /c247 /c232 /c248 /c232 /c248 2 2 COND RMS HS DS on HS RMS LS DS on LSP I R I R /c40 /c41/c61 /c180 /c180 /c180 g DD SWP 2 Q V f /c43 /c43 /c43/c230 /c246 /c62 /c231 /c247 /c231 /c247 /c68/c232 /c248 gH HB ON(max) rr BST Q I t Q C V LMG5200 www.ti.com SNOSCY4B –MARCH 2015–REVISED JANUARY 2016 Feature Description (continued)
8.3.1 Bootstrap Capacitor
The bootstrap capacitor provides the gate charge for the high-side gate drive, dc bias power for HB undervoltage lockout circuit, and the reverse recovery charge of the bootstrap diode. The required bypass capacitance can be calculated using Equation 1. where
- IHB is the quiescent current of the high-side gate driver (100 µA, max)
- tON(max) is the maximum on-time period of the high-side gate driver
- Qrr is the reverse recovery charge of the bootstrap diode
- QgH is the gate charge of the high-side GaN FET
- ΔV is the permissible ripple in the bootstrap capacitor (< 100 mV, typ) (1) A 100-nF, 16-V, 0402 ceramic capacitor is suitable for most applications. Place the bootstrap capacitor as close to the HB and HS pins as possible.
8.3.2 Power Dissipation
Ensure that the power loss in the driver and the GaN FETs is maintained below the maximum power dissipation limit of the package at the operating temperature. The smaller the power loss in the driver and the GaN FETs, the higher the maximum operating frequency that can be achieved in the application.. The total power dissipation of the LMG5200 device is the sum of the gate driver losses, the bootstrap diode power loss and the switching and conduction losses in the FETs. The gate driver losses are incurred by charge and discharge of the capacitive load. It can be approximated using Equation 2. where
- Qg is the gate charge
- VDD is the bias supply
- fSW is the switching frequency (2) There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the outputs. Figure 1 shows the measured gate driver power dissipation versus frequency and load capacitance. Use this graph to approximate the power losses due to the gate drivers. The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Because each of these events happens once per cycle, the diode power loss is proportional to the operating frequency. Higher input voltages (VIN) to the half bridge also result in higher reverse recovery losses. The power losses due to the GaN FETs can be divided into conduction losses and switching losses. Conduction losses are resistive losses and can be calculated using Equation 3. where
- RDS(on)HS is the high-side GaN FET on-resistance
- RDS(on)LS is the low-side GaN FET on-resistance
- IRMS(HS) is the high-side GaN FET RMS current
- IRMS(LS) and low-side GaN FET RMS current (3) The switching losses can be computed to a first order using Equation 4. Copyright © 2015–2016, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: LMG5200
SNOSCY4B –MARCH 2015–REVISED JANUARY 2016 www.ti.com Feature Description (continued) where
- tTR is the switch transition time from ON to OFF and from OFF to ON (4) Note that the low-side FET does not suffer from this loss. The third quadrant loss in the low-side device is ignored in this first order loss calculation. The sum of the driver loss, the bootstrap diode loss and the switching and conduction losses in the GaN FETs is the total power loss of the device. Careful board layout with an adequate amount of thermal vias close to the power pads (VIN, SW and GND) allows optimum power dissipation from the package. A top-side mounted heat sink with airflow can also improve the package power dissipation.
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9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Figure 11. Typical Connection Diagram For a Buck Converter
10 Power Supply Recommendations
11 Layout
11.1 Layout Guidelines
more closely spaced due to negligible pollution. Figure 12. External Component Placement (Single Layer)
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4 Layer PCB
Figure 13. Four Layer Board Cross Section With Return Path Directly Underneath for Power Loop Figure 14. Top Layer Figure 15. Ground Plane
Figure 16. Middle Layer Figure 17. Bottom Layer Figure 18. External Component Placement (Double Layer PCB)
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2 Layer PCB
Figure 19. Two Layer Board Cross Section With Return Path Two-layer boards are not recommended for use with LMG5200 device due to the larger power loop inductance. behind the device on the back-side of the board to minimize loop inductance.
SNOSCY4B –MARCH 2015–REVISED JANUARY 2016 www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
LMG5200 PSpice Transient Model LMG5200 TINA-TI Transient Reference Design
12.2 Documentation Support
12.2.1 Related Documentation
Layout Guidelines for LMG5200 GaN Power Stage Module (SNVA729) Using the LMG5200: GaN Half-Bridge Power Module Evaluation Module (SNVU461)
12.3 Trademarks
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
13.1 Package Information
The LMG5200 device package is rated as a MSL3 package (Moisture Sensitivity Level 3). Please refer to application report SNOA550 for specific handling and process recommendations of a MSL3 package. Figure 20 and Figure 21 show preliminary packaging information for the device.
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2 MAX
Figure 20. Package Top, Side and Bottom View
0.07 MAX
0.07 MIN
Figure 21. Package Bottom View Showing Pinout
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www.ti.com 6-Jan-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PLMG5200MOFT ACTIVE QFM MOF 9 250 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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