PLM76202QPWPRQ1

LM76202-Q1_V01 TI1 | Alldatasheet

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Technical content

150 PŸ IN OUT UVLO dVdT RTN ILIM OVP IMON RIMON VIN VOUT R ILIM FLT GND SHDN MODE R FLTb CIN Health Monitor ON/OFF Control Load MonitorTVS R 1 R 2 C dVdT Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM76202-Q1 SLVSEM1A – MARCH 2019– REVISED SEPTEMBER 2019 LM76202-Q160-V,2.2-AIntegratedIdealDiodewithOvervoltageandOvercurrent Protection

1 Features

1• AEC-Q100 qualified for automotive applications – Temperature grade 1: –40°C ≤ TA ≤ +125°C – AEC-Q100-012 short circuit reliability Grade A – HBM ESD classification level 2 – CDM ESD classification level C6

• 4.2-V to 60-V operating voltage, 62-V maximum
• Integrated reverse input polarity protection down to –60-V
• Integrated back-to-back MOSFETs with 150 mΩ total RON
• Transient immunity up-to 65 V
• 0.1-A to 2.23-A adjustable current limit (±5% accuracy at 1 A)
• Load protection during ISO7637 and ISO16750-2 testing
• Short to battery and short to ground protection
• Reverse current blocking for protection from output short to battery
• IMON current indicator output (±8.5% accuracy)
• Low quiescent current (285 µA in operating, 16 µA in shutdown)
• Adjustable UVLO, OVP cut off, inrush current control
• Factory set 38-V overvoltage clamp option
• Selectable current-limiting fault response options (auto-retry, latch off, CB modes)
• Available in easy to use 16-Pin HTSSOP package

2 Applications

• Front camera, Rear camera
• Drive assist ECU
• Telematics control unit
• Cellular module asset tracking

3 Description

The LM76202-Q1 device is a compact, feature-rich 60-V integrated ideal diode with a full suite of protection features. The wide supply input range allows control of 12-V and 24-V automotive battery driven applications. The device withstands and protects the loads from positive and negative supply voltages up to ±60 V. Load, source and device protection are provided with many programmable features including overcurrent, inrush current control, overvoltage and undervoltage thresholds. The internal robust protection control blocks along with the 60-V rating of the device simplifies the system design for ISO standard pulse tesing. A shutdown pin provides external control for enabling and disabling the internal FETs and places the device in a low current shutdown mode. For system status monitoring and downstream load control, the device provides fault output and precise current monitor output. The MODE pin allows flexibility to configure the device between the three current-limiting fault responses (circuit breaker, latch off, and auto-retry modes). The device monitors V(IN) and V(OUT) to provide reverse current blocking when V(IN) < (V(OUT)-10mV). This function protects system bus from overvoltages during output short to battery faults and also helps in voltage holdup requirements during power fail and brownout conditions. The device is available in a 5 mm × 4.4 mm 16-pin HTSSOP and is fully specified over a –40°C to +125°C temperature range. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LM76202-Q1 HTSSOP (16) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic ISO16750-2 Load Dump Pulse 5b Performance at 24 V

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12.2 Receiving Notification of Documentation Updates 32

13 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Original (March 2019) to Revision A Page

3RZHU3$'Œ Integrated Circuit Package OVP UVLO IN MODE IN SHDN RTN NC OUT OUT GND dVdT ILIM IMON FLT NC LM76202-Q1 www.ti.com SLVSEM1A – MARCH 2019–REVISED SEPTEMBER 2019 Product Folder Links: LM76202-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

5 Pin Configuration and Functions

16-Pin HTSSOP With Exposed Thermal Pad Top View Pin Functions PIN TYPE DESCRIPTION NO. NAME 1, 2 IN P Input supply voltage. See IN, OUT, RTN and GND Pins section.

3 UVLO I

Input for setting the programmable Undervoltage Lockout threshold. An undervoltage event turns off the internal FET and asserts FLT to indicate power failure. If the Undervoltage Lockout function is not needed, the UVLO terminal must be connected to the IN terminal. See Undervoltage Lockout (UVLO) section. 4, 13 NC — No internal connection. These pins can be connected to RTN for enhanced thermal performance.

5 OVP I

Input for setting the programmable Overvoltage Protection threshold. An overvoltage event turns off the internal FET and asserts FLT to indicate the overvoltage fault. For fixed overvoltage clamp response connect OVP to RTN externally. See Overvoltage Protection (OVP) section. 6 MODE I Mode selection pin for overload fault response. See the Device Functional Modes section.

7 SHDN I

Shutdown pin. Pulling SHDN low enters the device into low-power shutdown mode. Cycling SHDN pin voltage resets the device that has latched off due to a fault condition. See Low Current Shutdown Control (SHDN) section. 8 RTN — Reference for device internal control circuits. If reverse input polarity protection is not required, this pin can be connected to GND. See IN, OUT, RTN and GND Pins section. 9 GND — Connect GND to system ground. See IN, OUT, RTN and GND Pins section.

10 IMON O

Analog current monitor output. This pin sources a scaled down ratio of current through the internal FET. A resistor from this pin to RTN converts current to proportional voltage. If pin is unused, leave pin floating. See Current Monitoring section. 11 ILIM I/O A resistor from this pin to RTN sets the overload and short-circuit current limit. See the Overload and Short Circuit Protection section. 12 dVdT I/O A capacitor from this pin to RTN sets output voltage slew rate. See the Hot Plug-In and In- Rush Current Control section. 14 FLT O Fault event indicator. Indicator is an open drain output. If indicator is unused, leave indicator floating. See FAULT Response section. 15,16 OUT P Power output of the device. See IN, OUT, RTN and GND Pins section. PowerPAD — PowerPAD integrated circuit package must be connected to RTN plane on PCB using multiple vias for enhanced thermal performance. PowerPAD is not internally connected to RTN. Do not use the PowerPAD as the only electrical connection to RTN.

SLVSEM1A – MARCH 2019– REVISED SEPTEMBER 2019 www.ti.com Product Folder Links: LM76202-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range, all voltages referred to GND (unless otherwise noted)(1) MIN MAX UNIT IN, IN-OUT -62 62 V IN, IN-OUT (350ms transient), TA = 25°C -65 65 [IN, OUT, FLT, UVLO, SHDN] to RTN -0.3 62 [OVP, dVdT, ILIM, IMON, MODE] to RTN -0.3 5 RTN -62 0.3 IFLT, IdVdT, ISHDN Sink current 10 mA IdVdT, IILIM, IIMON Source Current Internally limited Internally limited TJ Operating junction temperature -40 150 °C Transient junction temperature -65 T(TSD) °C Tstg Storage Temperature -65 150 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 VCharged device model (CDM), per AEC Q100-011 All pins ±1000

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT IN Input voltage range -60 60 VUVLO, OUT, FLT 0 60 OVP, dVdT, ILIM, IMON, SHDN 0 4 ILIM Resistance 5.36 120 kΩ IMON 1 IN, OUT External capacitance 0.1 1 µF dVdT 10 nF TJ Operating junction temperature range -40 25 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) LM76202-Q1 UNITPWP (HTSSOP)

16 PINS

RθJA Junction-to-ambient thermal resistance 38.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 22.7 °C/W RθJB Junction-to-board thermal resistance 18.2 °C/W ΨJT Junction-to-top characterization parameter 0.5 °C/W YJB Junction-to-board characterization parameter 18 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.5 °C/W

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6.5 Electrical Characteristics

–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 12 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(IN) = 0.1 μF, C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE V(IN) Operating input voltage 4.2 60 V VPORR Internal POR Threshold, Rising 3.89 4 4.14 V VPORHys Internal POR Hysteresis 55 275 305 mV IQON Supply Current with device enabled VIN = 24V, Enabled: V(SHDN) = 2 V 300 398 µA IQON Supply Current with device enabled VIN = 12V Enabled: V(SHDN) = 2 V, 285 390 µA IQOFF Supply Current with device disabled VIN = 24V, V(SHDN) = 0 V 18 35 µA IQOFF Supply Current with device disabled VIN = 12V, V(SHDN) = 0 V 16 32 µA IVINR Reverse Input supply current V(IN) = -60 V, V(OUT) = 0 V 66 µA UNDERVOLTAGE LOCKOUT (UVLO) INPUT V(UVLOR) UVLO Threshold Voltage, Rising 1.175 1.19 1.25 V V(UVLOR) UVLO Threshold Voltage, Falling 1.08 1.1 1.126 V I(UVLO) UVLO Input leakage current 0 V ≤ V(UVLO) ≤ 60 V –100 100 nA LOW IQ SHUTDOWN (SHDNb) INPUT V(SHDN) Output voltage I(SHDN) = 0.1µA 2 2.7 3.4 V V(SHUTF) SHDN Threshold Voltage for Low IQ Shutdown, Falling 0.45 V V(SHUTFR) SHDN Threshold, Rising 0.96 V I(SHDN) Input current V(SHDN) = 0.4 V -10 µA OVER VOLTAGE PROTECTION (OVP) INPUT V(SEL_OVP) Factory Set OV Clamp Select Threshold 180 200 240 mV VOVC Internal Over voltage clamp V(IN) > 42 V, I(OUT)=10mA V(OVP) = 0 V 36 37.5 40 V V(OVPR) Over-Voltage Threshold Voltage, Rising 1.175 1.19 1.225 V V(OVPF) Over-Voltage Threshold Voltage, Falling 1.085 1.125 I(OVP) OVP Input Leakage Current 0V ≤ V(OVP) ≤ 4V –100 0 100 nA OUTPUT RAMP CONTROL (dVdT) I(dVdT) dVdT Charging Current V(dVdT) = 0 V 4 4.7 5.82 µA R(dVdT) dVdT Discharging Resistance SHDN = 0 V, with I(dVdT) = 10mA sinking 28 Ω GAIN(dVdT) dVdT to OUT Gain △V(OUT) /△V(dVdT) 23.75 24.63 25.5 V/V CURRENT LIMIT PROGRAMMING (ILIM) V(ILIM) ILIM Bias Voltage 1 V I(OL) Overload Current Limit R(ILIM) = 120 kΩ, V(IN)-V(OUT)=1V 0.085 0.1 0.115 A R(ILIM) = 12 kΩ, V(IN)-V(OUT)=1V 0.95 1 1.05 R(ILIM) = 8 kΩ, V(IN)-V(OUT)=1V 1.425 1.5 1.575 R(ILIM) = 5.36 kΩ, V(IN)-V(OUT)=1V 2.11 2.23 2.35 I(OL_R-OPEN) R(ILIM)= OPEN, Open Resistor Current Limit 0.055 I(OL_R-SHORT) R(ILIM)= SHORT, Shorted Resistor Current Limit 0.095 I(CB) Circuit breaker detection threshold R(ILIM) = 120 kΩ, MODE = open 0.045 0.073 0.11 A I(CB) Circuit breaker detection threshold R(ILIM) = 5.36 kΩ, MODE = open 2 2.21 2.4 A

SLVSEM1A – MARCH 2019– REVISED SEPTEMBER 2019 www.ti.com Product Folder Links: LM76202-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Electrical Characteristics (continued) –40°C ≤ TA = TJ ≤ +125°C, V(IN) = 12 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(IN) = 0.1 μF, C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I(SCL) Short-Circuit Current Limit R(ILIM) = 120 kΩ, V(IN)-V(OUT)=5V 0.08 0.1 0.12 A R(ILIM) = 8 kΩ, V(IN)-V(OUT)=5V 1.425 1.5 1.575 A R(ILIM) = 5.36 kΩ, V(IN)-V(OUT)=5V 2.11 2.23 2.35 A I(FASTRIP) Fast-trip comparator threshold 1.87 x I(OL) + 0.015 A CURRENT MONITOR OUTPUT (IMON) GAIN(IMON) Gain Factor I(IMON):I(OUT) 0.1A ≤ I(OUT) ≤ 2A 72 78.28 85 µA/A PASS FET OUTPUT (OUT) RON IN to OUT Total ON Resistance 0.1A ≤ I(OUT) ≤ 2A,TJ = 25°C 130 150 168 mΩ0.1A ≤ I(OUT) ≤ 2A, -40°C ≤ TJ ≤ 85°C 150 220 0.1A ≤ I(OUT) ≤ 2A, -40°C ≤ TJ ≤ 125°C 78 150 265 Ilkg(OUT) OUT Leakage Current in Off State V(IN) = 60 V, V(SHDN)= 0 V, V(OUT) = 0 V, Sourcing 12 µA Ilkg(OUT) OUT Leakage Current in Off State V(IN) = 0 V, V(SHDN)= 0 V, V(OUT) = 24 V, Sinking -11 11 µA V(IN) = -60 V, V(SHDN)= 0 V, V(OUT) = 0 V, Sinking -40 -18 50 V(REVTH) V(IN)-V(OUT) Threshold for Reverse Protection Comparator, Falling -16.2 -10 -5 mV V(FWDTH) V(IN)-V(OUT) Threshold for Reverse Protection Comparator, Rising 85 96 110 mV FAULT FLAG (FLTb): ACTIVE LOW R(FLT) FLT Pull-Down Resistance V(OVP) = 2 V, I(FLT) = 5mA sinking 350 Ω I(FLT) FLT Input Leakage Current 0 V ≤ V(FLT) ≤ 60 V –200 200 nA THERMAL SHUT DOWN (TSD) T(TSD) TSD Threshold, rising 157 °C TSD hysteresis 10.1 °C MODE MODE_SEL Thermal fault mode selection MODE = 402 kΩ to RTN Current limiting with latch MODE = Open Circuit breaker mode with auto-retry MODE = Short to RTN Current limiting with auto- retry

6.6 Timing Requirements

–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 12 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(IN) = 0.1 μF, C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT UVLO INPUT UVLO Turn On Delay UVLO_tON(dly) UVLO↑ (100mV above V(UVLOR)) to V(OUT) = 100mV, C(dvdt) = Open 80 µs UVLO_tON(dly) UVLO↑ (100mV above V(UVLOR)) to V(OUT) = 100mV, C(dvdt) ≥ 10 nF, [C(dvdt) in nF] 80+14. 5 x C(dvdt) UVLO Turn-Off delay UVLO_toff(dly) UVLO↓ (100mV below V(UVLOF)) to FLT ↓ 9 µs SHUTDOWN INPUT

www.ti.com SLVSEM1A – MARCH 2019–REVISED SEPTEMBER 2019 Product Folder Links: LM76202-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated Timing Requirements (continued) –40°C ≤ TA = TJ ≤ +125°C, V(IN) = 12 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(IN) = 0.1 μF, C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT SHUTDOWN Exit delay SHDN_ton(dly) SHDN ↑ (above V(SHUTR) to V(OUT) = 100mV, C(dvdt) ≥ 10 nF, [C(dvdt) in nF] 350+14 .5 x C(dvdt) µs SHDN_ton(dly) SHDN ↑ (above V(SHUTR) to V(OUT) = 100mV, C(dvdt)= Open 355 SHUTDOWN Entry delay SHDN_toff(dly) SHDN ↓ (below V(SHUTF) to FLT ↓ 10 µs OVP INPUT OVP Exit delay tOVP(dly) OVP ↓(20mV below V(OVPF)) to V(OUT) = 100mV 205 µs OVP Disable delay tOVP(dly) OVP↑ (20mV above V(OVPR)) to FLT ↓ 2 µs OVP clamp delay tOVC(dly) V(IN) step from 24V to 60V in 50µs, Iload: 10mA, CL: 0.1uF. OVP connected to RTN 3 µs CURRENT LIMIT Fast-Trip Comparator Delay tFASTTRIP(dly) I(OUT) = 1.5x I(FASTRIP) 170 ns REVERSE CURRENT BLOCKING COMPARATOR RCB comparator delay tREV(dly) (V(IN)-V(OUT)) ↓ (100mV overdrive below V(REVTH)) to internal FET OFF 1.29 µs (V(IN)-V(OUT)) ↓ (10mV overdrive below V(REVTH)) to FLT ↓ 40 µs tFWD(dly) (V(IN)-V(OUT)) ↑ (10mV overdrive above V(FWDTH)) to FLT ↑ 60 µs THERMAL SHUTDOWN Retry Delay in TSD tretry 540 ms OUTPUT RAMP TIME Output Ramp Time tdVdT SHDN↑ to V(OUT) = V(IN) 1.6 ms SHDN↑ to V(OUT) = V(IN), with C(dVdT) = 47nF 10 ms FAULT FLAG FLT assertion delay in circuit breaker mode tCB(dly) MODE = OPEN,Delay from I(out)>I(lim) to FLT ↓(and internal FET turned off) 4 ms Retry Delay in circuit breaker mode tCBretry(dly) MODE= OPEN, C(dVdT) = Open. I(out)>I(lim). Delay from FLT ↓ to V(dVdT) = 50mV (Rising) 540 ms PGOOD delay time tPGOODR Delay for rising FLT edge 1.8 ms tPGOODF Delay for falling FLT edge 900 µs

6.7 Typical Characteristics

Figure 1. POR Threshold (VPOR) vs Temperature Figure 2. Supply Current ON (IQON) vs Supply Voltage (VIN) Figure 3. Supply Current OFF (IQOFF) vs Supply Voltage Figure 4. UVLO Thresholds (VUVLOR, VUVLOF) vs Temperature Figure 5. OVP Thresholds (VOVPR, VOVPF) vs Temperature Figure 6. GAIN(dVdT) vs Temperature

7 Parameter Measurement Information

Figure 19. Timing Waveforms

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8 Detailed Description

8.1 Overview

LM76202-Q1 is an ideal diode with integrated back-to-back FETs and enhanced built-in protection circuitry. It provides robust protection for all systems and applications powered from 4.2 V to 60 V. The device integrates reverse battery input, reverse current, overvoltage, undervoltage, overcurrent and short circuit protection. The precision overcurrent limit (±5% at 1A) helps to minimize over design of the input power supply, while the fast response short circuit protection immediately isolates the load from input when a short circuit is detected. The device allows the user to program the overcurrent limit threshold between 0.1 A and 2.23 A with an external resistor. The device monitors the bus voltage for brown-out and overvoltage protection, asserting the FLTb pin to notify downstream systems. The device is designed to protect systems such as ADAS camera supplies against sudden output short to battery events. The device monitors V(IN) and V(OUT) to provide true reverse blocking from output when output short to battery fault condition or input power fail condition is detected. The internal robust protection control blocks of the LM76202-Q1 device along with its ±60 V rating helps to simplify the system designs for the various ISO and LV124 compliance ensuring complete protection of the load and the device. The device monitors V(IN) and V(OUT) to provide true reverse current blocking when a reverse condition or input power failure condition is detected. The LM76202-Q1 device is also designed to control redundant power supply systems. Additional features of the LM76202-Q1 device include:

• Reverse input battery protection
• Reverse current blocking
• Current monitor output for health monitoring of the system
• Electronic circuit breaker operation with overload timeout using MODE pin
• A choice of latch off or automatic restart mode response during current limit fault using MODE pin
• Over temperature protection to safely shutdown in the event of an overcurrent event
• De-glitched fault reporting for brown-out and overvoltage faults
• Look ahead overload current fault indication (see the Look Ahead Overload Current Fault Indicator section)

3.72 V dVdT 5 µA PORb UVLOb SWEN 24.6 x LM76202-Q1 R dVdT 150 PŸ RTN OVP OVP 85 Ÿ REVERSE X78.2 µ ILIM 1.19 V 1.1 V 1.19 V 1.1 V Ramp Control Q Q SET CLR S R 1 V SHDNb Current Limit Amp Fast-Trip Comp (Threshold=1.8 x IOL ) PORb Gate Control Logic FLT -10 mV +100 mV Charge Pump CP GNDReverse Input Polarity Protection circuit TSD PORb UVLOb SHDNb MODE Thermal Shutdown SHDN Avdd Fault Latch 4 msec timer I(LOAD) •,(CB) Timeout Overload fault response select detection Short detect Avdd Avdd VSHUTx SHDNb 400 NŸ Gate Enhanced (tPGOOD ) TSD 900 µs 1.8 msec OLR OLR RTN SWEN VSEL_OVP * Only for Latch ModeOLR Over Voltage clamp detect LM76202-Q1 www.ti.com SLVSEM1A – MARCH 2019–REVISED SEPTEMBER 2019 Product Folder Links: LM76202-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Undervoltage Lockout (UVLO)

network from IN supply to UVLO terminal to RTN as shown in Figure 20. Figure 20. UVLO and OVP Thresholds Set by R1, R2 and R3 terminal. UVLO terminal must not be left floating. threshold has a hysteresis of 275 mV.

8.3.2 Overvoltage Protection (OVP)

required for protection from over voltage.

Figure 25. Internal Fixed OV Clamp Setting Figure 26. Internal OV Clamp Response

8.3.3 Reverse Battery Protection

without damage. Figure 28 illustrates the reverse input polarity protection functionality. Figure 27. Reverse Battery Protection Circuits - Discrete vs LM76202-Q1 Figure 28. Reverse Input Supply Protection at –60 V

8.3.4 Hot Plug-In and In-Rush Current Control

Figure 29. Output Ramp Up Time tdVdT is Set by C(dVdT) Equation 1 and Equation 2 to calculate the external C(dVdT) capacitance. Equation 1 governs slew rate at start-up.

• I(dVdT) = 4.7 µA (typical)
• Gain(dVdT) = dVdT to VOUT gain = 24.6 (1) The total ramp time (tdVdT) of V(OUT) for 0 to V(IN) can be calculated using Equation 2. tdVdT = 8.7 × 103 × V(IN) × C(dVdT) (2) The inrush current can be calculated by Equation 3 IINRUSH = COUT/[8.7 x 103 x CdVdT] (3)

Figure 30. Hot Plug-In and In-Rush Current Control at 24-V Input

8.3.5 Overload and Short Circuit Protection

is monitored during start-up and normal operation.

8.3.5.1 Overload Protection

• Active current limiting (Auto-retry and Latch-off modes)
• Electronic Circuit Breaker with overload timeout (Auto-retry mode) See the configurations in Table 1 to select a specific overload fault response.

Table 1. Overload Fault Response Configuration

8.3.5.1.1 Active Current Limiting

load current to the overcurrent limit I(OL) programmed by the R(ILIM) resistor as shown in Equation 4.

• I(OL) is the overload current limit in Ampere
• R(ILIM) is the current limit resistor in kΩ (4) During an overload condition, the internal current-limit amplifier regulates the output current to I(LIM). The FLT signal assert after a delay of tPGOODF. The output voltage droops during the current regulation, resulting in increased power dissipation in the device. If the device junction temperature reaches the thermal shutdown threshold (T(TSD)), the internal FET is turn off. The device configured in latch-off mode stays latched off until it is reset by either of the following conditions:

• Cycling V(IN) below V(PORF)
• Toggling SHDN When the device is configured in auto-retry mode, it commences an auto-retry cycle tCBretry(dly) ms after TJ < [T(TSD) – 10°C]. The FLT signal remains asserted until the fault condition is removed and the device resumes normal operation. Figure 31 and Figure 32 illustrates the behavior of the system during current limiting with auto- retry functionality. Load transition from 22 Ω to 12 Ω MODE pin connected to RTN RILIM = 8 kΩ

Figure 31. Auto-Retry MODE Fault Behavior Figure 32. Response During Coming Out of Overload Fault

8.3.5.1.2 Electronic Circuit Breaker with Overload Timeout, MODE = OPEN

• I(CB) is circuit breaker current threshold in A
• R(ILIM) is the current limit resistor in kΩ (5) The device commences an auto-retry cycle after a delay of tCBretry(dly). The FLT signal remains asserted until the fault condition is removed and the device resumes normal operation. Figure 33 and Figure 34 illustrate behavior of the system during electronic circuit breaker with auto-retry functionality.

Figure 33. Circuit Breaker Functionality Figure 34. Zoomed at the Instance of Load Step

8.3.5.2 Short Circuit Protection

behavior of the system when the current exceeds the fast-trip threshold. Figure 35. Output Hot Short Functionality at 24-V Input Figure 36. Zoomed at the Instance of Output Short

8.3.5.2.1 Start-Up With Short-Circuit On Output

and behaves similarly to the overload condition. Figure 37 illustrates the behavior of the device in this condition. This feature helps in quick isolation of the fault and hence ensures stability of the DC bus. Figure 37. Start-Up With Short on Output

8.3.5.3 FAULT Response

• Fault events such as undervoltage, overvoltage, overload, reverse current and thermal shutdown conditions
• When the device enters low current shutdown mode when SHDN is pulled low
• During start-up when the internal FET GATE is not fully enhanced (for example: VOUT has not reached VIN). The FLT output does not assert in the event of reverse voltage on Input. The device is designed to eliminate false reporting by using an internal "de-glitch" circuit for fault conditions without the need for an external circuitry. The FLT signal can also be used as Power Good indicator to the downstream loads like DC-DC converters. An internal Power Good (PGOOD) signal is OR'd with the fault logic. During start-up, when the device is operating in dVdT mode, PGOOD and FLT remains low and is de-asserted after the dVdT mode is completed and the internal FET is fully enhanced and VOUT has reached VIN. The PGOOD signal has deglitch time incorporated to ensure that internal FET is fully enhanced before heavy load is applied by the downstream converters. Rising deglitch delay is determined by tPGOOD(degl) = Maximum {(900 + 20 × C(dVdT)), tPGOODR}, where C(dVdT) is in nF and tPGOOD(degl) is in µs. FLT can be left open or connected to RTN when not used. V(IN) falling below V(PORF) resets FLT.

8.3.5.3.1 Look Ahead Overload Current Fault Indicator

condition is removed and the device resumes normal operation. Figure 38. Look Ahead Overload Current Fault Indication Figure 39. Output Turnoff Due to Thermal Shutdown With

8.3.5.4 Current Monitoring

OUT. This current can be converted into a voltage using a resistor R(IMON) from IMON terminal to RTN terminal. range (V(IMONmax) for monitoring the current is limited to minimum of ([V(IN) – 1.5 V, 4 V]) to ensure linear output. This puts a limitation on maximum value of R(IMON) resistor and is determined by Equation 6.

IMON (IMON _ OS) (IMON)V (I ) R u > @ IMON OUT IMON IMONV I GAIN R u u LM76202-Q1 www.ti.com SLVSEM1A – MARCH 2019–REVISED SEPTEMBER 2019 Product Folder Links: LM76202-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated The output voltage at IMON terminal is calculated using Equation 7 and Equation 8. For IOUT > 50 mA, Where,

• GAIN(IMON) is the gain factor I(IMON):I(OUT)
• I(OUT) is the load current
• I(MON_OS) = 2 µA (Typical) (7) For IOUT < 50 mA (typical), IMON output current is close to I(MON_OS) and Equation 8 provides the voltage output with RIMON. (8) This pin must not have a bypass capacitor to avoid delay in the current monitoring information. In case of reverse input polarity fault, an external 100-kΩ resistor is recommended between IMON pin and ADC input to limit the current through the ESD protection structures of the ADC.

8.3.5.5 IN, OUT, RTN and GND Pins

The device has two pins for input (IN) and output (OUT). All IN pins must be connected together and to the power source. A ceramic bypass capacitor close to the device from IN to GND is recommended to alleviate bus transients. The recommended input operating voltage range is 4.2 V to 60 V. Similarly all OUT pins must be connected together and to the load. V(OUT), in the ON condition, is calculated using Equation 9. Where,

• RON is the total ON resistance of the internal FETs. (9) The GND pin must be connected to the system ground. RTN is the device ground reference for all the internal control blocks. Connect the device support components: R(ILIM), C(dVdT), R(IMON), R(MODE) and resistors for UVLO and OVP with respect to the RTN pin. Internally, the device has reverse input polarity protection block between RTN and the GND terminal. Connecting RTN pin to GND pin disables the reverse input polarity protection feature. if negative input voltage is applied on IN pins with RTN pin connected to GND, the device can get damaged.

8.3.5.6 Thermal Shutdown

The device has a built-in overtemperature shutdown circuitry designed to protect the internal FETs, if the junction temperature exceeds T(TSD). After the thermal shutdown event, depending upon the mode of fault response, the device either latches off or commences an auto-retry cycle 540 ms after TJ < [T(TSD) – 10°C]. During the thermal shutdown, the fault pin FLT pulls low to indicate a fault condition.

8.3.5.7 Low Current Shutdown Control (SHDN)

Figure 40. Shutdown Control

8.4 Device Functional Modes

Table 2. Device Operational Differences Under Different MODE Configurations

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

Pulse 1 and ISO 16750-2 Pulse 5b) due to cables and switches in different automotive systems such as an ECU. The Detailed Design Procedure section can be used to select component values for the device.

9.2 Typical Application

(1) OVP connection for Programmable over voltage clamp. See Overvoltage Protection (OVP). Figure 41. 24-V, 2-A Ideal Diode Load Protection Circuit for Automotive ECU

9.2.1 Design Requirements

designed to provide protection for transients as per ISO 7637-2 Pulse 1 and ISO 16750-2 Pulse 5b. Table 3. Design Requirements

9.2.2 Detailed Design Procedure

9.2.2.1 Step by Step Design Procedure

• Operating voltage range

• Maximum output capacitance
• Start-up time
• Maximum current limit
• Transient voltage levels

9.2.2.2 Setting Undervoltage Lockout and Overvoltage Set Point for Operating Voltage Range

• Overvoltage threshold rising, VOVPR = 1.19 V
• VOV is overvoltage protection voltage (= 33.8 V) (10) However, the leakage current due to external active components connected at resistor string can add error to these calculations. So, the resistor string current, I(R23) must be chosen to be 20x greater than the leakage current of OVP pin.

9.2.2.3 Programming the Current-Limit Threshold— R(ILIM) Selection

The R(ILIM) resistor at the ILIM pin sets the over load current limit, this can be set using Equation 4. R(ILIM) = 5.36 kΩ was selected to set ILIM to 2.23 A.

9.2.2.4 Programming Current Monitoring Resistor— RIMON

the maximum input voltage range of the ADC used. R(IMON) is set using Equation 11. V to 4 V, V(IMONmax) is 4 V and R(IMON) is selected as 20 kΩ.

9.2.2.5 Limiting the Inrush Current

To limit the inrush current and power dissipation during start-up, an appropriate value of CdVdT must be selected. inrush current less than 0.5 A.

9.2.2.5.1 Selection of Input TVS for Transient Protection

ISO 7637 pulse 1 as per Table 4, SMBJ54A and SMBJ26A are selected for protection from transients. Table 4. Input TVS Selection for Transients

Table 4. Input TVS Selection for Transients (continued)

• VC is the clamping voltage of TVS at IPulse current through it.
• VBR is break down voltage of TVS with IT test current through it.
• VClamp-max is maximum clamping voltage of TVS at peak pulse current IPP
• VBR, IT, VClamp-max and IPP are the specifications of the TVS diode. (13)

9.2.3 Application Curves

Figure 42. Protection from Output Short to GND [VIN = 24 Figure 43. Protection from Output short to Battery [VIN = Figure 44. Protection from ISO 7637-2 Pulse 1 [24 V Figure 45. Protection from ISO 16750-2 Pulse 5b [24 V Figure 46. Protection from Reverse Battery [VIN = -24 V, Figure 47. Protection from OverVoltage at Input [VIN = 36

10 Power Supply Recommendations

than the current limit set to avoid voltage droops during overcurrent and short circuit conditions.

10.1 Transient Protection

are not taken to address the issue.

• Minimizing lead length and inductance into and out of the device
• Using large PCB GND plane
• Schottky diode across the output to absorb negative spikes
• A ceramic capacitor at input (C(IN)) with value more than 1µF to absorb the energy and dampen the transients. The approximate value of input capacitance can be estimated with Equation 14. where
• V(IN) is the nominal supply voltage
• I(LOAD) is the load current
• L(IN) equals the effective inductance seen looking into the source
• C(IN) is the capacitance present at the input (14) Automotive applications could require additional Transient Voltage Suppressor (TVS) to prevent transients from exceeding the Absolute Maximum Ratings of the device. These transients include ISO 7637 Pulse 1, Output short to battery, Output short to GND and reverse battery at input. The circuit implementation with optional protection components (TVS Diode at Input and schottky diode at output) is shown in Figure 48. For protection from automotive transients similar to ISO 7637 Pulse 1, Output short to battery , output short to GND and reverse battery, use CIN ≥ 1 µF and COUT ≥ 3.3 µF. For selection of TVS diode and other components, see Application Information. * Optional components needed for suppression of transients

Figure 48. Circuit Implementation for Automotive Transient Protection

SLVSEM1A – MARCH 2019– REVISED SEPTEMBER 2019 www.ti.com Product Folder Links: LM76202-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

11 Layout

11.1 Layout Guidelines

• For all the applications, a 0.1 µF or higher value ceramic decoupling capacitor is recommended between IN terminal and GND. Use CIN ≥ 1 µF for automotive transient protection. See Transient Protection.
• The optimum placement of decoupling capacitor is closest to the IN and GND terminals of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the GND terminal of the device. See Figure 49 for PCB layout example with HTSSOP package.
• High current carrying power path connections must be as short as possible and must be sized to carry atleast twice the full-load current.
• RTN, which is the reference ground for the device must be a copper plane or island.
• Locate all the device support components R(ILIM), C(dVdT), R(IMON), and MODE, UVLO, OVP resistors close to their connection pin. Connect the other end of the component to the RTN with shortest trace length.
• The trace routing for the RILIM and R(IMON) components to the device must be as short as possible to reduce parasitic effects on the current limit and current monitoring accuracy. These traces must not have any coupling to switching signals on the board.
• Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect, and routed with short traces to reduce inductance. For example, a protection Schottky diode is recommended to address negative transients due to switching of inductive loads, and it must be physically close to the OUT and GND pins.
• Thermal Considerations: When properly mounted, the PowerPAD package provides significantly greater cooling ability. To operate at rated power, the PowerPAD must be soldered directly to the board RTN plane directly under the device. Other planes, such as the bottom side of the circuit board can be used to increase heat sinking in higher current applications. Designs that do not need reverse input polarity protection can have RTN, GND and PowerPAD connected together. PowerPAD in these designs can be connected to the PCB ground plane.

11.2 Layout Example

Figure 49. Typical PCB Layout Example With HTSSOP Package With a 2-Layer PCB

SLVSEM1A – MARCH 2019– REVISED SEPTEMBER 2019 www.ti.com Product Folder Links: LM76202-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

• LM76202-Q1 EVM User's Guide

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 7-Sep-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM76202QPWPRQ1 ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 M76202Q PLM76202QPWPRQ1 ACTIVE HTSSOP PWP 16 2000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2019 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM76202QPWPRQ1 HTSSOP PWP 16 2000 350.0 350.0 43.0 PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2019 Pack Materials-Page 2

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