Power Management

PLM65460SRZTRQ1

Texas Instruments

LM654x0-Q1 High Performance, Stackable Power Converter, 3V to 36V, Pin-Compatible, 4A, 6A, 8A, Automotive, Low EMI, Synchronous Buck Converter JULY 2025

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LM654x0-Q1 High Performance, Stackable Power Converter, 3V to 36V, Pin-Compatible, 4A, 6A, 8A, Automotive, Low EMI, Synchronous Buck Converter

1 Features

AEC-Q100 qualified for automotive applications: – Temperature grade 1: –40°C to +125°C, TA
Wide input voltage range: 3V to 36V
Designed for low EMI requirements – Facilitates CISPR 25 class 5 compliance – ±5% dual-random spread spectrum – Enhanced HotRod™ QFN package with symmetrical pinout – Switching frequency from 300kHz to 2.2MHz – Pin-configurable 400kHz and 2.1MHz – Pin-configurable AUTO or FPWM operation – Dual phase capable up to 16A for high current designs – Pin-pin with 65V LM656x5-Q1 family
Low minimum on time: 40ns (maximum)
High-efficiency power conversion at all loads – > 94.65% peak efficiency at 12VIN, 5VOUT, 400kHz – 3.0µA PFM no-load input current
High power density – Internal compensation, current limit, and TSD – 3.6mm × 2.6mm, wettable flank, 20-pin package – ϴJA = 24.0°C/W (LM654x0-Q1EVM)
Create a custom design using the LM654x0-Q1 with the WEBENCH® Power Designer

2 Applications

Advanced driver assistance systems (ADAS)
Automotive infotainment and cluster
Hybrid, electric, and powertrain systems

3 Description

The LM654x0-Q1 are a family of automotive buck converters designed for high efficiency, high power density, and ultra-low electromagnetic interference (EMI). The converters operate over a wide input voltage range of 3V to 36V (42V tolerant) The LM654x0-Q1 is dual phase capable by simply connecting the compensated error signal between the primary and secondary device. The LM654x0- Q1 comes with pin selectable fixed output voltages of 3.3V and 5V or in adjustable configuration. The low EMI operation is enabled with minimized loop inductance and optimized switch node slew rate. The current-mode control architecture with a 30ns typical minimum on-time allows high conversion ratios at high frequencies coupled with a fast transient response and excellent load and line regulation. Device Information PART NUMBER(3) PACKAGE (1) PACKAGE SIZE(2) LM65440-Q1(4) RZT (WQFN-FCRLF, 20) 3.6mm × 2.6mmLM65460-Q1 LM65480-Q1(4) (1) For more information, see Section 11. (2) The package size (length × width) is a nominal value and includes pins, where applicable. (3) See the Device Comparison Table. (4) Preview information (not Advance Information). VIN1 VIN2 EN/ UVLO VCC MODE/ SYNC RT BST SW1 SW2 FB PG BIAS NC1 NC2PGND PGND VIN 5VOUT VOUT FSW = 2.1MHz VCC Simplified Schematic ADVANCE INFORMATION LM65460-Q1 SNVSCU7 – JULY 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains ADVANCE INFORMATION for pre-production products; subject to change without notice.

11 Mechanical, Packaging, and Orderable

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4 Device Comparison Table

ORDERABLE PART NUMBER CURRENT SAMPLING LM65440SRZTR(2) 4A No LM65460SRZTR 6A Yes LM65480SRZTR(1) (2) 8A No (1) For more information about sampling requests, please contact Texas Instruments. (2) Preview information (not Advance Information). www.ti.com LM65460-Q1 SNVSCU7 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

5 Pin Configuration and Functions

Figure 5-1. 20 Pin RZT, WQFN-FCRLF Single Phase Package (Top View) VIN2 PGND2 SW1 NC VIN1 PGND1 NC BOOT SW2 NC FB RT/ SYNCOUT EN/UVLO PG NC DAP 1 2 3 4 6 7 1113141516 COMP BIAS VCC MODE/ SYNC/ TEMP NC Figure 5-2. 20 Pin RZT, WQFN-FCRLF Package Dual Phase (Top View) Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. NC or COMP 1 — No connect pin. Leave floating. In dual phase configuration NC becomes COMP where the external compensation network is connected to. PG 2 O Power-Good flag output. Open drain output that goes low if VOUT is outside of the specified regulation window. FB 3 A Feedback configuration pin. Connect to GND to configure 3.3V fixed output voltage. Connect to VCC to configure 5V fixed output voltage. Connect this pin to a feedback divider for adjustable output options. The regulation threshold is 0.8V. VCC 4 P Internal LDO output. Used as supply to internal control circuits. Do not connect this pin to any external loads. Can be used for logic pullup to control or flag pins. Connect a high quality 1µF capacitor from this pin to GND. MODE / SYNC 5 I/O Mode and synchronization input pin. Connect to GND, or drive the pin low to operate in AUTO mode. Connect to VCC, or drive the pin high, or send a synchronization clock signal to operate in FPWM mode. When synchronized to an external clock, use the RT pin to set the internal frequency close to the synchronized frequency. Note that in dual phase configuration this pin becomes a clock input for the secondary device. See also Section 7.3.5 section for details. RT/ SYNCOUT 6 I/O Switching frequency programming pin. This pin must be tied to VCC for 400kHz operation, or to GND for 2.1MHz operation in dual phase configuration. For single phase applications, connect this pin to ground through a resistor to set the switching frequency between 300kHz and 2200kHz. This pin also be tied to VCC or GND for single phase designs. Do not float. LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

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Table 5-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. EN / UVLO 7 P Precision enable pin. High = ON, Low = OFF. This pin can be directly connected to VIN. The precision threshold on this input enables use as an adjustable UVLO. Do not float. NC 8 — No connect pin. Leave floating. PGND1 9 G Power ground to low-side MOSFET. Connect to system ground. Connect a high-quality bypass capacitor or capacitors between this pin and VIN1. NC 10 — No connect pin. Leave floating. VIN1 11 P Input supply to the regulator. Connect high-quality bypass capacitors from this pin to PGND1. NC 12 — No connect pin. Leave floating. SW1, SW2 13, 14 P Device switch pins. Connect to the output inductor. BOOT 15 P High-side driver upper supply rail. Connect a high quality 100nF capacitor between the SW node and BOOT. An internal diode charges the capacitor while SW node is low. NC 16 — No connect pin. Leave floating. VIN2 17 P Input supply to the regulator. Connect high-quality bypass capacitors from this pin to PGND2. NC 18 — No connect pin. Leave floating. PGND2 19 G Power ground to internal low-side MOSFET. Connect to system ground. Connect high- quality bypass capacitors between this pin and VIN2. BIAS 20 P Input to internal voltage regulator. If configured for fixed VOUT, connect this pin to the VOUT node to close the control loop. If configured for an adjustable VOUT, connect this pin to the VOUT node or an external bias supply from 3.3V to 30V. If output voltage is above 30V and no external supply is used, tie the pin to GND. DAP — G Exposed ground pad. Connect to system GND on the PCB. This pin is a major heat dissipation path for the die. The pad must be used for heat sinking by soldering to the GND copper on a PCB. Implementing as many thermal vias as suggested in the example board layout makes sure of the lowest package thermal resistance and best possible thermal performance. (1) I = input, O = output, A = Analog, P = Power, G = Ground www.ti.com LM65460-Q1 SNVSCU7 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

6 Specifications

6.1 Absolute Maximum Ratings

Over operating junction temperature range (unless otherwise noted) (1) MIN MAX UNIT Input voltage VIN to PGND –0.3 42 V Input voltage EN/UVLO TO PGND –0.3 42 V Input voltage RT to PGND –0.3 42 V Input voltage BIAS TO PGND –0.3 42 V Input voltage MODE/CLKIN to PGND –0.3 5.5 V Input voltage FB to PGND –0.3 5.5 V Output voltage SW to PGND –0.6 VIN + 0.3 V Output voltage COMP to PGND –0.3 42 V Output voltage PGOOD to PGND –0.3 42 V Output voltage BST to SW –0.3 5.5 V Output voltage VCC to PGND –0.3 5.5 V Temperature Operating junction temperature TJ –40 150 °C Temperature Storage temperature Tstg –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 V Charged device model (CDM), per AEC Q100-011 ±750 (1) AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

Over operating junction temperature range (unless otherwise noted) MIN MAX UNIT Input voltage VIN 3 36 V Input voltage EN 0 36 V Input voltage BIAS, PGOOD 0 30 V Input voltage FB 0 5.5 V Input voltage MODE/SYNC, RT 0 5.5 V Pullup resistance RPU(PGOOD) 4 kΩ Pullup refernce voltage VPU(PGOOD) 0.8 30 V Output voltage VOUT 0.8 V Output current LM6X480 0 8.0 A Output current LM6X460 0 6.0 A Output current LM6X460 0 4.0 A Temperature Operating junction temperature TJ –40 150 °C LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

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6.4 Thermal Information

THERMAL METRIC(1) DEVICE UNITRZT (WQFN-FCRLF)

20 PINs

RθJA Junction-to-ambient thermal resistance(3) 24.0 °C/W RθJA Junction-to-ambient thermal resistance (JESD 51-7)(2) TBD °C/W RθJC(top) Junction-to-case (top) thermal resistance TBD °C/W RθJB Junction-to-board thermal resistance TBD °C/W ΨJT Junction-to-top characterization parameter TBD °C/W ΨJB Junction-to-board characterization parameter TBD °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance TBD °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics (Rev. D) application note. (2) The value of RΘJA given in this table is only valid for comparison with other packages and can not be used for design purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. These values do not represent the performance obtained in an actual application. For example, the EVM RΘJA = 24.0 °C/W. For design information please see the maximum ambient temperature section. (3) Refer to the LM65460 EVM user guide for board layout and additional information. For thermal design information please see the maximum ambient temperature section.

6.5 Electrical Characteristics

6.5 Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature (TJ) range of -40°C to +150°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 13.5V, VEN = VIN, VOUT = 3.3V, fSW = 2.2MHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VVCC-OVLO(F) VCC OVLO falling threshold VCC overvoltage falling threshold, IVCC = 0A 3.63 V tVCC-OVLO_DEGLITCH(R) VCC OVLO rising edge comparator delay 20 us VOLTAGE REFERENCE (FB PIN) VFB Internal feedback reference voltage FPWM Mode 0.792 0.8 0.88 V IFB-LKG Feedback pin input leakage current VFB = 0.8V, Adjustable Version 0.05 nA RFB-SEL-5V Resistance for fixed 5.0V setting from FB pin to VCC 200 Ω RFB-SEL-3V Resistance for fixed 3.3V setting from FB pin to GND 200 Ω RFB-SEL-ADJ Thevenin Equivalent resistance of external FB divider on FB pin to select adjustable output voltage setting 4 100 kΩ FIXED OUTPUT VOLTAGE (BIAS PIN) VOUT(5V) 5.0V fixed output voltage FB shorted to VCC 4.95 5 5.05 V STARTUP (SS PIN) tEN_HIGH Enable HIGH to start of switching delay VFB = VRT = VMODE = GND, VBIAS = VOUT 1.5 ms tSS Internal Fixed Soft-start time Time from first SW pulse to VREF at 90% of set point 2.9 4.8 8.1 ms gm(EXTERNAL) EA transconductance – external COMP VCOMP = 0.8V, VFB = +5% & VFB = -5% 1000 µS VCOMP-EXT(h-clamp) COMP clamp voltage VFB = 0V, adjustable output voltage setting. Simulation only 1.2 V CURRENT LIMITS AND HICCUP ILS-NEG-LIM Low side negative current limit Sinking current limit on LS FET, FPWM mode -7.32 A IL-ZC-LIM Zero-cross current limit VVCC = 3.3V, auto mode 110 mA VHIC Over-current hiccup threshold on FB Pin LS FET On-time > 165ns, Not during softstart 0.32 V tHIC_DLY Hiccup mode activation delay 128 256 cycles tHIC Hiccup mode duration time 40 ms POWER GOOD (PG PIN) VPG-OVP-R PG overvoltage rising threshold % of FB voltage (Adj) or Bias Voltage (Fixed) 103 105 107 % VPG-OVP-F PG overvoltage falling threshold % of FB voltage (Adj) or Bias Voltage (Fixed) 102 104 106 % VPG-UVP-R PG undervoltage rising threshold % of FB voltage (Adj) or Bias Voltage (Fixed) 94 96 98 % VPG-UVP-F PG undervoltage falling threshold % of FB voltage (Adj) or Bias Voltage (Fixed) 93 95 97 % tPG-DEGLITCH-F Deglitch filter delay on PG falling edge 55 114 175 µs tPG-DEGLITCH-R Deglitch filter delay on PG rising edge 1.4 2 4.5 ms VIN-PG-VALID Minimum VIN for valid PG output VOL(PG) < 0.4V, RPU = 50kΩ, VPU = 5V 1.25 V VOL-PG Output low voltage IOL = 1mA, VIN = 1.25V 0.4 V RON-PG PGOOD ON resistance IPG = 1mA 35 110 Ω SWITCHING FREQUENCY (RT PIN) fSW1(FPWM) Switching frequency, FPWM operation RRT = GND 1.89 2.1 2.31 MHz fSW2(FPWM) Switching frequency, FPWM operation RRT = 15.8kΩ, 1% 900 1000 1100 kHz fSW3(FPWM) Switching frequency, FPWM operation RRT = VCC (standalone) 360 400 440 kHz SYNCHRONIZATION (MODE/SYNC PIN) VIH(MODE/CLKIN) MODE/CLKIN input high level threshold 1.3 V LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

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7 Detailed Description

7.1 Overview

The LM654x0-Q1 is a family of high-efficiency, high-power density, ultra low-EMI buck converters. These converters operate over a wide input voltage range of 3V to 36V (42V tolerant) with pin selectable fixed output voltages of 3.3V, 5V, or as in adjustable output configuration. The current-mode control architecture, with 30ns minimum on-time, allows high conversion ratios at high frequencies, fast transient response, and excellent load and line regulation. If the minimum on-time or minimum off-time does not support the desired conversion ratio, the switching frequency is automatically reduced. This feature allows regulation to be maintained during load dump events and cold cranking situations. This device is designed to minimize end-product cost and size while operating in demanding automotive and high-performance industrial environments. The LM654x0-Q1 can be set to operate at fixed 400kHz, fixed 2.1MHz, or in adjustable mode from 300kHz to 2.2MHz by using the RT pin. An integrated compensation network combined with an accurate current limit scheme minimizes bill of material cost and component count. The LM654x0-Q1 has been designed for low EMI. The device includes the following:

±5% dual random spread spectrum (DRSS) frequency hopping
Symmetrical pin out minimizing parasitic package inductance
Operation over a frequency range above and below AM radio band
Pin-configurable for auto or FPWM mode along with external clock synchronization capabilities These features can eliminate shielding and other expensive EMI mitigation measures. To use the device in reliability-conscious environments, the LM654x0-Q1 has a package with enlarged corner terminals for improved board level reliability and wettable flanks, allowing optical inspection. LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

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7.2 Functional Block Diagram

PG comparators, deglitch filters, and logic FB MODE / SYNC PGND2 PGND1 SW2 VIN1 BST HS and LS current control Internal EA HS current sense Slope compensation ramp BIASVCC PWM comparator CLK Frequency foldback TSD CLK Softstart System EN LS ILIM EN / UVLO LS current comparator LS current sense UVP / OVP RT SW1 PLL and Oscillator MODE /SYNC detect LDO VIN2 VCC UVLO OVLO BOOT-SW UVLO Spread spectrum CLKOUT Drivers and logic FB decoder 3.3V, 5V ADJ BIAS Bandgap System EN VIN UVLO RRT detect ZX current comparator VREF EN UVLO EN Control System EN www.ti.com LM65460-Q1 SNVSCU7 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

7.3 Feature Descriptions

7.3.1 Output Voltage Selection

The LM654x0-Q1 features pin-selectable fixed output voltage or adjustable output voltage mode. In fixed output voltage mode, the output voltage is selected by the FB pin. Connect the FB pin to GND to select the fixed 3.3V output, or connect to VCC for a fixed 5V output. When the fixed output voltage mode is selected, the BIAS pin is connected directly to the output of the regulator. In this mode, the BIAS pin closes the feedback loop of the regulator and provides input power to the internal bias regulator. Because of the internal LDO is supplied through this pin, a reliable bode plot cannot be taken in fixed output voltage mode however this measurement can be take in adjustable mode. Connect BIAS to VOUT as shown in Figure 8-1 . Table 7-1. Output Voltage Selection FB VOUT Short to GND 3.3V Short to VCC 5V Connect to a feedback resistor divider (Figure 7-1) ADJ In the adjustable output voltage mode, a voltage divider is connected between the regulator output voltage and the FB pin. The resistor values are calculated based on the desired output voltage and the 0.8V reference of the regulator. See Figure 7-1 for detailed connections. RFBT RFBB FB AGND VOUT CFF Figure 7-1. Setting Output Voltage of Adjustable Versions Use Equation 1 to select a value for RFBB, based on a desired value of RFBT. Limiting the value of RFBT to 100kΩ or less is best practice. Larger values of resistance are susceptible to leakage currents on the PCB, caused by environmental contamination, that can shift the desired output voltage. Values up to about 1M Ω can be used to reduce the no-load supply current, in those cases where excessive PCB leakage currents are not present. R FBB = R FBT × 0.8 V O UT − 0.8 (1) In some cases, when using the adjustable mode, a feed forward capacitor can be used to improve the loop phase margin or load transient response. The exact value of C FF is best selected empirically during the initial bench evaluation of the design. Leave a placeholder for this capacitor in the PCB layout if needed at some stage during development.

7.3.2 EN Pin and Use as VIN UVLO

Start-up and shutdown are controlled by the EN input. This input features precision thresholds, allowing the use of an external voltage divider to provide an adjustable input undervoltage lockout (UVLO), if desired. Applying a voltage greater than V EN_TH_R fully enables the device, allowing the device to enter start-up mode and begin the soft-start period. When the EN input is brought below V EN_TH_F, the regulator stops switching and enters shutdown mode, with a VIN input current of less than 1 μA (maximum). Note that the EN input draws a current of about 0.2μA (typical). The EN input can be connected directly to VIN if this feature is not needed. The enable LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

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must not float, as floating the enable pin turns the device off. The values for the various EN thresholds can be found in the Electrical Characteristics table. RENT RENB EN VIN Figure 7-2. VIN UVLO Using the EN Pin In some cases, an input UVLO level different than that provided internal to the device is needed. This feature can be used for special sequencing or to prevent input voltage oscillations caused by excessively long power cables. External UVLO can be accomplished by using the circuit shown in Figure 7-2. The input voltage at which the device turns on is designated as V ON while the turnoff voltage is V OFF. The current in the divider must be greater than the current into the EN input (I EN_LKG), to preserve accuracy. Values for R ENB between 10k Ω and 50kΩ are reasonable. Then, Equation 2 is used to calculate RENT and Equation 3 is used to calculate VOFF. R ENT = R EN B × V O N V EN _ TH _R − 1 (2) V OFF = V O N × V EN _ T H_F V EN _ TH_R (3) where

VON = VIN turn-on voltage
VOFF = VIN turn-off voltage

7.3.3 Mode Selection

The MODE / SYNC pin is a multifunction pin that configures the mode of operation, and serves as an input for an external synchronization signal. If the pin is grounded or driven to logic low, the converter operates in auto mode. If the pin is tied to VCC or driven to logic high, or synchronized to an external clock source, the converter operates in FPWM mode. Table 7-2. Mode Selection MODE/SYNC MODE DYNAMIC MODE CHANGE SPREAD SPECTRUM Short to GND or driven low AUTO Enabled Standard ±5% DRSS 49.9kΩ to GND FPWM Disabled Wide ±5% DRSS 149.9kΩ to GND AUTO Disabled Wide ±5% DRSS Short to VCC or driven high FPWM Enabled Standard ±5% DRSS Synchronizing Signal FPWM Enabled Disabled Transitioning the device from auto to FPWM mode requires driving the pin from low to high or sending a synchronization signal. Transitioning the device from FPWM to auto mode requires driving the pin from high to low or stop sending the synchronization signal. Note that a short to ground or a pullup to VCC requires < 200 Ω resistor. www.ti.com LM65460-Q1 SNVSCU7 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

7.3.3.1 MODE/SYNC Pin Uses for Synchronization

The LM654x0-Q1 MODE/SYNC pin can be used to synchronize the internal oscillator to an external clock. The internal oscillator can be synchronized by coupling a positive edge into the pin. The coupled edge voltage at the pin must exceed the SYNC amplitude threshold of V IH(SYNC) to trip the internal synchronization pulse detector. The minimum SYNC ON pulse and OFF pulse durations must be longer than t SYNC(TON-MIN) and tSYNC(TOFF-MIN) respectively. The LM654x0-Q1 switching action can be synchronized to an external clock from 300kHz to 2.2MHz. Note, an external SYNC signal can be applied after pin detection. If applied during the pin detection, the SYNC signal can not be detected. MODE/SYNCClock Range Figure 7-3. Typical Implementation Allowing Synchronization Using the MODE/SYNC Pin VIH(MODE/ CLKIN) tCLKIN(TOFF) tCLKIN(TON) t VIL(MODE/ CLKIN) This figure shows the conditions needed for detection of a synchronization signal. Figure 7-4. Typical SYNC Waveform

7.3.3.2 Clock Locking

After a valid synchronization signal is detected, a clock locking procedure is initiated. After approximately 2048 pulses, the clock frequency locks to the frequency of the synchronization signal. While the switching frequency adjusts, phase is maintained so that the clock cycle lying between the operation at the default and synchronization frequencies is of intermediate length. There are no very long or very short pulses. After frequency is adjusted, phase is adjusted over a few tens of cycles so that the rising synchronization edges correspond with the rising SW node pulses. See the following figure. LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

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VIH(SYNC) VIL(SYNC) Pulse 1 Pulse 2 Pulse 3 Pulse 4 Phase lock achieved, Rising edges align to within approximately 45ns, no spread spectrum VIN GND Pulse 2048 Pulse 2049 Pulse 2050 Pulse 2051 SW Node Synchronization signal Spread Spectrum is on between pulse 1 and pulse 2048, there is no change to the operating frequency. At pulse 4, the device transitions from Auto to FPWM mode. At approximately pulse 2048, spread spectrum turns off Also clock frequency matches the synchronization signal and phase locking begins On the fourth pulse, the synchronization signal is detected. After approximately 2048 pulses, the synchronization signal is ready to synchronize, and the frequency is adjusted using a glitch-free technique, then the phase is locked. Figure 7-5. Synchronization Process

7.3.4 Adjustable Switching Frequency

The RT pin is configurable. This pin can be tied to VCC for 400kHz operation, grounded for 2.1MHz operation, or a resistor to GND can be used to set an adjustable operating frequency; see Table 7-3. Note that if a resistor value falls outside of the recommended range, the LM654x0-Q1 reverts to 400kHz or 2.1MHz. Do not apply a pulsed signal to this pin to force synchronization. If synchronization is needed, see the SYNC/MODE pin in Section 7.3.3.1. The switching frequency can be programmed in the range of 300kHz to 2200kHz by placing a resistor from the RT pin to GND. RT (kΩ) = 14972 / (fSW (kHz) – 8.5) (4) For example, for fSW = 380kHz, RT = 40.37kΩ so a 40.2kΩ resistor can be selected as the closest value. Table 7-3. Switching Frequency Settings RT SWITCHING FREQUENCY VCC 400kHz GND 2100kHz RT Resistor to GND 300kHz to 2200kHz Float Do not float Note that a short to ground or a pullup to VCC requires < 200Ω resistor.

7.3.5 Dual Phase Operation

The LM654x0-Q1 is capable of dual-phase operation for high-current applications. The dual phase operation can be configured for FPWM or PFM mode or operation by simply configuring the primary device MODE pin as described in the MODE/SYNC section of the data sheet. For dual phase designs, simply connect RT and the COMP pins as shown in the typical application circuits below. The primary device is recognized by tying a resistor to ground on the RT pin where as the secondary device RT is either pulled up to VCC or down to ground. During start-up, the primary device sends a clock signal 180 degrees out of phase to the secondary device. To enable low-IQ operation in dual-phase configuration, both devices can be programmed in PFM mode. The COMP pin is the error signal of the internal transconductance amplifier. Connect the COMP pin of the primary to the COMP pin of the secondary to make sure of a balanced current sharing between the phases. For fixed VOUT options tie FB, BIAS of the primary and secondary as shown below. For adjustable configurations, tie the FB, BIAS signals as shown. Unlike single phase applications, in dual phase configurations, the RT pins have to be configured on the primary and secondary devices as shown in the table. At start-up, the device senses the RT pin and configures to a primary or secondary and enables external compensation mode to externally compensate the loop with an RC. www.ti.com LM65460-Q1 SNVSCU7 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

Table 7-4. Switching Frequency Configuration DEVICE RT FSW Primary 33kΩ to GND 2100kHz Primary 100kΩ to GND 400kHz Secondary GND 2100kHz Secondary VCC 400kHz VOUT SW BIAS VIN PGND FB COUT 2.2uH CIN 100k BST EN / UVLO VBATT CBST 100nF PG COMP RT/SYNCOUT MODE/ SYNC/ TEMP VOUT L 2 × 47uF CIN 100nF4.7uF VCC SW BIAS VIN PGND FB COUT 2.2uH CIN BST EN / UVLO Secondary CBST 100nF PG COMP RT MODE/ SYNC L 2 × 47uF CIN 100nF4.7uF VCC1.0uF 33k 1.0uF Primary Figure 7-6. Typical Fixed 3.3V Vout 400kHz Dual Phase Schematic LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

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L 2 × 22uF CIN 100nF4.7uF VCC SW BIAS VIN PGND FB COUT CIN BST EN / UVLO Secondary CBST 100nF PG COMP RT MODE/ SYNC VCC L 2 × 22uF CIN 100nF4.7uF VCC 1.0uF 100k VCC 1.0uF 1uH Primary Figure 7-7. Typical fixed 5V Vout 2100kHz Dual Phase Schematic

7.3.6 Dual Randrom Spread Spectrum (DRSS)

The LM654x0-Q1 provides a Dual Random Spread Spectrum (DRSS) function, which reduces the EMI of the power supply over a wide-frequency range. The DRSS function combines a low-frequency triangular modulation profile (standard or wide) with a high-frequency cycle-by-cycle pseudo-random modulation profile. The low frequency triangular modulation improves performance in the lower radio frequency bands, while the high frequency random modulation improves performance in the higher radio frequency bands. www.ti.com LM65460-Q1 SNVSCU7 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

The low frequency triangular modulation spreads the switching frequency by ±5% with a 12kHz modulation frequency. Spread spectrum works by converting a narrowband signal into a wideband signal which spreads the energy over multiple frequencies. Industry standards require different spectrum analyzer resolution bandwidth (RBW) settings for different frequency bands. The RBW has an impact on the spread spectrum performance. For example, the CISPR-25 requires 9kHz RBW for the 150kHz to 30MHz frequency band. For frequencies greater than 30MHz, the required RBW is 120kHz. DRSS is able to simultaneously improve the EMI performance in the high and low RBWs with the low frequency triangular modulation and high-frequency cycle-by-cycle pseudo-random modulation. In the low-frequency band (150kHz – 30MHz), the DRSS function can reduce the conducted emissions by as much as 15dBμV, and in the high-frequency band (30MHz – 108MHz) by as much as 5dBμV. The DRSS function is disabled when an external clock is applied to the MODE/SYN/ pin. Time Clock Frequency DRSS Low RBWHigh RBW Figure 7-8. Dual Random Spread Spectrum Implementation

7.3.7 Internal LDO, VCC UVLO, and BIAS Input

The LM654x0-Q1 has a dual input for the VCC regulator that is supplied from either VIN or BIAS. After the LM654x0-Q1 is active, power comes from VIN if BIAS is less than approximately 3.1V. However, power comes from BIAS if BIAS is more than 3.2V (maximum). VCC is typically 3.3V under most conditions, but can be lower if VIN is very low. To prevent unsafe operation, VCC has a UVLO that prevents switching if the internal voltage is too low. See V CC-UVLO_R and VCC-UVLO_HYST in Electrical Characteristics. TI recommends a 1 μF capacitor rated for 10V with X7R or better dielectric for the VCC capacitor.

7.3.8 Bootstrap Voltage (BST Pin)

The driver of the power switch (HS switch) requires bias higher than VIN when the HS switch is ON. The capacitor connected between BST and SW works as a charge pump to boost voltage on the BST terminal to (SW + VCC). The boot diode is integrated on the LM654x0-Q1 die to minimize the physical design size. TI recommends a 100nF capacitor rated for 10V with X7R or better dielectric for the BST capacitor.

7.3.9 Soft Start and Recovery From Dropout

When designing with the LM654x0-Q1, slower rise in output voltage due to recovery from dropout and soft start must be considered separate phenomena. Soft start is triggered by any of the following conditions:

EN is used to turn on the device.
Recovery from a hiccup waiting period; see Section 7.3.10.3.
Recovery from shutdown due to overtemperature protection.
Power is applied to the VIN of the IC or the VCC UVLO is released. After soft start is initiated, the IC takes the following actions:
The reference used by the IC to regulate output voltage is slowly ramping up from zero. The net result is that output voltage, if previously 0V, takes tSS to reach 90% of regulation value.
Operating mode is set to auto, activating diode emulation. This action allows start-up without pulling the output voltage low if there is a voltage already present on the output. LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

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Hiccup is disabled for the duration of soft start; see Section 7.3.10.3. All of these actions together provide a controlled start-up with limited inrush current. These actions also allow the use of output capacitors and loading conditions that can cause current limit during start-up without triggering hiccup. In addition, if the output voltage is already present the output voltage does not discharge. Any time the output voltage is more than a few percent low for any reason, the output voltage ramps back up slowly. This is the recovery from dropout condition which differs from soft start in three important ways:
Hiccup is allowed only if output voltage is less than 40 percent the set point. Note that during dropout regulation, hiccup is inhibited unless the FB node is less than 40% of the set point, 128 switching cycles have
FPWM mode is allowed during recovery from dropout. If the output voltage were to suddenly be pulled up by an external supply, the LM654x0-Q1can pull down on the output. Note that all the protections that are present during normal operation are in place, protecting the device if output is shorted to a high voltage or ground.
The reference voltage is set to approximately 1% above that needed to achieve the current output voltage. The reference voltage is not started from zero. Despite the name, recovery from dropout is active whenever output voltage is more than a few percent lower than the setpoint for long enough that:
Duty factor is controlled by minimum on-time or
When the part is operating in current limit. This event primarily occurs under the following conditions:
Dropout: when there is insufficient input voltage for the desired output voltage to be generated.
Overcurrent that is not severe enough to trigger hiccup or if the duration is too short to trigger hiccup. See Section 7.3.10.3. Load current VOUT Set Point and max output current Output Voltage and Current Slope the same as during soft start Time t VOUT V Whether output voltage falls due to high load or low input voltage, after the condition that causes output to fall below the setpoint is removed, output climbs at the same speed as during start-up. Even though hiccup does not trigger due to dropout, hiccup can, in principal, be triggered during recovery if output voltage is below 0.4 times output the setpoint for more than 128 clock cycles during recovery. Figure 7-9. Recovery From Dropout

7.3.10 Safety Features

The LM654x0-Q1 includes a set of safety features:

Power-Good monitor with output undervoltage (UV) and overvoltage (OV) protection
Overcurrent and short-circuit protection with HICCUP mode
Thermal shutdown (TSD)

7.3.10.1 Power-Good Monitor

The LM654x0-Q1 includes a power-good function to simplify supply sequencing and supervision in a system. The power-good function can be used to enable downstream circuits that are supplied by the LM654x0-Q1, control downstream protection circuits such as load switches, or to turn on sequenced supplies. The function monitors the output voltage with a window comparator through the FB pin for adjustable V OUT configurations www.ti.com LM65460-Q1 SNVSCU7 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

and the BIAS pin for fixed V OUT configurations. The power-good output (PG) switches to a high impedance open-drain state when the output voltage is in regulation. When the output voltage is outside of the ±5% range from the set voltage, the PG pin is driven low (< V OL(PG)) warning the system of an output over-voltage or under-voltage condition. A 114µs deglitch filter on the PG falling edge prevents false tripping of the power good signals during transients. When the output voltage returns within the regulation window, a 2ms filter on the PG rising edge allows extra processing time for the downstream components. TI recommends a100k Ω pullup resistor from the PG pin to the relevant logic rail not greater than 30V. PG is asserted low during soft start and when the LM654x0-Q1 is disabled.

7.3.10.2 Overcurrent and Short-Circuit Protection

The LM654x0-Q1 is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high- side and the low-side MOSFETs. High-side MOSFET overcurrent protection is implemented by the nature of the peak current mode control. The HS switch current is sensed when the HS is turned on after a short blanking time. The HS switch current is compared to the minimum of a fixed current setpoint, or the output of the voltage regulation loop minus slope compensation, every switching cycle. Because the voltage loop has a maximum value and slope compensation increases with duty cycle, the HS current limit decreases with increased duty cycle if duty cycle is above 35%. When the LS switch is turned on, the current going through is also sensed and monitored. Like the high-side MOSFET, the low-side MOSFET turn-off is commanded by the voltage control loop. For a low-side device, turn-off is prevented if the current limit is exceeded, even if the oscillator normally starts a new switching cycle. Also like the high-side device, there is a limit on how high the turn-off current is allowed to be. This is called the low-side current limit; see the Electrical Characteristics for values. If the LS current limit is exceeded, the LS MOSFET stays on and the HS switch is not turned on. The LS switch is turned off after the LS current falls below the limit. The HS switch is turned on again as long as at least one clock period has passed since the last time the HS device has turned on. iL VSW IL-LS Inductor Current t t SW Voltage VIN Typically, tSW > Clock setting tON < tON_MAX IL-HS IOUT Figure 7-10. Current Limit Waveforms The net effect of the operation of high-side and low-side current limit is that the IC operates in hysteretic control. Because the current waveform assumes values between I L-HS and I L-LS, output current is close to the average of these two values unless duty cycle is very high. After operating in current limit, hysteretic control is used and current does not increase as output voltage approaches zero. If the duty cycle is very high, current ripple must be very low to prevent instability; refer to Section 8.2.2.4. Since the current ripple is low, the device is able to deliver the full load current. The current delivered is close to IL-LS. After the overload condition is removed, the device recovers as though in soft start; see Section 7.3.9. Note that hiccup can be triggered if output voltage drops below approximately 0.4 times the intended output voltage. LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

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7.3.10.3 Hiccup

The LM654x0-Q1 employs hiccup overcurrent protection when all of the following conditions are met for 128 consecutive switching cycles:

A time greater than tSS has passed since soft start has started; see Section 7.3.9.
Output voltage is below approximately 0.4 times output setpoint.
The part is not operating in dropout defined as having minimum off-time controlled by duty factor. In hiccup mode, the device shuts down and attempts to soft start after t HIC. Hiccup mode helps reduce the device power dissipation under severe overcurrent and short-circuit conditions.

7.3.10.4 Thermal Shutdown

Thermal shutdown limits total power dissipation by turning off the internal switches when the IC junction temperature exceeds 165°C (typical) and power-good (PG) asserts. Thermal shutdown does not trigger below 155°C. After thermal shutdown occurs, hysteresis prevents the device from switching until the junction temperature drops to approximately 156°C. When the junction temperature falls below 156°C (typical), the LM654x0-Q1 attempts to soft start.

7.4 Device Functional Modes

7.4.1 Shutdown Mode

The EN pin provides electrical on and off control of the device. When the EN pin voltage is below 0.9V, both the regulator and the internal LDO have no output voltage and the part is in shutdown mode. In shutdown mode, the quiescent current drops below 0.81µA.

7.4.2 Active Mode

The LM654x0-Q1 is in active mode when the following occurs:

The EN pin is above VEN_TH_R
VIN is above VIN_UVLO_R
VIN is high enough to satisfy the VIN minimum operating input voltage
No other fault conditions are present See Section 7.3 for protection features. The simplest way to enable the operation is to connect EN to VIN, allowing self-start-up when the applied input voltage exceeds the minimum VIN_OPERATE. In active mode, depending on the load current, input voltage, and output voltage, the LM654x0-Q1 is in one of six sub-modes:
Continuous conduction mode (CCM) with fixed switching frequency and peak current mode operation
Discontinuous conduction mode (DCM) while in auto mode when the load current is lower than half of the inductor current ripple. If current continues to reduce, the device enters Pulse Frequency Modulation (PFM) which reduces the switch frequency to maintain regulation while reducing switching losses to achieve higher efficiency at light load.
Minimum on-time operation while the on-time of the device needed for full-frequency operation at the requested low-duty cycle is not supported by TON_MIN
Forced pulse width modulation (FPWM) similar to CCM with fixed-switching frequency, but extends the fixed frequency range of operation from full to no load
A current limiting condition where the output voltage remains above 0.4 times the output setpoint
Dropout mode when switching frequency is reduced to minimize dropout
Recovery from dropout similar to other modes of operation except the output voltage setpoint is gradually moved up until the programmed setpoint is reached.

7.4.2.1 Peak Current Mode Operation

The following operating description of the LM654x0-Q1 refers to Section 7.2 and the waveforms in Figure 7-11. Both supply a regulated output voltage by turning on the internal high-side (HS) and low-side (LS) NMOS switches with varying duty cycle (D). During the HS switch on-time, the SW terminal voltage, V SW, swings up to approximately VIN, and the inductor current, i L, increases with a linear slope. The HS switch is turned off by the www.ti.com LM65460-Q1 SNVSCU7 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

control logic. During the HS switch off-time, tOFF, the LS switch is turned on. Inductor current discharges through the LS switch, forcing V SW to swing below ground by the voltage drop across the LS switch. The regulator loop adjusts the duty cycle to maintain a constant output voltage. D is defined by the on-time of the HS switch over the switching period: D = TON / (TON + TOFF). In an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = VOUT / VIN. iL VSW ILPK IOUT Iripple Inductor Current - IOUTÂ5DSLS D = t t SW Voltage tON tSWVIN tSW tON tOFF VOUT VIN Figure 7-11. SW Voltage and Inductor Current Waveforms in Continuous Conduction Mode (CCM) To get accurate DC load regulation, a voltage feedback loop is used. Peak and valley inductor currents are sensed for peak current mode control and current protection. The regulator operates with continuous conduction mode with constant switching frequency when load level is above one half of the minimum peak inductor current. The internally-compensated regulation network achieves fast and stable operation with small external components and low-ESR capacitors.

7.4.2.2 Auto Mode Operation

The LM654x0-Q1 can have two behaviors while lightly loaded. One behavior, called auto mode operation, allows a seamless transition between normal current mode operation while heavily loaded and in highly-efficient light-load operation. The other behavior known as FPWM mode, maintains full frequency even when unloaded. Which mode the LM654x0-Q1 operates in depends on the SYNC/MODE pin. When SYNC/MODE is high, the part is in FPWM. When SYNC/MODE is low, the part is in PFM. In auto mode, light-load operation is employed in the LM654x0-Q1 at load lower than approximately 1/10th of the rated maximum output current. Light-load operation employs two techniques to improve efficiency:

Diode emulation, which allows DCM operation
Frequency foldback Note that while these two features operate together to create excellent light load behavior, these features operate independently of each other.

7.4.2.2.1 Diode Emulation

Diode emulation prevents reverse current though the inductor, which requires a lower frequency needed to regulate given a fixed peak inductor current. Diode emulation also limits ripple current as frequency is reduced. Frequency is reduced when peak inductor current goes below I PEAK-MIN. With a fixed peak current, as output current is reduced to zero, frequency must be reduced to near zero to maintain regulation. LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

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D = t t SW Voltage tON tSW VIN tSW tON tOFF tHIGHZ VOUT VIN In auto mode, the low-side device is turned off after inductor current is near zero. As a result, after output current is less than half of inductor ripple in CCM, the device operates in DCM. This is equivalent to saying that diode emulation is active. Figure 7-12. PFM Operation The LM654x0-Q1 has a minimum peak inductor current setting in auto mode. That being said, when current is reduced to a low value with fixed input voltage, on-time is constant. Regulation is then achieved by adjusting frequency. This mode of operation is called PFM mode regulation.

7.4.2.3 FPWM Mode Operation

Like auto mode operation, FPWM mode operation during light-load operation is selected using the SYNC/MODE pin. In FPWM Mode, frequency is maintained while lightly loaded. To maintain frequency, a limited reverse current is allowed to flow through the inductor. Reverse current is limited by reverse current limit circuitry. See the Electrical Characteristics for reverse current limit values. iL VSW ILPK IOUT Iripple Inductor Current D = t t SW Voltage tON tSW VIN tSW tON tOFF VOUT VIN FPWM mode Continuous Conduction (CCM) is possible even if IOUT is less than half of Iripple. Figure 7-13. FPWM Mode Operation In FPWM mode, frequency reduction is still available if the input voltage is high enough to command minimum on-time, even while lightly loaded. www.ti.com LM65460-Q1 SNVSCU7 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

7.4.2.4 Dropout

Dropout operation is defined as any input-to-output voltage ratio that requires frequency to drop to achieve the needed duty factor. At a given clock frequency, duty factor is limited by minimum off-time. After this limit is reached, if clock frequency is maintained, output voltage falls. Instead of allowing the output voltage to drop, the LM654x0-Q1 extends on-time past the end of the clock cycle until the required peak inductor current is achieved. The clock can start a new cycle after peak inductor current is achieved or after a pre-determined maximum on-time, t ON-MAX, of approximately 13.3µs elapses. As a result, after the needed duty factor cannot be achieved at the selected clock frequency due to the existence of a minimum off-time, frequency drops to maintain regulation. If input voltage is low enough that the output voltage cannot be regulated even with an on-time of tON_MAX, output voltage drops to slightly below input voltage, VDROP1. See Section 6. iL Output Setting Output Voltage VIN0 Input Voltage iL IOUT Switching Frequency VIN0 Frequency Setting Input Voltage Input Voltage ~100kHz VDROP1 Output Voltage VDROP2 if frequency =

1.85 MHz

Output voltage and frequency versus input voltage: If there is little difference between input voltage and output voltage setting, the IC reduces frequency to maintain regulation. If input voltage is too low to provide the desired output voltage at approximately 110 kHz, output voltage tracks input voltage. Figure 7-14. Frequency and Output Voltage in Dropout iL VSW IOUT Iripple Inductor Current - IOUTÂ5DSLS D = t t SW Voltage tON tSWVIN tSW > Clock setting tOFF = tOFF_MIN tON < tON_MAX VOUT VIN ILPK This image shows the switching waveforms while in dropout. Inductor current takes longer than a normal clock to reach the desired peak value. As a result, frequency drops. This frequency drop is limited by tON_MAX. Figure 7-15. Dropout Waveforms LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

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7.4.2.5 Recovery from Dropout

In some applications, input voltage can drop below the desired output voltage then recover to a higher value suddenly. With most regulators, the sudden increase in input voltage results in output voltage rising at a rate limited only by current limit until regulation is achieved. As input voltage reaches the desired output voltage, there is overshoot due to wind up in the control loop. This overshoot can be large in applications that have small output capacitors and light loads. Also, large inrush currents can cause large fluctuations on the input line after the regulator starts regulating the output voltage. This typically requires less current than during this initial inrush. The LM654x0-Q1 greatly reduces inrush current and overshoot. This is done by engaging the soft-start circuit whenever the input voltage suddenly rises, after dipping low enough to cause the output voltage to droop. To prevent this feature from accidentally engaging, output voltage must fall more than 1% to engage this feature. Also, this feature engages only if operating in dropout or current limit, preventing interference with normal transient response but allowing several percent overshoot while engaging. If output voltage is very close to the desired level, overshoot is reduced by inductor current not having time to rise to a high level before regulation starts. VIN VOUT Set Point Input and Output Voltage Slope the same as during soft start Time t VOUT V Figure 7-16. When Output Voltage Falls, Output Voltage Recovers Slowly, Preventing Overshoot and Large Inrush Currents www.ti.com LM65460-Q1 SNVSCU7 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The LM654x0-Q1 step-down DC-to-DC converter is used to convert a higher DC voltage to a lower DC voltage with a maximum output current of 4A, 6A, or 8A. The following design procedure can be used to select components for the LM654x0-Q1. Alternately, use the WEBENCH Design Tool to generate a complete design: WEBENCH. This tool uses an iterative design procedure and has access to a comprehensive database of components. This feature allows the tool to create an optimized design and allows the user to experiment with various options. Note All of the capacitance values given in the following application information refer to effective values unless otherwise stated. The effective value is defined as the actual capacitance under DC bias and temperature, not the rated or nameplate values. Use high-quality, low-ESR, ceramic capacitors with an X7R or better dielectric throughout. All high value ceramic capacitors have a large voltage coefficient in addition to normal tolerances and temperature effects. Under DC bias, the capacitance drops considerably. Large case sizes and higher voltage ratings are better in this regard. To help mitigate these effects, multiple capacitors can be used in parallel to bring the minimum effective capacitance up to the required value. This action can also ease the RMS current requirements on a single capacitor. A careful study of bias and temperature variation of any capacitor bank must be made to make sure that the minimum value of effective capacitance is provided. LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

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8.2 Typical Application

The following figures show typical application circuits for the LM654x0-Q1, when using the adjustable output mode or the fixed output mode, respectively. This device is designed to function over a wide range of external components and system parameters. However, the internal compensation is designed for a certain range of external inductance and output capacitance. As a quick-start guide, Table 8-1 provides typical component values for a range of application parameters. The component values in these table represent stable designs and are not necessarily optimized. Note that the designs in these tables are based on a typical input voltage of 12V. VIN EN VCC SW BOOT FB VIN VOUT L CBOOT COUT CIN CVCC 2 × 4.7µF 0.1µF 1µF RT LM654x0CHF 2 × 100nF GND PG MODE BIAS Connect as required RFBT RFBB CFF Figure 8-1. Example Application Circuit for Adjustable Output Voltage Mode With LM654x0-Q1 www.ti.com LM65460-Q1 SNVSCU7 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

L CBOOT COUT CIN CVCC 2 x 4.7µF 0.1µF 1µF RT LM654x0CHF 2 x 100nF GND PG MODE BIAS Connect as required Figure 8-2. Example Application Circuit for Fixed Output Voltage Mode With LM654X0-Q1 Table 8-1. External Components for the LM654x0-Q1 OUTPUT VOLTAGE FREQUENCY FB LM6x440 LM6x460 LM6x480 L COUT L COUT L COUT 3.3V 400kHz GND 4.7μH 75μF 3.3μH 94μF 3.3μH 160μF 3.3V 2100kHz GND 1μH 18μF 1μH 36μF 0.68μH 54μF 5V 400kHz VCC 8.2μH 50μF 3.3μH 50μF 2.2μH 120μF 5V 2100kHz VCC 1.5μH 15μF 1μH 25μF 0.47μH 36μF Note that the capacitor values in the tables is the derated effective value

8.2.1 Design Requirements

The following example provides a detailed design procedure based on the specifications found in Table 8-2. Table 8-2. Detailed Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage 12V (typical) Output voltage 5V Maximum output current 0A to 6A Switching frequency 2100kHz LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

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8.2.2 Detailed Design Procedure

The following design procedure applies to Figure 8-2 and Table 8-2.

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM654x0-Q1 device with the WEBENCH Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Choosing the Switching Frequency

The choice of switching frequency is a compromise between conversion efficiency and overall design size. Lower switching frequency implies reduced switching losses and usually results in higher system efficiency. However, higher switching frequency allows the use of smaller inductors and output capacitors, hence, a more compact design. For this application example, select a frequency of 2100kHz. See Section 7.3.4 for more details.

8.2.2.3 FB for Adjustable or Fixed Output Voltage Mode

this example uses the fixed output voltage mode to set the output voltage to 5V, by connecting the FB pin to the VCC pin. If an output voltage different from either 3.3V or 5V is required, then the adjustable output voltage mode must be used. In that case, an external voltage divider must be connected between the output node and the FB pin, while Equation 5 and Equation 6 are used to determine the divider values. R FBB = R FBT × 0.8 V O UT − 0.8 (5) 100 k Ω ≥ R FBB R F BT ≥ 4 k Ω (6) Note that Equation 6 states that the parallel combination of R FBB and R FBT must be greater than 4k Ω and less than 100kΩ. This limit is required because the regulator must reliably detect the sate of the FB pin during the start-up sequence to set the output voltage mode correctly. If the adjustable output voltage mode was chosen for this example, then values of R FBT = 100k Ω and R FBB = 19.1kΩ satisfy both Equation 5 and Equation 6. See also Section 7.3.1.

8.2.2.4 Inductor Selection

The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of the maximum output current rating of the device. Experience shows that the best value for inductor ripple current is 30% of the maximum output current rating. Larger values of ripple current can restrict the maximum output current, before current limit is reached. Smaller values of ripple current reduce the SNR of the current mode controller and can lead to increased jitter in the duty cycle. Both the inductor and switching frequency www.ti.com LM65460-Q1 SNVSCU7 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

tolerance have an impact on the selection of ripple current, and, therefore, inductor value. Use the maximum device current rating when calculating the ripple current for applications with much smaller maximum load than the maximum available from the device. The ratio of inductor ripple current over maximum output current is designated as K. Equation 7 is used to determine the value of inductance L = V I N − V OUT × V OUT V IN × K × I OUT − r at ed × F SW (7) The typical input voltage for the application is usually used in Equation 7. However, if the application requires and very wide range of input voltages, then some voltage near the upper end of the range can be used. In any case, after the inductor has been selected, the ripple current must be checked at the maximum input voltage. Too large a ripple current can limit the maximum output current, as mentioned above. Use Equation 8 to check for these concerns. I O UT − max ≅ I HS − LIM − 1 2 × V I N − V OUT × V OUT V IN × L × F SW (8) Ideally, the saturation current rating of the inductor is at least as large as the high-side switch current limit, IHS-LIM. This size makes sure that the inductor does not saturate even during a short circuit on the output. When the inductor core material saturates, the inductance falls to a very low value, causing the inductor current to rise very rapidly. Although the valley current limit is designed to reduce the risk of current run-away, a saturated inductor can cause the current to rise to high values very rapidly. This rise can lead to component damage. Inductors with a ferrite core material have very hard saturation characteristics, but usually have lower core losses than powdered iron cores. Powered iron cores exhibit a soft saturation, allowing some relaxation in the current rating of the inductor. However, powered iron cores have more core losses at frequencies above about 1MHz In any case, the inductor saturation current must not be less than the maximum peak inductor current at full load. To avoid subharmonic oscillation, the inductance value must not be less than that given in Equation 9. This limit applies to applications where the switch duty cycle becomes greater than or equal to 50%, under any operating condition. L mi n ≥ M × V OUT F S W (9) where

M = 0.30 for the 4A device
M = 0.20 for the 6A device
M = 0.15 for the 8A device The maximum inductance is limited by the minimum current ripple required for the current mode control to perform correctly. As a rule, the minimum inductor ripple current must be no less than about 10% of the device maximum rated current under nominal conditions. For this example, assuming a 12V input, Equation 7 gives a value of 0.77 μH. A standard value of 0.68 μH is selected for this design. Alternatively,Table 8-1 can be used to select the inductor value for a typical input voltage of 12V.

8.2.2.5 Output Capacitor Selection

The current mode control scheme of the LM654x0-Q1 devices allows operation over a wide range of output capacitance. The output capacitor bank is usually limited by the load transient requirements and stability rather than the output voltage ripple. The best starting point for estimating the required output capacitance is to use the values in Table 8-1. The values found in those tables can be interpolated for other output voltages or switching frequencies. In general, higher output voltages and higher switching frequencies require less output capacitance. In addition, when using the adjustable output voltage mode, the C FF capacitor can be used to optimize the loop performance. LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

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After the output capacitance is selected, and assuming a low ESR ceramic is used, the approximate peak-to- peak output voltage ripple can be estimated using Equation 10 and Equation 11. V r ≅ ∆ I 8 × F SW × C O UT (10) ∆ I = V IN − V OUT × V OUT V I N × F SW × L (11) In practice, the output capacitor has the most influence on the transient response and loop-phase margin. Load transient testing and Bode plots are the best way to validate any given design and must always be completed before the application goes into production. In addition to the required output capacitance, a small ceramic placed on the output can help reduce high-frequency noise. Small-case size ceramic capacitors in the range of 1nF to 100nF can be very helpful in reducing spikes on the output caused by inductor and board parasitics. The maximum output capacitance must be limited to approximately 10 times the design value, or 1000µF, whichever is smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load and loop stability must be performed. This example uses an output capacitance of 25 μF, based on Table 8-1. Keep in mind that this represents the value after applying D.C. bias derating and any other applicable tolerance in the capacitance. This is true for all the values shown in the tables. Any ceramic capacitor, or combination of capacitors, with an X7R or better dielectric, that provides 25 μF at 5V bias, can be used. The values shown in the table must be considered as typical to provide a stable design. Maximum and minimum limits on the output capacitance can be found by testing the application, as mentioned above.

8.2.2.6 Input Capacitor Selection

The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple current and isolating switching noise from other circuits. A minimum ceramic capacitance of 2 × 4.7µF is required on the input of the regulator. Place one capacitor on each side of the package and connected directly to the VIN and GND pins of the device. This capacitance must be rated for at least the maximum input voltage that the application requires, preferably twice the maximum input voltage. The value can be increased to help reduce input voltage ripple and maintain the input voltage during load transients. In addition, a high frequency bypass capacitance of 2 × 100nF ceramic capacitor must be used at the input, as close a possible to the regulator. Place one capacitor on each side of the package and connected directly to the VIN and GND pins of the device. This requirement provides a high frequency bypass for the control circuits internal to the device. For this example, 2 × 4.7µF, 50V, X7R (or better) ceramic capacitors are chosen. The 100nF capacitors must also be rated at 50V with an X7R dielectric. Using an electrolytic capacitor on the input in parallel with the ceramics is often desirable. This statement is especially true if long leads or traces are used to connect the input supply to the regulator, or an input EMI filter is used. The moderate ESR of this capacitor can help damp any ringing on the input supply caused by any inductance on the input. The use of this additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance. Most of the input switching current passes through the ceramic input capacitor or capacitors. The approximate RMS value of this current can be calculated from Equation 12 and must be checked against the manufacturers maximum ratings. (12) www.ti.com LM65460-Q1 SNVSCU7 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

8.2.2.7 CBOOT

The LM654x0-Q1 requires a bootstrap capacitor connected between the BOOT pin and the SW pin. This capacitor stores energy that is used to supply the high-side gate driver for the power MOSFET, along with other critical control circuits. A high-quality ceramic capacitor of 100nF and at least 16V is required.

8.2.2.8 External UVLO

In some cases, an input UVLO level different than that provided internal to the device is needed. This need can be accomplished by using the circuit shown in Figure 8-3. The turn-on voltage is designated as V ON while the turn-off voltage is V OFF. First, a value for R ENB is chosen in the range of 10k Ω to 100kΩ, then use Equation 13 and Equation 14 to calculate RENT and VOFF. EN RENT RENB VIN Figure 8-3. Setup for External UVLO Application R ENT = R ENB × V O N V E N − H − 1 (13) V OFF = V EN − L × V ON V EN − H (14) where

VON = VIN turn-on voltage
VOFF = VIN turn-off voltage

8.2.2.9 Maximum Ambient Temperature

As with any power conversion device, the regulator dissipates internal power while operating. The effect of this power dissipation is to raise the internal temperature of the converter above ambient. The internal die temperature (TJ) is a function of the ambient temperature, the power loss, and the effective thermal resistance, RθJA, of the device and PCB combination. The maximum junction temperature for the LM654x0-Q1 must be limited to 150°C. This limit establishes a limit on the maximum device power dissipation and, therefore, the load current. Equation 15 shows the relationships between the important parameters. Higher ambient temperatures (TA) and larger values of R θJA reduce the maximum available output current. The converter efficiency can be estimated by using the curves provided in this data sheet. If the desired operating conditions cannot be found in one of the curves, interpolation can be used to estimate the efficiency. Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be measured directly. The correct value of RθJA is more difficult to estimate. As stated in the Semiconductor and IC Package Thermal Metrics application note, the values given in the Thermal Information table are not valid for design purposes and must not be used to estimate the thermal performance of the application. The values reported in that table were measured under a specific set of conditions that are rarely obtained in an actual application. The data given for R θJC(bott) and ΨJT can be useful when determining thermal performance. See the Semiconductor and IC Package Thermal Metrics application note for more information and the resources given at the end of this section. I O UT M AX = T J − T A R θJA × ƞ 1 − ƞ × 1 V OUT (15) where

η = efficiency LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

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The effective RθJA is a critical parameter and depends on many factors such as the following:

Power dissipation
Air temperature, flow
PCB area
Copper heat-sink area
Number of thermal vias under the package
Adjacent component placement
Thermal Design by Insight not Hindsight application note
A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages application note
How to Properly Evaluate Junction Temperature with Thermal Metrics application note www.ti.com LM65460-Q1 SNVSCU7 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

8.2.3 Application Curves

The applications curves were measured using the LM65460EVM. Unless otherwise specified the following condition apply: TA = 25ºC, VIN = 12V, 2100kHz. I o u t 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 V i n = 9 V V i n = 1 2 V V i n = 1 8 V V i n = 2 4 V VOUT = 5V 2100kHz, Auto Mode Figure 8-4. Efficiency VOUT = 5V 2100kHz, Auto Mode Figure 8-5. Line and Load Regulation 200 ns/div Inductor Current 1A/div Output Voltage 10mV/div SW 10V/div IOUT = 6A VIN = 12V VOUT = 5V Figure 8-6. Typical Switching Waveform in PWM 2 µs/div Inductor Current 1A/div Output Voltage 20mV/div SW 5V/div IOUT = 50mA VIN = 12V VOUT = 5V Figure 8-7. Typical Switching Waveform in PFM 50 µs/div Inductor Current 2A/div Output Voltage 200mV/div IOUT = 0A to 6A (1A/μs) VIN = 12V FPWM Mode VOUT = 5V Figure 8-8. Load Transient (FPWM) 50 µs/div Inductor Current 2A/div Output Voltage 200mV/div IOUT = 0A to 6A (1A/μs) VIN = 12V Auto Mode VOUT = 5V Figure 8-9. Load Transient (AUTO) LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

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8.3 Best Design Practices

Do not exceed the Absolute Maximum Ratings.
Do not exceed the Recommended Operating Conditions.
Do not exceed the ESD Ratings.
Do not allow the EN input to float.
Do not allow the output voltage to exceed the input voltage, nor go below ground.
Follow all the guidelines and suggestions found in this data sheet before committing the design to production. TI application engineers are ready to help critique design and PCB layout to help make the project a success.

8.4 Power Supply Recommendations

The characteristics of the input supply must be capable of delivering the required input current to the loaded regulator. Use Equation 16 to estimate the average input current. I IN = V IN V O UT × I O UT η (16) where η is the efficiency. If the regulator is connected to the input supply through long wires or PCB traces, special care is required to achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR ceramic input capacitors, can form an underdamped resonant circuit. This action can result in overvoltage transients at the input to the regulator or tripping UVLO. Consider that the supply voltage can dip when a load transient is applied to the output depending on the parasitic resistance and inductance of the harness and characteristics of the supply. If the application is operating close to the minimum input voltage, this dip can cause the regulator to momentarily shut down and reset. The best way to solve these kinds of issues is to reduce the distance from the input supply to the regulator. Additionally, use an aluminum input capacitor in parallel with the ceramics. The moderate ESR of this type of capacitor helps damp the input resonant circuit and reduce any overshoots or undershoots. A value in the range of 20µF to 100µF is usually sufficient to provide input damping and help hold the input voltage steady during large load transients. In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device has a snap-back characteristic (thyristor type). TI does not recommend to use a device with this type of characteristic. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the output voltage of the regulator, the output capacitors discharge through the device back to the input. This uncontrolled current flow can damage the device. The input voltage must not be allowed to fall below the output voltage. In this scenario, such as a shorted input test, the output capacitors discharge through the internal parasitic diode found between the VIN and SW pins of the device. During this condition, the current can become uncontrolled, possibly causing damage to the device. If this scenario is considered likely, then use a Schottky diode between the input supply and the output.

8.5 Layout

8.5.1 Layout Guidelines

The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Bad PCB layout can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore, the EMI performance of the regulator is dependent on the PCB layout, to a great extent. In a buck converter, the most critical PCB feature is the loop formed by the input capacitor or input capacitors, and power ground, as shown inFigure 8-14. This loop carries large transient currents that can cause large transient voltages when reacting with the trace inductance. These unwanted transient voltages disrupt the proper operation of the converter. Because of this disruption, the traces in this loop must be wide and short, and the loop area as LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

small as possible to reduce the parasitic inductance. Section 8.5.2 shows a recommended layout for the critical components of the LM654x0-Q1 .

Place the input capacitors as close as possible to the VIN pins and connect to ground through a short wide trace.
Apply the symmetrical input capacitors technique as shown in the LM65460EVM.
Use wide traces for the CBOOT capacitor. Place CBOOT close to the device with short/wide traces to the BOOT and SW pins. The BOOT and SW pins are adjacent which simplifies the CBOOT capacitor placement.
Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF, if used, physically close to the device. The connections to FB and GND must be short and close to those pins on the device. The connection to VOUT can be somewhat longer. However, this latter trace must not be routed near any noise sources (such as the SW node) that can capacitively couple into the feedback path of the regulator.
Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and also act as a heat dissipation path.
Connect the thermal pad to the ground plane. The WQFN package has a thermal pad (PAD) connection that can be soldered down to the PCB ground plane. This pad acts as a heat-sink connection. The integrity of this solder connection has a direct bearing on the total effective RθJA of the application.
Provide wide planes for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces any voltage drops on the input or output paths of the converter and maximizes efficiency.
Provide enough PCB area for proper heat sinking. Enough copper area must be used to keep a low RθJA, commensurate with the maximum load current and ambient temperature. Make the top and bottom PCB layers with two-ounce copper; and no less than one ounce. With the WQFN package, use at least six heat-sinking vias to connect the thermal pad (PAD) to the ground plane on the bottom PCB layer. If the PCB design uses multiple copper layers (recommended), thermal vias can also be connected to the inner layer heat-spreading ground planes.
Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as possible. At the same time the total area of this node must be minimized to help reduce radiated EMI. See the following PCB layout resources for additional important guidelines:
Layout Guidelines for Switching Power Supplies application note
Simple Switcher PCB Layout Guidelines application note
Construction Your Power Supply- Layout Considerations seminar
Low Radiated EMI Layout Made Simple with LM4360x and LM4600x application note www.ti.com LM65460-Q1 SNVSCU7 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

Figure 8-14. Current Loops With Fast Edges

8.5.1.1 Ground and Thermal Considerations

As mentioned above, TI recommends using one of the middle layers as a solid ground plane. A ground plane provides shielding for sensitive circuits and traces. A ground plane also provides a quiet reference potential for the control circuitry. PGND pins are connected directly to the source of the low-side MOSFET switch, and also connected directly to the grounds of the input and output capacitors. The PGND net contains noise at the switching frequency and can bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be constrained to one side of the ground planes. The other side of the ground plane contains much less noise and must be used for sensitive routes. TI recommends providing adequate device heat sinking by using the thermal pad (PAD) of the device as the primary thermal path. Use a minimum of six 10mil thermal vias to connect the PAD to the system ground plane heat sink. The vias must be evenly distributed under the PAD. Use as much copper as possible, for system ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top as: 2oz, 1oz, 1oz,2oz. A four-layer board with enough copper thickness, and proper layout, provides low current conduction impedance, proper shielding, and lower thermal resistance. LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

8.5.2 Layout Example

Figure 8-16. PCB Image LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

9 Device and Documentation Support

9.1 Device Support

9.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

9.1.2 Development Support

9.1.2.1 Custom Design With WEBENCH® Tools

Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation, see the following:

Texas Instruments, Thermal Design by Insight not Hindsight application note
Texas Instruments, A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages application note
Texas Instruments, How to Properly Evaluate Junction Temperature with Thermal Metrics application note
Texas Instruments, Layout Guidelines for Switching Power Supplies application note
Texas Instruments, Simple Switcher PCB Layout Guidelines application note
Texas Instruments, Construction Your Power Supply- Layout Considerations seminar
Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x application note
Texas Instruments, Semiconductor and IC Package Thermal Metrics application note

9.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. www.ti.com LM65460-Q1 SNVSCU7 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

9.5 Trademarks

HotRod™ and TI E2E™ are trademarks of Texas Instruments. WEBENCH® is a registered trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. DATE REVISION NOTES July 2025 * Initial Release LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

11.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant LM65440SRZTRQ1 WQFN- LM65460SRZTRQ1 WQFN- LM65480SRZTRQ1 WQFN- www.ti.com LM65460-Q1 SNVSCU7 – JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM65440SRZTRQ1 WQFN-FCRLF RZT 20 2500 346.0 346.0 33.0 LM65460SRZTRQ1 WQFN-FCRLF RZT 20 2500 346.0 346.0 33.0 LM65480SRZTRQ1 WQFN-FCRLF RZT 20 2500 346.0 346.0 33.0 LM65460-Q1 SNVSCU7 – JULY 2025 www.ti.com

Product Folder Links: LM65460-Q1 ADVANCE INFORMATION

www.ti.com 10-Jul-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) PLM65460SRZTRQ1 Active Preproduction WQFN-FCRLF (RZT) | 20 3000 | LARGE T&R - Call TI Call TI -40 to 150 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com PACKAGE OUTLINE 2.7 2.5 3.7 3.5 0.7 0.6 2X 1.5 .000 PKG 0 2X 1 2X 0.5 2X 0.5 2X 1 2X 1.5 2X 1.05 .000 PKG 0 2X 0.55 2X 0.05 2X 0.5 2X 1.05 2.1 0.1 0.95 0.1 24X 0.3 0.2 16X 0.5 0.3 4X 0.475 0.275 4X 0.525 0.325 (0.85) (0.85) 0.01 0.00

0.1 MIN

(0.075) DAP (0.18) TYP (0.21) TYP (0.1) WQFN-FCRLF - 0.7 mm max heightRZT0020A PLASTIC QUAD FLATPACK - NO LEAD 4228518/C 06/2022 0.08 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 4.500 PIN1 INDEX AREA SEATING PLANE PIN 1 ID 45 X 0.282 2X 45 X 0.294

0.1 C A B

0.05 C A A 7 11 A-A40.000 SECTION A-A TYPICAL AB C

www.ti.com EXAMPLE BOARD LAYOUT .000 PKG 0 .000 PKG 0 4X 0.625 4X 0.575

0.07 MAX

0.07 MIN

( ) 1.7 2X ( ) 1.5 2X ( ) 1 2X ( ) 0.5 2X ( ) 0.5 2X ( ) 1 2X ( ) 1.5 ( ) 1.7 ( ) 1.2 2X ( ) 1.05 2X ( ) 0.55 2X ( ) 0.05 2X ( ) 0.5 2X ( ) 1.05 ( ) 1.2 (2.1) (0.95) 16X (0.6) 24X (0.25) (R0.05) TYP ( 0.2) TYP VIA 2X (1.007) 2X (0.372) 3X (R0.223) ( ) 0.515 ( ) 0.035 3X ( ) 0.15 3X ( ) 0.3 ( ) 0.79 ( ) 0.24 ( ) 0.31 ( ) 0.585 WQFN-FCRLF - 0.7 mm max heightRZT0020A PLASTIC QUAD FLATPACK - NO LEAD 4228518/C 06/2022 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK DETAILS LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X SEE SOLDER MASK DETAILS METAL EDGE SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN .000 PKG 0 .000 PKG 0 2X 1.007 3X R0.243 0.975 3X ( ) 1.7 2X ( ) 1.5 2X ( ) 1 2X ( ) 0.5 ( ) 0.588 2X ( ) 0.5 ( ) 0.553 2X ( ) 1 2X ( ) 1.5 3X ( ) 1.7 5X ( ) 1.2 2X ( ) 1.05 2X ( ) 0.55 2X ( ) 0.05 2X ( ) 0.5 2X ( ) 1.05 2X ( ) 0.075 5X ( ) 1.2 (R0.05) TYP 4X (0.625) 4X (0.575) 16X (0.6) 24X (0.25) (0.905) 2X (0.9) 2X (0.372) WQFN-FCRLF - 0.7 mm max heightRZT0020A PLASTIC QUAD FLATPACK - NO LEAD 4228518/C 06/2022 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 20X EXPOSED PAD 21: 85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated

Product Information

PLM65460SRZTRQ1 specifications and overview.

Summary

LM654x0-Q1 High Performance, Stackable Power Converter, 3V to 36V, Pin-Compatible, 4A, 6A, 8A, Automotive, Low EMI, Synchronous Buck Converter JULY 2025

Description

LM654x0-Q1 High Performance, Stackable Power Converter, 3V to 36V, Pin-Compatible, 4A, 6A, 8A, Automotive, Low EMI, Synchronous Buck Converter JULY 2025

Source title PLM65460SRZTRQ1 Datasheet(PDF) - Texas Instruments

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