PLM5192QRGYRQ1

LM5192-Q1 TI | Alldatasheet

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Technical content

LM5192-Q1 80V, Automotive, High-Efficiency CC-CV Buck Controller With I2C

1 Features

• AEC-Q100 qualified for automotive applications: – Device temperature grade 1: –40°C to +125°C ambient operating temperature
• Synchronous CC-CV buck controller with I2C – Wide input voltage range: 4.5V to 80V
• Meets LV148 / ISO21780 requirements – 1% accurate, programmable VOUT from 1V (3.3V) to 24V (48V) in 10mV (20mV) steps – 3% accurate, programmable ILIM(avg) from 0.5A to 7.5A in 50mA steps (8mΩ RSENSE), 2A to 30A in 200mA steps (2mΩ RSENSE) – Output slew rate: 0.5mV/μs to 40mV/μs – Adjustable cable drop compensation – Output active discharge
• Compatible with TPS2674x-Q1 USB PD controllers
• Designed for low EMI requirements – Facilitates CISPR 25 Class 5 compliance – ±8% dual-random spread spectrum – Programmable fSW: 200kHz to 2.2MHz – Programmable PFM or FPWM operation
• Programmable protection features – UV/OV (PG) warning: ±5% or ±10% – OVP warning, fault: 5% to 36% in 1% steps – Internal hiccup-mode overcurrent protection – Enable, interrupt, and thermal shutdown
• IMON pin to monitor output current
• 3.5mm × 4.5mm QFN-19 package with wettable flanks

2 Applications

• Automotive electronic systems
• Infotainment and cluster
• 48V Automotive USB charging
• Automotive Lighting

3 Description

The LM5192-Q1 is an 80V, high-efficiency, synchronous buck controller with constant-current constant-voltage (CC-CV) regulation and I 2C interface. The current-mode control architecture with a 30ns typical minimum on-time allows high conversion ratios at high frequencies coupled with a fast transient response and excellent load and line regulation. The highly accurate CC-CV operation enables seamless transition between constant-current and constant- voltage modes. The I2C interface allows programming of output voltage in 10mV or 20mV steps, average output current limit in 50mA to 200mA steps, as well as output voltage slew rate, switching frequency, soft-start slew rate, mode of operation, current loop compensation, output active discharge strength, and cable drop compensation gain. The LM5192-Q1 also features an array of safety features including undervoltage and overvoltage protection with programmable thresholds, overcurrent protection with programmable hiccup mode, and thermal shutdown. Additional features of the LM5192-Q1 include programmable diode emulation for lower current consumption at light-load conditions, open-drain nINT flag for fault reporting and output monitoring, precision enable input, monotonic start-up into prebiased load, integrated dual input (VIN and VOUTF) VCC supply regulator, and oversized VDDA regulator for powering external loads, such as companion USB PD controllers. O u t p u t C u r r e n t ( A ) Efficiency (%) V O U T = 1 2 V F S W = 4 0 0 k H z P F M 6 0 7 0 8 0 9 0 1 0 0 2 4 V 3 6 V 4 8 V 6 0 V LM5192-Q1 Efficiency VOUT VIN PFM/SYNC COMP CFG / IMON VOUTS ISNS+ SW CBOOTEN/UVLO LO SCL VIN VOUTF AGND RCFG CVDDA CVCC CIN COUT RS LO VDDA RC CC SDA nINT PGND PGNDAGND CBOOT HO VCC PGND PGND PGND LM5192-Q1 Typical Application Circuit ADVANCE INFORMATION LM5192-Q1 SNVSD17 – APRIL 2026 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

The LM5192-Q1 includes several features to simplify compliance with CISPR 25 emissions requirements. First, a symmetrical pinout provides excellent input capacitor placement and enables an ultra-low effective value for the power-loop parasitic inductance, which reduces switching losses and improves EMI performance at high input voltage and high switching frequency. A pin-selectable switch-node slew-rate control feature further reduces emissions at high frequencies. Resistor-adjustable switching frequency as high as 2.2MHz can be synchronized to an external clock source to eliminate beat frequencies in noise-sensitive applications. Finally, the LM5192-Q1 has a pin-selectable ±5% or ±10% dual-random spread spectrum (DRSS) significantly reduces peak emissions through a combination of triangular and pseudo-random modulation while keeping output voltage ripple very low.. The LM5192-Q1 controller comes in a 3.5mm × 4.5mm thermally-optimized, 19-pin QFN package. The large PGND die-attach pad improves thermal performance and board level reliability (BLR). Also included are wettable-flank pins to facilitate optical inspection during manufacturing. The 19-pin QFN packaging with useable current, lifetime reliability, and cost advantages targets applications requiring high power density. The wide input voltage range, low quiescent current consumption, high-temperature operation, cycle-by-cycle current limit, low EMI signature, and small design size provide an excellent point-of-load regulator design for applications requiring enhanced robustness and durability.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) LM5192-Q1 RGY (VQFN, 19) 4.5mm × 3.5mm (1) For more information, see Mechanical, Packaging, and Orderable Information. (2) The package size (length × width) is a nominal value and includes pins, where applicable. LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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4 Related Products

DEVICE OPTION VIN (Max) VOUT (Max) IOUT (Max) ILIM(avg) (Max) LM25192-Q1 42V 24V 5A (RS = 8mΩ) 7.5A 20A (RS = 2mΩ) 30A LM5192-Q1 80V 48V 5A (RS = 8mΩ) 7.5A 20A (RS = 2mΩ) 30A LM5192 80V 48V 5A (RS = 8mΩ) 7.5A 20A (RS = 2mΩ) 30A LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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5 Pin Configuration and Functions

(EP) VIN HO AGND VOUTF VOUTS PFM/SYNC SW CBOOT SDA SCL ISNS+ nINT VCC Figure 5-1. RGY 19-Pin VQFN (Top View) Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME 1 VOUTF P Output voltage discharge pin and the VCC bias regulator input. Connect the VOUTF pin to the output side of the respective output capacitor. 2 CFG/IMON I Configuration and output current monitoring pin. Connect a resistor to ground to set the I2C address and enable or disable the IMON feature and constant-current regulation. 3 COMP O External compensation pin. This pin is the output of the transconductance amplifier. Connect a compensation network from the COMP pin to AGND. 4 nINT O Interrupt pin. This pin is an open-collector output that toggles low in case of a status register change. 5 AGND G Analog ground pin. Ground return for the internal voltage reference and analog circuits. 6 VDDA P Internal analog bias regulator output pin. Connect a 22μF ceramic decoupling capacitor from VDDA to AGND as close as possible to the pins. 7 VCC P VCC bias supply pin. Connect a 4.7μF ceramic capacitors between VCC and PGND as close as possible to the pins. 8 PGND G Controller power ground pin. Connect to the system ground. 9 LO O Low-side power MOSFET gate driver output. 10 VIN P Controller input pin to the VCC regulator. Connect to the input supply and the input filter capacitors. The path from the VIN pin to the input capacitors must be as short as possible. 11 HO O High-side power MOSFET gate driver output. 12 CBOOT P High-side driver supply for the bootstrap gate drive. Connect a 47nF bootstrap capacitor between the CBOOT and SW pins.

13 SW P

Switch node pin and the high-side gate driver return. Connect a 47nF bootstrap capacitor between the CBOOT and SW pins, the source terminal of the high-side MOSFET, and the drain terminal of the low-side MOSFET. 14 SCL I/O I2C clock pin. 15 SDA I/O I2C data pin. www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

Table 5-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NO. NAME

16 PFM /

PFM / FPWM mode selection and synchronization input pin. Connect the PFM / SYNC pin to VDDA to enable diode emulation mode. Connect the PFM / SYNC pin to AGND to operate in forced PWM (FPWM) mode with continuous conduction at light loads. The PFM / SYNC pin can also be used as a synchronization input to synchronize the internal oscillator to an external clock.

17 EN / UVLO I

Enable / undervoltage lockout pin. Drive this pin high, low to place the device into the ready mode. When in ready mode, the I2C interface is available and the controller can be enabled by setting the CONTROLLER_EN bit in the OPERATION register. If the EN/UVLO function is not needed, tie this pin to VIN. Connect an external resistor divider network to set the UVLO threshold. 18 ISNS+ I Current sense amplifier input. Connect the ISNS+ pin to the inductor side of the external current sense resistor using a low-current Kelvin connection. 19 VOUTS I Output voltage sense and the current sense amplifier input. Connect the VOUTS pin to the output side of the respective current sense resistor. — EP — Exposed thermal pad. Connect to the system ground using multiple vias. (1) P = Power, G = Ground, I = Input, O = Output. LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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6 Specifications

6.1 Absolute Maximum Ratings

Over the recommended operating junction temperature temperature range (unless otherwise noted) (1) MIN MAX UNIT Input Voltage VIN to PGND –0.3 87.5 V Input Voltage SW to PGND –0.3 87.5 V Input Voltage SW to PGND transient < 20ns –5 90 V Input Voltage EN/UVLO to PGND –0.3 87.5 V Input Voltage VOUTF, VOUTS, ISNS+ to PGND –0.3 55 V Input Voltage VOUTS to ISNS+ –0.3 0.3 V Input Voltage VDDA, SDA, SCL, nINT, CONFIG, PFM/SYNC, COMP to AGND –0.3 6.5 V Input Voltage PGND to AGND –0.3 0.3 V Output Voltage CBOOT to SW, transient < 20ns –2 V Output Voltage CBOOT to SW –0.3 10 V Output Voltage VCC to AGND –0.3 10 V Output Voltage HO to SW –0.3 VCBOOT + 0.3 V Output Voltage HO to SW transient < 20ns –5 V Output Voltage LO to PGND –0.3 VVCC + 0.3 V Output Voltage LO to PGND transient < 20ns –1.5 V Operating junction temperature, TJ Operating junction temperature, TJ –55 150 °C Storage temperature, Tstg Storage temperature, Tstg –40 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002 (1) ±2000 V Charged device model (CDM), per AEC Q100-011 Corner pins (1, 2, 9, 10, 11, 12, 18 and 19) ±750 Other pins ±750 (1) AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

Over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input supply voltage range 4.5 80 V VOUT Output voltage range (10mV step) 1 24 V VOUT Output voltage range (20mV step) 3.3 48 V VIN, EN/UVLO, SW to PGND VIN, EN/UVLO, SW to PGND 0 80 V SDA, SCL, PFM/SYNC, nINT to AGND SDA, SCL, PFM/SYNC, nINT to AGND 0 5.25 V VOUTF, VOUTS, ISNS+ to PGND VOUTF, VOUTS, ISNS+ to PGND 0 48 V PGND to AGND 0 0.3 V TJ Operating junction temperature –40 150 °C www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

6.4 Thermal Information

THERMAL METRIC(1) LM5192-Q1 UNITRGY (VQFN)

19 PINs

RθJA Junction-to-ambient thermal resistance 44.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 40.1 °C/W RθJB Junction-to-board thermal resistance 21.1 °C/W ψJT Junction-to-top characterization parameter 0.9 °C/W ψJB Junction-to-board characterization parameter 21.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.0 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.

6.5 Electrical Characteristics

TJ = –40°C to +150°C. Typical values are at TJ = 25°C VIN = 24V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY (VIN) IQ-SD VIN shutdown current Non-switching, VIN = 48V, VEN = 0V, VFB = VREF + 50mV 4.7 11 µA IQ-SBY VIN standby current (1) Non-switching, VIN = 48V, 0.5V ≤ VEN ≤ 1V 310 µA IQ-READY VIN ready current (1) Non-switching, VIN = 48V, VEN ≥ 1V 1.4 mA IQ-SLEEP VIN sleep current, 5V output, no load VIN = 48V, VEN = 5V, VOUTF = VVOUTS = 5V, no-load, non-switching, VPFM/SYNCIN = 5V 85 100 µA ENABLE (EN / UVLO) VSBY-TH Shutdown-to-standby threshold voltage VEN/UVLO rising 0.55 V VEN-TH Enable voltage rising threshold VEN/UVLO rising 0.93 1.0 1.07 V INTERNAL LDO (VCC) VVCC1 VCC regulation voltage IVCC = 50mA 4.5 5 5.5 V VVCC2 VCC regulation voltage IVCC = 50mA 7.5 8 8.5 V VVCC(DO1) VIN to VCC dropout voltage VIN = 5V, IVCC = 50mA 130 mV VVCC(DO2) BIAS to VCC dropout voltage VVOUTF = 5V, IVCC = 50mA 110 mV IVCC(LIM) VCC current limit VCC = 4V 80 220 367 mA INTERNAL LDO (VDDA) VVDDA VDDA regulation voltage IVDD = 5mA 4.75 5 5.25 V VVDDA(DO) VCC to VDDA dropout voltage VIN = 5V, IVDD = 30mA 125 mV IVDDA-CL VDDA current limit VDDA = 4.5V 36 50 67 mA EXTERNAL BIAS (VOUTF) VBIAS-TH VIN to VVOUTF switchover rising threshold 4.85 4.9 4.967 V VBIAS-HYS VIN to VVOUTF switchover hysteresis 140 mV ACTIVE DISCHARGE (VOUTF) IDISCHARGE Output discharge current 0xD2[2:1] = 01b 24 mA 0xD2[2:1] = 10b 48 mA 0xD2[2:1] = 11b 72 mA OUTPUT VOLTAGE (VOUTS) VOUT(MIN) Minimum output voltage setpoint - 10mV step 0xD1[7] = 0b, 0x21 = 0x64h 0.98 1 1.02 V VOUT(MIN) Minimum output voltage setpoint - 20mV step 0xD1[7] = 1b, 0x21 = 0xA5h 3.267 3.3 3.333 V VOUT(DEFAULT) Default output voltage setpoint 0xD1[7] = 1b, 0x21 = 0xFAh 4.95 5.0 5.05 V VOUT(MAX) Maximum output voltage setpoint 0xD1[7] = 1b, 0x21 = 0x960h 23.76 24 24.24 V LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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6.5 Electrical Characteristics (continued)

TJ = –40°C to +150°C. Typical values are at TJ = 25°C VIN = 24V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOUT(MAX) Maximum output voltage setpoint - 10mV step 0xD1[7] = 0b, 0x21 = 0x960h 23.76 24 24.24 V VOUT(MAX) Maximum output voltage setpoint - 20mV step 0xD1[7] = 1b, 0x21 = 0x960h 47.52 48 48.48 V ERROR AMPLIFIER (COMP) gm-EXTERNAL EA transconductance external compensation 700 1000 µS PULSE FREQUENCY MODULATION (PFM/SYNC) VIL-SYNC PFM/SYNC input threshold low 0.8 V VIH-SYNC PFM/SYNC input threshold high 1.17 V ΔfSYNC Synchronization frequency range –20 20 % tSYNC-TON-MIN Minimum positive pulse width of external synchronization signal 25 ns tSYNC-TOFF-MIN Minimum negative pulse width of external synchronization signal 250 ns SWITCHING FREQUENCY (SW) fSW1 Switching frequency 1 0xD1[4:3] = 00b 180 200 225 kHz fSW2 Switching frequency 2 0xD1[4:3] = 01b 360 400 444 kHz fSW3 Switching frequency 3 0xD1[4:3] = 10b 540 600 660 kHz fSW4 Switching frequency 4 0xD1[4:3] = 11b 1.98 2.2 2.42 MHz tON-MIN Minimum on-time(1) 25 ns tOFF-MIN Minimum off-time 80 126 ns DUAL RANDOM SPREAD SPECTRUM (DRSS) ΔfSS Modulation range 10 % fm Modulation frequency 0xD1[5] = 0b 10 kHz POWER GOOD VPG-UV Power-Good UV trip level Falling with respect to the set VOUT, 0xD9[3] = 0b 93.5 95 96.5 % Falling with respect to the set VOUT, 0xD9[3] = 1b 88.5 90 91.5 % VPG-OV Power-Good OV trip level Rising with respect to the set VOUT, 0xD9[3] = 0b 103.2 105 106.8 % Rising with respect to the set VOUT, 0xD9[3] = 1b 108.5 110 111.5 % VPG-UV-HYST Power-Good UV hysteresis Falling with respect to the regulated output 1.1 % VPG-OV-HYST Power-Good OV hysteresis Raising with respect to the regulated output 1.1 % tPG-DEGLITCH Power-Good deglitch filter time VOUT falling or rising 30 µs OVERVOLTAGE PROTECTION (nINT) VOVP Overvoltage protection Rising with respect to the set VOUT, 0xD5 = 60h 105 % VOVP Overvoltage protection Rising with respect to the set VOUT, 0xD5 = 7Fh 136 % VOVP_HYST Overvoltage protection hysteresis Rising with respect to the set VOUT 2 % VOL_nINT nINT voltage low Open collector, InFAULT = 2mA 0.4 V STARTUP (SOFT START) SRSS Internal soft-start slew rate 0xD2[0] = 0b 4 V/ms 0xD2[0] = 1b 2 V/ms INTERNAL HICCUP MODE tHIC-DLY HICCUP mode activation delay VISNS+ − VVOUT > 60mV 512 CYCLES tHIC-DURATION HICCUP mode fault duration VISNS+ − VVOUT > 60mV 16384 CYCLES HIGH-SIDE GATE DRIVER (HO) VHO-HIGH HO high-state output voltage IHO = –100mA, VHO-HIGH = VCBOOT – VHO 370 mV www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

TJ = –40°C to +150°C. Typical values are at TJ = 25°C VIN = 24V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VHO-LOW HO low-state output voltage IHO = 100mA 75 mV VHO-RISE HO rise time (10% to 90%) CLOAD = 2.7nF 27 ns VHO-FALL HO fall time (90% to 10%) CLOAD = 2.7nF 8 ns LOW-SIDE GATE DRIVER (LO) VLO-HIGH LO high-state output voltage ILO = –100mA 340 mV VLO-LOW LO low-state output voltage ILO = 100mA 75 mV VLO-RISE LO rise time (10% to 90%) CLOAD = 2.7nF 20 ns VLO-FALL LO fall time (90% to 10%) CLOAD = 2.7nF 8 ns ADAPTIVE DEADTIME CONTROL tDEAD1 HO off to LO on deadtime 25 ns tDEAD2 LO off to HO on deadtime 15 ns OVERCURRENT PROTECTION (OCP) VCS-TH CS voltage threshold Measured from ISNS+ to VOUTS 54 60 66 mV tDELAY-CS CS delay to output 85 ns ACS CS amplifier gain (1) 10 V/V IBIAS-CS CS amplifier input bias current (1) 0.3 µA VCS-TH-NEG CS negative voltage threshold 30 mV AVERAGE OUTPUT CURRENT LIMIT ILIM(MIN) Minimum constant current setpoint RSENSE = 2mΩ, 0xD0 = 0Ah 2 A ILIM(MIN) Minimum constant current setpoint RSENSE = 8mΩ, 0xD0 = 0Ah 0.5 A ILIM(TYP) Maximum constant current setpoint RSENSE = 2mΩ, 0xD0 = 64h, TJ = –40°C to +85°C 19.2 20 20.8 A ILIM(TYP) Maximum constant current setpoint RSENSE = 8mΩ, 0xD0 = 64h, TJ = –40°C to +85°C 4.8 5 5.2 A ILIM(MAX) Maximum constant current setpoint RSENSE = 2mΩ, 0xD0 = 96h 30 A ILIM(MAX) Maximum constant current setpoint RSENSE = 8mΩ, 0xD0 = 96h 7.5 A ILIM_STEP Constant current step size RSENSE = 2mΩ 200 mA ILIM_STEP Constant current step size RSENSE = 8mΩ 50 mA OUTPUT CURRENT MONITOR (IMON) AIMON IOUT monitor amplifier gain from VCS to VOUT VCS = 60mV 24.6 25 25.4 V/V VOFFSET IOUT monitor amplifier offset voltage VCS = 0 mV 0.975 1 1.025 V CABLE DROP COMPENSATION ACDC Maximum cable drop compensation gain 0xD8[5:0] = 3Fh 62 V/V ACDC_STEP Cable drop compensation gain step size 2 V/V SERIAL CONTROL BUS (SCL, SDA) VIH Input high level 2 V VIL Input low level 0.8 V VHYST Input hysteresis 320 mV VOL Output low level IOL = 3mA, standard-mode/fast-mode 0 0.4 V VOL Output low level IOL = 20mA, fast-mode plus 0 0.4 V IIH Input high current Pin connected to VI2C –10 10 µA IIL Input low current Pin connected to GND –10 10 µA CIN Input capacitance 5 pF THERMAL SHUTDOWN (TSD) TJ-SD Thermal shutdown threshold (1) Temperature rising 175 °C TJ-HYS Thermal shutdown hysteresis (1) 15 °C (1) Specified by design. Not production tested. LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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6.6 Timing Requirements for the Serial Control Bus

Over I2C supply and temperature ranges unless otherwise specified. MIN TYP MAX UNIT fSCL SCL clock frequency Standard-mode > 0 100 kHz Fast-mode > 0 400 kHz Fast-mode Plus > 0 1 MHz tLOW SCL low period Standard-mode 4.7 µs Fast-mode 1.3 µs Fast-mode Plus 0.5 µs tHIGH SCL high period Standard-mode 4.0 µs Fast-mode 0.6 µs Fast-mode Plus 0.26 µs tHD;STA Hold time for a start or a repeated start condition Standard-mode 4.0 µs Fast-mode 0.6 µs Fast-mode Plus 0.26 µs tSU;STA Setup time for a start or a repeated start condition Standard-mode 4.7 µs Fast-mode 0.6 µs Fast-mode Plus 0.26 µs tHD;DAT Data hold time Standard-mode 0 µs Fast-mode 0 µs Fast-mode Plus 0 µs tSU;DAT Data setup time Standard-mode 250 ns Fast -mode 100 ns Fast-mode Plus 50 ns tSU;STO Setup time for STOP condition Standard-mode 4.0 µs Fast-mode 0.6 µs Fast-mode Plus 0.26 µs tBUF Bus free time between STOP and START Standard-mode 4.7 µs Fast-mode 1.3 µs Fast-mode Plus 0.5 µs tr SCL and SDA rise time Standard-mode 1000 ns Fast-mode 300 ns Fast-mode Plus 120 ns tf SCL and SDA fall time Standard-mode 300 ns Fast-mode 300 ns Fast-mode Plus 120 ns Cb Capacitive load for each bus line Standard-mode 400 pF Fast-mode 400 pF Fast-mode Plus 550 pF tVD:DAT Data valid time Standard-mode 3.45 µs Fast-mode 0.9 µs Fast-mode Plus 0.45 µs tVD;ACK Data vallid acknowledge time Standard-mode 3.45 µs Fast-mode 0.9 µs Fast-mode Plus 0.45 µs tSP Input filter Fast-mode 50 ns Fast-mode Plus 50 ns www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

7 Detailed Description

7.1 Overview

The LM5192-Q1 is an 80V, high-efficiency, synchronous buck controller with constant-current constant-voltage (CC-CV) regulation and I2C interface. The controller uses a peak current-mode control architecture for easy loop compensation, fast transient response, and excellent load and line regulation. The highly accurate CC-CV operation enables seamless transition between constant-current and constant-voltage modes. The device features integrated dual input (VIN and VOUTF) VCC supply regulator, and oversized VDDA regulator for powering external loads such as companion USB PD controllers. The I2C interface allows programming of output voltage in 10mV or 20mV steps, average output current limit in 50mA to 200mA steps, as well as output voltage slew rate, switching frequency, soft-start slew rate, mode of operation, current loop compensation, output active discharge strength, and cable drop compensation gain. The output can be connected to the VOUTF pin to maximize efficiency in high input voltage applications. A programmable diode emulation feature enables discontinuous conduction mode (DCM) operation to further improve efficiency and reduce power dissipation during light-load conditions. The LM5192-Q1 also features an array of safety features including output undervoltage and overvoltage protection with programmable thresholds, overcurrent protection with programmable hiccup mode, thermal shutdown, precision enable, and open-drain nINT flag for fault and status reporting. The LM5192-Q1 incorporates features to simplify the compliance with various EMI standards including CISPR 25 Class 5 that defines automotive EMI requirements. Dual Random Spread Spectrum (DRSS) technique reduces the peak harmonic EMI signature. LM5192-Q1 is provided in a 19-pin QFN package with the exposed PGND pad to maximize thermal dissipation. LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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7.2 Functional Block Diagram

512 CYCLES

– BOOT UVLO Q Q R S CBOOT SCL PFM/SYNC SW SW VCC nINT COMP VOUTS ISNS+ EN/UVLO AGND VDDA VCC VIN VOUTF DEM/FPWM VCC SOFT START DUAL RANDOM SPREAD SPECTURM (DRSS) I2C I2C GAIN = 10 VCC (5V to 8V) ILIMHICCUP LEVEL SHIFT ADAPTIVE DEADTIME CLK I2C ADDRESS IEA gm VISET VEA gm DEM/FPWM HICCUP PWM CLK 60mV CURRENT LIMIT ILIM SLOPE COMP RAMP PGND ZCD – 5mV I2C VDDA LDO VDDA (5V) I2C GAIN = 1 DAC IMIN SELECTOR PWM COMPARATOR VREF SS CONFIG DECODERCFG/IMON SDA DIGITAL CONTROL REGISTERS I2C ACTIVE DISCHARGE TSD LPF CDC IDAC LPF VDAC VFB VIMONRCDC RFBT RFBB GAIN = 25 HO LO I2C www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

7.3 Feature Description

7.3.1 Input Voltage Range (VIN)

The LM5192-Q1 operational input voltage range is from 4.5V to 80V. The device is intended for step-down conversions from 12V , 24V and 48V automotive supply rails. The LM5192-Q1 uses internal LDOs to provide a 5V to 8V VCC bias rail and a 5V VDDA rail for the gate drive and control circuits. In high input voltage applications, make sure that the VIN and SW pins do not exceed the absolute maximum voltage rating of 87.5V during line or load transient events. Voltage excursions that exceed the absolute maximum ratings of these pins can damage the IC. Follow PCB board layout recommendations and use high-quality input bypass capacitors to minimize voltage overshoot and ringing. As VIN approaches VOUT, the LM5192-Q1 skips tOFF cycles to allow the controller to extend the duty cycle up to approximately 99%. See also Input Voltage Range (VIN). Use Equation 1 to calculate when the LM5192-Q1 enters dropout mode. V IN = V O UT × t P t P − t O F F (1)

• tP is the oscillator period
• tOFF is the minimum off time VOUT SW Low Drop-out ModePWM Mode Approximately 99% Duty Cycle VIN one tOFF skip two tOFF skip three tOFF skip up to fifteen tOFF skip up to fifteen tOFF skip Figure 7-1. Dropout Mode Operation

7.3.2 High-Voltage Bias Supply Regulators (VCC, VDDA)

The LM5192-Q1 contains an internal high-voltage VCC bias regulator that provides the bias supply for the gate drivers for the power MOSFETs. The input voltage pin (VIN) can be connected directly to an input voltage source up to 80V. However, when the input voltage is below the VCC setpoint level, the VCC voltage tracks VIN minus a small voltage drop. When the output voltage is ≤ 5V, the VCC bias regulator output voltage is 5V. When the output voltage is between 5V and 8V the VCC bias regulator output voltage is tracking the output voltage. When the output voltage is ≥ 8V, the VCC bias regulator output is 8V. TI recommends that a 4.7µF capacitor is connected from the VCC pin to PGND. The LM5192-Q1 also contains a linear regulator, VDDA, that takes the VCC regulator output as an input, and generates a 5V output. The VDDA powers internal control circuitry including the digital block. The VDDA can also power external companion USB Type-C controller device. Bypass VDDA with a 22µF ceramic capacitor to achieve a low-noise internal bias rail. LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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7.3.3 Enable (EN)

The enable pin can be connected to a voltage as high as 80V. If the EN pin is pulled below 0.55V, the LM5192-Q1 is in shutdown mode with an I Q of 2.2 μA (typical) current draw from V IN. When the enable voltage is between 0.55V < EN < 1V, the LM5192-Q1 is in standby mode. When in standby mode, the VCC regulator is enabled, default registers and trim bits loaded, the digital block is disabled, the device is not switching, and the IQ current is 350 μA (typical). When the enable voltage is above 1V, the LM5192-Q1 is in ready mode after the 100μs (typical) enable to ready delay. When in ready mode, the I 2C interface is available, the device is not switching, and the I Q current is 900 μA (typical). The LM5192-Q1 starts up and enters active mode, when the CONTROLLER_EN bit in the OPERATION register is set.

7.3.4 Switching Frequency

The LM5192-Q1 oscillator is programmed by setting the FREQ bits in the MFG_DEVICE_CFG_D1 device configuration register according to the following table. Table 7-1. Switching Frequency Selection MFG_DEVICE_CFG_D1[4:3] SWITCHING FREQUENCY SELECTION 0b00 200kHz 0b01 400kHz (default) 0b10 600kHz 0b110 2.2MHz Under low VIN conditions when the high-side MOSFETs on-time exceeds the programmed oscillator period, the LM5192-Q1 extends the switching period of that channel until the PWM latch is reset by the current sense ramp exceeding the controller compensation voltage. In such an event, the oscillators operate independently and asynchronously until the channel can maintain output regulation at the programmed frequency. Equation 2 gives the approximate input voltage level where this occurs, where t SW is the switching period and tOFF(min) is the minimum off-time of 60ns. V IN min = V OUT × t SW t SW − t O F F min (2)

7.3.5 Dual Random Spread Spectrum (DRSS)

The LM5192-Q1 provides a Dual Random Spread Spectrum (DRSS) function, which reduces the EMI of the power supply over a wide frequency range. The DRSS function combines a low-frequency triangular modulation profile with a high frequency cycle-by-cycle random modulation profile. The low frequency triangular modulation improves performance in the lower radio frequency bands, while the high frequency random modulation improves performance in the higher radio frequency bands. Spread spectrum works by converting a narrowband signal into a wideband signal which spreads the energy over multiple frequencies. Industry standards require different spectrum analyzer resolution bandwidth (RBW) settings for different frequency bands. The RBW has an impact on the spread spectrum performance. For example, the CISPR-25 requires 9kHz RBW for the 150kHz to 30MHz frequency band. For frequencies greater than 30MHz, the required RBW is 120kHz. DRSS is able to simultaneously improve the EMI performance in the high and low RBWs with the low-frequency triangular modulation and high-frequency cycle-by-cycle random modulation as shown in Figure 7-2 . In the low-frequency band (150kHz – 30MHz), the DRSS function can reduce the conducted emissions by as much as 15dB μV, and in the high-frequency band (30MHz – 108MHz) by as much as 5dBμV. www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

Figure 7-2. Dual Random Spread Spectrum Implementation The DRSS function can be enabled by setting the EN_DRSS bit in the MFG_DEVICE_CFG_D1 device configuration register. The LM5192-Q1 also supports two modulation frequencies that can be selected by setting the DRSS_FMOD bit in the MFG_DEVICE_CFG_D1 device configuration register according to Table 7-2. Table 7-2. DRSS Modulation Frequency Selection DRSS_FMOD MODULATION FREQUENCY 0b0 10kHz 0b1 2.5kHz

7.3.6 Soft Start

The LM5192-Q1 has a programmable soft-start slew rate. The soft-start feature allows the regulator to gradually reach the steady-state operating point, therefore reducing start-up stresses and surges. The soft-start slew rate can be selected using the SOFT_START_TIME bit in the MFG_DEVICE_CFG_D2 device configuration register according to Table 7-3. Table 7-3. Soft-Start Slew Rate Selection SOFT_START_TIME SOFT-START SLEW RATE 0b0 5V/ms 0b1 2.5V/ms

7.3.7 Output Voltage

The LM5192-Q1 output voltage can be programmed from 1V to 24V in 10mV steps or from 3.3V to 48V in 20mV steps by setting bits in the VOUT_COMMAND register. Prior to programming the output voltage, select the output voltage step size and range by setting the SEL_FB_DIV20 bit in the MFG_DEVICE_CFG_D1 device configuration register according to Table 7-4. Table 7-4. Output Voltage Step Size and Range Selection SEL_FB_DIV20 OUTPUT VOLTAGE STEP SIZE OUTPUT VOLTAGE RANGE 0b0 10mV 1V – 24V 0b1 20mV 3.3V – 48V LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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7.3.8 Minimum Controllable On-Time

There are two limitations to the minimum output voltage adjustment range: the LM5192-Q1 voltage reference and the minimum controllable switch-node pulse width, tON(min). tON(min) effectively limits the voltage step-down conversion ratio V OUT/VIN at a given switching frequency. For fixed-frequency PWM operation, the voltage conversion ratio must satisfy Equation 3. V OUT V IN > t ON min × F SW (3) where

• tON(min) is 25ns (typical).
• FSW is the switching frequency. If the desired voltage conversion ratio does not meet the above condition, the LM5192-Q1 transitions from a fixed switching frequency operation mode to a pulse-skipping mode to maintain output voltage regulation. For wide V IN applications and low output voltages, an alternative is to reduce the LM5192-Q1 switching frequency to meet the requirement of Equation 3.

7.3.9 Dual Loop Architecture

The LM5192-Q1 has two control loops, a voltage loop and a current loop, and an IMIN selector block that compares output currents from the voltage loop error amplifier and the current loop error amplifier. The IMIN selector block selects the lower current to take the control of the constant voltage (CV) or constant current (CC) regulation. The block enables seamless transition between CC an CV operation, and is shown in the following figure. VEA gm SS VREF IMIN SELECTOR IEA gm VISET COMP CCOMP RCOMP IIEA IVEA MIN(IIEA,IVEA) Internal FB VIMON Figure 7-3. Dual Loop Architecture Block Diagram

7.3.9.1 Voltage Loop Error Amplifier

In the voltage control loop, the LM5192-Q1 has a high-gain transconductance amplifier that generates an error current proportional to the difference between the internal feedback voltage and a programmable precision reference, V REF. The transconductance of the amplifier is 1000µS. The voltage loop error amplifier takes the control when the internal minimum function block, IMIN SELECTOR, selects the current from the voltage loop error amplifier as shown in the following figure. www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

Q Q R S VOUTSISNS+ GAIN = 10 VEA gm PWM CLK SLOPE COMP RAMP PWM COMPARATOR SS VREF IMIN SELECTOR IEA gm OUTPUT RCS IL + – COMP CCOMP RCOMP CHF VDAC Internal FB CDC RCDC RFBT RFBB Figure 7-4. Voltage Loop Functional Block Diagram The voltage control loop requires an external compensation network. TI generally recommends a type-II compensation network for peak current-mode control.

7.3.9.2 Current Loop Error Amplifier

In the current control loop, the LM5192-Q1 has a high-gain transconductance amplifier that generates an error current proportional to the difference between the IMON voltage, V IMON, and the programmable ISET reference voltage, V ISET. The transconductance of the amplifier is 1000µS. The current loop error amplifier takes the control when the internal minimum function block, IMIN SELECTOR, selects the current from the current loop error amplifier as shown in the following figure. LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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Q Q R S VOUTSISNS+ GAIN = 10 PWM CLK SLOPE COMP RAMP COMP PWM COMPARATOR IMIN SELECTOR RCS IL GAIN = 25 VEA gm OUTPUT VISET CFG/IMON RCFG IEA gm CCOMP RCOMP CHF IDAC LPF LPF VIMON Figure 7-5. Current Loop Functional Block Diagram

7.3.10 Programmable ILIM

The LM5192-Q1 has a programmable average output current limit. The average output current limit is set by programming an internal 8-bit DAC. Use the AVG_ILIM_THRESHOLD field in the register 0xD0 to set the average output current limit between 0.5A – 2A and 7.5A – 30A in 50mA – 200mA steps with a recommended 8mΩ – 2mΩ sense resistor.

7.3.11 IOUT Monitor

The LM5192-Q1 has the IMON pin that can be used as the average inductor current or regulator output current monitor when the regulator is operating in the constant voltage control loop. The average inductor current can be read from the voltage on the IMON pin by using Equation 4. I AV G = V IM ON − V O FF SE T A I MON × R S (4) where

• VIMON is the voltage on the IMON pin.
• VOFFSET is the output current monitor amplifier offset voltage of 1V (typical).
• AIMON is the output current monitor amplifier gain of 25V/V (typical).
• RS is the sense resistor of 8mΩ (typical). www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

7.3.12 Cable Drop Compensation

The LM5192-Q1 has a cable drop compensation (CDC) feature. The CDC feature increases the output voltage based on the output current and the programmable CDC gain to offset the voltage drop across a USB cable. The CDC gain is programmable from 0V/V to 62V/V in 2V/V steps. Set the CDC gain to a value closest to the ratio of the cable resistance and the sense resistor, R S. For example, if the cable resistance is 150m Ω and the selected sense resistor is 8mΩ, the desired CDC gain is calculated as 150m Ω / 8mΩ = 18.75. The closest programmable CDC gain value is 18V/V. Use the CDC_EN bit in the register 0xD8 to enable the cable drop compensation. Set the CDC gain using the CDC_GAIN_CFG field in the 0xD8 register. For example, to set the CDC gain to 18V/V, set the CDC_GAIN_CFG field to 18V/V / 2V/V(LSB) = 9h.

7.3.13 Slope Compensation

The LM5192-Q1 provides internal slope compensation for stable operation with peak current-mode control and a duty cycle greater than 50%. Calculate the buck inductance to provide a slope compensation contribution equal to one times the inductor downslope using the following equation. L O sc = V OUT V × R S mΩ 24 × F SW MHz (5)

• A lower inductance value increases the peak-to-peak inductor current, which typically minimizes size and cost, and improves transient response at the cost of reduced light-load efficiency due to higher cores losses and peak currents.
• A higher inductance value decreases the peak-to-peak inductor current, which typically increases the full-load efficiency by reducing switch peak and RMS currents at the cost of requiring larger output capacitors to meet load-transient specifications.

7.3.14 Shunt Current Sensing

Figure 7-6 illustrates inductor current sensing using a shunt resistor. This configuration continuously monitors the inductor current to provide accurate overcurrent protection across the operating temperature range. For optimal current sense accuracy and overcurrent protection, use a low inductance ±1% tolerance shunt resistor between the inductor and the output, with a Kelvin connection to the LM5192-Q1 current sense amplifier. If the peak differential current signal sensed from ISNS+ to VOUT exceeds the current limit threshold of 60mV, the current limit comparator immediately terminates the high-side gate driver output for cycle-by-cycle current limiting. Use the following equation to calculate the shunt resistance. R S = V C S TH I OUT C L + ∆ I L (6) where

• VCS(TH) is current sense threshold of 60mV.
• IOUT(CL) is the overcurrent setpoint that is set higher than the maximum load current to avoid tripping the overcurrent comparator during load transients.
• ΔILis the peak-to-peak inductor ripple current. LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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CS gain = 10 Figure 7-6. Shunt Current Sensing Implementation The typical current sense delay (tDELAY(CS)) is 75ns. Use the following equation to calculate the resultant inductor current overshoot above the overcurrent threshold. I L ov er s ℎ oo t = V I N − V O U T × t DEL A Y C S L O (7) The respective SS voltage is clamped 150mV above FB during an overcurrent condition. 16 overcurrent events must occur before the SS clamp is enabled. This requirement makes sure that SS can be pulled low during brief overcurrent events, preventing output voltage overshoot during recovery.

7.3.15 Hiccup Mode Current Limiting

The LM5192-Q1 includes an internal hiccup mode protection function. When an overload condition occurs, a 512-cycle counter starts counting consecutive cycle-by-cycle current limit incidents after the internal soft-start sequence is completed. The 512-cycle counter is reset if four consecutive switching cycles occur without exceeding the current limit threshold. If after 512-cycle counts are completed, the internal soft start is pulled low and the internal high-side and low-side drivers are disabled. Then, a 16384 counter is enabled. After the counter reaches 16384, the internal soft start is enabled, and the output restarts. Note the hiccup mode current limit is not enabled during soft start and until the output voltage exceeds 50% of the set voltage. The hiccup mode can be enabled or disabled using the HICCUP_EN bit. www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

7.3.16 Device Configuration (CFG)

The LM5192-Q1 I2C address is configured, and IMON function and CC regulation are enabled as detailed in Table 7-5. After VDDA is above 3.8V (typical), the CFG pin is sampled and latched. The configuration cannot be changed easily. The LM5192-Q1 input voltage must be recycled and VCC must drop below 3.65V before the device can be reconfigured. Figure 7-7 shows the configuration timing diagram. Table 7-5. Device Configuration I2C ADDRESS RCFG MIN TYP MAX 0x6A 40.2kΩ 49.9kΩ 57.6kΩ 0x6C 18.2kΩ 25kΩ 31kΩ EN / UVLO VCC VDDA CFG_START I2C_READY VDDAUV 100µs SS(internal) CONFIGURATION TIME CONTROLLER_EN (I2C Command) Figure 7-7. Configuration Timing

7.3.17 Pulse Frequency Modulation (PFM) / Synchronization

The LM5192-Q1 provides a diode emulation feature that can be enabled to prevent reverse (drain-to-source) current flow in the low-side MOSFET. When configured for diode emulation (DEM), the low-side MOSFET is switched off when reverse current flow is detected by sensing of the SW voltage using a zero-cross comparator. The benefit of this configuration is lower power loss during light load operation. Note configuring the device for DEM has an effect of slower response to load transients during light load operation. The diode emulation feature is configured with the PFM / SYNC pin. To enable diode emulation and achieve discontinuous conduction mode (DCM) operation at light loads, connect PFM / SYNC to VDDA. If forced pulse- width modulation (FPWM) or continuous conduction mode (CCM) operation is desired, tie PFM / SYNC to AGND. Note that diode emulation is automatically engaged to prevent reverse current flow during a prebias start-up in PFM. During start-up, when the output voltage approaches the regulation set point a gradual change from DCM to CCM occurs, preventing the output voltage overshoot. To synchronize the LM5192-Q1 to an external source, apply a logic-level clock (greater than 2V) to the PFM / SYNC pin. The LM5192-Q1 can be synchronized to ±20% of the programmed frequency up to a maximum of 2.2MHz. Under low V IN conditions when the minimum off-time is reached, the synchronization signal is ignored, allowing the switching frequency to be reduced to maintain output voltage regulation. LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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7.3.18 Thermal Shutdown (TSD)

The LM5192-Q1 includes an internal junction temperature monitor. If the temperature exceeds 175°C (typical), thermal shutdown occurs. When entering thermal shutdown, the device: 1. Turns off the high-side and low-side MOSFETs 2. Turns off the VCC regulator 3. Sets the TEMPERATURE bit in the STATUS_BYTE and STATUS_WORD registers 4. Initiates a soft-start sequence when the die temperature decreases by the thermal shutdown hysteresis of 15°C (typical). This protection is a non-latching protection, therefore, the device cycles into and out of thermal shutdown if the fault persists.

7.4 Device Functional Modes

7.4.1 Shutdown Mode

The EN / UVLO pin provides ON and OFF control for the LM5192-Q1. When VEN is below 0.55V, the device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in shutdown mode drops to 2.3 μA (typical). The LM5192-Q1 also includes undervoltage (UV) protection of the internal bias LDO. If the internal bias supply voltage is below the UV threshold level, the switching regulator remains off.

7.4.2 Standby Mode

The internal bias LDO has a lower enable threshold than the switching regulator. When V EN is above 0.55V and below the precision enable threshold (1V typical), the internal VCC and VDDA LDOs are enabled and regulating, the default register values and trim bits are loaded, the digital block is disabled, the device is not switching, and the IQ current is 350μA (typical).

7.4.3 Ready Mode

When the enable voltage is above 1V and after the 100 μs (typical) enable to ready delay, the LM5192-Q1 is in ready mode. When in ready mode, the I2C interface is available, the device is not switching, and the I Q current is 900μA (typical).

7.4.4 Active Mode

The LM5192-Q1 is in active mode when V EN is above the precision enable threshold, the internal bias rail is above the UV threshold level, and when the CONTROLLER_EN bit in the OPERATION register is set. In active mode, the device operates in one of two modes depending on the load current, input voltage, output voltage, and PFM / SYNC pin configuration: 1. Forced pulse width modulation (FPWM) mode. This mode of operation is configured by tying the PFM / SYNC pin to GND or driving with an external clock source. The device operates in continuous conduction mode (CCM) with fixed switching frequency regardless of the load current. 2. Pulse frequency modulation (PFM) mode. This mode of operation is configured by tying the PFM / SYNC pin to VDDA. The device operates in discontinuous conduction mode (DCM) if the load current is less than half of the peak-to-peak inductor current, otherwise the device operates in continuous conduction mode (CCM). The transition between CCM and DCM is automatic.

7.4.5 Sleep Mode

The LM5192-Q1 operates with peak current-mode control such that the compensation voltage is proportional to the peak inductor current. During no-load or light-load conditions, the output capacitor discharges slowly. As a result, the compensation voltage goes low and the switching is stopped. When the LM5192-Q1 controller detects 16 missed switching cycles, the LM5192-Q1 enters sleep mode and switches to a low I Q-SLEEP state to reduce the current drawn from the input. For the LM5192-Q1 to go into sleep mode, the device must be programmed for PFM mode. www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

8 LM5192-Q1 Registers

Table 8-1 lists the memory-mapped registers for the LM5192-Q1 registers. All register offset addresses not listed in Table 8-1 should be considered as reserved locations and the register contents should not be modified. Table 8-1. LM5192-Q1 Registers Offset Acronym Register Name Section 1h OPERATION Operation register Section 8.1 3h CLEAR_FAULTS Clear faults register Section 8.2 21h VOUT_COMMAND Set output voltage register Section 8.3 78h STATUS_BYTE Device status register Section 8.4 79h STATUS_WORD Device status word Section 8.5 D0h MFG_DEVICE_CFG_D0 Set average output current limit register Section 8.6 D1h MFG_DEVICE_CFG_D1 Device configuration register 1 Section 8.7 D2h MFG_DEVICE_CFG_D2 Device configuration register 2 Section 8.8 D5h MFG_DEVICE_CFG_D5 Device configuration register 3 Section 8.9 D8h MFG_DEVICE_CFG_D8 Device configuration register 4 Section 8.10 D9h MFG_DEVICE_CFG_D9 Device configuration register 5 Section 8.11 Complex bit access types are encoded to fit into small table cells. Table 8-2 shows the codes that are used for access types in this section. Table 8-2. LM5192-Q1 Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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8.1 OPERATION Register (Offset = 1h) [Reset = 00h]

OPERATION is shown in Table 8-3. Return to the Summary Table. Operation register is used to enable or disable the device. Table 8-3. OPERATION Register Field Descriptions Bit Field Type Reset Description 7 CONTROLLER_EN R/W 0h Controller enable bit. 0h = Disabled 1h = Enabled 6-0 RESERVED R 0h Reserved. This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations the value of 0 is returned. www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

8.2 CLEAR_FAULTS Register (Offset = 3h) [Reset = 00h]

CLEAR_FAULTS is shown in Table 8-4. Return to the Summary Table. Clear faults register is used to clear the fault bits in the status register 0x78h. Table 8-4. CLEAR_FAULTS Register Field Descriptions Bit Field Type Reset Description 7-0 CLEAR_FAULTS W 0h Clear faults bit. LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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8.3 VOUT_COMMAND Register (Offset = 21h) [Reset = 00FAh]

VOUT_COMMAND is shown in Table 8-5. Return to the Summary Table. Set output voltage register is used to set the target output voltage. Table 8-5. VOUT_COMMAND Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h Reserved. This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations the value of 0 is returned. 11-8 VOUT_MSB R/W 0h Output voltage setting upper byte. Lower limit: 3.3V (1V) Upper limit: 48V (24V) Step size: 20mV (10mV) SEL_FB_DIV20 =1 (SEL_FB_DIV20 =0) 0000h = 3.3V (1V) 0064h = 3.3V (1V) 00A5h = 3.3V (1.65V) 00FAh = 5V (2.5V) 01C2h = 9V (4.5V) 02EEh = 15V (7.5V) 03E8h = 20V (10V) 0578h = 28V (14V) 0708h = 36V (18V) 0960h = 48V (24V) FFFFh = 48V (24V) 7-0 VOUT_LSB R/W FAh Output voltage setting lower byte. Lower limit: 3.3V (1V) Upper limit: 48V (24V) Step size: 20mV (10mV) SEL_FB_DIV20 =1 (SEL_FB_DIV20 =0) 0000h = 3.3V (1V) 0064h = 3.3V (1V) 00A5h = 3.3V (1.65V) 00FAh = 5V (2.5V) 01C2h = 9V (4.5V) 02EEh = 15V (7.5V) 03E8h = 20V (10V) 0578h = 28V (14V) 0708h = 36V (18V) 0960h = 48V (24V) FFFFh = 48V (24V) www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

8.4 STATUS_BYTE Register (Offset = 78h) [Reset = 00h]

STATUS_BYTE is shown in Table 8-6. Return to the Summary Table. Device status register. Table 8-6. STATUS_BYTE Register Field Descriptions Bit Field Type Reset Description 7 BUSY R/W 0h Device busy status bit. If set, the device is busy and unable to respond. 0h = No fault 1h = Fault 6 OFF R/W 0h Device on/off status bit. If set, the device is disabled / off. 0h = No fault 1h = Fault 5 VOUT_OV R/W 0h Device output overvoltage status bit. If set, the voltage on the device output has exceeded the set OVP threshold. 0h = No fault 1h = Fault 4 IOUT_OC R/W 0h Device output overcurrent status bit. Is set, the cycle-by-cycle current limit has been triggered. 0h = No fault 1h = Fault 3 RESERVED R 0h Reserved. This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations the value of 0 is returned. 2 TEMPERATURE R/W 0h Device overtemperature status bit. If set, the device temperature has triggered the thermal shut down (TSD) threshold. 0h = No fault 1h = Fault 1 CML R/W 0h Device communication, memory, or logic fault status bit. If triggered, the device memory (parity) error has occurred. 0h = No fault 1h = Fault 0 NONE_OF_THE_ABOVE R/W 0h Device other fault or warning status bit. If set, a fault or warning listed in the 0x79[15:8] byte has occurred. 0h = No fault 1h = Fault LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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8.5 STATUS_WORD Register (Offset = 79h) [Reset = 0000h]

STATUS_WORD is shown in Table 8-7. Return to the Summary Table. Device status word. Table 8-7. STATUS_WORD Register Field Descriptions Bit Field Type Reset Description 15 VOUT R/W 0h Device output voltage status bit. If set, the voltage on the device output has exceeded the set OVP threshold or PG OV threshold. 0h = No fault 1h = Fault 14 IOUT_POUT R/W 0h Output current or output power warning. 0h = No fault 1h = Fault 13 RESERVED R 0h Reserved. This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations the value of 0 is returned. 12 CC_STATUS R/W 0h Constant current (CC) status bit. If set, the device operates in CC regulation mode. Otherwise, the device operates in constant voltage (CV) regulation mode. 0h = CV regulation 1h = CC regulation 11 nPG_STATUS R/W 0h Power not good status bit. If set, the voltage on the output of the device has triggered either PG UV or PG OV threshold. 0h = No fault 1h = Fault 10 RESERVED R 0h Reserved. This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations the value of 0 is returned. 9 RESERVED R 0h Reserved. This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations the value of 0 is returned. 8 RESERVED R 0h Reserved. This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations the value of 0 is returned. 7 BUSY R/W 0h Device busy status bit. If set, the device is busy and unable to respond. 0h = No fault 1h = Fault 6 OFF R/W 0h Device on/off status bit. If set, the device is disabled / off. 0h = No fault 1h = Fault 5 VOUT_OV R/W 0h Device output overvoltage status bit. If set, the voltage on the device output has exceeded the set OVP threshold. 0h = No fault 1h = Fault 4 IOUT_OC R/W 0h Device output overcurrent status bit. Is set, the cycle-by-cycle current limit has been triggered. 0h = No fault 1h = Fault 3 RESERVED R 0h Reserved. This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations the value of 0 is returned. 2 TEMPERATURE R/W 0h Device overtemperature status bit. If set, the device temperature has triggered the thermal shut down (TSD) threshold. 0h = No fault 1h = Fault www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

Table 8-7. STATUS_WORD Register Field Descriptions (continued) Bit Field Type Reset Description 1 CML R/W 0h Device communication, memory, or logic fault status bit. If triggered, the device memory (parity) error has occurred. 0h = No fault 1h = Fault 0 NONE_OF_THE_ABOVE R/W 0h Device other fault or warning status bit. If set, a fault or warning listed in the 0x79[15:8] byte has occurred. 0h = No fault 1h = Fault LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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8.6 MFG_DEVICE_CFG_D0 Register (Offset = D0h) [Reset = 0Ah]

MFG_DEVICE_CFG_D0 is shown in Table 8-8. Return to the Summary Table. Set average output current limit register. Table 8-8. MFG_DEVICE_CFG_D0 Register Field Descriptions Bit Field Type Reset Description 7-0 AVG_ILIM_THRESHOLD R/W Ah Set average output current limit threshold. Assumes 8mΩ (2mΩ) sense resistor is selected. Lower limit: 0.5A (2A) Upper limit: 7.5A (30A) Step size: 50mA (200mA) 0h = 0.5A (2A) Ah = 0.5A (2A) 3Ch = 3A (12A) 64h = 5A (20A) 96h = 7.5A (30A) FFh = 7.5A (30A) www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

8.7 MFG_DEVICE_CFG_D1 Register (Offset = D1h) [Reset = 8Ah]

MFG_DEVICE_CFG_D1 is shown in Table 8-9. Return to the Summary Table. Device configuration register 1 is used to select FB divider, configure DRSS function, set the switching frequency, and select compensation for the constant current loop. Table 8-9. MFG_DEVICE_CFG_D1 Register Field Descriptions Bit Field Type Reset Description 7 SEL_FB_DIV20 R/W 1h Select FB divider. The selection determines the output voltage range and step size. 0h = DIV10 (10mV step size, 1V-24V range) 1h = DIV20 (20mV step size, 3.3V-48V range) 6 DRSS_EN R/W 0h Enable DRSS function. 0h = DRSS disabled 1h = DRSS enabled 5 DRSS_FMOD R/W 0h Select DRSS triangular modulation frequency. 0h = 10kHz 1h = 2.5kHz 4-3 FREQ R/W 1h Select switching frequency. 0h = 200kHz 1h = 400kHz 2h = 600kHz 3h = 2.2MHz 2-1 CC_COMP R/W 1h Select CC compensation time constant. 0h = 0.1ms 1h = 0.2ms 2h = 0.3ms 3h = 0.4ms 0 RESERVED R 0h Reserved. This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations the value of 0 is returned. LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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8.8 MFG_DEVICE_CFG_D2 Register (Offset = D2h) [Reset = CBh]

MFG_DEVICE_CFG_D2 is shown in Table 8-10. Return to the Summary Table. Device configuration register 2 is used to configure output active discharge, output voltage slew rate, and select soft-start time. Table 8-10. MFG_DEVICE_CFG_D2 Register Field Descriptions Bit Field Type Reset Description

7 ACTIVE_DISCHARGE_C

R/W 1h Enable active discharge during VOUT high to low transition. 0h = Disabled 1h = Enabled

6 ACTIVE_DISCHARGE_C

R/W 1h Enable active discharge during PFM to FPWM transition. 0h = Disabled 1h = Enabled

5 ACTIVE_DISCHARGE_C

R/W 0h Enable continuous active discharge. 0h = Disabled 1h = Enabled 4-3 VOUT_SLEW_RATE R/W 1h Select output voltage slew rate. SEL_FB_DIV20 =1 (SEL_FB_DIV20 =0) 0h = 40mV/us (20mV/us) 1h = 20mV/us (10mV/us) 2h = 1mV/us (0.5mV/us) 3h = 0.5mV/us (0.25mV/us) 2-1 ACTIVE_DISCHARGE_S TRENGTH R/W 1h Select active discharge strength. 0h = Disabled 1h = 25mA 2h = 50mA 3h = 75mA 0 SOFT_START_TIME R/W 1h Select soft-start ramp time. 0h = 5V/ms 1h = 2.5V/ms www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

8.9 MFG_DEVICE_CFG_D5 Register (Offset = D5h) [Reset = 65h]

MFG_DEVICE_CFG_D5 is shown in Table 8-11. Return to the Summary Table. Device configuration register 3 is used to enable and configure overvoltage protection (OVP) function and set OVP thresholds. Table 8-11. MFG_DEVICE_CFG_D5 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h Reserved. This bit is not implemented in hardware. During write operations data for this bit is ignored. During read operations the value of 0 is returned. 6 OVP_EN R/W 1h Enable OVP detection. 0h = Disabled 1h = Enabled 5 OVP_CFG R/W 1h Configure OVP detection. 0h = OVP detection only results in the Status register update 1h = OVP detection interrupts switching, discharges VOUT, sets the VOUT_OV bit in the Status register 4-0 OVP_THRESHOLD R/W 5h Select OVP rising threshold. Lower limit: 105% Upper limit: 136% Step size: 1% 0h = 105% 5h = 110% Ah = 115% 1Fh = 136% LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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8.10 MFG_DEVICE_CFG_D8 Register (Offset = D8h) [Reset = CAh]

MFG_DEVICE_CFG_D8 is shown in Table 8-12. Return to the Summary Table. Device configuration register 4 is used to set the NINT mask, enable a connection from the VCC and VDD regulator inputs to the VOUTF pin, enable and configure gain of the cable drop compensation function. Table 8-12. MFG_DEVICE_CFG_D8 Register Field Descriptions Bit Field Type Reset Description 7 NINT_MASK R/W 1h Mask NINT for all STATUS register bits except the CC_STATUS bit. 0h = NINT for most STATUS BYTE/WORD faults. 1h = NINT for only MFG_SPECIFIC bit (CC regulation) in the STATUS register

6 BIAS_EN R/W 1h Enable connection from the VDD and VCC regulator bias inputs to

the VOUTF pin. 0h = Disabled 1h = Enabled 5 CDC_EN R/W 0h Enable cable drop compensation. 0h = Disabled 1h = Enabled 4-0 CDC_GAIN R/W Ah Configure CDC gain. Lower limit: 0V/V Upper limit: 62V/V Step size: 2V/V 0h = 0V/V 1h = 2V/V Ah = 20V/V 1Fh = 62V/V www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

8.11 MFG_DEVICE_CFG_D9 Register (Offset = D9h) [Reset = 00h]

MFG_DEVICE_CFG_D9 is shown in Table 8-13. Return to the Summary Table. Device configuration register 5 is used to enable MFI function, enable HICCUP mode, override mode selection of the PFM pin, select MODE, and power good (PG) detection window. Table 8-13. MFG_DEVICE_CFG_D9 Register Field Descriptions Bit Field Type Reset Description 7 MFI_EN R/W 0h Enable MFI CC regulation (1.6xILIM for the 1ms of CC regulation). 0h = Disabled 1h = Enabled 6 HICCUP_EN R/W 0h Enable HICCUP operation. 0h = Disabled 1h = Enabled 5 OVERRIDE_PFM R/W 0h Override PFM pin setting. 0h = PFM pin sets the mode of operation 1h = MODE bit sets the mode of operation 4 MODE R/W 0h Select mode of operation. 0h = FPWM 1h = PFM 3 PG_10PCT R/W 0h Select PG window. 0h = 5% 1h = 10%

2 SPARE2 R/W 0h Spare bit#2

0h = Disabled 1h = Enabled

1 SPARE1 R/W 0h Spare bit#1

0h = Disabled 1h = Enabled

0 SPARE0 R/W 0h Spare bit#0

0h = Disabled 1h = Enabled LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Powertrain Components

A comprehensive understanding of the buck regulator power train components is critical to successfully completing a synchronous buck regulator design. The following sections discuss the output inductor, input and output capacitors, power MOSFETs, and EMI input filter.

9.1.1.1 Buck Inductor

For most applications, select a buck inductance such that the inductor ripple current, ΔIL, is between 30% to 50% of the maximum DC output current at typical input voltage. Select the inductance using Equation 8. L O = V OUT ∆ I L × f SW × 1 − V OUT V IN (8) Check the inductor data sheet to make sure that the saturation current of the inductor is above the peak inductor current of a particular design. Ferrite cores have very low core loss and are preferred at high switching frequencies, so design goals can then concentrate on copper loss and preventing saturation. Low inductor core loss is evidenced by reduced no-load input current and higher light-load efficiency. However, ferrite core materials exhibit a hard saturation characteristic and the inductance collapses abruptly when the saturation current is exceeded. This action results in an abrupt increase in inductor ripple current and higher output voltage ripple, not to mention reduced efficiency and compromised reliability. Note that the saturation current of an inductor generally decreases as the core temperature increases.

9.1.1.2 Output Capacitors

The output capacitors combined with the control loop response make sure the output voltage stays within the dynamic transient tolerance specifications. The usual boundaries restricting the output capacitor are driven by finite available PCB area, component size, and cost. The equivalent series resistance (ESR) and equivalent series inductance (ESL) of the output capacitor dominates shaping the load transient response as the load step amplitude and slew rate increase. The output capacitor, COUT, filters the inductor ripple current and provides a reservoir of charge for load transient events. Typically, ceramic capacitors provide low ESR to reduce the output voltage ripple and noise spikes, while tantalum or electrolytic capacitors provide a large bulk capacitance in a relatively compact footprint for transient loading events. Figure 9-1 conceptually illustrates the relevant current waveforms during both load step-down and step-up transitions. As shown, the large-signal slew rate of the inductor current is limited as the inductor current ramps to match the new load-current level following a load transient. This slew-rate limiting exacerbates the deficit of charge in the output capacitor, which must be replenished as fast as possible during and after the load step-up transient. Similarly, during and after a load step-down transient, the slew rate limiting of the inductor current adds to the surplus of charge in the output capacitor that must be depleted as quickly as possible. www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

= - dILOUT dt VLOAD LOUT = -VSUPPLY dILOAD dt tramp = ∆ILOAD Figure 9-1. Load Transient Response Representation Showing COUT Charge Surplus or Deficit For example, in a typical regulator application of 12V input to 3.3V output voltage, the load-off transient represents the worst case in terms of output voltage transient deviation. In that conversion ratio application, the steady-state duty cycle is approximately 28% and the large-signal inductor current slew rate when the duty cycle collapses to zero is approximately –V LOAD / L OUT. Compared to a load-on transient, the inductor current takes much longer to transition to the required level. The surplus of charge in the output capacitor causes the output voltage to overshoot. In fact, to deplete this excess charge from the output capacitor as quickly as possible, the inductor current must ramp below the nominal level following the load step. In this scenario, a large output capacitance can be advantageously employed to absorb the excess charge and minimize the voltage overshoot. To meet the dynamic specification of output voltage overshoot during such a load-off transient (denoted as ΔVOVERSHOOT with step reduction in output current given by ΔILOAD), the output capacitance must be larger than: C O UT ≥ L O U T × ∆ I LOAD 2 V LOAD + ∆ V OVE RSH O OT 2 − V LOAD 2 (9) Based on the static specification of peak-to-peak output voltage ripple denoted by ΔVLOAD, select an output capacitance that is larger than that given by Equation 10. C O UT ≥ ∆ I LOUT 8 × f SW × ∆ V LOAD 2 − R ES R × ∆ I L O UT 2 (10) The ESR of a capacitor is provided in the manufacturer datasheet, either explicitly as a specification or implicitly in the impedance versus frequency curve. Depending on type, size, and construction, electrolytic capacitors have significant ESR, 5m Ω and above, and relatively large ESL, 5nH to 20nH. PCB traces contribute some parasitic resistance and inductance as well. Ceramic output capacitors have low-ESR and ESL contributions at the switching frequency, and the capacitive impedance component dominates. However, depending on package and voltage rating of the ceramic capacitor, the effective capacitance can drop quite significantly with applied DC voltage and operating temperature. Ignoring the ESR term in Equation 10 gives a quick estimation of the minimum ceramic capacitance necessary to meet the output ripple specification. Use Equation 9 to determine if additional capacitance is necessary to meet the load-off transient overshoot specification. LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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A composite implementation of ceramic and electrolytic capacitors highlights the rationale for paralleling capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range. While the ceramic provides excellent mid- and high-frequency decoupling characteristics with the low ESR and ESL to minimize the switching frequency output ripple, the electrolytic device with the large bulk capacitance provides low-frequency energy storage to cope with load transient demands.

9.1.1.3 Input Capacitors

Input capacitors are necessary to limit the input ripple voltage to the buck power stage due to switching- frequency AC currents. TI recommends using X7S or X7R dielectric ceramic capacitors to provide low impedance and high RMS current rating over a wide temperature range. To minimize the parasitic inductance in the switching loop, position the input capacitors as close as possible to the drain of the high-side MOSFET and the source of the low-side MOSFET. Equation 11 gives the input capacitor RMS current for a single-channel buck regulator. I CIN, rms = D × I LOAD 2 × 1 − D + ∆ I L O UT 2 12 (11) The highest input capacitor RMS current occurs at D = 0.5, at which point, the RMS current rating of the input capacitors must be greater than half the output current. Ideally, the DC component of input current is provided by the input voltage source and the AC component by the input filter capacitors. Neglecting inductor ripple current, the input capacitors source current of amplitude (I LOAD − ISUPPLY) during the D interval and sinks I SUPPLY during the 1 −D interval. Thus, the input capacitors conduct a square-wave current of peak-to-peak amplitude equal to the output current. The resultant capacitive component of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, Equation 12 gives the peak-to-peak ripple voltage amplitude. ∆ V S U PPLY = I LOAD × D × 1 − D f SW × C IN + I LOAD × R ESR (12) Equation 13 gives the input capacitance required for a particular load current, based on an input voltage ripple specification of ΔVSUPPLY. C I N ≥ D × 1 − D × I L O AD f SW × ∆ V SUPPLY − I L O AD × R ES R (13) Low-ESR ceramic capacitors can be placed in parallel with higher valued bulk capacitance to provide optimized input filtering for the regulator and damping to mitigate the effects of input parasitic inductance resonating with high-Q ceramics. Select the input bulk capacitor based on the ripple current rating and operating temperature range.

9.1.1.4 Power MOSFETs

The choice of power MOSFETs has significant impact on DC/DC regulator performance. A MOSFET with low on-state resistance, R DS(on), reduces conduction loss, whereas low parasitic capacitances enable faster transition times and reduced switching loss. Normally, the lower the R DS(on) of a MOSFET, the higher the gate charge and output charge (Q G and Q OSS, respectively), and vice versa. As a result, the product of R DS(on) and QG is commonly specified as a MOSFET figure-of-merit. Low thermal resistance of a given package makes sure that the MOSFET power dissipation does not result in excessive MOSFET die temperature. The main parameters affecting power MOSFET selection are as follows:

• RDS(on) at 7.5V
• Drain-source voltage rating, BVDSS
• Gate charge parameters at 7.5V
• Output charge, QOSS, at the relevant input voltage www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

• Body diode reverse recovery charge, QRR
• Gate threshold voltage, VGS(th), derived from the Miller plateau evident in the QG versus VGS plot in the MOSFET datasheet. To enhance MOSFET adequately, the miller plateau voltage must be 2V to 3V lower than the gate drive amplitude, especially at the minimum input voltage. The MOSFET-related power losses for one channel are summarized by the equations presented in Table 9-1, where suffixes one and two represent high-side and low-side MOSFET parameters, respectively. While the influence of inductor ripple current is considered, second-order loss modes, such as those related to parasitic inductances and SW node ringing, are not included. Table 9-1. MOSFET Power Losses POWER LOSS MODE HIGH-SIDE MOSFET LOW-SIDE MOSFET MOSFET conduction (2) (3) P cond 1 = D × I LOAD 2 + ∆ I LOUT 2 12 × R DS on 1 (14) P cond 2 = D ′ × I LOAD 2 + ∆ I LOUT 2 12 × R D S on 2 (15) MOSFET switching P sw1 = V SUPPLY × f SW 2 × I LOAD − ∆ I LOUT 2 × t R + I LOAD + ∆ I L O U T 2 × t F (16) Negligible MOSFET gate drive(1) P gat e1 = V CC × f SW × Q G1 (17) P gat e2 = V CC × f SW × Q G2 (18) MOSFET output charge(4) P C oss = f S W × V SUPPLY × Q OSS2 + E o ss1 − E oss 2 (19) Body diode conduction N/A P cond B D = V F × f SW × I L O AD + ∆ I LOUT 2 × t dt 1 + I L O AD − ∆ I L O UT 2 × t dt 2 (20) Body diode reverse recovery(5) P RR = V SUPP LY × f SW × Q RR2 (21) (1) Gate drive loss is apportioned based on the internal gate resistance of the MOSFET, externally added series gate resistance and the relevant driver resistance of the device. (2) MOSFET RDS(on) has a positive temperature coefficient of approximately 4500ppm/°C. The MOSFET junction temperature, TJ, and the rise over ambient temperature is dependent upon the device total power dissipation and the thermal impedance. When operating at or near minimum input voltage, make sure that the MOSFET RDS(on) is rated for the available gate drive voltage. (3) D' = 1–D is the duty cycle complement. (4) MOSFET output capacitances, Coss1 and Coss2, are highly non-linear with voltage. These capacitances are charged losslessly by the inductor current at high-side MOSFET turn-off. During turn-on, however, a current flows from the input to charge the output capacitance of the low-side MOSFET. Eoss1, the energy of Coss1, is dissipated at turn-on, but this dissipation is offset by the stored energy Eoss2 on Coss2. (5) MOSFET body diode reverse recovery charge, QRR, depends on many parameters, particularly forward current, current transition speed, and temperature. The high-side (control) MOSFET carries the inductor current during the PWM on-time (or D interval) and typically incurs most of the switching losses. Choosing a high-side MOSFET that balances conduction and switching loss contributions is imperative. The total power dissipation in the high-side MOSFET is the sum of the losses due to conduction, switching (voltage-current overlap), output charge, and typically two-thirds of the net loss attributed to body diode reverse recovery. The low-side (synchronous) MOSFET carries the inductor current when the high-side MOSFET is off (or 1–D interval). The low-side MOSFET switching loss is negligible as the low-side MOSFET switching loss is switched at zero voltage – current just communicates from the channel to the body diode or vice versa during the LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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transition dead-times. The device, with the adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such losses scale directly with switching frequency. In high step-down ratio applications, the low-side MOSFET carries the current for a large portion of the switching period. Therefore, to attain high efficiency, optimizing the low-side MOSFET for low R DS(on) is critical. In cases where the conduction loss is too high or the target R DS(on) is lower than available in a single MOSFET, connect two low-side MOSFETs in parallel. The total power dissipation of the low-side MOSFET is the sum of the losses due to channel conduction, body diode conduction, and typically one-third of the net loss attributed to body diode reverse recovery.

9.1.1.5 EMI Filter

Switching regulators exhibit negative input impedance, which is lowest at the minimum input voltage. An underdamped LC filter exhibits a high output impedance at the resonant frequency of the filter. For stability, the filter output impedance must be less than the absolute value of the converter input impedance. Z IN = − V SUPPLY MI N 2 P SUPPLY (22) The passive EMI filter design steps are as follows:

• Calculate the required attenuation of the EMI filter at the switching frequency, where CIN represents the existing capacitance at the input of the switching converter.
• Input filter inductor LF is typically selected between 1μH and 10μH, but can be lower to reduce losses in a high-current design.
• Calculate input filter capacitor CF. VSUPPLY-EMI GND LF CF CD RD VSUPPLY CIN Figure 9-2. Passive π-Stage EMI Filter for Buck Regulator By calculating the first harmonic current from the Fourier series of the input current waveform and multiplying by the input impedance (the impedance is defined by the existing input capacitor CIN), a formula is derived to obtain the required attenuation as shown by Equation 23. At t n = 20log I LOUT PEAK π 2 × f SW × C IN × si n π × D MA X × 1 1 µ V − V MAX (23) where
• VMAX is the allowed dBμV noise level for the applicable conducted EMI specification.
• CIN is the existing input capacitance of the buck regulator.
• DMAX is the maximum duty cycle.
• ILOUT(PEAK) is the peak inductor current. For filter design purposes, the current at the input can be modeled as a square-wave. Use Equation 24 to determine the passive EMI filter capacitance CF. www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

C F = 1 L F At t n 2 π × f SW (24) Adding an input filter to a switching regulator modifies the control-to-output transfer function. The output impedance of the filter must be sufficiently small so that the input filter does not significantly affect the loop gain of the buck converter. The impedance peaks at the filter resonant frequency. Equation 25 gives the resonant frequency of the passive filter. f res = 1 2 π × L F × C F (25) The purpose of R D is to reduce the peak output impedance of the filter at the resonant frequency. Capacitor C D blocks the DC component of the input voltage to avoid excessive power dissipation in R D. Capacitor C D must have lower impedance than RD at the resonant frequency with a capacitance value greater than that of the input capacitor CIN. This requirement prevents C IN from interfering with the cutoff frequency of the main filter. Added input damping is needed when the output impedance of the filter is high at the resonant frequency (Q of filter formed by LF and CIN is too high). An electrolytic capacitor C D can be used for input damping with a value that Equation 26 gives. C D ≥ 4 × C IN (26) Use Equation 27 to select the input damping resistor RD. R D = L F C IN (27)

9.1.2 Error Amplifier and Compensation

Figure 9-3 shows a type-ll compensator using a transconductance error amplifier (EA). The dominant pole of the EA open-loop gain is set by the EA output resistance, R O(EA), and effective bandwidth-limiting capacitance, CBW, as shown by Equation 28. G EA s = − g m E A × R O EA 1 + s × R O EA × C B W (28) The EA high-frequency pole is neglected in the above expression. Equation 29 calculates the compensator transfer function from output voltage to COMP node, including the gain contribution from the (internal or external) feedback resistor network. G C O MP s = V COMP s V LOAD s = − V REF V LOAD × g m × R O EA × 1 + s ω Z1 1 + s ω P1 × 1 + s ω P 2 (29) where

• VREF is the feedback voltage reference.
• gm(EA) is the EA gain transconductance of 1mS.
• RO(EA) is the error amplifier output impedance of 70MΩ. ω Z1 = 1 R C O MP × C COM P (30) ω P1 = 1 R O E A × C COMP + C HF + C B W ≅ 1 R O E A × C C O MP (31) LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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ω P2 = 1 R COMP × C C OM P C H F + C B W ≅ 1 R C O MP × C HF (32) The EA compensation components create a pole close to the origin, a zero, and a high-frequency pole. Typically, RCOMP << RO(EA) and CCOMP >> CBW and CHF, so the approximations are valid. Error Amplifier Model VREF COMPFB CHFCBW RO(EA) RFBT VLOAD gm RFBB CCOMP RCOMP AGND Figure 9-3. Error Amplifier and Compensation Network www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

9.2 Typical Application

For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation and test results, refer to TI Designs reference design library.

9.2.1 High Efficiency, Wide Input, 400kHz, Synchronous Buck Regulator

Figure 9-4 shows the schematic diagram of a single-output, synchronous, buck regulator with I 2C interface, which provides maximum output voltages of 12V and a rated load current of 8A. In this example, the target full-load efficiencies at 48V input is 96%. The regulator is designed for 400kHz switching frequency. VSUPPLY PFM/SYNC COMP CFG / IMON VOUTS / ISNS- ISNS+ CBOOT EN/UVLO VCC SCL VIN VOUTF / BIAS AGND RCNFG CVDDA CVCC CVIN VDDA RCOMP CCOMP SDA nINT PGND To MCU To MCU To MCU PFM = VDDA : PFM mode PFM = GND : FPWM mode PFM = fSYNC : Clock synchronization in FPWM MCU VDD To MCU_ADC (MCU_GPIO must be high-Z during initial start-up) RENT RENB CIN CHF CCBOOT LO HO SW LOUT COUTB VLOAD RLOAD RESR COUTHF RS QH QL 4.75V < BIAS <48V Figure 9-4. Application Circuit With I2C Interface Note Depending on the source impedance of the input supply bus, an electrolytic capacitor can be required at the input to make sure of stability, particularly at low input voltage and high output current operating conditions. LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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9.2.1.1 Design Requirements

Table 9-2 shows the intended input, output, and performance parameters for this design example. Table 9-2. Design Parameters DESIGN PARAMETER VALUE Input operating range 15V, 48V, 70V (minimum, typical, maximum) CV regulation target 12V CC regulation target 8A Switching frequency 400kHz The switching frequency is set at 400KHz by resistor R RT. In terms of control loop performance, the target loop crossover frequency is 40kHz with a phase margin greater than 60°.

9.2.1.2 Detailed Design Procedure

Use the Quick Start Calculator to expedite the process of designing a regulator for a given application based on the device specifications. Download the LM5192-LM25192-DESIGN-CALC Quick Start Calculator for a detailed design procedure. See the LM5192-Q1 CC-CV Buck Controller with I 2C Evaluation Module EVM user's guide for recommended components and typical application curves.

9.2.1.2.1 Buck Inductor

1. Use Equation 33 to calculate the required buck inductance based on a 40% inductor ripple current at nominal input voltages. L O = V OUT ∆ I L × f SW × 1 − V OUT V IN = 12 3.2 × 400 k × 1 − 12 48 = 7.0µH (33) 2. Select a standard inductor value of 6.8µH to account for effective inductance derating with current of molded inductors. Use Equation 34 to calculate the peak inductor currents at maximum steady-state input voltage. I LO PK = I LOAD + ∆ I L 2 = I LOAD + V OUT 2 × L O × f SW × 1 − V O U T V IN MAX = 8 + 3.655 2 = 9.83 A (34) 3. Subharmonic oscillation occurs with a duty cycle greater than 50% for peak current-mode control if no slope compensation. For design simplification, the device has an internal slope compensation ramp proportional to the switching frequency that is added to the current sense signal to damp any tendency toward subharmonic oscillation. Use Equation 35 to cross-check the inductance to set a slope compensation close to the ideal one times the inductor current downslope. L O MI N = V OUT × R S 0.04 × f SW = 12 × 5 m 0.04 × 400 k = 3 . 75µH (35)

9.2.1.2.2 Current-Sense Resistance

1. Calculate the current-sense resistance based on a maximum peak current capability of at least 20% higher than the peak inductor current at full load to provide sufficient margin during start-up and load-on transients. Use Equation 36 to calculate the current sense resistances. R S = V CS − TH 1.2 × I LO PK = 60 m 2. Select a standard resistance value of 5mΩ for the shunt. Carefully adhere to the layout guidelines in Section 9.4.1 to make sure that noise and DC errors do not corrupt the differential current-sense voltages measured at the ISNS+ and VOUTS pins. 3. Place the shunt resistor close to the inductor. 4. Use Kelvin-sense connections, and route the sense lines differentially from the shunt to the device. www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

1. The CS-to-output propagation delay (related to the current limit comparator, internal logic, and power MOSFET gate drivers) causes the peak current to increase above the calculated current limit threshold. For a total propagation delay tDELAY of 105ns, use Equation 37 to calculate the worst-case peak inductor current with the output shorted. I LO − PK SC = V C S − TH M AX R S + V I N M AX × t D ELAY L O = 66m 5m + 70 × 105 n 6 . 8µ = 14.3 A (37) 6. Based on this result, select an inductor with saturation current greater than 14.3A across the full operating temperature range.

9.2.1.2.3 Output Capacitors

1. Use Equation 38 to estimate the output capacitance required to manage the output voltage overshoot during a load-off transient (from full load to no load) assuming a load transient deviation specification of 3% . C O UT ≥ L O × ∆ I LOAD 2 V LOAD + ∆ V OVE RSH O OT 2 − V LOAD 2 = 6 . 8 µ × 8 2 12 + 12 × 0.03 2 − 12 2 = 49.6µF (38) 2. Noting the voltage coefficient of ceramic capacitors where the effective capacitance decreases significantly with applied voltage, select four 22µF, 25V, X7R ceramic output capacitors. Generally, when sufficient capacitance is used to satisfy the load-off transient response requirement, the voltage undershoot during a no-load to full-load transient is also satisfactory. 3. Use Equation 39 to estimate the peak-peak output voltage ripple at nominal input voltage. ∆ V OUT = ∆ I L 8 × f SW × C OUT + R ESR × ∆ I L 2 = 3.65 8 × 400 k × 62u 2 + 1m × 3.65 2 = 19 m V (39) where

• RESR is the effective equivalent series resistance (ESR) of the output capacitors.
• 62µF is the total effective (derated) ceramic output capacitance at 12V. 4. Use Equation 40 to calculate the output capacitor RMS ripple current and verify that the ripple current is within the capacitor ripple current rating. I CO RM S = ∆ I L O UT 12 = 3.65 12 = 1.05 A (40)

9.2.1.2.4 Input Capacitors

A power supply input typically has a relatively high source impedance at the switching frequency. Good-quality input capacitors are necessary to limit the input ripple voltage. In general, the ripple current splits between the input capacitors based on the relative impedance of the capacitors at the switching frequency. 1. Select the input capacitors with sufficient voltage and RMS ripple current ratings. 2. Use Equation 41 to calculate the input capacitor RMS ripple current assuming a worst-case duty-cycle operating point of 50%. I CIN, rms = D × I LOAD 2 × 1 − D + ∆ I L O UT 2 12 = 0.5 × 8 2 × 1 − 0.5 + 3.65 2 12 = 4.1 A (41) 3. Use Equation 42 to find the required input capacitance. C I N ≥ D × 1 − D × I L O AD f SW × ∆ V SUPPLY − I L O AD × R ES R 400 k × 0.25 − 8 × 1 m = 21 µ F (42) where

• ΔVSUPPLY is the input peak-to-peak ripple voltage specification.
• RESR is the input capacitor ESR. LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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1. Recognizing the voltage coefficient of ceramic capacitors, select six 4.7µF, 100V, X7R ceramic input capacitors. Place these capacitors adjacent to the power MOSFETs. 5. Use six 10nF, 100V, X7R, 0603 ceramic capacitors near the high-side MOSFET to supply the high di/dt current during MOSFET switching transitions. Such capacitors offer high self-resonant frequency (SRF) and low effective impedance above 100MHz. The result is lower power loop parasitic inductance, thus minimizing switch-node voltage overshoot and ringing for lower conducted and radiated EMI signature.

9.2.1.2.5 Compensation Components

Select compensation components for a stable control loop using the procedure outlined as follows. 1. Based on a specified loop gain crossover frequency, fC, of 40kHz, use Equation 43 to calculate RCOMP, assuming an effective output capacitance of 62µF. Choose a standard value for RCOMP of 7.68kΩ. VREF is VOUT/10 if VSTEP is 10mV. VREF is VOUT/20 if VSTEP is 20mV. R COMP = 2 × π × f C × V OUT V REF × R S × G CS gm × C OUT = 2 × π × 40 k Hz × 12 V 1.2V × 5mΩ × 10 1000 µ S × 62 µ F = 7.79 k Ω (43) 2. To provide adequate phase boost at crossover while also allowing a fast settling time during a load or line transient, select CCOMP to place a zero at the higher (1) one tenth of the crossover frequency, or (2) the load pole. Choose a standard value for CCOMP of 4.7nF . C COM P = 10 2 × π × f C × R C OM P = 10 2 × π × 40k Hz × 7.68 k Ω = 5.18 nF (44) 3. Calculate CHF to create a pole at the ESR zero and to attenuate high-frequency noise on the COMP pin. CBW is the bandwidth-limiting capacitance of the error amplifier. 1pF CHF can be ignored in this design. However, in noisy environments, especially at high VIN and high load currents, additional capacitance can help filter out the noise. C HF = 1 2 × π × f ESR × R COM P − C BW = 1 2 × π × 642k H z × 7.68 k Ω − 15pF = 17 pF (45) Note Set a fast loop with high RCOMP and low CCOMP values to improve the response when recovering from operation in dropout. www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

9.2.1.3 Application Curves

Figure 9-5. FPWM Mode Efficiency, Linear Scale Figure 9-6. PFM Mode Efficiency, Log Scale IMON 1V/DIV ILOUT 5A/DIV VOUT 5V/DIV Figure 9-7. Start-Up, EN ON, VSUPPLY = 48V, ILOAD = 8A Resistive Load IMON 1V/DIV ILOUT 5A/DIV VOUT 5V/DIV Figure 9-8. Shutdown, EN OFF, VSUPPLY = 48V, ILOAD = 8A Resistive Load VOUT 1 0 0mV/DIV , AC COUPLED ILOUT 5A/DIV Figure 9-9. Output Ripple, , VSUPPLY = 48V, ILOAD = VOUT 200mV/DIV ILOUT 1A/DIV At no load, switching occurs at every 650ms when BIAS is enabled Figure 9-10. No Load Operation in PFM Mode, VSUPPLY = 48V, ILOAD = 0A LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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9.3 Power Supply Recommendations

The device is designed to operate from a wide input supply voltage range . The input supply must be capable of delivering the required input supply current to the fully loaded regulator over the wide input voltage range. Estimate the average input supply current using Equation 46. I SUPPLY = V L O A D × I LO AD V SUPPL Y × Ef f icie n c y (46) If the regulator is connected to an input supply through long wires or PCB traces with a large impedance, take special care to achieve stable performance. The parasitic inductance and resistance of the input cables can have an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients at the regulator input each time the input supply is cycled ON and OFF. The parasitic resistance causes the input supply voltage to dip during a load transient. The best way to solve such issues is to reduce the distance from the input supply to the regulator and use an aluminum or tantalum input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitors helps damp the input resonant circuit and reduce any voltage overshoots. An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as well as some of the effects mentioned above. The AN-2162 Simple Success With Conducted EMI From DCDC Converters application note provides helpful suggestions when designing an input filter for any switching regulator.

9.4 Layout

9.4.1 Layout Guidelines

Proper PCB design and layout is important in a high-current, fast-switching circuit to achieve a robust and reliable design. The high power switching loop of a buck regulator power stage is denoted by loop 1 in the shaded area of Figure 9-15. The topological architecture of a buck regulator means that particularly high di/dt current flows in the components of loop 1, reducing the parasitic inductance of this loop by minimizing the effective loop area becomes mandatory. Also important are the gate drive loops of the high-side and low-side MOSFETs, denoted by 3 and 4, respectively. CBOOT HO SW LO VCC PGND VSUPPLY VLOAD GND VCC Low-side gate driver High-side gate driver CVCC CCBOOT CIN COUT QH QL LOUT High-current loops HS gate-drive loop LS gate-drive loop Figure 9-15. DC/DC Regulator Ground System With Power Stage and Gate Drive Circuit Switching Loops LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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9.4.1.1 Power Stage Layout

• Input capacitors, output capacitors, and MOSFETs are the constituent components of the power stage of a buck regulator and are typically placed on the top side of the PCB. The benefits of convective heat transfer are maximized because of leveraging any system-level airflow. In a two-sided PCB layout, small-signal components are typically placed on the bottom side. Insert at least one inner plane, connected to ground, to shield and isolate the small-signal traces from noisy power traces and lines.
• The DC/DC regulator has several high-current loops. Minimize the area of these loops to suppress generated switching noise and optimize switching performance. – Loop 1: the most important loop area to minimize. The path is from the input capacitor or capacitors through the high- and low-side MOSFETs, and back to the capacitor or capacitors through the ground connection. Connect the input capacitor or capacitors negative terminal close to the source of the low-side MOSFET. Similarly, connect the input capacitor or capacitors positive terminal close to the drain of the high-side MOSFET. – Loop 2: loop 2 is not as critical as loop 1. The path is from the low-side MOSFET through the inductor and output capacitor or capacitors, and back to source of the low-side MOSFET through ground. Connect the source of the low-side MOSFET and negative terminal of the output capacitor or capacitors at ground as close as possible.
• The PCB trace defined as SW node, which connects to the source of the high-side MOSFET, the drain of the low-side MOSFET and the high-voltage side of the inductor, must be short and wide. However, the SW connection is a source of injected EMI and thus must not be too large.
• Follow any layout considerations of the MOSFETs as recommended by the MOSFET manufacturer, including pad geometry and solder paste stencil design.
• The SW pin connects to the switch node of the power conversion stage and acts as the return path for the high-side gate driver. The parasitic inductance inherent to loop 1 and the output capacitance (COSS) of both power MOSFETs form a resonant circuit that induces high frequency (> 50MHz) ringing at the SW node. The voltage peak of this ringing, if not controlled, can be significantly higher than the input voltage. Make sure that the peak ringing amplitude does not exceed the absolute maximum rating limit for the SW pin. In many cases, a series resistor and capacitor snubber network connected from the SW node to GND damps the ringing and decreases the peak amplitude. If testing reveals that the ringing amplitude at the SW pin is excessive, then include snubber components as needed.

9.4.1.2 Gate-Drive Layout

Minimizing stray or parasitic gate loop inductance is key to optimizing gate drive switching performance. The following loops are important:

• Loop 3: high-side MOSFET, QH. During the high-side MOSFET turn-on, high current flows from the bootstrap capacitor through the gate driver and high-side MOSFET, and back to the negative terminal of the boot capacitor through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from the gate of the high-side MOSFET through the gate driver and SW, and back to the source of the high-side MOSFET through the SW trace.
• Loop 4: low-side MOSFET, QL. During the low-side MOSFET turn-on, high current flows from the VCC decoupling capacitor through the gate driver and low-side MOSFET, and back to the negative terminal of the capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from the gate of the low-side MOSFET through the gate driver and GND, and back to the source of the low-side MOSFET through ground. TI recommends following circuit layout guidelines when designing with high-speed MOSFET gate drive circuits.
• Connections from gate driver outputs, HO and LO, to the respective gates of the high-side or low-side MOSFETs must be as short as possible to reduce series parasitic inductance. Be aware that peak gate drive currents can be as high as a few amperes. Use 0.65mm (25mils) or wider traces. Use via or vias, if necessary, of at least 0.mm (20 mils) diameter along these traces. Route HO and SW traces as a differential pair from the device to the high-side MOSFET, taking advantage of flux cancellation. Also, route LO trace and PGND trace/copper area as a differential pair from the device to the low-side MOSFET, taking advantage of flux cancellation. www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

• Locate the bootstrap capacitor, CCBOOT, close to the CBOOT and SW pins of the device to minimize the area of loop 3 associated with the high-side driver. Similarly, locate the VCC capacitor, CVCC, close to the VCC and PGND pins of the device to minimize the area of loop 4 associated with the low-side driver.

9.4.1.3 PWM Controller Layout

Locate the device as close as possible to the power MOSFETs to minimize gate driver trace runs, the components related to the analog and feedback signals as well as current sensing are considered in the following:

• Separate power and signal, analog traces, and use a ground plane to provide noise shielding.
• Place all sensitive analog traces and components related to COMP, ISNS+, VOUTS, and IMON away from high-voltage switching nodes such as SW, HO, LO, or CBOOT to avoid mutual coupling. Use internal layer or layers as ground plane or planes.
• Route the ISNS+ and VOUT sense traces as differential pairs to minimize noise pickup and use Kelvin connections to the applicable shunt resistor. Shield the current sense (ISNS+ and VOUTS) traces from power traces and components.
• Minimize the loop area from the VCC and VIN pins through the respective decoupling capacitors to the PGND pin. Locate these capacitors as close as possible to the device.

9.4.1.4 Thermal Design and Layout

The operating temperature range of a PWM controller with integrated gate drivers and bias supply LDO regulator is greatly affected by the following:

• Average gate drive current requirements of the power MOSFETs
• Switching frequency
• Operating input supply voltage (affecting bias regulator LDO voltage drop and hence the power dissipation)
• Thermal characteristics of the package and operating environment For a PWM controller to be useful over a particular temperature range, the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The VQFN package offers a means of removing heat from the semiconductor die through the exposed thermal pad at the base of the package. The exposed pad of the package is thermally connected to the substrate of the device. This connection allows a significant improvement in heat sinking and becomes imperative that the PCB is designed with thermal lands, thermal vias, and a ground plane to complete the heat removal subsystem. The exposed pad of the device is soldered to the ground-connected copper land on the PCB directly underneath the device package, reducing the thermal resistance to a low value. Numerous vias with a 0.3mm diameter connected from the thermal land to the internal and solder-side ground plane or planes are vital to help dissipation. In a multi-layer PCB design, a solid ground plane is typically placed on the PCB layer below the power components. Not only does this placement provide a plane for the power stage currents to flow but this placement also represents a thermally conductive path away from the heat generating devices. The thermal characteristics of the MOSFETs also are significant. The drain pads of the high-side MOSFETs are normally connected to a VIN plane for heat sinking. The drain pads of the low-side MOSFETs are tied to the SW plane, but the SW plane area is purposely kept as small as possible to mitigate EMI concerns.

9.4.1.5 Ground Plane Design

TI recommends using one or more of the inner PCB layers as a solid ground plane. A ground plane offers shielding for sensitive circuits and traces and also provides a quiet reference potential for the control circuitry. In particular, a full ground plane on the layer directly underneath the power stage components is essential. Connect the source terminal of the low-side MOSFET and return terminals of the input and output capacitors to this ground plane. Connect the PGND and AGND pins of the device at the exposed pad and then connect to the system ground plane using an array of vias under the exposed pad. The PGND nets contain noise at the switching frequency and can bounce because of load current variations. The power traces for PGND, VIN, and LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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SW can be restricted to one side of the ground plane, for example, on the top layer. The other side of the ground plane contains much less noise and is deigned for sensitive analog trace routes.

9.4.2 Layout Example

Figure 9-16 shows a layout example of a synchronous buck regulator with discrete power MOSFETs. The design uses an inner layer as a power-loop return path directly underneath the top layer to create a low-area switching power loop. This loop area, and hence parasitic inductance, must be as small as possible to minimize EMI as well as switch-node voltage overshoot and ringing. The high-frequency power loop current flows through MOSFETs, through the power ground plane on the inner layer, and back to VIN through the ceramic capacitors . Multiple ceramic capacitors are placed in parallel close to the drain of the high-side MOSFET. The low equivalent series inductance (ESL) and high self-resonant frequency (SRF) of the small footprint capacitors yield excellent high-frequency performance. The negative terminals of these capacitors are connected to the inner layer ground plane with multiple vias, further minimizing parasitic loop inductance. Additional guidelines to improve noise immunity and reduce EMI are as follows:

• Connect PGND directly to the low-side MOSFET and power ground. Connect AGND directly to an analog ground plane for sensitive analog components. The analog ground plane for AGND and the power ground plane for PGND must be connected at a single point directly under the device at the exposed pad.
• Connect the MOSFETs directly to the inductor terminal with short copper connections (without vias) as this net has high dv/dt and contributes to radiated EMI. The single-layer routing of the switch-node connection means that switch-node vias with high dv/dt do not appear on the bottom side of the PCB. This event avoids e-field coupling to the reference ground plane during the EMI test. VIN and PGND plane copper pours shield the polygon connecting the MOSFETs to the inductor terminal, further reducing the radiated EMI signature.
• Place the EMI filter components on the bottom side of the PCB so that the components are shielded from the power stage components on the top side. Input capacitors Input capacitors Inductor Current sense resistor Output capacitors Output capacitorsHS MOSFET LS MOSFET Input capacitors AGND copper island Keep the switch node copper area small Place CBOOT close to the IC Place CVCC close to the IC Use multiple vias around the positive and negative connections of CIN Connect AGND and PGND directly to the DAP/EP on the top layer Use multiple vias around the positive and negative connections of CIN Place CVIN close to the IC Locate the device close to the MOSFETs Use Multiple VIAs Legend Top layer Layer-2 ground Top solder Figure 9-16. PCB Top Layer www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

10 Device and Documentation Support

10.1 Device Support

10.1.1 Development Support

For development support, see the following:

• For TI's reference design library, visit TI Designs
• TI designs: – ADAS 8-Channel Sensor Fusion Hub Reference Design with Two 4-Gbps Quad Deserializers – Automotive EMI and Thermally Optimized Synchronous Buck Converter Reference Design – Automotive High Current, Wide VIN Synchronous Buck Controller Reference Design Featuring LM5141- – 25W Automotive Start-Stop Reference Design Operating at 2.2MHz – Synchronous Buck Converter for Automotive Cluster Reference Design – 137W Holdup Converter for Storage Server Reference Design – Automotive Synchronous Buck With 3.3V at 12.0A Reference Design – Automotive Synchronous Buck Reference Design – Wide Input Synchronous Buck Converter Reference Design With Frequency Spread Spectrum – Automotive Wide VIN Front-end Reference Design for Digital Cockpit Processing Units
• Technical articles: – High-Density PCB Layout of DC/DC Converters – Synchronous Buck Controller Solutions Support Wide VIN Performance and Flexibility – How to Use Slew Rate for EMI Control

10.2 Documentation Support

10.2.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage Layout application brief
• Application notes: – Texas Instruments, AN-2162 Simple Success with Conducted EMI from DC-DC Converters – Texas Instruments, Maintaining Output Voltage Regulation During Automotive Cold-Crank with LM5140- Q1 Dual Synchronous Buck Controller
• Texas Instruments, Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics analog design journal
• White papers: – Texas Instruments, An Overview of Conducted EMI Specifications for Power Supplies – Texas Instruments, An Overview of Radiated EMI Specifications for Power Supplies – Texas Instruments, Valuing Wide VIN, Low EMI Synchronous Buck Circuits for Cost-driven, Demanding

Applications

10.2.1.1 PCB Layout Resources

• Application notes: – Texas Instruments, AN-1149 Layout Guidelines for Switching Power Supplies – Texas Instruments, AN-1229 SIMPLE SWITCHER® PCB Layout Guidelines – Texas Instruments, Low Radiated EMI Layout Made SIMPLE with LM4360x and LM4600x
• Texas Instruments, Constructing Your Power Supply – Layout Considerations seminar

10.2.1.2 Thermal Design Resources

• Application notes: – Texas Instruments, AN-2020 Thermal Design by Insight, Not Hindsight – Texas Instruments, AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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– Texas Instruments, Semiconductor and IC Package Thermal Metrics – Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602 – Texas Instruments, PowerPAD™ Thermally Enhanced Package – Texas Instruments, Using New Thermal Metrics

• Texas Instruments, PowerPAD™ Made Easy application brief

10.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.5 Trademarks

PowerPAD™ and TI E2E™ are trademarks of Texas Instruments. SIMPLE SWITCHER® is a registered trademark of Texas Instruments. All trademarks are the property of their respective owners.

10.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. DATE REVISION NOTES April 2026 * Initial Release

12 Mechanical, Packaging, and Orderable Information

The following pages show mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

12.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant LM5192-Q1 SNVSD17 – APRIL 2026 www.ti.com

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TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PLM5192QRGYR QFN RGY 19 3000 367.0 367.0 35.0 www.ti.com LM5192-Q1 SNVSD17 – APRIL 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: LM5192-Q1 ADVANCE INFORMATION

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www.ti.com 7-Apr-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) PLM5192QRGYRQ1 Active Preproduction VQFN (RGY) | 19 3000 | LARGE T&R - Call TI Call TI - (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRGY 19 PLASTIC QUAD FLATPACK - NO LEAD3.5 x 4.5, 0.5 mm pitch 4230073/A

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