PLM5190QRGYR.A

LM5190-Q1 TI | Alldatasheet

Document overview

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Technical content

LM5190-Q1 80V, Automotive, Synchronous Buck Controller With Constant-Current and Constant-Voltage Regulation

1 Features

• AEC-Q100 qualified for automotive applications: – Device temperature grade 1: –40°C to +125°C ambient operating temperature
• Functional Safety-Capable – Documentation available to aid functional safety system design
• Wide input voltage operating range: 5V to 80V
• Adjustable output voltage from 0.8V to 79V, or fixed output of 5V or 12V
• Constant-Current Constant-Voltage (CC-CV) operation – Current regulation accuracy: ±3% – Voltage regulation accuracy: ±1%
• Current monitoring and constant current features – Analog voltage proportional to output current (IMON) – Programmable average output current limit (ILIM) – Dynamic average output current limit (ISET)
• 2.3µA typical shutdown mode IQ and 15µA typical sleep mode IQ
• Standard level MOSFET gate drivers
• Power-good status indicator (PGOOD)
• Programmable switching frequency from 100kHz to 2.2MHz
• Optional external clock synchronization
• Selectable Dual Random Spread Spectrum (DRSS) feature for enhanced EMI performance across low and high-frequency bands
• Internal slope compensation and bootstrap diode
• Dual-input VCC regulator to reduce power dissipation (BIAS)
• Create a custom design using the LM5190-Q1 with the WEBENCH® Power Designer

2 Applications

• Super capacitor energy backup
• USB power delivery
• E-bikes
• Automotive audio amplifiers
• Automotive driver assistance systems
• Automotive body electronics

3 Description

The LM5190-Q1 is an 80V, ultra-low I Q, synchronous buck DC/DC controller with Constant-Current Constant-Voltage (CC-CV) regulation. The controller uses a peak current-mode control architecture for easy loop compensation, fast transient response, and excellent load and line regulation. The integrated CC-CV operation features a high accuracy for the regulation of both voltage (±1%) and current (±3%) . The CC-CV operation also provides seamless transition between constant-current and constant- voltage mode. The CC-CV operation effectively reduces the Bill Of Materials (BOM) count and cost for applications that require average output current control. The output current limit is programmable and can be dynamically changed. The LM5190-Q1 has an output current monitor.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) LM5190-Q1 RGY (VQFN, 19) 3.5mm × 4.5mm (1) For more information, see Section 10. (2) The package size (length × width) is a nominal value and includes pins, where applicable. VIN EN FPWM/SYNC IMON/ILIM ISET RT CBOOT HO SW LO ISNS+ VCC VOUT FB AGND COMP PGND VOUT VIN BIAS PGOOD CVIN CIMON RENT RENB QH QL LOUT RS CCBOOT COUT RFBT RFBB CVCC RIMON RCOMP CCOMP RRT Typical Application Schematic N o r m a l i z e d I O U T ( A / A ) VOUT(V) 1 0 1 2 1 4 Constant-Current Constant-Voltage Operation In Steady State LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

The LM5190-Q1 has a unique EMI (Electromagnetic Interference) reduction feature known as Dual Random Spread Spectrum (DRSS) . Combining low-frequency triangular and high-frequency random modulations mitigates EMI disturbances across lower and higher frequency bands, respectively. This hybrid technique aligns with the multiple resolution bandwidth (RBW) settings specified in industry-standard EMC tests. Additional features of the LM5190-Q1 include 150°C maximum junction temperature operation, user-selectable diode emulation for lower current consumption at light-load conditions, open-drain power-good flag for fault reporting and output monitoring, precision enable input, monotonic start-up into prebiased load, integrated dual- input VCC bias supply regulator, internal 2.75ms soft-start time, and thermal shutdown protection with automatic recovery. The LM5190-Q1 controller comes in a 3.5mm × 4.5mm, thermally enhanced, 19-pin VQFN package with wettable flank pins to facilitate optical inspection during manufacturing. LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

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10 Mechanical, Packaging, and Orderable

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4 Pin Configuration and Functions

(EP) ISET VOUT IMON/ILIM BIAS Connect the exposed pad to AGND and PGND on the PCB. Figure 4-1. 19-Pin VQFN RGY Package With Wettable Flanks (Top View) Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME

1 ISET I/O Dynamic current setting pin for the constant-current operation

2 RT I

Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 100kHz and 2.2MHz and DRSS disabled. A resistor from RT to VCC sets the oscillator frequency between 100kHz and 2.2MHz and DRSS enabled. 3 COMP O Transconductance error amplifier output. Connect the compensation network from COMP to AGND.

4 FB I

Connect FB to VCC during initial power on to set the output voltage to pre-programmed fixed 12V. Connect FB to AGND during initial power on to set the output voltage to pre-programmed fixed 5V. Alternatively, install a resistor divider from VOUT to AGND to set the output voltage setpoint between 0.8V and 79V. The FB regulation voltage is 0.8V. 5 AGND G Analog ground connection. Ground return for the internal voltage reference and analog circuits.

6 IMON/ILIM O Current monitor and current limit programming pin

7 VCC P VCC bias supply pin. Connect a ceramic capacitor between VCC and PGND. 8 PGND G Power ground connection pin for low-side MOSFET gate driver. 9 LO P Low-side power MOSFET gate driver output. 10 VIN P Supply voltage input source for the VCC regulator. 11 HO P High-side power MOSFET gate driver output.

12 SW P

Switching node of the buck regulator and high-side gate driver return. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET, and the drain terminal of the low-side MOSFET. 13 CBOOT P High-side driver supply for bootstrap gate drive. 14 BIAS P Optional supply voltage input source for VCC regulator. This input takes over if VBIAS > 9V (typical). 15 PGOOD O Power-good pin. An open-collector output that goes low if VOUT is outside the specified regulation window. LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

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Table 4-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NO. NAME

16 FPWM/SYNC I

Connect FPWM/SYNC to VCC to enable forced PWM (FPWM) mode with continuous conduction at light loads. Connect FPWM/SYNC to AGND to operate the LM5190-Q1 in diode emulation mode. FPWM/SYNC can also be used as a synchronization input to synchronize the internal oscillator to an external clock signal. 17 EN I An active-high precision input with rising threshold of 1V and hysteresis voltage of 100mV. If the EN voltage is less than 0.55V, the LM5190-Q1 is in shutdown mode. 18 ISNS+ I Current sense amplifier input. Connect this pin to the inductor side of the external current sense resistor using a low-current Kelvin connection. 19 VOUT I Output voltage sense and the current sense amplifier input. Connect VOUT to the output side of the current sense resistor. (1) P = Power, G = Ground, I = Input, O = Output

4.1 Wettable Flanks

100% automated visual inspection (AVI) post-assembly is typically required to meet reliability and robustness standards. Standard quad-flat no-lead (QFN) packages do not have solderable or exposed pins and terminals that are easily viewed. Visually determining whether or not the package is successfully soldered onto the printed-circuit board (PCB) is difficult. The wettable-flank process was developed to resolve the issue of side- lead wetting of leadless packaging. The LM5190-Q1 is assembled using a custom 19-pin VQFN package with wettable flanks to provide a visual indicator of solderability, which reduces the inspection time and manufacturing costs. www.ti.com LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LM5190-Q1

5 Specifications

5.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of –40℃ to 150℃ (unless otherwise noted). (1) MIN MAX UNIT Input voltage VIN to AGND –0.3 85 V Input voltage SW to AGND –0.3 85 V Input voltage SW to AGND, transient < 20ns –5 V Input voltage CBOOT to SW –0.3 10 V Input voltage CBOOT to AGND –0.3 93 V Input voltage EN to AGND –0.3 85 V Input voltage BIAS to AGND –0.3 30 V Input voltage VCC, FB, PGOOD, FPWM/SYNC, RT to AGND –0.3 8 V Input voltage ISET, IMON/ILIM to AGND –0.3 5.5 V Input voltage VOUT, ISNS+ to AGND –0.3 85 V Input voltage VOUT to ISNS+ –0.3 0.3 V Output voltage HO to SW, transient < 20ns –5 V Output voltage LO to PGND, transient < 20ns –1.5 V Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –55 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002 (1) ±2000 V Charged device model (CDM), per AEC Q100-011 Corner pins (1, 2, 11, 12, 13, 14, 23, and 24) ±750 Other pins ±500 (1) AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

5.3 Recommended Operating Conditions

Over the operating junction temperature range of –40℃ to 150℃ (unless otherwise noted). (1) MIN NOM MAX UNIT VIN Input supply voltage range 5 80 V VOUT Output voltage range 0.8 79 V Pin Voltage PGOOD, FB, FPWM/SYNC, RT 0 8 V Pin Voltage COMP, ISET, IMON 0 5.25 V Pin Voltage EN 0 80 V Pin Voltage BIAS 0 28 V Pin Voltage VOUT, ISNS+ 0 79 V TJ Operating junction temperature –40 150 °C (1) Recommended operating conditions are conditions under which the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics. LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

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5.4 Thermal Information

THERMAL METRIC(1) LM5190-Q1 UNITRGY (VQFN)

19 PINS

RθJA Junction-to-ambient thermal resistance 44.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 40.1 °C/W RθJB Junction-to-board thermal resistance 21.1 °C/W ψJT Junction-to-top characterization parameter 0.9 °C/W ψJB Junction-to-board characterization parameter 21.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.0 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.

5.5 Electrical Characteristics

TJ = –40°C to 150°C. Typical values are at TJ = 25°C, VIN = 12V, and EN tied to VIN (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY (VIN) IQ-SD VIN shutdown current VEN = 0V 2.3 4.5 µA IQ-SD-48V VIN shutdown current VEN = 0V, VIN = 48V 4.5 µA IQ-SBY VIN standby current Non-switching, 0.5V ≤ VEN ≤ 1V 100 µA IQ-SBY-48V VIN standby current Non-switching, 0.5V ≤ VEN ≤ 1V, VIN=48V 120 µA ISLEEP1 Sleep current, 5V VIN = 24V, VVOUT = VBIAS = 5V, in sleep mode, VFPWM/SYNC = AGND, ISET floating 15 30 µA ISLEEP1-48V Sleep current, 5V, VIN = 48V VIN = 48V, VVOUT = VBIAS = 5V, in sleep mode, VFPWM/SYNC = AGND, ISET floating 12 µA ISLEEP2 Sleep current, 12V VIN = 24V, VVOUT = VBIAS = 12V, in sleep mode, VFPWM/SYNC = AGND, ISET floating 20 35 µA ISLEEP2-48V Sleep current, 12V, VIN = 48V VIN = 48V, VVOUT = VBIAS = 12V, in sleep mode, VFPWM/SYNC = AGND, ISET floating 12 µA ENABLE (EN) VSBY-TH Shutdown-to-standby threshold VEN rising 0.55 V VEN-TH Enable voltage rising threshold VEN rising, enable switching 0.95 1.0 1.05 V VEN-HYS Enable hysteresis voltage 100 mV INTERNAL LDO (VCC) VVCC-REG VCC regulation voltage IVCC = 0mA to 110mA 7.125 7.5 7.875 V VVCC-UVLO VCC UVLO rising threshold 4.65 4.8 4.95 V VVCC-HYS VCC UVLO hysteresis 425 mV IVCC-LIM Internal LDO short-circuit current limit 220 mA EXTERNAL BIAS (BIAS) VBIAS-TH VIN to VBIAS switchover rising threshold 8.55 9 9.45 V VBIAS-HYS VIN to VBIAS switchover hysteresis 400 mV REFERENCE VOLTAGE VREF-V Regulated FB voltage VIMON = 0V 792 800 808 mV VREF-I Current loop reference voltage VFB = 0V 0.99 1 1.01 V OUTPUT VOLTAGE (VOUT) VOUT-5V 5V output voltage setpoint FB tied to AGND 4.95 5.0 5.05 V VOUT-12V 12V output voltage setpoint FB tied to VCC, VIN = 24V 11.88 12 12.12 V ERROR AMPLIFIER (COMP) gm-VEA Voltage loop EA transconductance ΔVFB = 100mV 1000 µS gm-IEA Current loop EA transconductance ΔVIMON = 100mV 1000 µS IFB Error amplifier input bias current 75 nA www.ti.com LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LM5190-Q1

5.5 Electrical Characteristics (continued)

TJ = –40°C to 150°C. Typical values are at TJ = 25°C, VIN = 12V, and EN tied to VIN (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ICOMP-SRC EA source current VCOMP = 1V 120 µA ICOMP-SINK EA sink current VCOMP = 1V 120 µA OUTPUT CURRENT MONITOR (IMON/ILIM) gm-IMON Monitor amplifier gain from VCS VCS = 40mV 1.94 2 2.06 µA/mV IOFFSET Monitor amplifier offset current VCS = 0mV 22.5 25 27.5 µA CURRENT SETTING (ISET) IISET ISET source current 9 10 11 µA FORCED PWM MODE (FPWM/SYNC) VZC-SW Zero-cross threshold SW-PGND threshold –5.5 mV SWITCHING FREQUENCY VRT RT pin regulation voltage 10kΩ < RRT < 242kΩ 1 V FSW1 Switching frequency 1 VIN = 12V, RRT = 242kΩ to AGND 90 100 110 kHz FSW2 Switching frequency 2 VIN = 12V, RRT = 10kΩ to AGND 2.0 2.2 2.4 MHz VSLOPE Slope compensation ramp amplitude Referenced to ISNS+ to VOUT input 45 mV tON-MIN Minimum on-time 26 50 ns tOFF-MIN Minimum off-time 80 125 ns POWER GOOD (PGOOD) VPG-UV Power-Good UV trip level Falling with respect to the regulated voltage 90% 92% 94% VPG-OV Power-Good OV trip level Rising with respect to the regulated voltage 108% 110% 112% VPG-UV-HYST Power-Good UV hysteresis 3.1% VPG-OV-HYST Power-Good OV hysteresis 3.1% VPG-OL PG voltage Open collector, IPG = 4mA 0.8 V OVERVOLTAGE PROTECTION VOVTH-RISING Overvoltage threshold Rising with respect to regulated voltage 108% 110% 112% VOVTH-HYST Overvoltage threshold hysteresis 3.1% STARTUP (Soft Start) tSS-INT Internal fixed soft-start time 1.9 2.75 3.8 ms BOOT CIRCUIT VBOOT-DROP Internal diode forward drop ICBOOT = 20mA, VCC to CBOOT 0.8 1 V IBOOT CBOOT to SW quiescent current, not switching VEN = 5V, VCBOOT-SW = 7.5V 25 µA VBOOT-SW-UV-F CBOOT to SW UVLO falling threshold VCBOOT-SW falling 2.75 3.1 3.75 V VBOOT-SW-UV-HYS CBOOT to SW UVLO hysteresis 0.24 V HIGH-SIDE GATE DRIVER (HO) VHO-HIGH HO high-state output voltage IHO = –100mA, VHO-HIGH = VCBOOT – VHO 300 mV VHO-LOW HO low-state output voltage IHO = 100mA 75 mV tHO-RISE HO rise time (10% to 90%) CLOAD = 2.7nF 20 ns tHO-FALL HO fall time (90% to 10%) CLOAD = 2.7nF 8 ns LOW-SIDE GATE DRIVER (LO) VLO-HIGH LO high-state output voltage ILO = –100mA 300 mV VLO-LOW LO low-state output voltage ILO = 100mA 75 mV tLO-RISE LO rise time (10% to 90%) CLOAD = 2.7nF 20 ns tLO-FALL LO fall time (90% to 10%) CLOAD = 2.7nF 8 ns ADAPTIVE DEADTIME CONTROL tDEAD1 HO off to LO on deadtime (1) 21 ns tDEAD2 LO off to HO on deadtime (1) 21 ns OVERCURRENT PROTECTION VCS-TH Current limit threshold Measured from ISNS+ to VOUT 54 60 68 mV LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

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TJ = –40°C to 150°C. Typical values are at TJ = 25°C, VIN = 12V, and EN tied to VIN (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCS-TH-MIN Minimum peak current limit threshold Measured from ISNS+ to VOUT 12 mV ACS CS amplifier gain 9.5 10 10.6 V/V VCS-NEG CS negative voltage threshold –30 mV THERMAL SHUTDOWN TJ-SD Thermal shutdown threshold (1) Temperature rising 175 °C TJ-HYS Thermal shutdown hysteresis (1) 15 °C (1) Specified by design. Not production tested. www.ti.com LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LM5190-Q1

5.6 Typical Characteristics

VIN = 12V, unless otherwise specified J u n c t i o n T e m p e r a t u r e (  C ) Shutdown Current (A) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 VEN = 0V Figure 5-1. Shutdown Current vs Temperature J u n c t i o n T e m p e r a t u r e (  C ) Sleep Current (A) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 1 2 1 6 2 0 VIN = 24V VVOUT = 5V Figure 5-2. Sleep1 Current vs Temperature J u n c t i o n T e m p e r a t u r e (  C ) Sleep Current (A) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 1 2 1 6 2 0 VIN = 24V VVOUT = 12V Figure 5-3. Sleep2 Current vs Temperature J u n c t i o n T e m p e r a t u r e (  C ) Output Voltage (V) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 4 . 9 5 4 . 9 7 5 5 . 0 2 5 5 . 0 5 Figure 5-4. Fixed 5V Output Voltage vs Temperature J u n c t i o n T e m p e r a t u r e (  C ) Output Voltage (V) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 1 1 . 8 8 1 1 . 9 4 1 2 1 2 . 0 6 1 2 . 1 2 VIN = 24V Figure 5-5. Fixed 12V Output Voltage vs Temperature J u n c t i o n T e m p e r a t u r e (  C ) Feedback Voltage (mV) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 7 8 8 7 9 2 7 9 6 8 0 0 8 0 4 8 0 8 8 1 2 Figure 5-6. Feedback Voltage vs Temperature LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

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5.6 Typical Characteristics (continued)

VIN = 12V, unless otherwise specified J u n c t i o n T e m p e r a t u r e (  C ) PGOOD OV Threshold (%) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 1 0 4 1 0 5 1 0 6 1 0 7 1 0 8 1 0 9 1 1 0 1 1 1 1 1 2 R i s i n g F a l l i n g Figure 5-7. PG OV Thresholds vs Temperature J u n c t i o n T e m p e r a t u r e (  C ) PGOOD UV Threshold (%) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 F a l l i n g R i s i n g Figure 5-8. PG UV Thresholds vs Temperature J u n c t i o n T e m p e r a t u r e (  C ) VCC Voltage (V) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 7 . 2 7 . 3 7 . 4 7 . 5 7 . 6 7 . 7 7 . 8 I V C C = 0 m A I V C C = 1 1 0 m A Figure 5-9. VCC Regulation Voltage vs Temperature J u n c t i o n T e m p e r a t u r e (  C ) BIAS Switchover Threshold (V) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 8 . 1 8 . 3 8 . 5 8 . 7 8 . 9 9 . 1 9 . 3 9 . 5 R i s i n g F a l l i n g Figure 5-10. BIAS Switchover Thresholds vs Temperature J u n c t i o n T e m p e r a t u r e (  C ) CS Threshold Voltage (mV) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 5 0 5 5 6 0 6 5 7 0 Figure 5-11. Current Sense (CS) Threshold vs Temperature J u n c t i o n T e m p e r a t u r e (  C ) CS Amplifier Gain (V/V) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 9 . 5 1 0 1 0 . 5 1 1 Figure 5-12. Current Sense (CS) Amplifier Gain vs Temperature www.ti.com LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LM5190-Q1

VIN = 12V, unless otherwise specified J u n c t i o n T e m p e r a t u r e (  C ) Minimum On Time (ns) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 1 0 2 0 3 0 4 0 5 0 Figure 5-13. Minimum On Time (HO) vs Temperature J u n c t i o n T e m p e r a t u r e (  C ) Internal Soft-Start Time (ms) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 5 Figure 5-14. Soft-Start Time vs Temperature J u n c t i o n T e m p e r a t u r e (  C ) Oscillator Frequency (MHz) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 1 . 9 2 . 1 2 . 2 2 . 3 2 . 4 2 . 5 RRT = 10kΩ Figure 5-15. Switching Frequency vs Temperature J u n c t i o n T e m p e r a t u r e (  C ) Monitor Amplifier Gain (A/mV) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 1 . 9 1 . 9 5 2 . 0 5 2 . 1 Figure 5-16. Monitor Amplifier Gain vs Temperature J u n c t i o n T e m p e r a t u r e (  C ) Monitor Offset Current (A) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 2 2 2 3 2 4 2 5 2 6 2 7 2 8 Figure 5-17. Monitor Offset Current vs Temperature V I M O N ( V ) VOUT(V) 1 0 1 2 1 4 VIN = 48V Figure 5-18. Constant-Current Constant-Voltage Operation During a Charing Transient LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

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6 Detailed Description

6.1 Overview

The LM5190-Q1 is a switching DC/DC controller that features all of the functions necessary to implement a high-efficiency constant-current constant-voltage synchronous buck regulator operating over a wide input voltage range from 5V to 80V. The LM5190-Q1 is configured to provide a fixed 5V or 12V output, or an adjustable output from 0.8V to 79V. This easy-to-use controller integrates high-side and low-side MOSFET gate drivers capable of sourcing and sinking peak currents of 1.5A and 2.5A, respectively. Adaptive dead-time control is designed to minimize body diode conduction during switching transitions. The current-mode control architecture using a shunt resistor current sensing provides inherent line feedforward, cycle-by-cycle peak current limiting, and easy loop compensation. Current-mode control also supports a wide duty cycle range for high input voltage and low-dropout applications as well as when application require a high step-down conversion ratio (for example, 10-to-1). The oscillator frequency is user-programmable between 100kHz to 2.2MHz, and the frequency can be synchronized as high as 2.5MHz by applying an external clock to the FPWM/SYNC pin. An external bias supply can be connected to BIAS to maximize efficiency in high input voltage applications. A user-selectable diode emulation feature enables discontinuous conduction mode (DCM) operation to further improve efficiency and reduce power dissipation during light-load conditions. Fault protection features include current limiting, hiccup mode over-load protection, thermal shutdown, UVLO, and remote shutdown capability. The LM5190-Q1 incorporates features to simplify the compliance with various EMI standards, for example CISPR 25 Class 5 automotive EMI requirements. DRSS techniques reduce the peak harmonic EMI signature. The LM5190-Q1 is provided in a custom 19-pin VQFN package with a wettable flank pinout and an exposed pad to aid in thermal dissipation. www.ti.com LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LM5190-Q1

6.2 Functional Block Diagram

– BOOT UVLO PG DELAY 25µs Q Q R S CBOOT FPWM/SYNC RT HO SW LO PGND VCC PG FB VOUT ISNS+ EN AGND VCC BIAS VIN FPWM/PFM VCC SOFT-START PGOV PGUV 0.736V DRIVER DRIVER DRSS ENABLE GAIN = 10 GATE LOGIC ADAPTIVE DEADTIME CLK VEA gm VREFV 0.880V FPWM/PFM PWM CLK 60mV CURRENT LIMIT ILIM SLOPE COMP RAMP RT AMP and CONFG DECODER DUAL RANDOM SPREAD SPECTURM (DRSS) DUAL-INPUT VCC REGULATOR FB DECODER INTERNAL FB GAIN = 1 IMIN Selector IEA gm COMP VREFI ISET IMON/ILIM COMP gm_IMON INTERNAL FB VCC UVLO VCC_UV PWM COMPARATOR 0.5V EN_VCC ENABLE 10uA SS OVP CLK 25uA LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

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6.3 Feature Description

6.3.1 Input Voltage Range (VIN)

The LM5190-Q1 operational input voltage range is from 5V to 80V. The device is intended for step-down conversions from 12V, 24V, and 48V supply rails. The LM5190-Q1 uses an internal LDO to provide a 7.5V VCC bias rail for the gate drive and control circuits (assuming the input voltage is higher than 7.5V with additional voltage margin necessary for the subregulator dropout specification). In high input voltage applications, take extra care to make sure that the VIN and SW pins do not exceed the absolute maximum voltage rating of 85V during line or load transient events. Voltage excursions that exceed the applicable voltage specifications can damage the device.

6.3.2 High-Voltage Bias Supply Regulator (VCC, BIAS)

The LM5190-Q1 contains an internal high-voltage VCC bias regulator that provides the bias supply for the PWM controller and the gate drivers for the external MOSFETs. The VCC voltage is regulated at 7.5V to support the standard-level MOSFETs as well as the logic-level MOSFETs. The input voltage pin (VIN) can be connected directly to an input voltage source up to 80V. However, when the input voltage is below the VCC setpoint level, the VCC voltage tracks VIN minus a small voltage drop. At power up, the controller sources current into the capacitor connected at the VCC pin. When the VCC voltage exceeds 4.8V and the EN pin is connected to a voltage greater than 1V, the soft-start sequence begins. The output remains active unless the VCC voltage falls below the VCC UVLO falling threshold of 4.375V (typical) or EN is switched to a low state. Connect a ceramic capacitor from VCC to PGND. The recommended range of the VCC capacitor is from 2.2µF to 10µF. The VCC regulator is a dual-input regulator which uses BIAS pin as the other input in addition to the VIN pin. A lower voltage supply such as the buck output (VOUT) or other applicable system rails can be tied to BIAS to reduce the power dissipation of the internal VCC regulator. The VCC regulator switches over to use BIAS voltage as the input when rising across 9V (typical). The switchover voltage hysteresis is 400mV. When using BIAS as the supply, VIN voltage must be greater than VCC voltage during all conditions to avoid damage to the controller. Tie BIAS to PGND if unused. The operational maximum voltage of BIAS is 28V.

6.3.3 Precision Enable (EN)

The EN pin can be connected to a voltage as high as 80V. The LM5190-Q1 has a precision enable. When the EN voltage is greater than 1V, controller switching is enabled. If the EN pin is pulled below 0.55V, the LM5190-Q1 is in shutdown with an I Q of 2.3μA (typical) current consumption from V IN. When the enable voltage is between 0.55V and 1V, the LM5190-Q1 is in standby mode with the VCC regulator active but the controller is not switching. In standby mode, the non-switching input quiescent current is 100 μA typical. The LM5190-Q1 is enabled with a voltage greater than 1.0V. Many applications benefit from using a resistor divider R ENT and RENB to establish a precision UVLO level from VSUPPLY (supply voltage of power stage tied to the VIN pin). TI does not recommend leaving the EN pin floating.

6.3.4 Power-Good Monitor (PGOOD)

The LM5190-Q1 includes an output voltage monitoring signal for V OUT to simplify sequencing and supervision. The power-good signal is used for start-up sequencing of downstream converters, fault protection, and output monitoring. The power-good output (PGOOD) switches to a high impedance open-drain state when the output voltage is in regulation. The PGOOD switches low when the output voltage drops below the lower power-good threshold (92% typical) or rises above the upper power-good threshold (110% typical). If the upper PG threshold is exeeded, the high-side switch is turned off immediately and the low-side switch is turn on to prevent overvoltage and discharge the output. A 25µs deglitch filter prevents false tripping of the power-good signal during transients. TI recommends a pullup resistor of 100kΩ (typical) from PGOOD to the relevant logic rail. PGOOD is asserted low during soft start and when the buck regulator is disabled.

6.3.5 Switching Frequency (RT)

Program the LM5190-Q1 oscillator with a resistor from RT to AGND or VCC to set an oscillator frequency from 100kHz and 2.2MHz. If the resistor is connected between RT and VCC during initial power on, the dual random www.ti.com LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LM5190-Q1

spread spectrum (DRSS) is on. If the resistor is connected between RT and AGND during initial power on, the DRSS is off. See more details about DRSS in Section 6.3.7. Calculate the RT resistance for a given switching frequency using Equation 1. When DRSS is on, use Equation 2 to calculate RT resistance based on the average switching frequency. R RT kΩ = 10 6 f s w kHz − 59 41 (1) R RT kΩ = 10 6 f s w kHz − 233.7 29.3 (2)

6.3.6 Low Dropout Mode

For extended minimum input voltage, LM5190-Q1 enters the low dropout (LDO) mode if the required duty cycle is greater than the maximum duty cycle that is limited by the minimum off time. During the LDO mode, the LM5190-Q1 extends the on-time pulse until the PWM latch is reset by the current sense ramp exceeding the controller compensation voltage. The LM5190-Q1 skips up to 15 tOFF cycles to allow the controller to extend the duty cycle. Figure 6-1 shows the normal PWM mode to LDO mode transition. VOUT HO-SW Low Drop-out ModePWM Mode ≅99% Duty Cycle VIN one tOFF skip two tOFF skip three tOFF skip up to fifteen tOFF skip up to fifteen tOFF skip ... Figure 6-1. PWM to LDO Mode Transition Equation 3 gives the approximate input voltage level at which this event occurs. V I N MI N = V OU T × t S W t S W − t O FF MI N (3) where

• tSW is the extended switching period.
• tOFF(MIN) is the minimum off time of 80ns (typical).

6.3.7 Dual Random Spread Spectrum (DRSS)

The LM5190-Q1 provides a digital spread spectrum, which reduces the EMI of the power supply over a wide frequency range. DRSS combines a low-frequency triangular modulation profile with a high frequency cycle-by-cycle random modulation profile. The low-frequency triangular modulation improves performance in lower radio-frequency bands, while the high-frequency random modulation improves performance in higher radio frequency bands. Spread spectrum works by converting a narrowband signal into a wideband signal that spreads the energy over multiple frequencies. Because industry standards require different EMI receiver resolution bandwidth (RBW) LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

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settings for different frequency bands, the RBW has an impact on the spread spectrum performance. For example, the CISPR 25 spectrum analyzer RBW in the frequency band from 150kHz to 30MHz is 9kHz. For frequencies greater than 30MHz, the RBW is 120kHz . DRSS can simultaneously improve the EMI performance in the low and high RBWs using the low-frequency triangular modulation profile and at high frequency cycle- by-cycle random modulation, respectively. DRSS can reduce conducted emissions up to 15dB μV in the low- frequency band (150kHz to 30MHz) and 5dBμV in the high-frequency band (30MHz to 108MHz). To enable DRSS, connect RT to VCC through a resistor during initial power on. The resistor is still used to set the switching frequency with the same equation in Equation 1. Spread spectrum ON (c) Low-frequency triangular + high- frequency randomized modulations (a) Low-frequency triangular modulation (b) High-frequency randomized modulation Spread spectrum OFF Frequency Low RBW High RBW fs(t) 2¨Is t Figure 6-2. Dual Random Spread Spectrum Implementation

6.3.8 Soft Start

The LM5190-Q1 has an internal 2.75ms (typical) soft-start timer. The soft-start feature allows the regulator to gradually reach the steady-state operating point, thus reducing start-up stresses and surges.

6.3.9 Output Voltage Setpoint (FB)

The LM5190-Q1 regulator output can be independently configured for one of two fixed output voltages without external feedback resistors, or adjusted to a desired voltage using an external resistor divider. Set the output to 5V by connecting FB to AGND during initial power on. Set the output to 12V by connecting FB to VCC during initial power on. See Table 6-1. Table 6-1. Output Regulation Targets FB SELECTION VOUT SETPOINT FB = VCC 12V FB = AGND 5V FB = FB resistors Adjustable The configuration settings are latched and cannot be changed until the LM5190-Q1 is powered down (with the VCC voltage decreasing below the falling UVLO threshold) and then powered up again (VCC rises above 4.8V typical). Alternatively, the output regulation target can be adjusted during operation by connecting external feedback divider resistors whose parallel resistance is greater than 5.0kΩ (see Equation 4). 5 kΩ < R F BT × R FB B R F B T + R F BB (4) www.ti.com LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LM5190-Q1

The output voltage adjustment range is between 0.8V and 79V. The regulation voltage at FB is 0.8V (V REF-V). Use Equation 5 to calculate the top and bottom feedback resistors, designated as RFBT and RFBB, respectively. R FB T = V OU T V R EF − 1 × R F BB (5) If low-I Q operation is required, take care when selecting the external feedback resistors. The current consumption of the external divider adds to the LM5190-Q1 sleep current (15µA typical). The divider current reflected to VIN is scaled by the ratio of VOUT / VIN.

6.3.10 Minimum Controllable On Time

There are two limitations to the minimum output voltage adjustment range: the LM5190-Q1 voltage reference of 0.8V and the minimum controllable switch-node pulse width, tON(min). tON(min) effectively limits the voltage step-down conversion ratio V OUT / V IN at a given switching frequency. For fixed-frequency PWM operation, the voltage conversion ratio must satisfy Equation 6. V O U T V I N > t O N mi n × f SW (6) where

• tON(min) is 26ns (typical).
• fSW is the switching frequency. If the desired voltage conversion ratio does not meet the above condition, the LM5190-Q1 transitions from fixed switching frequency operation to a pulse-skipping mode to maintain output voltage regulation. For example, if the desired output voltage is 5V with an input voltage of 24V and switching frequency of 2.1MHz, use Equation 7, Equation 8 to check the conversion ratio. 24V > 26ns × 2.1MHz (7) 0.208 > 0.055 (8) For wide V IN applications and low output voltages, an alternative is to reduce the LM5190-Q1 switching frequency to meet the requirement of Equation 6.

6.3.11 Inductor Current Sense (ISNS+, VOUT)

Figure 6-3 illustrates inductor current sensing using a shunt resistor. This configuration continuously monitors the inductor current to provide accurate overcurrent protection across the operating temperature range. For the best current sense accuracy and overcurrent protection, use a low inductance ±1% tolerance shunt resistor between the inductor and the output, with a Kelvin connection to the LM5190-Q1 current sense amplifier. If the peak voltage signal sensed from ISNS+ to VOUT exceeds the current limit threshold of 60mV, the current limit comparator immediately terminates the HO output for cycle-by-cycle peak current limiting. Calculate the shunt resistance using Equation 9. R S = V C S − TH I o ut C L + ∆ I L (9) where

• VCS-TH is current sense threshold of 60mV.
• IOUT(CL) is the overcurrent setpoint that is set higher than the maximum load current to avoid tripping the overcurrent comparator during load transients.
• ΔIL is the peak-to-peak inductor ripple current. LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

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CS gain = 10 Figure 6-3. Shunt Current Sensing Implementation The soft-start voltage is clamped 60mV above FB if the regulator is in an overcurrent condition or if the output is in UV (undervoltage) condition in CC mode operation. Eight overcurrent events must occur before the SS clamp is enabled. This requirement makes sure that SS can be pulled low during brief overcurrent events, preventing output voltage overshoot during recovery.

6.3.12 Voltage Loop Error Amplifier

In the voltage loop, the LM5190-Q1 has a high-gain transconductance amplifier that generates an error current proportional to the difference between the feedback voltage and an internal precision reference (0.8V). The transconductance of the amplifier is 1000µS. The voltage loop error amplifier only takes control when the internal minimum function block IMIN selector selects the current from the voltage loop error amplifier. See Section 6.3.14 for more details regarding the constant-current constant-voltage operation. www.ti.com LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LM5190-Q1

Q Q R S VOUTISNS+ GAIN = 10 VEA gm PWM CLK SLOPE COMP RAMP INTERNAL FB PWM COMPARATOR SS VREFV IMIN SELECTOR IEA gm OUTPUT RCS IL COMP CCOMP RCOMP CHF Figure 6-4. Voltage Loop Functional Block Diagram A type-II compensation network is generally recommended for peak current-mode control.

6.3.13 Current Monitor, Programmable Current Limit, and Current Loop Error Amplifier (IMON/ILIM, ISET)

In the current loop, the LM5190-Q1 has a high-gain transconductance amplifier that generates an error current proportional to the difference between the IMON voltage and an internal precision reference (1V). The transconductance of the amplifier is 1000µS. The current loop error amplifier only takes control when the internal minimum function block IMIN selector selects the current from the current loop error amplifier. See Section 6.3.14 for more details regarding the constant-current constant-voltage operation. LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

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Q Q R S VOUTISNS+ GAIN = 10 PWM CLK SLOPE COMP RAMP COMP PWM COMPARATOR IMIN SELECTOR RCS IL GAIN = 1 VEA gm OUTPUT VREFI gm_IMON ISETIMON RIMON CIMON IEA gm 10 A 25 A CCOMP RCOMP CHF Figure 6-5. Current Loop Functional Block Diagram The RIMON is used to programmed the CC regulation target. The CC regulation target is usually defined to be smaller than the maximum current defined by the cycle-by-cycle peak current limit in Inductor Current Sense (ISNS+, VOUT). Equation 10 selects the RIMON. R I MON = V re f I R C S × g m _ I MON × I C C + I IM ON _ o f f s et (10) where

• VrefI is 1V (typical).
• RCS is the current sensing resistance.
• gm_IMON is the current monitor gain of 2µA/mV.
• ICC is the CC regulation target.
• IIMON_offset is the IMON offset current of 25µA. The C IMON is used to form the RC filter with R IMON and filter out the sensed inductor current ripple to the achieve average current regulation. The CIMON also sets the response of the current loop. With RIMON and CIMON selected, IMON/ILIM multifunctional pin can be used as the current monitor when the regulator is operating in CV loop. The average inductor current can be read from IMON/ILIM voltage by using Equation 11. I AV G = V I MON R I MON − I I MON _ o f f s et R C S × g m _ I MO N (11) www.ti.com LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LM5190-Q1

where VIMON is the voltage on IMON/ILIM pin and I AVG is the average inductor current. The DC offset current is introduced at IMON/ILIM pin to raise the no-load signal above the possible ground noise floor. ISET can be used to dynamically program the CC regulation current. An external voltage forced at ISET can set the CC regulation current by Equation 12. V I S ET = R I MON × I C C s et × R C S × g m I MO N + I I MON _ o f fs et (12) where I CCset is the desired average current to be programmed by ISET. ISET is only functional when ISET voltage is smaller than V refI (1V typical). ISET has an internal current source of 10µA typical so ISET can be used with a capacitor at the pin to achieve the current soft start during CC transient such as super capacitor and battery charging conditions. Discharge this ISET capacitor externally if needed. Due to this internal current source, a resistor connected to ISET and AGND can also determine the voltage on ISET.

6.3.14 Dual Loop Architecture

In Section 6.3.12 and Section 6.3.13, the voltage loop and current loop operation have been discussed respectively. To have a seamless transition between CC and CV operation, a minimum function block called IMIN selector is used for the dual loop architecture. To operate LM5190-Q1 as normal buck in CV, ground IMON pin and leave ISET pin open. VEA gm INTERNAL FB SS VREFV IMIN SELECTOR IEA gm –IMON ISET VREFI COMP CCOMP RCOMP IIEA IVEA MIN(IIEA,IVEA) Figure 6-6. Dual Loop Architecture

6.3.15 PWM Comparator

The PWM comparator compares the sum of the amplified sensed inductor current and the slope compensation ramp with the COMP pin voltage minus a 0.6V internal offset, and terminates the present cycle if the sum of the amplified sensed inductor current and the slope compensation ramp is greater than the COMP pin voltage minus the 0.6V internal offset.

6.3.16 Slope Compensation

The LM5190-Q1 provides internal slope compensation for stable operation with peak current-mode control and a duty cycle greater than 50%. Calculate the buck inductance to provide a slope compensation contribution equal to one times the inductor downslope using Equation 13. L O − I DE AL μH = V OU T V × R CS mΩ 45 × f SW MHz (13)

• A lower inductance value generally increases the peak-to-peak inductor current, which minimizes size and cost, and improves transient response at the cost of reduced light-load efficiency due to higher cores losses and peak currents. LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

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• A higher inductance value generally decreases the peak-to-peak inductor current, reducing switch peak and RMS currents at the cost of requiring larger output capacitors to meet load-transient specifications.

6.3.17 Hiccup Mode Current Limiting

The LM5190-Q1 includes an internal hiccup-mode protection function. After 512 cycles of cycle-by-cycle peak current limiting occurs, the internal soft start is pulled low, the HO and LO driver outputs are disabled, and the 16384 counter is enabled. The 512-cycle counter is reset if four consecutive switching cycles occur without exceeding the current limit threshold. After the counter reaches 16384, the internal soft start is enabled and the output restarts.

6.3.18 High-Side and Low-Side Gate Drivers (HO, LO)

The LM5190-Q1 contains gate drivers and an associated high-side level shifter to drive the external N-channel power MOSFETs. The high-side gate driver works in conjunction with an internal bootstrap diode D BOOT and bootstrap capacitor C BOOT. During the conduction interval of the low-side MOSFET, the SW voltage is approximately 0V and CBOOT charges from VCC through the internal D BOOT. TI recommends a 0.1 μF ceramic capacitor connected with short traces between the CBOOT and SW pins. The HO and LO outputs are controlled with an adaptive dead-time methodology so that both outputs (HO and LO) are never on at the same time, preventing cross conduction. Before the LO driver output is allowed to turn on, the adaptive dead-time logic first disables HO and waits for the HO voltage to drop below 1.5V typical. LO is allowed to turn on after a small delay (HO fall to LO rising delay). Similarly, the HO turn-on is delayed until the LO voltage has dropped below 1.5V. This technique makes sure of adequate dead-time for any size N-channel power MOSFET implementations, including parallel MOSFET configurations. Caution is advised when adding series gate resistors, as this addition can impact the effective dead-time. The selected high-side MOSFET determines the appropriate bootstrap capacitance value C BOOT in accordance with Equation 14. C BOOT = Q G ∆ V C BOOT (14) where

• QG is the total gate charge of the high-side MOSFET at the applicable gate drive voltage.
• ΔVCBOOT is the voltage variation of the high-side MOSFET driver after turn-on. To determine CBOOT, choose ΔVCBOOT such that the available gate drive voltage is not significantly impacted. An acceptable range of ΔVCBOOT is 100mV to 300mV. The bootstrap capacitor must be a low-ESR ceramic capacitor, typically 0.1µF. Select FETs to make sure that the minimum input supply voltage is higher than gate plateau voltage of the FET plus 0.5V so that the FET works in the ohmic region when turned on. When the LM5190-Q1 is configured for a target output voltage smaller than 7.5V, the internal bootstrap UV circuit can source a 25uA current out of the SW pin. In the light load or no load case where the resistance of the feedback divider is not low enough to sink the extra amount of current, some dummy load is required to bleed off the charge on the output capacitors. www.ti.com LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LM5190-Q1

6.4 Device Functional Modes

6.4.1 Sleep Mode

The LM5190-Q1 operates with peak current-mode control such that the compensation voltage is proportional to the peak inductor current. During no-load or light-load conditions, the output capacitor discharges very slowly. As a result, the compensation voltage does not demand the driver output pulses on a cycle-by-cycle basis. When the LM5190-Q1 controller detects 16 missed switching cycles, the controller enters sleep mode and switches to a low I Q state to reduce the current drawn from the input. For the LM5190-Q1 to go into sleep mode, the controller must be programmed for diode emulation (tie FPWM/SYNC to AGND). The typical controller IQ in sleep mode is 15μA with a 12V output.

6.4.2 Forced PWM Mode and Synchronization (FPWM/SYNC)

A synchronous buck regulator implemented with a low-side synchronous MOSFET rather than a diode has the capability to sink negative current from the output during conditions of, light-load, output overvoltage, and prebias start-up conditions. The LM5190-Q1 provides a diode emulation feature that can be enabled to prevent reverse (drain-to-source) current flow in the low-side MOSFET. When configured for diode emulation mode, the low-side MOSFET is switched off when reverse current flow is detected by sensing the SW voltage using a zero-cross comparator. The benefit of this configuration is lower power loss during light-load conditions. The disadvantage of diode emulation mode is slower light-load transient response. The FPWM/SYNC pin configures diode emulation mode and forced PWM mode. To enable diode emulation and thus achieve low-IQ current at light loads, connect FPWM/SYNC to AGND. If FPWM with continuous conduction mode (CCM) operation is desired, tie FPWM/SYNC to VCC. Note that diode emulation is automatically engaged to prevent reverse current flow during a prebias start-up. A gradual change from DCM to CCM operation provides monotonic start-up performance. To synchronize the LM5190-Q1 to an external source, apply a logic-level clock to the FPWM/SYNC pin. The LM5190-Q1 can be synchronized to ±20% of the programmed frequency up to a maximum of 2.5MHz. When the LM5190-Q1 is operating in synchronization mode, LM5190-Q1 operates in FPWM mode. If there is an RT resistor tied to AGND and a synchronization signal, the LM5190-Q1 ignores the RT resistor and synchronizes to the external clock. If there is an RT resistor tied to VCC and a synchronization signal, the synchronization signal is ignored and the LM5190-Q1 operates in RT defined frequency with DRSS. Under low V IN conditions when the minimum off time is reached, the synchronization signal is ignored, allowing the switching frequency to reduce to maintain output voltage regulation.

6.4.3 Thermal Shutdown

The LM5190-Q1 includes an internal junction temperature monitor. If the temperature exceeds 175°C (typical), thermal shutdown occurs. When entering thermal shutdown, the device: 1. Turns off the high-side and low-side MOSFETs. 2. PG/SYNCOUT switches low. 3. Turns off the VCC regulator. 4. Initiates a soft-start sequence when the die temperature decreases by the thermal shutdown hysteresis of 15°C (typical). This protection is a non-latching protection, and, as such, the device cycles into and out of thermal shutdown if the fault persists. LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

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7 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

7.1 Application Information

7.1.1 Power Train Components

A comprehensive understanding of the buck regulator power train components is critical to successfully completing a synchronous buck regulator design. The following sections discuss the output inductor, input and output capacitors, power MOSFETs, and EMI input filter.

7.1.1.1 Buck Inductor

For most applications, choose a buck inductance such that the inductor ripple current, ΔIL, is between 30% to 50% of the maximum DC output current at typical input voltage. Choose the inductance using Equation 15. L O = V OUT ∆ I L × f SW × 1 − V OUT V IN (15) Check the inductor data sheet to make sure that the saturation current of the inductor is above the peak inductor current of a particular design. Ferrite cores have very low core loss and are preferred at high switching frequencies, so design goals can then concentrate on copper loss and preventing saturation. Low inductor core loss is evidenced by reduced no-load input current and higher light-load efficiency. However, ferrite core materials exhibit a hard saturation characteristic and the inductance collapses abruptly when the saturation current is exceeded. This action results in an abrupt increase in inductor ripple current and higher output voltage ripple, not to mention reduced efficiency and compromised reliability. Note that the saturation current of an inductor generally decreases as the core temperature increases.

7.1.1.2 Output Capacitors

The output capacitor combined with the control loop response make sure the output voltage stays within the dynamic transient tolerance specifications. The usual boundaries restricting the output capacitor are driven by finite available PCB area, component size, and cost. The equivalent series resistance (ESR) and equivalent series inductance (ESL) of the output capacitor dominates shaping the load transient response as the load step amplitude and slew rate increase. The output capacitor, COUT, filters the inductor ripple current and provides a reservoir of charge for load transient events. Typically, ceramic capacitors provide low ESR to reduce the output voltage ripple and noise spikes, while tantalum or electrolytic capacitors provide a large bulk capacitance in a relatively compact footprint for transient loading events. Figure 7-1 conceptually illustrates the relevant current waveforms during both load step-down and step-up transitions. As shown, the large-signal slew rate of the inductor current is limited as the inductor current ramps to match the new load-current level following a load transient. This slew-rate limiting exacerbates the deficit of charge in the output capacitor, which must be replenished as fast as possible during and after the load step-up transient. Similarly, during and after a load step-down transient, the slew rate limiting of the inductor current adds to the surplus of charge in the output capacitor that must be depleted as quickly as possible. www.ti.com LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: LM5190-Q1

= - dILOUT dt VLOAD LOUT = -VSUPPLY dILOAD dt tramp = ∆ILOAD Figure 7-1. Load Transient Response Representation Showing COUT Charge Surplus or Deficit For example, in a typical regulator application of 12V input to 3.3V output voltage, the load-off transient represents the worst case in terms of output voltage transient deviation. In that conversion ratio application, the steady-state duty cycle is approximately 28% and the large-signal inductor current slew rate when the duty cycle collapses to zero is approximately –V LOAD / L OUT. Compared to a load-on transient, the inductor current takes much longer to transition to the required level. The surplus of charge in the output capacitor causes the output voltage to overshoot. In fact, to deplete this excess charge from the output capacitor as quickly as possible, the inductor current must ramp below the nominal level following the load step. In this scenario, a large output capacitance can be advantageously employed to absorb the excess charge and minimize the voltage overshoot. To meet the dynamic specification of output voltage overshoot during such a load-off transient (denoted as ΔVOVERSHOOT with step reduction in output current given by ΔILOAD), the output capacitance must be larger than: C O UT ≥ L O U T × ∆ I LOAD 2 V LOAD + ∆ V OVE RSH O OT 2 − V LOAD 2 (16) Based on the static specification of peak-to-peak output voltage ripple denoted by ΔVLOAD, choose an output capacitance that is larger than that given by Equation 17. C O UT ≥ ∆ I LOUT 8 × f SW × ∆ V LOAD 2 − R ES R × ∆ I L O UT 2 (17) The ESR of a capacitor is provided in the manufacturer data sheet, either explicitly as a specification or implicitly in the impedance versus frequency curve. Depending on type, size, and construction, electrolytic capacitors have significant ESR, 5m Ω and above, and relatively large ESL, 5nH to 20nH. PCB traces contribute some parasitic resistance and inductance as well. Ceramic output capacitors have low-ESR and ESL contributions at the switching frequency, and the capacitive impedance component dominates. However, depending on package and voltage rating of the ceramic capacitor, the effective capacitance can drop quite significantly with applied DC voltage and operating temperature. Ignoring the ESR term in Equation 17 gives a quick estimation of the minimum ceramic capacitance necessary to meet the output ripple specification. Use Equation 16 to determine if additional capacitance is necessary to meet the load-off transient overshoot specification. LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

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A composite implementation of ceramic and electrolytic capacitors highlights the rationale for paralleling capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range. While the ceramic provides excellent mid- and high-frequency decoupling characteristics with the low ESR and ESL to minimize the switching frequency output ripple, the electrolytic device with the large bulk capacitance provides low-frequency energy storage to cope with load transient demands.

7.1.1.3 Input Capacitors

Input capacitors are necessary to limit the input ripple voltage to the buck power stage due to switching- frequency AC currents. TI recommends using X7S or X7R dielectric ceramic capacitors to provide low impedance and high RMS current rating over a wide temperature range. To minimize the parasitic inductance in the switching loop, position the input capacitors as close as possible to the drain of the high-side MOSFET and the source of the low-side MOSFET. Equation 18 givues the input capacitor RMS current for a single-channel buck regulator. I CIN, rms = D × I LOAD 2 × 1 − D + ∆ I L O UT 2 12 (18) The highest input capacitor RMS current occurs at D = 0.5, at which point, the RMS current rating of the input capacitors must be greater than half the output current. Ideally, the DC component of input current is provided by the input voltage source and the AC component by the input filter capacitors. Neglecting inductor ripple current, the input capacitors source current of amplitude (I LOAD − ISUPPLY) during the D interval and sinks I SUPPLY during the 1 −D interval. Thus, the input capacitors conduct a square-wave current of peak-to-peak amplitude equal to the output current. The resultant capacitive component of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, Equation 19 gives the peak-to-peak ripple voltage amplitude. ∆ V S U PPLY = I LOAD × D × 1 − D f SW × C IN + I LOAD × R ESR (19) The input capacitance required for a particular load current, based on an input voltage ripple specification of ΔVSUPPLY, is given by Equation 20. C I N ≥ D × 1 − D × I L O AD f SW × ∆ V SUPPLY − I L O AD × R ES R (20) Low-ESR ceramic capacitors can be placed in parallel with higher valued bulk capacitance to provide optimized input filtering for the regulator and damping to mitigate the effects of input parasitic inductance resonating with high-Q ceramics. Select the input bulk capacitor based on the ripple current rating and operating temperature range.

7.1.1.4 Power MOSFETs

The choice of power MOSFETs has significant impact on DC/DC regulator performance. A MOSFET with low on-state resistance, R DS(on), reduces conduction loss, whereas low parasitic capacitances enable faster transition times and reduced switching loss. Normally, the lower the R DS(on) of a MOSFET, the higher the gate charge and output charge (Q G and Q OSS, respectively), and vice versa. As a result, the product of R DS(on) and QG is commonly specified as a MOSFET figure-of-merit. Low thermal resistance of a given package makes sure that the MOSFET power dissipation does not result in excessive MOSFET die temperature. The main parameters affecting power MOSFET selection are as follows:

• RDS(on) at 7.5V.
• Drain-source voltage rating, BVDSS.
• Gate charge parameters at 7.5V.
• Output charge, QOSS, at the relevant input voltage. www.ti.com LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: LM5190-Q1

• Body diode reverse recovery charge, QRR.
• Gate threshold voltage, VGS(th), derived from the Miller plateau evident in the QG versus VGS plot in the MOSFET data sheet. To enhance MOSFET adequately, the miller plateau voltage must be 2V to 3V lower than the gate drive amplitude, especially at the minimum input voltage. The MOSFET-related power losses for one channel are summarized by the equations presented in Table 7-1, where suffixes one and two represent high-side and low-side MOSFET parameters, respectively. While the influence of inductor ripple current is considered, second-order loss modes, such as those related to parasitic inductances and SW node ringing, are not included. Table 7-1. MOSFET Power Losses POWER LOSS MODE HIGH-SIDE MOSFET LOW-SIDE MOSFET MOSFET conduction (2) (3) P cond 1 = D × I LOAD 2 + ∆ I LOUT 2 12 × R DS on 1 (21) P cond 2 = D ′ × I LOAD 2 + ∆ I LOUT 2 12 × R D S on 2 (22) MOSFET switching P sw1 = V SUPPLY × f SW 2 × I LOAD − ∆ I LOUT 2 × t R + I LOAD + ∆ I L O U T 2 × t F (23) Negligible MOSFET gate drive(1) P gat e1 = V CC × f SW × Q G1 (24) P gat e2 = V CC × f SW × Q G2 (25) MOSFET output charge(4) P C oss = f S W × V SUPPLY × Q OSS2 + E o ss1 − E oss 2 (26) Body diode conduction N/A P cond B D = V F × f SW × I L O AD + ∆ I LOUT 2 × t dt 1 + I L O AD − ∆ I L O UT 2 × t dt 2 (27) Body diode reverse recovery(5) P RR = V SUPP LY × f SW × Q RR2 (28) (1) Gate drive loss is apportioned based on the internal gate resistance of the MOSFET, externally added series gate resistance and the relevant driver resistance of the device. (2) MOSFET RDS(on) has a positive temperature coefficient of approximately 4500ppm/°C. The MOSFET junction temperature, TJ, and the rise over ambient temperature is dependent upon the device total power dissipation and the thermal impedance. When operating at or near minimum input voltage, make sure that the MOSFET RDS(on) is rated for the available gate drive voltage. (3) D' = 1–D is the duty cycle complement. (4) MOSFET output capacitances, Coss1 and Coss2, are highly non-linear with voltage. These capacitances are charged losslessly by the inductor current at high-side MOSFET turn-off. During turn-on, however, a current flows from the input to charge the output capacitance of the low-side MOSFET. Eoss1, the energy of Coss1, is dissipated at turn-on, but this dissipation is offset by the stored energy Eoss2 on Coss2. (5) MOSFET body diode reverse recovery charge, QRR, depends on many parameters, particularly forward current, current transition speed, and temperature. The high-side (control) MOSFET carries the inductor current during the PWM on-time (or D interval) and typically incurs most of the switching losses. Choosing a high-side MOSFET that balances conduction and switching loss contributions is imperative. The total power dissipation in the high-side MOSFET is the sum of the losses due to conduction, switching (voltage-current overlap), output charge, and typically two-thirds of the net loss attributed to body diode reverse recovery. The low-side (synchronous) MOSFET carries the inductor current when the high-side MOSFET is off (or 1–D interval). The low-side MOSFET switching loss is negligible as the low-side MOSFET switching loss is switched at zero voltage – current just communicates from the channel to the body diode or vice versa during the LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

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transition dead-times. The device, with the adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such losses scale directly with switching frequency. In high step-down ratio applications, the low-side MOSFET carries the current for a large portion of the switching period. Therefore, to attain high efficiency, optimizing the low-side MOSFET for low R DS(on) is critical. In cases where the conduction loss is too high or the target R DS(on) is lower than available in a single MOSFET, connect two low-side MOSFETs in parallel. The total power dissipation of the low-side MOSFET is the sum of the losses due to channel conduction, body diode conduction, and typically one-third of the net loss attributed to body diode reverse recovery.

7.1.1.5 EMI Filter

Switching regulators exhibit negative input impedance, which is lowest at the minimum input voltage. An underdamped LC filter exhibits a high output impedance at the resonant frequency of the filter. For stability, the filter output impedance must be less than the absolute value of the converter input impedance. Z IN = − V SUPPLY MI N 2 P SUPPLY (29) The passive EMI filter design steps are as follows:

• Calculate the required attenuation of the EMI filter at the switching frequency, where CIN represents the existing capacitance at the input of the switching converter.
• Input filter inductor LF is usually selected between 1μH and 10μH, but can be lower to reduce losses in a high-current design.
• Calculate input filter capacitor CF. VSUPPLY-EMI GND LF CF CD RD VSUPPLY CIN Figure 7-2. Passive π-Stage EMI Filter for Buck Regulator By calculating the first harmonic current from the Fourier series of the input current waveform and multiplying by the input impedance (the impedance is defined by the existing input capacitor CIN), a formula is derived to obtain the required attenuation as shown by Equation 30. At t n = 20log I LOUT PEAK π 2 × f SW × C IN × si n π × D MA X × 1 1 μ V − V MAX (30) where
• VMAX is the allowed dBμV noise level for the applicable conducted EMI specification.
• CIN is the existing input capacitance of the buck regulator.
• DMAX is the maximum duty cycle.
• ILOUT(PEAK) is the peak inductor current. For filter design purposes, the current at the input can be modeled as a square-wave. Determine the passive EMI filter capacitance CF from Equation 31. www.ti.com LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: LM5190-Q1

C F = 1 L F At t n 2 π × f SW (31) Adding an input filter to a switching regulator modifies the control-to-output transfer function. The output impedance of the filter must be sufficiently small so that the input filter does not significantly affect the loop gain of the buck converter. The impedance peaks at the filter resonant frequency. The resonant frequency of the passive filter is given by Equation 32. f res = 1 2 π × L F × C F (32) The purpose of R D is to reduce the peak output impedance of the filter at the resonant frequency. Capacitor C D blocks the DC component of the input voltage to avoid excessive power dissipation in R D. Capacitor C D must have lower impedance than RD at the resonant frequency with a capacitance value greater than that of the input capacitor CIN. This requirement prevents C IN from interfering with the cutoff frequency of the main filter. Added input damping is needed when the output impedance of the filter is high at the resonant frequency (Q of filter formed by LF and CIN is too high). An electrolytic capacitor C D can be used for input damping with a value given by Equation 33. C D ≥ 4 × C IN (33) Use Equation 34 to select the input damping resistor RD. R D = L F C IN (34)

7.1.2 Error Amplifier and Compensation

Figure 7-3 shows a type-ll compensator using a transconductance error amplifier (EA). The dominant pole of the EA open-loop gain is set by the EA output resistance, R O(EA), and effective bandwidth-limiting capacitance, CBW, as shown by Equation 35. G EA s = − g m E A × R O EA 1 + s × R O EA × C B W (35) The EA high-frequency pole is neglected in the above expression. Equation 36 calculates the compensator transfer function from output voltage to COMP node, including the gain contribution from the (internal or external) feedback resistor network. G C O MP s = V COMP s V LOAD s = − V REF V LOAD × g m × R O EA × 1 + s ω Z1 1 + s ω P1 × 1 + s ω P 2 (36) where

• VREF is the feedback voltage reference.
• gm(EA) is the EA gain transconductance of 1mS.
• RO(EA) is the error amplifier output impedance of 70MΩ. ω Z1 = 1 R C O MP × C COM P (37) ω P1 = 1 R O E A × C COMP + C HF + C B W ≅ 1 R O E A × C C O MP (38) LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

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ω P2 = 1 R COMP × C C OM P C H F + C B W ≅ 1 R C O MP × C HF (39) The EA compensation components create a pole close to the origin, a zero, and a high-frequency pole. Typically, RCOMP << RO(EA) and CCOMP >> CBW and CHF, so the approximations are valid. Error Amplifier Model VREF COMPFB CHFCBW RO(EA) RFBT VLOAD gm RFBB CCOMP RCOMP AGND Figure 7-3. Error Amplifier and Compensation Network www.ti.com LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: LM5190-Q1

7.2 Typical Applications

7.2.1 High Efficiency 400kHz CC-CV Regulator

Figure 7-4 shows the typical schematic diagram of a CC-CV buck regulator. In this example, the CV regulation target is 12V and the CC regulation target is 8A. Full-load efficiency is 95% at 48V input. The switching frequency is set at 400kHz by resistor R RT. The 12V output is connected to BIAS to reduce IC bias power dissipation and improve efficiency. CCBOOT RRT RENT RENB FPWM = VCC : FPWM mode FPWM = AGND : Diode emulation / PFM / Pulse skipping mode FPWM = fSYNC : Clock synchronization in FPWM FB = Resistor divider > 5 k : Adjustible VOUT FB = VCC : Fixed 12.0V FB = AGND : Fixed 5.0V LO HO AGND CBOOT SW VIN LOUT RFBT COUTB RFBB VLOAD CFF RLOAD RFF PGND ISNS(+) VOUT BIAS FB RESR COUTHF RS COMPIMON/ILIM ISET VCC RT FPWM/SYNC EN PGOOD To MCU VDD RT resistor to AGND : Fixed frequency RT resistor to VCC : Spread Spectrum / DRSS From ADC To MCU VSUPPLY VCC / AGND / fSYNC To RFB / VCC / AGND RPGOOD CISET RISET RIMON CIMON RIMONHF RCOMP CHF CVCC QH QL RISETD To MCU CCOMP CVIN AGND / VCC CIN BIAS 28V Figure 7-4. Typical CC-CV Buck Regulator Circuit Note Depending on the source impedance of the input supply bus, an electrolytic capacitor can be required at the input to make sure of stability, particularly at low input voltage and high output current operating conditions. See Section 7.3 for more details. LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

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7.2.1.1 Design Requirements

Table 7-2 shows the intended input, output, and performance parameters for this design example. Table 7-2. Design Parameters DESIGN PARAMETER VALUE Input operating range 15V, 48V, 72V (minimum, typical, maximum) CV regulation target 12V CC regulation target 8A Switching frequency 400kHz The switching frequency is set at 400KHz by resistor R RT. In terms of control loop performance, the target loop crossover frequency is 28kHz with a phase margin greater than 60°.

7.2.1.2 Detailed Design Procedure

Use the Quick Start Calculator to expedite the process of designing a regulator for a given application based on the device specifications. Download the LM25190-LM5190-DESIGN-CALC Quick Start Calculator for a detailed design procedure. See the LM5190-Q1 CCCV Buck Controller Evaluation Module EVM user's guide for recommended components and typical application curves.

7.2.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5190-Q1 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible designs from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

7.2.1.2.2 Custom Design With Excel Quickstart Tool

Use the Quick Start Calculator to expedite the process of designing of a regulator for a given application. Download the Quickstart Calculator for detailed design procedure.

7.2.1.2.3 Recommended Components

Table 7-3 shows a recommended list of materials for Figure 7-4. Please refer to the LM5190-Q1 CCCV Buck Controller Evaluation Module EVM user’s guide for the complete list of materials. Table 7-3. List of Materials QTY REF DES DESCRIPTION PART NUMBER MFR 1 CIN CAP, AL, 100uF, 100V, +/- 20%, 0.33ohm, SMD EMVY101ATR101MKE0S Chemi-Con

2 CCBOOT, CISET

CAP, CERM, 0.1µF, VAC/100 VDC,+/- 20%, X7R, AEC-Q200 Grade 1, 0603 HMK107B7104MAHT Taiyo Yuden 6 CIN 4.7µF ±10% 100V Ceramic Capacitor X7R 1210 (3225 Metric) CNC6P1X7R2A475K250A E TDK 1 CIMON CAP, CERM, 0.01µF, 100V,+/- 10%, X7R, 0603 885012206114 Wurth Elektronik 1 CVIN CAP, CERM, 0.22µF, 100V,+/- 20%, X7S, AEC-Q200 Grade 1, 0603 HMK107C7224MAHTE Taiyo Yuden www.ti.com LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: LM5190-Q1

Table 7-3. List of Materials (continued) QTY REF DES DESCRIPTION PART NUMBER MFR

4 COUT CAP, CERM, 22µF, 25V,+/- 10%, X7R, 1210 C1210C226K3RAC7800 Kemet

1 CVCC CAP, CERM, 2.2uF, 16V, +/- 20%, X7S, AEC-Q200 Grade 1, 0603 CGA3E1X7S1C225M080A C TDK 1 CCOMP CAP CER 0.012UF 25V C0G/NP0 0603 C0603C123J3GACTU Kemet

1 CHF

CAP, CERM, 47pF, 50V,+/- 5%, C0G/NP0, AEC-Q200 Grade 0, 0603 CGA3E2NP01H470J080A A TDK

1 LOUT

6.8µH Shielded Molded Inductor 14.8A 12.5mOhm Max Nonstandard XGL1060-682MEC Coilcraft

2 QH, QL

N-Channel 80V 13A (Ta), 57A (Tc) 3.7W (Ta), 73W (Tc) Surface Mount 5-DFN (5x6) (8-SOFL) NTMFS6H848NT1G onsemi 1 RIMONHF RES, 0, 5%, 0.1 W, 0603 RC0603JR-070RL Yageo 3 RENT, RPGOOD, RFBT RES, 100 k, 1%, 0.1 W, 0603 RC0603FR-07100KL Yageo 1 RENB RES, 8.87 k, 1%, 0.1 W, 0603 RC0603FR-078K87L Yageo 1 RFBB RES, 7.15 k, 1%, 0.1 W, 0603 RC0603FR-077K15L Yageo 1 RS RES, 0.005, 1%, 2 W, 2512 WIDE FCSL64R005FER Ohmite 1 RRT RES, 54.9 k, 1%, 0.1 W, 0603 RC0603FR-0754K9L Yageo 1 RISETD RES, 4.99 k, 1%, 0.1 W, 0603 RC0603FR-074K99L Yageo 1 RIMON RES, 9.53 k, 1%, 0.1 W, 0603 RC0603FR-079K53L Yageo 1 RCOMP RES, 5.90 k, 1%, 0.1 W, 0603 RC0603FR-075K9L Yageo LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

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7.2.1.3 Application Curves

O u t p u t C u r r e n t [ A ] Efficiency [%] V L O A D = 1 2 V F S W = 4 0 0 k H z F P W M 0 1 2 3 4 5 6 6 0 6 5 7 0 7 5 8 0 8 5 9 0 9 5 1 0 0 V S U P P L Y = 2 4 V V S U P P L Y = 3 6 V V S U P P L Y = 4 8 V V S U P P L Y = 6 0 V Figure 7-5. FPWM Mode Efficiency, Linear Scale O u t p u t C u r r e n t [ A ] Efficiency [%] V L O A D = 1 2 V F S W = 4 0 0 k H z P F M 4 04 0 5 0 6 0 7 0 8 0 9 0 1 0 0 V S U P P L Y = 2 4 V V S U P P L Y = 3 6 V V S U P P L Y = 4 8 V V S U P P L Y = 6 0 V Figure 7-6. PFM Mode Efficiency, Log Scale IMON 500mV/DIV ILOUT 5A/DIV VOUT 5V/DIV EN 1V/DIV Figure 7-7. Start-Up, EN ON, VSUPPLY = 48V, ILOAD = 8A Resistive Load IMON 500mV/DIV ILOUT 5A/DIV VOUT 5V/DIV EN 1V/DIV Figure 7-8. Shutdown, EN OFF, VSUPPLY = 48V, ILOAD = 8A Resistive Load VOUT 100mV/DIV , AC COUPLED ILOUT 5A/DIV Figure 7-9. Output Ripple, , VSUPPLY = 48V, ILOAD = VOUT 1V/DIV ILOUT 2A/DIV Figure 7-10. No Load Operation in PFM Mode, VSUPPLY = 48V, ILOAD = 0A www.ti.com LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: LM5190-Q1

Figure 7-11. Load Transient Response, VSUPPLY = 48V, FPWM, 0A to 4A VOUT 1V/DIV ILOUT 5A/DIV Figure 7-12. Load Transient Response, VSUPPLY = 48V, PFM, 0A to 4A IMON 200mV/DIV ILOUT 5A/DIV VOUT 5V/DIV ISET 200mV/DIV Figure 7-13. ISET Modulation, VSUPPLY = 48V, RLOAD = 1.35Ω Figure 7-14. VSUPPLY = 48V, ILOAD = 8A, TA = 25°C, No Airflow LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

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7.3 Power Supply Recommendations

The device is designed to operate from a wide input supply voltage range . The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended Operating Conditions . In addition, the input supply must be capable of delivering the required input supply current to the fully loaded regulator. Estimate the average input supply current with Equation 40. I SUPPLY = V L O A D × I LO AD V SUPPL Y × Ef f icie n c y (40) If the regulator is connected to an input supply through long wires or PCB traces with a large impedance, take special care to achieve stable performance. The parasitic inductance and resistance of the input cables can have an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients at the regulator input each time the input supply is cycled ON and OFF. The parasitic resistance causes the input supply voltage to dip during a load transient. The best way to solve such issues is to reduce the distance from the input supply to the regulator and use an aluminum or tantalum input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitors helps damp the input resonant circuit and reduce any voltage overshoots. An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as well as some of the effects mentioned above. The AN-2162 Simple Success With Conducted EMI From DCDC Converters application note provides helpful suggestions when designing an input filter for any switching regulator.

7.4 Layout

7.4.1 Layout Guidelines

Proper PCB design and layout is important in a high-current, fast-switching circuit to achieve a robust and reliable design. The high power switching loop of a buck regulator power stage is denoted by loop 1 in the shaded area of Figure 7-15. The topological architecture of a buck regulator means that particularly high di/dt current flows in the components of loop 1, reducing the parasitic inductance of this loop by minimizing the effective loop area becomes mandatory. Also important are the gate drive loops of the high-side and low-side MOSFETs, denoted by 3 and 4, respectively. CBOOT HO SW LO VCC PGND VSUPPLY VLOAD GND VCC Low-side gate driver High-side gate driver CVCC CCBOOT CIN COUT QH QL LOUT High-current loops HS gate-drive loop LS gate-drive loop Figure 7-15. DC/DC Regulator Ground System With Power Stage and Gate Drive Circuit Switching Loops www.ti.com LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: LM5190-Q1

7.4.1.1 Power Stage Layout

• Input capacitors, output capacitors, and MOSFETs are the constituent components of the power stage of a buck regulator and are typically placed on the top side of the PCB. The benefits of convective heat transfer are maximized because of leveraging any system-level airflow. In a two-sided PCB layout, small-signal components are typically placed on the bottom side. Insert at least one inner plane, connected to ground, to shield and isolate the small-signal traces from noisy power traces and lines.
• The DC/DC regulator has several high-current loops. Minimize the area of these loops to suppress generated switching noise and optimize switching performance. – Loop 1: The most important loop area to minimize. The path is from the input capacitor or capacitors through the high- and low-side MOSFETs, and back to the capacitor or capacitors through the ground connection. Connect the input capacitor or capacitors negative terminal close to the source of the low-side MOSFET. Similarly, connect the input capacitor or capacitors positive terminal close to the drain of the high-side MOSFET. – Loop 2 : Loop 2 is not as critical as loop 1. The path is from the low-side MOSFET through the inductor and output capacitor or capacitors, and back to source of the low-side MOSFET through ground. Connect the source of the low-side MOSFET and negative terminal of the output capacitor or capacitors at ground as close as possible.
• The PCB trace defined as SW node, which connects to the source of the high-side MOSFET, the drain of the low-side MOSFET and the high-voltage side of the inductor, must be short and wide. However, the SW connection is a source of injected EMI and thus must not be too large.
• Follow any layout considerations of the MOSFETs as recommended by the MOSFET manufacturer, including pad geometry and solder paste stencil design.
• The SW pin connects to the switch node of the power conversion stage and acts as the return path for the high-side gate driver. The parasitic inductance inherent to loop 1 and the output capacitance (COSS) of both power MOSFETs form a resonant circuit that induces high frequency (> 50MHz) ringing at the SW node. The voltage peak of this ringing, if not controlled, can be significantly higher than the input voltage. Make sure that the peak ringing amplitude does not exceed the absolute maximum rating limit for the SW pin. In many cases, a series resistor and capacitor snubber network connected from the SW node to GND damps the ringing and decreases the peak amplitude. If testing reveals that the ringing amplitude at the SW pin is excessive, then include snubber components as needed.

7.4.1.2 Gate-Drive Layout

Minimizing stray or parasitic gate loop inductance is key to optimizing gate drive switching performance, whether series gate inductance resonates with MOSFET gate capacitance or common source inductance (common to gate and power loops) provides a negative feedback component opposing the gate drive command, thereby increasing MOSFET switching times. The following loops are important:

• Loop 3: high-side MOSFET, QH. During the high-side MOSFET turn-on, high current flows from the bootstrap capacitor through the gate driver and high-side MOSFET, and back to the negative terminal of the boot capacitor through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from the gate of the high-side MOSFET through the gate driver and SW, and back to the source of the high-side MOSFET through the SW trace.
• Loop 4: low-side MOSFET, QL. During the low-side MOSFET turn-on, high current flows from the VCC decoupling capacitor through the gate driver and low-side MOSFET, and back to the negative terminal of the capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from the gate of the low-side MOSFET through the gate driver and GND, and back to the source of the low-side MOSFET through ground. TI recommends following circuit layout guidelines when designing with high-speed MOSFET gate drive circuits.
• Connections from gate driver outputs, HO and LO, to the respective gates of the high-side or low-side MOSFETs must be as short as possible to reduce series parasitic inductance. Be aware that peak gate drive currents can be as high as a few amperes. Use 0.65mm (25mils) or wider traces. Use via or vias, if necessary, of at least 0.mm (20 mils) diameter along these traces. Route HO and SW traces as a differential pair from the device to the high-side MOSFET, taking advantage of flux cancellation. Also, route LO trace and LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

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PGND trace/copper area as a differential pair from the device to the low-side MOSFET, taking advantage of flux cancellation.

• Locate the bootstrap capacitor, CCBOOT, close to the CBOOT and SW pins of the device to minimize the area of loop 3 associated with the high-side driver. Similarly, locate the VCC capacitor, CVCC, close to the VCC and PGND pins of the device to minimize the area of loop 4 associated with the low-side driver.

7.4.1.3 PWM Controller Layout

Locate the device as close as possible to the power MOSFETs to minimize gate driver trace runs, the components related to the analog and feedback signals as well as current sensing are considered in the following:

• Separate power and signal/analog traces, and use a ground plane to provide noise shielding.
• Place all sensitive analog traces and components related to COMP, FB, ISNS+, IMON, ISET, and RT away from high-voltage switching nodes such as SW, HO, LO, or CBOOT to avoid mutual coupling. Use internal layer or layers as ground plane or planes. Pay particular attention to shielding the feedback (FB) and current sense (ISNS+ and VOUT) traces from power traces and components.
• Locate the upper and lower feedback resistors close to the FB pin, keeping the FB trace as short as possible. Route the trace from the upper feedback resistor to the required output voltage sense point at the load.
• Route the ISNS+ and VOUT sense traces as differential pairs to minimize noise pickup and use Kelvin connections to the applicable shunt resistor.
• Minimize the loop area from the VCC and VIN pins through the respective decoupling capacitors to the PGND pin. Locate these capacitors as close as possible to the device.

7.4.1.4 Thermal Design and Layout

The operating temperature range of a PWM controller with integrated gate drivers and bias supply LDO regulator is greatly affected by the following:

• Average gate drive current requirements of the power MOSFETs
• Switching frequency
• Operating input supply voltage (affecting bias regulator LDO voltage drop and hence the power dissipation)
• Thermal characteristics of the package and operating environment For a PWM controller to be useful over a particular temperature range, the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The VQFN package offers a means of removing heat from the semiconductor die through the exposed thermal pad at the base of the package. The exposed pad of the package is thermally connected to the substrate of the device. This connection allows a significant improvement in heat sinking and becomes imperative that the PCB is designed with thermal lands, thermal vias, and a ground plane to complete the heat removal subsystem. The exposed pad of the device is soldered to the ground-connected copper land on the PCB directly underneath the device package, reducing the thermal resistance to a very low value. Numerous vias with a 0.3mm diameter connected from the thermal land to the internal and solder-side ground plane or planes are vital to help dissipation. In a multi-layer PCB design, a solid ground plane is typically placed on the PCB layer below the power components. Not only does this placement provide a plane for the power stage currents to flow but this placement also represents a thermally conductive path away from the heat generating devices. The thermal characteristics of the MOSFETs also are significant. The drain pads of the high-side MOSFETs are normally connected to a VIN plane for heat sinking. The drain pads of the low-side MOSFETs are tied to the SW plane, but the SW plane area is purposely kept as small as possible to mitigate EMI concerns.

7.4.1.5 Ground Plane Design

TI recommends using one or more of the inner PCB layers as a solid ground plane. A ground plane offers shielding for sensitive circuits and traces and also provides a quiet reference potential for the control circuitry. In particular, a full ground plane on the layer directly underneath the power stage components is essential. Connect the source terminal of the low-side MOSFET and return terminals of the input and output capacitors to www.ti.com LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: LM5190-Q1

this ground plane. Connect the PGND and AGND pins of the device at the exposed pad and then connect to the system ground plane using an array of vias under the exposed pad. The PGND nets contain noise at the switching frequency and can bounce because of load current variations. The power traces for PGND, VIN, and SW can be restricted to one side of the ground plane, for example on the top layer. The other side of the ground plane contains much less noise and is deigned for sensitive analog trace routes.

7.4.2 Layout Example

Figure 7-16 shows a layout example of a synchronous buck regulator with discrete power MOSFETs. The design uses an inner layer as a power-loop return path directly underneath the top layer to create a low-area switching power loop. This loop area, and hence parasitic inductance, must be as small as possible to minimize EMI as well as switch-node voltage overshoot and ringing. The high-frequency power loop current flows through MOSFETs, through the power ground plane on the inner layer, and back to VIN through the 0603/1210 ceramic capacitors . Six 0603 case size capacitors are placed in parallel very close to the drain of the high-side MOSFET. The low equivalent series inductance (ESL) and high self-resonant frequency (SRF) of the small footprint capacitors yield excellent high-frequency performance. The negative terminals of these capacitors are connected to the inner layer ground plane with multiple vias, further minimizing parasitic loop inductance. Additional guidelines to improve noise immunity and reduce EMI are as follows:

• Connect PGND directly to the low-side MOSFET and power ground. Connect AGND directly to an analog ground plane for sensitive analog components. The analog ground plane for AGND and the power ground plane for PGND must be connected at a single point directly under the device at the exposed pad.
• Connect the MOSFETs directly to the inductor terminal with short copper connections (without vias) as this net has high dv/dt and contributes to radiated EMI. The single-layer routing of the switch-node connection means that switch-node vias with high dv/dt do not appear on the bottom side of the PCB. This avoids e-field coupling to the reference ground plane during the EMI test. VIN and PGND plane copper pours shield the polygon connecting the MOSFETs to the inductor terminal, further reducing the radiated EMI signature.
• Place the EMI filter components on the bottom side of the PCB so that the components are shielded from the power stage components on the top side. LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

40 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

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to the IC Use multiple vias around the positive and negative connections of CIN Use multiple vias around the positive and negative connections of the output capacitors Connect AGND and PGND directly to the DAP/EP on the top layer Use multiple VIAs Use multiple vias around the positive and negative connections of CIN Place CVIN close to the IC Locate the device close to the MOSFETs Figure 7-16. PCB Top Layer www.ti.com LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: LM5190-Q1

8 Device and Documentation Support

8.1 Device Support

8.1.1 Development Support

For development support, see the following:

• For TI's reference design library, visit TI Designs
• Technical articles: – High-Density PCB Layout of DC/DC Converters – Synchronous Buck Controller Solutions Support Wide VIN Performance and Flexibility – How to Use Slew Rate for EMI Control

8.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5190-Q1 device with the WEBENCH® Power Designer. 1. Start by entering the input supply voltage, output load voltage, and output load current requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible designs from Texas Instruments. The WEBENCH Power Designer gives a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2 Documentation Support

8.2.1 Related Documentation

For related documentation, see the following:

• EVM user's guides: – Texas Instruments, LM5190-Q1 CCCV Buck Controller Evaluation Module User's Guide
• Application brief: – Texas Instruments, Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage Layout
• Application note: – Texas Instruments, AN-2162 Simple Success with Conducted EMI from DC-DC Converters
• Analog design journal: – Texas Instruments, Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics
• White papers: – Texas Instruments, An Overview of Conducted EMI Specifications for Power Supplies – Texas Instruments, An Overview of Radiated EMI Specifications for Power Supplies – Texas Instruments, Valuing Wide VIN, Low EMI Synchronous Buck Circuits for Cost-driven, Demanding

Applications

8.2.1.1 PCB Layout Resources

• Application notes: – Texas Instruments, AN-1149 Layout Guidelines for Switching Power Supplies – Texas Instruments, AN-1229 Simple Switcher PCB Layout Guidelines – Texas Instruments, Low Radiated EMI Layout Made SIMPLE with LM4360x and LM4600x
• Application brief: LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

42 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

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– Texas Instruments, Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage Layout

• Seminars: – Constructing Your Power Supply – Layout Considerations

8.2.1.2 Thermal Design Resources

• Application brief: – Texas Instruments, PowerPAD™ Made Easy
• Application notes: – Texas Instruments, AN-2020 Thermal Design by Insight, Not Hindsight – Texas Instruments, AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages – Texas Instruments, Semiconductor and IC Package Thermal Metrics – Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602 – Texas Instruments, PowerPAD™Thermally Enhanced Package – Texas Instruments, Using New Thermal Metrics

8.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

8.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

8.5 Trademarks

TI E2E™ is a trademark of Texas Instruments. WEBENCH® is a registered trademark of Texas Instruments. All trademarks are the property of their respective owners.

8.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (July 2024) to Revision A (November 2025) Page

• Updated the Features, Electrical Characteristics table, Feature Description, Application Information, and www.ti.com LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: LM5190-Q1

10 Mechanical, Packaging, and Orderable Information

The following pages show mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. LM5190-Q1 SNVSCE8A – JULY 2024 – REVISED NOVEMBER 2025 www.ti.com

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www.ti.com 4-Dec-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) LM5190QRGYRQ1 Active Production VQFN (RGY) | 19 3000 | LARGE T&R - NIPDAU Level-2-260C-1 YEAR -40 to 150 LM5190 QRGYQ1 PLM5190QRGYR Active Preproduction VQFN (RGY) | 19 3000 | LARGE T&R - Call TI Call TI -40 to 150 PLM5190QRGYR.A Active Preproduction VQFN (RGY) | 19 3000 | LARGE T&R - Call TI Call TI -40 to 150 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LM5190-Q1 : Addendum-Page 1

www.ti.com 4-Dec-2025

• Catalog : LM5190 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 5-Dec-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5190QRGYRQ1 VQFN RGY 19 3000 367.0 367.0 35.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRGY 19 PLASTIC QUAD FLATPACK - NO LEAD3.5 x 4.5, 0.5 mm pitch 4230073/A

www.ti.com PACKAGE OUTLINE C 19X 0.3 0.2 1.7 0.1 20X 0.5 0.3 1.0 0.8 (0.2) TYP 0.05 0.00 12X 0.5 3.5 2X 1.5 2.3 0.1

0.1 MIN

A 3.6 3.4 B 4.6 4.4 (0.16) TYP (0.13) VQFN - 1 mm max heightRGY0019B PLASTIC QUAD FLATPACK - NO LEAD 4230037/A 10/2023 PIN 1 INDEX AREA 0.08 C SEATING PLANE 9 12 10 11 X 0.3)(45 PIN 1 ID

0.1 C A B

0.05 C EXPOSED THERMAL PAD 20SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.000 A-A40.000 SECTION A-A TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

19X (0.6) 19X (0.25) 12X (0.5) (1.7) (2.3) (4.3) (0.75) TYP (0.9) (3.3) (0.6) (R0.05) TYP VQFN - 1 mm max heightRGY0019B PLASTIC QUAD FLATPACK - NO LEAD 4230037/A 10/2023 SYMM 10 11 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 19X (0.6) 19X (0.25) 12X (0.5) (3.3) (4.3) 2X (1.55) (R0.05) TYP (1.02) 4X (0.75) VQFN - 1 mm max heightRGY0019B PLASTIC QUAD FLATPACK - NO LEAD 4230037/A 10/2023 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 21 81% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X SYMM 20 10 11

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