PLM5066H2NLPR

LM5066H TI | Alldatasheet

Document overview

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Technical content

LM5066Hx 5.5V to 90V, Advanced Hotswap Controller With I/V/P Monitoring and PMBus Interface

1 Features

• 5.5V to 90V operation – 100V Continuous absolute max – Withstand up to -5V at output
• Adjustable ILIM thresholds from 10mV to 50mV
• Programmable FET SOA protection
• Programmable overcurrent blanking with digital timer
• Strong gate pull down (1.5A) for fast turn OFF
• Robust short circuit protection – Fast trip response (360ns) – Immune to supply line transients
• LM5066H2 with advanced features – Dual gate drive for high power applications – SYNC pin for parallel controller operation – Soft start capacitor disconnect
• Failed FET detection
• Programable UV, OV, tFAULT thresholds
• External FET temperature sensing
• Failed FET detection
• I2C / SMBus interface
• PMBus® interface for telemetry, control, configuration and debug – On chip EEPROM nonvolatile memory for configuration – Precision VIN, VOUT, IIN, PIN, VAUX monitoring V – Power cycle with a single command – Blackbox fault recording of multiple events with relative time stamp stored in internal EEPROM
• 12-bit ADC with 250kHz sampling rate
• Supports energy monitoring via Read_EIN command
• External FET temperature sensing
• –40°C < TJ < 125°C operation

2 Applications

• 12V and 48V servers and datacenter
• Base station power distribution
• Networking routers and switchers
• PLC power management
• 24V to 48V industrial systems

3 Description

The LM5066Hx provides robust protection and precision monitoring for 12V, 24V and 48V systems with programmable UV, OV, ILIM, and fast short circuit protection for customized input power applications. Programmable power limit threshold along with adjustable fault timer (t FAULT) limits maximum power dissipation and ensures FET SOA protection under all conditions including startup and fault events. Two level over current blanking with digital timers allows higher load transients to pass, enabling lower current limit settings and reducing requirements for strong SOA MOSFETs. An integrated PMBus™interface enables remote monitoring, control, and configuration of the system in real time. Key parameters can be accessed remotely for telemetry, and various thresholds can be configured through PMBus or stored in internal non volatile memory. The fast, accurate analog load current monitor supports predictive maintenance and dynamic power management including Intel PSYS and PROCHOT functionality to optimize server performance. A blackbox fault recording feature helps in debugging field failures. The LM5066H2 features dual gate drive architecture which enables use of a single strong SOA FET to handle power stress during startup and fault conditions, combined with multiple small low R DS(ON) FETs for normal load current operation, reducing the total solution size. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) LM5066H1PWPR PWP (TSSOP 28) 9.70mm × 4.40mm LM5066H2NLPR NLP (QFN 35) 5.00mm x 7.00mm (1) For all available packages, see the orderable addendum at the end of the data sheet. ADVANCE INFORMATION LM5066H SNVSCT1 – OCTOBER 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

VIN_K GND SDAO RSNS CTIMER CIN D1 QT IMON RIMON Cdvdt LM5066H1 Simplified Schematic OUT UVLO/EN VIN GATE1 DIODE FB OVLO SDAI SCL PGD SENSE VDD SMBus Interface SMBA CL RETRY VAUX VDD VREF TIMERPWR AGND LM5066H2 VOUT COUT VIN 1F 1 F RPWR ADR2 ADR1 ADR0 VDD VIN_K GND SDAO RSNS CTIMER CIN D1 IMON RIMON Cdvdt SYNC SFT_STRT QT GATE2 Q3 Low RDS(ON) MOSFETs Strong SOA MOSFET LM5066H2 Simplified Schematic LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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11 Mechanical, Packaging, and Orderable

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4 Device Comparison Table

Table 4-1 summarizes the differences between the LM50666H1 and the LM5066H2. Table 4-1. LM5066H1 vs LM5066H2 KEY FUNCTIONALITY LM5066H1 LM5066H2 GATE2 ✔ IMON ✔ ✔ SYNC ✔ SFT_STRT ✔ LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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5 Pin Configuration and Functions

VIN_K NC VIN CL PGDOUT UVLO/EN TIMER OVLO AGND SDAI GND SDAO ADR2 ADR1 VDD VAUX ADR0 SMBA SCL

15 VREF

Figure 5-1. LM5066H1 PWP Package Top View SDAI SDAO SCL SMBA VREF DIODE VAUX ADR2 ADR1 ADR0 VDD FB IMON TIMER PWR PGD SYNC GND SFT_STRT GATE2 OUT GATE1 SENSE VIN_K VIN VIN UVLO/EN OVLO AGND GND GND CL RETRY GND VIN 1234567891011 17 18 19 20 2524232221 2726 GND Solder exposed pad to ground. Figure 5-2. LM5066H2 QFN Package Top View Table 5-1. Pin Functions PIN NAME PIN NO.

DESCRIPTION

Pad Pad Pad Exposed pad of package Solder to the ground plane to reduce thermal resistance OUT 1 13 Output feedback Connect to the output rail (external MOSFET source). Internally used to determine the MOSFET VDS voltage for power limiting and to monitor the output voltage. GATE1 2 14 Gate drive output Connect to the external MOSFET's gate. Connect to single strong SOA MOSFET's gate for LM5066H2 SENSE 3 16 Current sense input The voltage across the current sense resistor (RSNS) is measured from VIN_K to this pin. If the voltage across RSNS reaches overcurrent threshold the load current is limited and the fault timer activates. VIN_K 4 17 Positive supply Kelvin pin The input voltage is measured on this pin. VIN 5 18, 19, 20 Positive supply input This pin is the input supply connection for the deviceA 10Ω resistor can be connected between VIN and input power supply. Connect a 100nF capacitor on this pin to ground for bypassing. N/C 6 - No connection UVLO/EN 7 21 Undervoltage lockout An external resistor divider from the system input voltage sets the undervoltage turn ON threshold. OVLO 8 22 Overvoltage lockout An external resistor divider from the system input voltage sets the overvoltage turn off threshold. AGND 9 23 Circuit ground Analog device ground. Connect to GND at the pin. GND 10 9, 15, 24, 35 Circuit ground SDAI 11 25 SMBus data input pin Data input pin for SMBus. Connect to SDAO if the application does not require unidirectional isolation devices. www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: LM5066H ADVANCE INFORMATION

Table 5-1. Pin Functions (continued) PIN NAME PIN NO. Data output pin for SMBus. Connect to SDAI if the application does not require unidirectional isolation devices. SCL 13 27 SMBus clock Clock pin for SMBus SMBA 14 28 SMBus alert line Alert pin for SMBus, active low VREF 15 29 Internal reference Internally generated precision reference used for analog to digital conversion. Connect a 1µF capacitor on this pin to ground for bypassing. DIODE 16 30 External diode Connect this to a diode configured MMBT3904 NPN transistor for temperature monitoring. VAUX 17 31 Auxiliary voltage input Auxiliary pin allows voltage telemetry from an external source. Full scale input of 2.97V. ADR2 18 32 SMBUS address line 2 Tri-state address line. Should be connected to GND, VDD, or left floating. ADR1 19 33 SMBUS address line 1 Tri-state address line. Should be connected to GND, VDD, or left floating. ADR0 20 34 SMBUS address line 0 Tri-state address line. Should be connected to GND, VDD, or left floating. VDD 21 1 Internal sub-regulator output Internally sub-regulated 4.85V bias supply. Connect a 1µF capacitor on this pin to ground for bypassing. CL 22 2 Current limit range Connect this pin to GND or leave floating to set the nominal over current threshold at 50mV. Connecting CL to VDD sets the overcurrent threshold to be 25mV. FB 23 3 Power Good feedback An external resistor divider from the output sets the output voltage at which the PGD pin switches. SYNC - 4 Synchronous turn ON and turn OFF of parallel controllers Tie this pin of all parallel controllers for synchronous operation. RETRY 24 5 Fault retry input This pin configures the power up fault retry behavior. When this pin is connected to GND or left floating, the device will continually try to engage power during a fault. If the pin is connected to VDD, the device will latch off during a fault. TIMER 25 6 Timing capacitor An external capacitor connected to this pin sets insertion time delay, fault timeout period, and restart timing. PWR 26 7 Power limit set An external resistor connected to this pin, in conjunction with the current sense resistor (RSNS), sets the maximum power dissipation allowed in the external series pass MOSFET. IMON 27 8 Load current monitorAn external resistor needs to be connected from this pin to GND. IMON pin outputs current proportional to the load current. PGD 28 10 Power Good indicator An open-drain output. This output is high when the voltage at the FB pin is above VFBTH and VGS1, VGS2 are high. SFT_STRT - 11 Soft start capacitor disconnectdvdt capacitor (Cdvdt) for inrush current limiting has to be connected from this pin to GND Internal switches connect Cdvdt to GATE1 during startup/retry. After successful startup, the Cdvdt cap is connected to OUT GATE2 - 12 GATE2 drive outputConnect to the external Low RDS(ON) MOSFETs gate. LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Input voltage VIN, VIN_K, SENSE, UVLO/EN, PGD to GND –0.3 100 V OVLO, FB, TIMER, PWR, SYNC, SCL, SDAI, SDAO, CL, ADR0, ADR1, ADR2, VDD, VAUX, DIODE, RETRY, IMON, SMBA, VREF to GND –0.3 6 GATE1, GATE2, SFT_STRT to GND –5 115 VIN_K to SENSE, AGND to GND –0.3 0.3 GATE1, GATE2, SFT_STRT to OUT –0.3 15 V Output voltage OUT to GND -5 100 V Operating junction temperature, Tj (2) –40 150 Storage temperature, Tstg –65 150 (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 VCharged device model (CDM), per JEDEC specificationJESD22- C101, all pins(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1) MIN NOM MAX UNIT Input voltage VIN, VIN_K, SENSE, OUT, UVLO/EN, PGD to GND 5.5 90 V OVLO, CL, RETRY, ADR0, ADR1, ADR2, SYNC to GND VVDD Inuput Voltage VAUX to GND 3 V Output Voltage OUT to GND VVIN V Output Voltage IMON to GND 3.3 V Pull-up Voltage SCL, SDAI, SDAO, SMBA 1.8 5 V External Capacitanc e VDD, VREF to GND 1 µF External Resistor PWR to GND 120 kΩ TJ Operating Junction temperature(2) –40 125 °C (1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test conditions, see Electrical Characteristics. www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: LM5066H ADVANCE INFORMATION

(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

6.4 Thermal Information

THERMAL METRIC(1) LM5066H1 UNITPWP

28 PINS

RθJA Junction-to-ambient thermal resistance 35.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 19.9 RθJB Junction-to-board thermal resistance 16.8 ΨJT Junction-to-top characterization parameter 0.5 ΨJB Junction-to-board characterization parameter 16.7 RθJC(bot) Junction-to-case (bottom) thermal resistance 2.9 (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Unless otherwise stated, the following conditions apply: VVIN = 48 V, –40°C < TJ < 125°C, VUVLO = 3 V , VOVLO = 0 V, RPWR= 20 kΩ. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT (VIN PIN) VIN Operating input voltage range 5.5 90 V I(VIN) VIN pin current, I(VIN) VVIN = 48V, VUVLO/EN = 3 V and VOVLO = 2 V 4 mA I(Q) Total System Quiescent current, I(GND) VVIN = 48V, VUVLO/EN = 3 V and VOVLO = 2 V -4.3 mA VVIN = 12V, VUVLO/EN = 3 V and VOVLO = 2 V -4 mA PORR Power-on reset rising threshold at VVIN to enable all functions and trigger insertion timer VVIN increasing 4.75 V PORF Power-on reset falling threshold at VVIN to disable all functions VVIN decreasing 4.3 V VDD REGULATOR (VDD PIN) VDD IVDD = 0 mA 4.9 V IVDD = 10 mA, VIN > 8V 4.89 V VVDDILIM VVDD current limit –30 mA VVDDPOR VVDD voltage reset threshold VVDD rising 4.3 V UVLO/EN, OVLO PINS UVLOTH UVLO threshold VUVLO falling 2.48 V UVLOHYS UVLO hysteresis current VUVLO = 1 V 21 µA UVLOBIAS UVLO bias current VUVLO = 3 V 1 µA OVLOTH OVLO threshold VOVLO rising 2.48 V OVLOHYS OVLO hysteresis current VOVLO = 3 V –21 µA OVLOBIAS OVLO bias current VOVLO = 1 V 1 µA POWER LIMIT (PWR PIN) LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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6.5 Electrical Characteristics (continued)

Unless otherwise stated, the following conditions apply: VVIN = 48 V, –40°C < TJ < 125°C, VUVLO = 3 V , VOVLO = 0 V, RPWR= 20 kΩ. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VSNS,PLIM Power limit sense voltage (VVIN_K – VSENSE) VSENSE – VOUT = 48 V, RPWR = 60 kΩ 8.6 mV VSENSE – VOUT = 48 V, RPWR = 20 kΩ 2.9 VSENSE – VOUT = 48 V, RPWR = 20 kΩ, TJ = 0°C to 85°C 2.9 VSENSE – VOUT = 12 V, RPWR = 60 kΩ 34.4 VSENSE – VOUT = 12 V, RPWR = 20 kΩ 11.5 VSENSE – VOUT = 12 V, RPWR = 20 kΩ, TJ = 0°C to 85°C 11.5 IPWR Source current from PWR pin VPWR = 2.5 V –20 µA RSAT(PWR) Pull down of PWR pin if disabled VUVLO = 0 V 80 Ω GATE CONTROL (GATE PIN) IGATE1 Source current Normal operation, VGATE1 – VOUT = 5V -21 µA Fault sink current VUVLO = 2 V 10 mA POR circuit breaker sink current VVIN_K – VSENSE = 60 mV, VGATE1 – VOUT = 5V, CB/CL ratio bit = 0, CL = VDD 1.5 A Regulation max sink current VVINK – VSENSE = 30mV, CL = VDD 235 µA IGATE2 Source current Normal operation, VGATE2 – VOUT = 5V -130 µA Fault sink current VUVLO = 2 V 10 mA POR circuit breaker sink current VVIN_K – VSENSE = 60 mV, VGATE2 – VOUT = 5V, CB/CL ratio bit = 0, CL = VDD 1.5 A VGATE1Z Reverse-bias voltage of GATE to OUT Zener diode, IZ = –100 µA VGATE1– VOUT , VOUT = 0V 15.4 V VGATECP Peak charge pump voltage in normal operation (VIN = VOUT) VGATE1– VOUT , VGATE2– VOUT , VOUT = 48V 12.5 V OUT PIN IOUT-EN OUT bias current, enabled VIN = VOUT, normal operation, VVIN = 5.5V, 48V, 90V 2 µA IOUT-DIS OUT bias current, disabled Disabled, VVIN_K = VSENSE = OUT, EN/ UVLO = 0V, VVIN = 5.5V, 48V, 90V 40 µA Disabled, OUT = -5V, VVIN_K = VSENSE -340 µA Disabled, OUT = 0 V, VVIN_K = VSENSE , VVIN = 5.5V, 48V, 90V -30 µA VOUT-DIS OUT voltage, disabled Disabled, Meaure OUT, VVIN_K = VSENSE 0.8 V CURRENT LIMIT www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: LM5066H ADVANCE INFORMATION

Unless otherwise stated, the following conditions apply: VVIN = 48 V, –40°C < TJ < 125°C, VUVLO = 3 V , VOVLO = 0 V, RPWR= 20 kΩ. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCL Current limit threshold voltage (VVIN_K – VSENSE) DEVICE_SETUP1, bit 2 = 1; DEVICE_SETUP2, bits 3:5 = 001 10 mV DEVICE_SETUP1, bit 2 = 1; DEVICE_SETUP2, bits 3:5 = 010 12.5 mV DEVICE_SETUP1, bit 2 = 1; DEVICE_SETUP2, bits 3:5 = 100 15 mV DEVICE_SETUP1, bit 2 = 1; DEVICE_SETUP2, bits 3:5 = 100 17.5 mV DEVICE_SETUP1, bit 2 = 1; DEVICE_SETUP2, bits 3:5 = 101 20 mV DEVICE_SETUP1, bit 2 = 1; DEVICE_SETUP2, bits 3:5 = 110 22.5 mV DEVICE_SETUP1, bit 2 = 0; CL = VDD 25 mV DEVICE_SETUP1, bit 2 = 0; CL = GND 50 VFBCL Foldback Current Limit threshold (VVIN_K – VSENSE)FBCL/VCL VCL = 10mV; DEVICE_SETUP3, bits 4:5 = 01 0.053 V/V VCL = 10mV; DEVICE_SETUP3, bits 4:5 = 10 0.1 V/V Foldback Current Limit threshold (VVIN_K – VSENSE)FBCL/VCL VCL = 25mV; DEVICE_SETUP3, bits 4:5 = 01 0.05 V/V VCL = 25mV; DEVICE_SETUP3, bits 4:5 = 10 0.1 V/V VCBL1 Over Current Blanking1 threshold voltage (VVIN_K – VSENSE)CBL1/VCL , VCL = 10mV VCL = 10mV; DEVICE_SETUP3, bits 0:1 = 00 1.25 V/V VCL = 10mV; DEVICE_SETUP3, bits 0:1 = 01 1.5 V/V VCL = 10mV; DEVICE_SETUP3, bits 0:1 = 10 1.75 V/V VCL = 10mV; DEVICE_SETUP3, bits 0:1 = 11 2 V/V Over Current Blanking1 threshold voltage (VVIN_K – VSENSE)CBL1/VCL , VCL = 25mV VCL = 25mV; DEVICE_SETUP3, bits 0:1 = 00 1.25 V/V VCL = 25mV; DEVICE_SETUP3, bits 0:1 = 01 1.5 V/V VCL = 25mV; DEVICE_SETUP3, bits 0:1 = 10 1.75 V/V VCL = 25mV; DEVICE_SETUP3, bits 0:1 = 11 2 V/V LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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Unless otherwise stated, the following conditions apply: VVIN = 48 V, –40°C < TJ < 125°C, VUVLO = 3 V , VOVLO = 0 V, RPWR= 20 kΩ. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCBL2 Over Current Blanking2 threshold voltage (VVIN_K – VSENSE)CBL2/VCL, VCL = 10mV VCL = 10mV; DEVICE_SETUP3, bits 2:3 = 00 1.5 V/V VCL = 10mV; DEVICE_SETUP3, bits 2:3 = 01 1.75 V/V VCL = 10mV; DEVICE_SETUP3, bits 2:3 = 10 2 V/V VCL = 10mV; DEVICE_SETUP3, bits 2:3 = 11 2.25 V/V Over Current Blanking2 threshold voltage (VVIN_K – VSENSE)CBL2/VCL, VCL = 25mV VCL = 25mV; DEVICE_SETUP3, bits 2:3 = 00 1.5 V/V VCL = 25mV; DEVICE_SETUP3, bits 2:3 = 01 1.75 V/V VCL = 25mV; DEVICE_SETUP3, bits 2:3 = 10 2 V/V VCL = 25mV; DEVICE_SETUP3, bits 2:3 = 11 2.25 V/V ISENSE SENSE input current Enabled, SENSE = OUT µA Disabled, OUT = 0 V, VIN = VIN_K = SENSE = 5.5V Enabled, OUT = 0 V, VIN=VIN_K=SENSE=5.5V Disabled, OUT = 0 V, VIN=VIN_K=SENSE=48V Enabled, OUT = 0 V, VIN = VIN_K = SENSE = 48V Disabled, OUT = 0 V, VIN = VIN_K = SENSE = 90V Enabled, OUT = 0 V, VIN = VIN_K = SENSE = 90V IVIN_K VIN_K input current Enabled, VIN_K = 48V, VCL = 25mV VVIN_K – VSENSE = 25mV 285 µA IVIN_K VIN_K input current Enabled, VIN_K = 48V, VCL = 25mV VVIN_K – VSENSE = 5mV 265 µA CIRCUIT BREAKER www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: LM5066H ADVANCE INFORMATION

Unless otherwise stated, the following conditions apply: VVIN = 48 V, –40°C < TJ < 125°C, VUVLO = 3 V , VOVLO = 0 V, RPWR= 20 kΩ. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RTCB Circuit breaker to current limit ratio: (VVIN_K – VSENSE)CB/VCL, VCL = 10mV VCL = 10 mV DEVICE_SETUP2, bits 6:7 = 01 1.2 V/V VCL = 10 mV DEVICE_SETUP1, bit 3 = 0 DEVICE_SETUP2, bits 6:7 = 00

2 V/V

VCL = 10 mV DEVICE_SETUP2, bits 6:7 = 11 3 V/V VCL = 10 mV DEVICE_SETUP1, bit 3 = 1 DEVICE_SETUP2, bits 6:7 = 00

4 V/V

Circuit breaker to current limit ratio: (VVIN_K – VSENSE)CB/VCL, VCL = 25mV VCL = 25 mV DEVICE_SETUP2, bits 6:7 = 01 1.2 V/V VCL = 25 mV DEVICE_SETUP1, bit 3 = 0 DEVICE_SETUP2, bits 6:7 = 00 VCL = 25 mV DEVICE_SETUP2, bits 6:7 = 11 3 VCL = 25 mV DEVICE_SETUP1, bit 3 = 1 DEVICE_SETUP2, bits 6:7 = 00 RTSCP Short Circuit Protection threshold voltage: (VVIN_K – VSENSE)SCP/VCB VCL = 25 mV DEVICE_SETUP2, bits 6:7 = 01 DEVICE_SETUP2, bits 0 = 1 DEVICE_SETUP2, bits 0 = 1

1.5 V/V

VCL = 25 mV DEVICE_SETUP1, bit 3 = 0 DEVICE_SETUP2, bits 6:7 = 00 DEVICE_SETUP2, bits 0 = 1 VCL = 25 mV DEVICE_SETUP2, bits 6:7 = 11 DEVICE_SETUP2, bits 0 = 1 VCL = 25 mV DEVICE_SETUP1, bit 3 = 1 DEVICE_SETUP2, bits 6:7 = 00 DEVICE_SETUP2, bits 0 = 1 FBTH FB threshold falling VUVLO = 3 V and VOVLO = 0 V 2.48 V FBHYS FB hysteresis current –21 µA FBLEAK Off leakage current VFB = 2.3 V 1 µA TIMER (TIMER PIN) VTMRH Upper threshold 3.9 V VTMRL Lower threshold Restart cycles 1.2 V End of eighth cycle re-enable threshold 0.3 V LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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Unless otherwise stated, the following conditions apply: VVIN = 48 V, –40°C < TJ < 125°C, VUVLO = 3 V , VOVLO = 0 V, RPWR= 20 kΩ. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ITIMER Insertion time current TIMER pin = 2V –5 µA Sink current, end of insertion time TIMER pin = 2V 1.5 mA Fault detection current, Constant Current Timer TIMER pin = 2V –75 µA Fault sink current, Constant Current Timer TIMER pin = 2V; DEVICE_SETUP4, bit 6 = 0 2.5 µA TIMER pin = 2V; DEVICE_SETUP4, bit 6 = 1 75 µA Fault detection current, P2T Timer TIMER pin = 0.5V, VDS x VSENSE = 20V x 25mV; DEVICE_SETUP4, bits 3:2 = 10 or 11 -60 µA TIMER pin = 0.5V, VDS x VSENSE = 48V x 5mV; DEVICE_SETUP4, bits 3:2 = 10 or 11 -13.8 µA P2t Threshold P2t Timer threshold voltage VDS x VSENSE = 48V x 5mV; DEVICE_SETUP4, bits 3:2 = 10 or 11 1 V SYNC ISYNC_LEAK Leakage current on SYNC pin VSYNC = 5V, Normal Operation 800 nA ISYNC Sink current VSYNC = 0.1V, Fault state, OVLO high 20 mA VSYNC Steady State indication voltage Steady state, PGD high 5 V Fault Indication voltage Fault state, OVLO high 200 mV POWER GOOD (PGD PIN) PGDVOL Output low voltage ISINK = 2 mA 100 mV PGDIOH Off leakage current VPGD = 90V 2 µA VPGD = VDD V 1 µA VGS1_PGDH GATE1 VGS threshold for PGD high assertion VGATE1– VOUT 8.1 V VGS1_G2L GATE1 VGS falling threshold for GATE2 Pull Down VGATE1– VOUT 7.85 V VGS2_PGDH GATE2 VGS threshold for PGD high assertion VGATE2– VOUT 8.1 V VDS_PGDH VDS threshold for PGD high assertion VSENSE– VOUT 1.9 V VDS_G2L VDS threshold for G2 Pull Down VSENSE– VOUT 2.4 V SFT_STRT I(SFT_STRT, GATE1) GATE1 to SFT_STRT charging current VOUT = VSFT_STRT = 0V -22 µA R(SFT_STRT, OUT) Resistance of switch between SFT_STRT and OUT VSFT_STRT = VOUT + 0.1V 2 Ω IMON GIMON Transconductance Amplifier Gain (IIMON : VVIN_K - VSENSE) VCL = 10mV 10 µA/mV VCL = 25mV 10 µA/mV VCL = 50mV 10 µA/mV ILKG(IMON) IMON pin leakage VIMON = 3.3V 35 nA FET_FAIL VGS1_FFTH GATE1 VGS threshold for FET_FAIL detection 4.1 V www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: LM5066H ADVANCE INFORMATION

Unless otherwise stated, the following conditions apply: VVIN = 48 V, –40°C < TJ < 125°C, VUVLO = 3 V , VOVLO = 0 V, RPWR= 20 kΩ. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VGS2_FFTH GATE2 VGS threshold for FET_FAIL detection 4.1 V VDS_FFTH VDS threshold for FET_FAIL detection 2 V VSNS_FFTH VSNS threshold for FET_FAIL detection 2.5 mV INTERNAL REFERENCE VREF Reference voltage 2.97 V ADC AND MUX Resolution 12 Bits DNL Differential non-linearity ADC only 1 LSB INL Integral non-linearity ADC only 2 LSB Sampling rate Samples per second Any channel 250 kHz tAQUIRE Acquisition + conversion time Any channel 4 µs tRR Acquisition round robin time Cycle all channels 20 us IAUX_LK Leakage current on AUX VAUX=3V, Normal Operation 500 nA TELEMETRY ACCURACY IINACC Input current absolute accuracy VCL = 10mV, VVIN_K – VSENSE = 10mV ±1 %VCL = 10mV, VVIN_K – VSENSE = 2mV ±5 VCL = 10mV, VVIN_K – VSENSE = 10mV, ADC FS = 2 x VCL IINACC Input current absolute accuracy VCL = 25mV, VVIN_K – VSENSE = 25mV ±1 %VCL = 25mV, VVIN_K – VSENSE = 5mV ±5 VCL = 25mV, VVIN_K – VSENSE = 50mV, ADC FS = 2 x VCL VACC VIN, VOUT absolute accuracy VVIN, VVOUT = 48V ±1 % VIN, VOUT absolute accuracy VVIN, VVOUT = 12 V ±1.5 % VAUX absolute accuracy VAUX = 2.8 V ±1 % PINACC Input power accuracy, VCL = 10mV, ADC FS = 1 x VCL VVIN = 48 V, VVIN_K – VSENSE = 10mV ±2 % PINACC Input power accuracy, VCL = 25mV, ADC FS = 1 x VCL VVIN = 48 V, VVIN_K – VSENSE = 25mV ±2 % interval VCL = 10mV, VVIN = 48 V, VVIN_K – VSENSE = 10mV, ADC FS = 1 x VCL VCL = 25mV, VVIN = 48 V, VVIN_K – VSENSE = 25mV, ADC FS = 1 x VCL interval, VCL = 17.5mV VVIN = 48 V, VVIN_K – VSENSE = 17.5mV, ADC FS = 1 x VCL ±2 % REMOTE DIODE TEMPERATURE SENSOR TACC Temperature accuracy using local diode TA = 25°C to 85°C 2 °C Remote diode resolution

12 Bits

External diode current source High level -250 µA Low level -10 µA Diode current ratio 25 LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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Unless otherwise stated, the following conditions apply: VVIN = 48 V, –40°C < TJ < 125°C, VUVLO = 3 V , VOVLO = 0 V, RPWR= 20 kΩ. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PMBus PIN THRESHOLDS (SMBA, SDA, SCL) VIL SCL, SDAI Input logic low 0.85 V VIH SCL, SDAI Input logic high 1.25 V VOL Low-level output voltage - SCL, SDAI, SDAO IOL = 20 mA from supply. 0.4 V ILEAK Input leakage current for SMBAB SMBAB = 5 V 1 µA ADDRESS SELECT (ADR0, ADR1, ADR2) VADRx ADR0, ADR1 and ADR2 pin voltage ADRx pin floating 1.63 V CONFIGURATION PIN THRESHOLDS (CL, RETRY) Vthresh_CL Threshold voltage 2.6 V Vthresh_RETRY Threshold voltage 2.6 V ILEAK Input leakage current CL, RETRY = 5 V 0.06 µA www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: LM5066H ADVANCE INFORMATION

7 Detailed Description

7.1 Overview

The LM5066Hx provides comprehensive hot swap control and power monitoring functionality for 12V, 24V and 48V systems. Its inline protection circuitry limits inrush current when cards are inserted into live backplanes, preventing voltage sags and controlling dV/dt to connected loads. This minimizes disruption to other system components by avoiding unintended resets. The device also enables controlled shutdown when cards are removed. In addition to a programmable current limit, the LM5066Hx monitors and limits the maximum power dissipation in the MOSFET to maintain operation within the device safe operating area (SOA). Extended current or power limiting conditions trigger shutdown of the MOSFETs device, with configurable retry options (none, 1, 2, 4, 8, 16, or infinite attempts). The circuit breaker function provides rapid shutdown of MOSFETs upon detection of severe overcurrent conditions. Programmable undervoltage lockout (UVLO) and overvoltage lockout (OVLO) circuits shut down the LM5066Hx when the system input voltage is outside the desired operating range. Extensive configuration options are available through PMBus ® interface or can be stored in internal non volatile memory for autonomous operation without host intervention at power up. Comprehensive telemetry capabilities include monitoring of input voltage, output voltage, input current, input power, temperature, and an auxiliary input. The device features input voltage, current, power and temperature peak and programmable averaging of key parameters. Programmable warning thresholds for monitored parameters can trigger the SMBA pin through the PMBus interface. Advanced telemetry features include high speed ADC sample buffering ("digital oscilloscope") and Blackbox fault recording to simplify debugging and enable predictive maintenance. The integrated high accuracy, high bandwidth analog load current monitor enables precise load current measurement in both steady state and transient conditions, facilitating advanced dynamic platform power management techniques such as Intel PSYS to optimize system power usage and throughput without compromising safety. The LM5066H2 features dual gate driver architecture that optimizes board space and reduces component costs in high power applications requiring multiple hot swap FETs. The primary gate driver (GATE1) controls a single robust SOA FET specifically designed to handle demanding conditions such as startup, current limiting, and power limiting during fault events. The secondary gate driver (GATE2) becomes active only after the main FET reaches full enhancement, allowing system designers to select secondary FETs based solely on low RDS(ON) characteristics without requiring extensive SOA capability. This architecture significantly reduces component count and board space while maintaining robust system protection. The device's 100 μA sourcing current capability ensures rapid recovery during transient conditions, preventing system resets during events such as adjacent card removal. The LM5066H2 incorporates advanced soft start capacitor disconnect functionality that provides controlled startup sequencing while automatically disconnecting the soft start capacitor during normal operation. This feature enables the use of smaller hot swap FETs without sacrificing transient response performance, further optimizing system design. The device includes comprehensive diagnostic capabilities to detect damage to external MOSFETs connected to both GATE1 and GATE2 pins, enhancing system reliability and facilitating troubleshooting. LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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7.2 Functional Block Diagram

1.2 V TIMER Current Limit & Blanking Threshold CHARGE PUMP 20 A TIMER AND GATE LOGIC CONTROL Power Limit Threshold 10mA GATE CONTROL OUT 1.5 mA End Insertion Time 0.3 V LM5066Hx Power Limit Control 4.75 V VIN Enable POR VCL / VCBLx 1.5A S/H VAUX AMUX EEPROM SMBUS INTERFACE DIODE ADR0 ADR1 ADR2 SCL SDAO SMBA ADDRESS DECODER TELEMETRY STATE MACHINE CL RETRY Diode Temp Sense VDD REGVDD 2.48 V 2.46 V 2.48 V AGND UVLO/EN OVLO 12 bit ADC ov uv VDS<2V Snapshot VDS IDS Current Limit Sense VCB / VSCP Circuit Breaker Threshold SDAI 2.97 VRef VREF 4.8 A 75 A Current Limit/ PGD FB OUT SENSE VIN K _ VIN 20A 21A 3.9 V GND VGS1>8V 130A 10mA 1.5A GATE2* OUT ∝IDS GATE1 OUT SFT_STRT* IMON OUT OUT SYNC* VGS2>8V * Pin available in LM5066H2 only 1 V ∝P2 Inrush 10A/mV WORKING REGISTERS FET FAIL DETECTION Digital Timers S R Q VSNS VDS VGS1 VGS2

7.3 Feature Description

7.3.1 Current Limit

The LM5066Hx provides current limit protection with eight programmable thresholds ranging from 10 mV to 50 mV. Current limiting activates when the voltage across the sense resistor R SNS (between VIN_K and SENSE pins) exceeds the selected threshold. Two thresholds can be set directly using the CL pin, 25 mV when CL is connected to VDD and 50 mV when CL is connected to GND. The remaining six thresholds are available by programming the DEVICE_SETUP1 and DEVICE_SETUP2 registers through the PMBus interface. During an over current event, the device offers two protection modes: over current blanking and current limiting. These modes can operate independently or sequentially based on configuration. In over current blanking mode, the device allows the load current to flow without limiting it for a set time period, as long as it remains below the circuit breaker threshold (V CB). The LM5066Hx features two over current blanking thresholds with separate timers:

• VCBL1 with timer tCBL1 for moderate over currents
• VCBL2 with timer tCBL2 for higher over currents www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: LM5066H ADVANCE INFORMATION

These thresholds and timers are configured in the DEVICE_SETUP3 and OC_BLANKING_TIMERS registers. Typically, VCBL1 is set higher than V CL, and V CBL2 is set higher than V CBL1. For load currents between V CL and VCBL2, the tCBL1 timer activates. For load currents between VCBL1 and VCBL2, the tCBL2 timer activates. The timer resets if the current drops below the respective threshold before it expires. If either timer expires due to prolonged overload, the device transitions to current limiting mode. In the LM5066H2, GATE2 turns off immediately when either timer expires. Over current blanking mode can be disabled by setting t CBL1 and tCBL2 to 0 μs. In current limiting mode, the GATE voltage is regulated such that the current through MOSFET driven by GATE1 is limited to the set current limit threshold. The fault timer activates during current limiting. If the load current falls below the current limit threshold before the fault timer expires, normal operation resumes. If the current limit persists beyond the fault timeout period set by CTMR, GATE1 turns off. Current limiting can be disabled by setting bit 7 in DEVICE_SETUP3. When disabled, both GATE1 and GATE2 turn off after the blanking phase when either of the blanking timer expires. When a current limit fault occurs, the device sets fault flags in the STATUS_INPUT (7Ch), STATUS_WORD (79h), and DIAGNOSTIC_WORD (E1h) registers, and asserts the SMBA pin. SMBA signaling can be disabled using the ALERT_MASK (D8h) register.For reliable operation, the R SNS resistor value should not exceed 200 mΩ to avoid instability in the current limit control loop. Over Current Limit Threshold, Over Current Blanking2 Threshold, Circuit Breaker Threshold, No Blanking operation* There is No Blanking* or Regulation operation For VSNS > VCB > VSCP , GATE1 and GATE2 turned OFF immediately There is No Load Current Blanking or Limiting in any condition For CBL1 t *Load current is blanked for 100µs if VIN is rising and VOUT is not discharging Controller will enter Current limit mode, Load Current will be Regulated to VCL for Regulation fault timer duration Reduced Current Limiting threshold (Only during Startup and Retry) Short Circuit Protection Threshold, VSCP VCB VCBL2 Over Current Blanking1 Threshold, VCBL1 VCL Foldback Current Limit Threshold, VFBCL Digital Blanking Timer, t Load current is blanked for a maximum of CBL1 durationCL < VSNS < VCBL2 , For V For VCBL1 < VSNS< VCBL2 , durationtCBL2 Load Current is blanked for a maximum of Digital Blanking Timer, tCBL2 For VCBL2 < VSNS < VCB , Controller will enter Current Limit mode immediately VSNS > VSCP, GATE1 and GATE2 turned OFF immediately ,After Expiry of tCBL2 or tCBL2 Figure 7-1. Current Limit, Blanking and Circuit Breaker Thresholds Table 7-1. Current Limit, Foldback Current Limit, Over Current Blanking, Circuit Breaker and Other Threshold Settings Parameter No. of Configurable Thresholds Thresholds Values Analog / Digital Over Current Limit Threshold, VCL 8 10mV, 12.5mV, 15mV,17.5mV, 20mV, 22.5mV and 25mV, 50mV Analog Over Current Blanking1 Threshold, VCBL1 4 1.25xVCL, 1.5xVCL, 1.75xVC, 2xVCL Analog Over Current Blanking2 Threshold, VCBL2 4 1.5xVCL, 1.75xVCL, 2xVCL, 2.25xVCL Analog Circuit Breaker Threshold, VCB 4 1.2xVCL, 2xVCL, 3xVCL,4xVCL Analog Short Circuit Protection Threshold, VSCP 1 1.5xVCB Analog Foldback Factor during StartUp 3 0.05xVCL, 0.1xVCL Analog LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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Table 7-1. Current Limit, Foldback Current Limit, Over Current Blanking, Circuit Breaker and Other Threshold Settings (continued) Parameter No. of Configurable Thresholds Thresholds Values Analog / Digital Over Current Blanking Timer1 16 0ms - 100ms Digital Over Current Blanking Timer2 16 0ms -10ms, 100ms Digital Circuit Breaker Blanking Time 1 100us Analog Regulation Timer (Constant Current Timer / P2t Timer) Set with TIMER pin Configurable using CTIMER Analog P2t Timer - Insertion Timer 4 10ms – 100ms Digital P2t Timer - Retry Timer 16 10ms – 10s Digital Watch Dog Timer during Startup/ Retry 16 10ms – 10s Digital

7.3.2 Foldback Current Limit

The LM5066Hx features current foldback capability during startup, limiting current to either 5% or 10% of the normal current limit threshold. This feature enables safe startup into capacitive loads without requiring external dV/dt capacitors on the GATE1 or SFT_STRT pins. The foldback factor can be selected using bits 4:5 in the DEVICE_SETUP3 register, and the feature can be disabled through the same register if not needed. A Watchdog Timer function monitors if the hot swap startsup within the expected timeframe. The timer duration is programmable from 10 ms to 10 s through the WD_CONFIG register and should be set longer than the anticipated startup time. The MOSFET connected to GATE1 must be selected to handle the foldback current for the entire watchdog timer duration to ensure reliable operation during startup conditions.

7.3.3 Soft Start Disconnect (SFT_STRT)

The LM5066H2 features an advanced soft start mechanism that controls inrush current into output capacitors using a capacitor connected between the SFT_STRT pin and GND. This configuration allows precise control of startup current based on the below equation. Unlike conventional hot swap controllers that connect the dV/dt capacitor directly to the gate, the LM5066H2 implements a switching architecture between the GATE1 and SFT_STRT pins. This design includes a disconnect switch between GATE1 and SFT_STRT, plus a discharge switch between SFT_STRT and OUT. During initial hot plug and insertion delay, the GATE1 to SFT_STRT switch remains open while the SFT_STRT to OUT switch is closed. During startup, the SFT_STRT pin connects to GATE1 to control slew rate. Once normal operation begins, the SFT_STRT pin disconnects from GATE1 and connects to OUT. This architecture solves multiple issues that exist in traditional designs: it prevents slow response during current or power limiting in steady state, avoids delayed GATE turn off during circuit breaker or short circuit protection events, and eliminates slowed turn on during immediate retry after false circuit breaker faults that could further depress output voltage.

7.3.4 Circuit Breaker

The LM5066Hx provides programmable circuit breaker (CB) protection with multiple threshold options. The circuit breaker threshold can be configured at 1.2x, 2x, 3x, or 4x of the current limit threshold by programming the DEVICE_SETUP1 and DEVICE_SETUP2 registers. This feature protects against rapid current increases, such as short circuits, where the current through the sense resistor (R SNS) may exceed the circuit breaker threshold before the current limit loop responds. When the circuit breaker threshold is exceeded, both GATE1 and GATE2 are rapidly turned off using a strong 1.5A pulldown current. If required, the device can be configured using bit 7 of DEVICE_SETUP4 register to www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: LM5066H ADVANCE INFORMATION

retry immediately after a 30 μs deglitch time by releasing the pulldown current and enabling GATE1. During this immediate retry, the gate voltage is controlled by the dV/dt, current limit, or power limit functions as needed. If current or power limiting persists, the regulation timer activates. Should the timer reach 3.9 V before the limiting condition resolves, GATE1 is turned off using either 10mA or 1.5A pulldown current. During immediate retry, GATE1 turn on can be slowed by the limited 21 μA source current and any external dV/dt capacitor connected to the GATE1 or the SFT_STRT pin. To improve output voltage recovery speed after false circuit breaker trips, the device includes a fast recovery feature that can disable the dV/dt capacitor connection and/or enable GATE2 alongside GATE1. This fast recovery logic can be enabled or disabled using bit 1 in the DEVICE_SETUP2 register. For systems with multiple hot pluggable cards on a common backplane (like blade servers and telecom equipment), supply transients can cause current spikes large enough to falsely trigger the circuit breaker. To prevent nuisance tripping, the LM5066H implements a protection algorithm that blanks the circuit breaker threshold for 100 μs, allowing transients to settle without shutting down the system. During this blanking period, a fixed short circuit protection (SCP) threshold (1.5x the circuit breaker threshold) remains active to protect against severe overcurrent events. If this SCP threshold is exceeded, the device turns off both gates with 1.5A pulldown. Circuit breaker events set fault flags in the STATUS_OTHER (7Fh), STATUS_MFR_SPECIFIC (80h), and DIAGNOSTIC_WORD (E1h) registers, and assert the SMBA pin unless disabled via the ALERT_MASK (D8h) register. Circuit breaker configuration can be modified through the DEVICE_SETUP (D9h) register.

7.3.5 Power Limit

The LM5066Hx features MOSFET power limiting to protect the external FET from operating outside its safe operating area (SOA). This function monitors power dissipation in the MOSFET driven by GATE1 by measuring both its drain-source voltage (SENSE to OUT) and drain current through the sense resistor R SNS (VIN_K to SENSE). The power limit threshold is set using a resistor at the PWR pin. When power dissipation reaches the limiting threshold, the device turns off GATE2 and modulates GATE1 voltage to regulate current through Q1. During power limiting, the fault regulation timer activates. If the power limit condition persists beyond the Fault Timeout Period set by the C TMR capacitor, GATE1 turns off. This event sets the IIN_OC Fault bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD (79h) register, and the IIN_OC/PFET_OP_FAULT bit in the DIAGNOSTIC_WORD (E1h) register. The SMBA pin is also asserted unless disabled through the ALERT_MASK (D8h) register. For applications where input voltage can experience step changes (such as 45V to 55V), the device includes a power limit blanking mode. During normal operation, as V DS increases, the current limit threshold decreases in a constant power limit profile. This can cause the device to remain in power limit mode for the entire fault timer duration under high loads, potentially shutting down the FETs. Power limit blanking addresses this by disabling current limit foldback when VDS is below the V PLIM,BL threshold. This allows more current to flow and charge the output capacitor while serving the load, helping the output voltage reach the input voltage without MOSFET shutdown. The VPLIM,BL threshold is configurable through bits 0:1 of the DEVICE_SETUP4 register. In the VDS region below VPLIM,BL, FET power dissipation will exceed PLIM since current limit foldback is disabled in power limit blanking mode. This feature operates only in steady state (when PG=High) and is not available during startup or retry conditions. To maintain FET operation within its SOA, a digital timer activates during power limit blanking mode. This timer should be configured by the designer and is typically set shorter than the regulation timer duration. LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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The device provides flexible configuration options for different operating conditions, allowing selective enabling of SFT_STRT to GATE1 connection, current limiting, power limit blanking mode, over current blanking, and foldback current limiting based on system requirements. VDS ILIMIT VDS,MAX ILIM,CL ILIM,PL_MIN VPLIM_BL Constant Power Limit Profile Power Limit Blanking Profile Figure 7-2. Power Limit Profiles

7.3.6 UVLO

The LM5066Hx enables MOSFETs only when the input supply voltage is within the operating range defined by programmable undervoltage lockout (UVLO) and overvoltage lockout (OVLO) levels. The UVLO threshold at VIN is typically set using a resistor divider network. When VIN is below the UVLO threshold, an internal 20 μA current source at the UVLO pin activates while the current source at OVLO remains off. During this condition, the MOSFETs are held off by a strong pulldown current (10 mA or 1.5A) between the GATEx and OUT pins. As VIN increases and raises the UVLO pin voltage above its threshold, the 21 μA current source at UVLO switches off. This action increases the voltage at the UVLO pin, providing hysteresis for stable threshold operation. Once the UVLO/EN pin exceeds its threshold and the insertion time delay expires, GATE1 turns on with a 20 μA current source. GATE2 activation follows after GATE1's V GS reaches more than 8V and the voltage across the FET (VDS) drops below 2V. The Application and Implementation section provides detailed procedures for calculating threshold setting resistor values. For minimum UVLO level configuration, the UVLO/EN pin can connect directly to VIN, allowing MOSFET activation after insertion time when VIN reaches the power on reset (POR) threshold. After power up, an UVLO condition sets multiple status flags, the INPUT bit in the STATUS_WORD (79h) register, the VIN_UV_FAULT bit in the STATUS_INPUT (7Ch) register, and the VIN_UNDERVOLTAGE_FAULT bit in the DIAGNOSTIC_WORD (E1h) register. The SMBA pin pulls low during this condition unless disabled through the ALERT_MASK (D8h) register.

7.3.7 OVLO

When VIN causes the OVLO pin voltage to exceed its threshold, the MOSFETs are turned off through a strong pulldown current (10mA or 1.5A) at the GATE pin, disconnecting load from the power supply. During an OVLO condition, an internal 21 μA current source activates at the OVLO pin, increasing the voltage to create threshold hysteresis for stable operation. When VIN drops below the OVLO threshold, GATE1 reactivates first, followed by GATE2 turn on, but only after GATE1's gate-source voltage exceeds 8V and the drain-source voltage falls below 2V. An OVLO event sets multiple status flags: the VIN_OV_FAULT bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD (79h) register, and the VIN_OVERVOLTAGE_FAULT bit in the DIAGNOSTIC_WORD (E1h) register. The SMBA pin pulls low during this condition unless disabled through the ALERT_MASK (D8h) register. The Application and Implementation section provides procedures for calculating the appropriate threshold setting resistor values. www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LM5066H ADVANCE INFORMATION

7.3.8 Power Good

The LM5066Hx features a Power Good indicator pin (PGD) which requires an external pullup resistor to provide status indication to downstream circuits. The PGD pin's off-state voltage can operate above or below the VIN and OUT voltages. The PGD signal asserts HIGH when all of the below conditions are met,

• FB pin voltage exceeds the PGD threshold
• Both GATE1-OUT and GATE2-OUT voltages indicate full enhancement (VGS1 >8V and VGS2 >8V)
• Voltage across the FET (VDS) is less than 2V The PGD signal pulls LOW when,
• FB pin voltage drops below the PGD falling threshold The output voltage threshold is typically set using a resistor divider network from output to the feedback pin. However, other voltages can be monitored as long as the FB pin voltage remains within its maximum rating. For threshold hysteresis, the device includes a 21 μA current source at the FB pin. This current source remains disabled when FB voltage is below threshold. As output voltage increases and FB exceeds threshold, the current source activates, sourcing current from the pin to raise FB voltage. The PGD pin status can be read through the PMBus interface via either the STATUS_WORD (79h) or DIAGNOSTIC_WORD (E1h) registers.

7.3.9 VDD Sub-Regulator

The LM5066Hx includes an internal linear sub-regulator that converts the input voltage to a 4.9 V supply rail for powering low voltage circuits. This VDD output can serve as the pullup supply for the CL, RETRY, ADR2, ADR1, and ADR0 pins if they are to be tied high. It can also function as the pullup supply for the PGD pin and SMBus signals (SDA, SCL, and SMBA). The VDD sub-regulator is designed for light load applications and should not power other integrated circuits. For device protection, the VDD pin includes current limiting set at 30 mA to prevent damage during short circuit conditions. Proper operation requires a ceramic bypass capacitor of at least 1 μF connected as close as possible to the VDD pin.

7.3.10 Remote Temperature Sensing

The LM5066Hx features remote temperature sensing using an external MMBT3904 NPN transistor. Connect the transistor's base and collector to the DIODE pin and the emitter to the LM5066Hx ground. Position the transistor near the component requiring temperature monitoring, such as the hot swap pass MOSFET (Q1). The temperature measurement works by detecting changes in diode voltage in response to current steps from the DIODE pin. This pin supplies a constant 10 μA with periodic 250 μA pulses every 50 μs to measure temperature. For accurate readings, minimize parasitic resistance between the DIODE pin and transistor, implement a Kelvin connection from the transistor emitter to device ground, and place a 1 nF bypass capacitor in parallel with the transistor to reduce noise. Temperature readings are accessible through the READ_TEMPERATURE_1 PMBus command (8Dh). The default temperature fault and warning thresholds are set to 256°C (effectively disabled), but can be configured through the PMBus interface using OT_WARN_LIMIT (51h) and OT_FAULT_LIMIT (4Fh) commands. When not using the temperature sensing function, ground the DIODE pin. Note that inaccurate temperature readings may occur when input voltage falls below the minimum operating level (5.5V), as this causes VREF to drop below its nominal 2.97 V. At higher ambient temperatures, this condition may produce readings exceeding the OT_FAULT_LIMIT, triggering a fault that disables Q1. To recover, clear faults and reset the device by writing 0h followed by 80h to the OPERATION (03h) register.

7.3.11 Damaged MOSFET Detection

The LM5066Hx includes MOSFET fault detection capability to identify damaged external MOSFETs under specific conditions. The device monitors for two main fault types: Drain-to-source or drain-to-gate faults are detected when, LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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• During insertion, the voltage across the sense resistor exceeds 2mV (VSNS > 2mV) or the voltage across the FET falls below 2V (VDS < 2V)
• After startup, if GATE turns off due to any fault and the sense resistor voltage remains above 2 mV after 1ms Gate-to-source or drain-to-gate faults are detected when,
• VGS1 remains below 4V for more than 500ms after GATE1 is set high
• VGS2 remains below 4V for more than 500ms after GATE2 is set high When a drain fault is detected, multiple status registers are updated, the FET FAIL bit in STATUS_WORD (79h), the EXT_MOSFET_SHORTED bit in STATUS_MFR_SPECIFIC (80h) and DIAGNOSTIC_WORD (E1h), and the FET_FAULT_DRAIN bit in STATUS_MFR_SPECIFIC. The SMBA pin asserts unless disabled via the ALERT_MASK register (D8h). For gate faults, the device sets the FET FAIL bit in STATUS_WORD (79h), the EXT_MOSFET_SHORTED bit in STATUS_MFR_SPECIFIC (80h) and DIAGNOSTIC_WORD (E1h). Additionally, for GATE1 faults, the FET_FAULT_GATE1 bit in STATUS_MFR_SPECIFIC is set, while for GATE2 faults, the FET_FAULT_GATE2 bit is set. After detecting GATE type fault, GATE1 and GATE2 can be configured to turn off by setting bit 6 in the GATE_MASK (D7h) register.

7.3.12 Analog Current Monitor (IMON)

The LM5066Hx features a precision analog current monitor that outputs a current proportional to the load current through the external MOSFET. This current mode output appears at the IMON pin with a gain of 10 μA/mV relative to the voltage across the sense resistor (RSNS). The current output design allows the signal to be routed across long board distances without introducing errors from voltage drops or noise coupling from adjacent traces. In parallel hot swap configurations, multiple IMON pins can be tied together to provide a summed current measurement representing total system current. For measurement purposes, the IMON current can be converted to a voltage by connecting a resistor (R IMON) from the IMON pin to ground. The resulting voltage (V IMON) provides an accurate representation of load current according to the equation below. The IMON circuit delivers high bandwidth and accuracy across varying load and temperature conditions, independent of board layout and system operating parameters. This performance makes it ideal for advanced dynamic platform power management implementations like Intel PSYS or PROCHOT, enabling systems to maximize power usage and throughput without compromising safety or reliability. If the IMON feature is not required in the application, the pin can be left floating without affecting device operation.

7.4 Device Functional Modes

7.4.1 Power Up Sequence

The LM5066Hx operates across a 5.5V to 80V input range with 100V transient capability. During initial power up, the device prevents accidental MOSFET turn on by applying a 10 mA pulldown current between the GATEx and OUT pins, protecting against Miller capacitance charging effects. The TIMER pin starts at ground potential. When VIN reaches the power on reset (POR) threshold, the insertion delay sequence begins. During this period, a 4.8 μA current source charges the external timing capacitor (C TMR) while the 10mA pulldown maintains the MOSFET in the off state. This delay allows input voltage transients to settle before enabling the pass device. The insertion delay ends when the TIMER pin reaches 3.9 V, at which point C TMR rapidly discharges through an internal 1.5mA current sink. If VIN exceeds the UVLO threshold after the insertion delay, the GATE1 pin activates with a 21μA current source to charge the MOSFET gate. An internal 16.5V Zener diode limits the maximum gate-source voltage. For the LM5066H2, GATE2 turns on with a 130 μA source current once GATE1 VGS exceeds 8V and the VDS falls below 2V. As output voltage rises, the device monitors current flowing through the MOSFETs and power dissipation. During inrush current or power limiting, a 75 μA fault timer current charges C TMR. If limiting conditions resolve before TIMER reaches 3.9V, the current source turns off and C TMR discharges through a 2.5 μA current sink. If TIMER reaches 3.9V while still in limiting conditions, a fault is asserted and GATE1 turns off. www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: LM5066H ADVANCE INFORMATION

The CONFIG_PRESET bit in the STATUS_MFR_SPECIFIC register (80h) remains set until cleared with a CLEAR_FAULTS command. A configurable watchdog timer (10ms to 10s) monitors power up progress. This timer starts when GATE1 is enabled, and if PGD doesn't assert within the set duration, the WD timer fault is indicated in the STATUS_MFR_SPECIFIC_2 register. This fault can be configured to turn off both GATE1 and GATE2 through the GATE_MASK register. Normal OperationInsertion Time POR Load Current Inrush Limiting FB 4.8 A 75 A3.9 V 2.5 A

21 A sourceGATE

2.46 V t2t1 t3 PGD Figure 7-3. Power Up Sequence (Current Limit Only)

7.4.2 Gate Control

The LM5066H1 offers single gate drive capable of driving multiple MOSFETs in parallel. LM5066H2 features dual gate drive architecture that optimizes MOSFET selection for high power hot swap applications. GATE1 drives a single robust SOA MOSFET in dual gate configuration or multiple MOSFETs in single gate mode. With a 21μA gate source current, GATE1 provides controlled turn on for effective inrush current limiting or power limit based startup. A dV/dt capacitor can connect directly from GATE1 to GND for LM5066H1 or across SFT_STRT to GND for LM5066H2 to further manage inrush current. During current limiting or power limiting conditions, the device regulates GATE1 while keeping GATE2 off. In dual gate operation, GATE2 drives multiple low R DS(ON) MOSFETs for normal operation. To protect these MOSFETs, GATE2 turns off whenever V DS exceeds 2V, preventing power stress during startup, short circuit conditions, or current/power limiting events. GATE2 activates only after GATE1 V GS exceeds 8V and V DS drops below 2V. The higher gate source current (130μA) enables rapid turn on of multiple parallel MOSFETs. GATE1 and GATE2 are turned OFF for LM5066Hx if any of the below events occur,

• Current exceeds the current limit threshold after Over Current blanking and regulation fault timer expires
• Power dissipation in the MOSFET exceeds the power limit threshold and regulation fault timer expires
• Undervoltage or overvoltage conditions
• Circuit breaker or Short circuit protection
• Over temperature or damaged MOSFET detection or watchdog expiry faults
• PMBus Commands, OPERATION or POWER CYCLE command sets output disable LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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In steady state when any of the below conditions occur, GATE2 is turned OFF and GATE 1 remains ON or in regulation,

• VDS exceeds 2V for any reason
• Start of Current limiting or power limiting operation An internal charge pump supplies gate voltage to both outputs, producing approximately 13.5V at the gates under normal operation. During initial power up, a 10 mA pulldown prevents unwanted MOSFET activation from Miller capacitance effects. During insertion time, both gates are held low by 10 mA pulldown currents. After insertion, GATE1 voltage modulates to maintain current and power within programmed limits while the TIMER capacitor charges. If limiting conditions resolve before TIMER reaches 3.9 V, the capacitor discharges and normal operation begins. If limiting persists until TIMER reaches 3.9 V, GATE1 pulls low until a retry occurs. The LM5066Hx offers configurable gate pulldown strength (10 mA or 1.5 A) for various fault conditions, providing flexibility to match system requirements. Parameter Condition GATE1 GATE2 Source Current Normal Operation 21μA 130μA Sink Current VUVLO < VUVLOTH 10mA /1.5A Selectable in bit 0 of DEVICE_SETUP5 Register VOVLO > VOVLOTH 10mA /1.5A Selectable in bit 1 of DEVICE_SETUP5 Register OC / FET Plim Fault after Regulation Timer expiry 10mA /1.5A Selectable in bit 4 of DEVICE_SETUP5 Register x Blanking Timer Expiry, Device entering Current/Power limiting x 10mA /1.5A Selectable in bit 3 of DEVICE_SETUP5 Register Digital Faults / Commands (OT, FET_FAIL, Operation, Power Cycle, WD expiry) 10mA /1.5A Selectable in bit 2 of DEVICE_SETUP5 Register CB / SCP 1.5A VIN < POR Insertion Time 10mA Max Regulation sink current OC/FET Plim Limiting 235μA x

7.4.3 Fault Timer and Restart

When current or power limit thresholds are exceeded during startup or other fault events, the device regulates GATE1 voltage to control load current and limit power dissipation in the primary FET (Q1). During these regulation time periods, a 75 μA current source charges the external fault timer capacitor (C TMR) connected to the TIMER pin and for LM5066H2 the GATE2 remains completely off. If the limiting condition resolves before the TIMER pin voltage reaches 3.9V, the device returns to normal operation and C TMR discharges through a 10mA current sink. However, if TIMER pin voltage reaches 3.9V while still in limiting mode, GATE1 turns off through either a 10mA or 1.5A pulldown current. The subsequent restart behavior depends on the selected retry configuration. With the RETRY pin high, the device latches GATE low after the fault timeout period. The timing capacitor then discharges to ground through a 2.5 μA current sink. GATE remains low until a power up sequence is externally initiated by either cycling input voltage or momentarily pulling the UVLO/EN pin below its threshold using an open-collector or open-drain device. For successful restart, the TIMER pin voltage must be below 0.3V. While www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: LM5066H ADVANCE INFORMATION

in this latched off condition, the TIMER_LATCHED_OFF bit in the DIAGNOSTIC_WORD (E1h) register remains set. Restart Control VIN VIN UVLO/EN OVLO GND Figure 7-4. Latched Fault Restart Control The LM5066Hx features a configurable auto-retry mechanism for fault recovery. After a fault timeout period, the device initiates an automatic restart sequence where the TIMER pin cycles between 3.9V and 1.2V seven times. The duration of each cycle depends on the external timer capacitor (C TMR) value along with the internal 75 μA charging current and 2.5 μA discharge current. When the TIMER pin voltage reaches 0.3V during the eighth high-to-low transition, the device activates the 21 μA current source at the GATE pin to turn on the external MOSFET (Q1). If the fault condition persists, the fault timeout period and restart sequence repeat according to the programmed retry settings. Basic retry behavior can be selected through the RETRY pin, which allows for either no retries (latched-off mode) or infinite retries. For more precise control, the DEVICE_SETUP register (D9h) enables selection of specific retry counts: 0, 1, 2, 4, 8, 16, or infinite. This programmability allows system designers to optimize fault recovery behavior based on application requirements. The timer discharge current is configurable to be 2.5 μA or 75μA through bit 6 of the DEVICE_SETUP4 register. Retry delay timing can use either the analog fault timer with external capacitor or a digital timer, selectable via bits 2:3 of DEVICE_SETUP4. When using digital timing, the retry delay period is programmable from 10ms to 10s using bits 4:7 of the DELAY_CONFIG register. 1.2 V 1 2 3 7 8 10mA / 1.5A pulldown Fault Detection GATE Pin Load Current TILIMI tRESTARTFault Timeout Period 21 A Gate Charge 2.5A3.9 V 75 A 0.3 V TIMER Pin Figure 7-5. Restart Sequence

7.4.4 Shutdown Control

The load current can be remotely switched off by taking the UVLO/EN pin below its threshold with an open collector or open-drain device, as shown in Figure 7-6. When UVLO/EN pin is released, the LM5066Hx switches on the FET with in-rush current and power limiting. The output may also be enabled or disabled by writing 80h or 0h to the OPERATION (03h) register. LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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Figure 7-6. Shutdown Control

7.4.5 Enabling/Disabling and Resetting

The LM5066Hx output can be disabled during normal operation by pulling the UVLO/EN pin below its threshold or the OVLO pin above its threshold, forcing the GATE voltage low with a pulldown strength of 10mA or 1.5A. Toggling UVLO/EN also resets the device from a latched off state caused by exceeding the maximum retry count during overcurrent or overpower conditions. While UVLO/EN and OVLO pins control output state, they don't affect device memory. User programmed values for address, operation settings, and fault thresholds remain preserved in both volatile and non-volatile memory regardless of these pins states. Output can also be controlled through the PMBus interface by writing 80h (enable) or 0h (disable) to the OPERATION register. After a fault condition, the device can be re-enabled by writing 0h followed by 80h to this register. The POWER_CYCLE command provides controlled output cycling, powering down and then up after a configurable delay set through the RETRY_CONFIG register. The device SMBus address is determined by ADR0, ADR1, and ADR2 pin states at power up, latched after VDD exceeds its 4.3V POR threshold. Address capture can be postponed by holding the VREF pin low, which also resets logic and clears volatile memory. Upon release, the address latches when VREF exceeds 2.55V. For custom addressing, the hardware set address can be overridden by programming the PMBUS_ADDR register while leaving the address pins floating.

7.5 Programming

7.5.1 PMBus Command Support

The device features an SMBus interface that allows the use of PMBus commands to set warn levels, error masks, and get telemetry on VIN, VOUT, IIN, VAUX, and PIN. The supported PMBus commands are shown in Table 7-2. Table 7-2. Supported PMBus Commands S.No. Code Name Function Type R/W No. of Data Bytes Default Value Stored in Internal EEPROM 1 01h OPERATION Retrieves or stores the operation status Control R/W 1 80h No 2 03h CLEAR_FAULTS Clears the status registers and re- arms the black box registers for updating Control Send byte 0 NA No 3 10h WRITE_PROTECT Enable/Disable write protection for OPERATION & POWER_CYCLE commands, configuration registers, NVM, and EEPROM Control R/W 1 00h Yes www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: LM5066H ADVANCE INFORMATION

Table 7-2. Supported PMBus Commands (continued) S.No. Code Name Function Type R/W No. of Data Bytes Default Value Stored in Internal EEPROM 4 12h RESTORE_FACTORY_DEFAUL TS Initialize/Reset all configuration registers to their factory default values Control Send byte 0 NA No 5 15h STORE_USER_ALL Store configuration values to internal NVM/EEPROM Control Send byte 0 NA No 6 16h RESTORE_USER _ALL Initialize all configuration registers with the user programmed values stored in internal NVM/ EEPROM Control Send byte 0 NA No 7 19h CAPABILITY Supported PMBus® features Telemetry R 7 D0h No 8 43h VOUT_UV_WARN_LIMIT Retrieves or stores output undervoltage warn limit threshold Configuration R/W 2 0000h Yes 9 4Fh OT_FAULT_LIMIT Retrieves or stores over temperature fault limit threshold Configuration R/W 2 0FFFh (256°C) Yes 10 51h OT_WARN_LIMIT Retrieves or stores over temperature warn limit threshold Configuration R/W 2 0FFFh (256°C) Yes 11 57h VIN_OV_WARN_LIMIT Retrieves or stores input overvoltage warn limit threshold Configuration R/W 2 0FFFh Yes 12 58h VIN_UV_WARN_LIMIT Retrieves or stores input undervoltage warn limit threshold Configuration R/W 2 0000h Yes 13 5Dh IIN_OC_WARN_LIMIT Retrieves or stores input current warn limit threshold (mirror at D3h, F8h) Configuration R/W 2 0FFFh Yes 14 78h STATUS_BYTE Retrieves information about the parts operating status Telemetry R 1 01h No 15 79h STATUS_WORD Retrieves information about the parts operating status Telemetry R 2 0801h No 16 7Ah STATUS_VOUT Retrieves information about output voltage status Telemetry R 1 00h No LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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Table 7-2. Supported PMBus Commands (continued) S.No. Code Name Function Type R/W No. of Data Bytes Default Value Stored in Internal EEPROM 17 7Ch STATUS_INPUT Retrieves information about input status Telemetry R 1 00h No 18 7Dh STATUS_TEMPERATURE Retrieves information about temperature status Telemetry R 1 00h No 19 7Eh STATUS_CML Communications, Memory,Logic status Telemetry R 1 00h No 20 7Fh STATUS_OTHER Retrieves other status information Telemetry R 1 00h No 21 80h STATUS_MFR_SPECIFIC Retrieves information about circuit breaker and MOSFET shorted status Telemetry R 1 10h 22 86h READ_EIN Retrieves energy meter measurement Telemetry R 6 00h 00h 00h 00h 00h 00h No 23 88h READ_VIN Retrieves input voltage measurement Telemetry R 2 0000h No 24 89h READ_IIN Retrieves input current measurement (Mirrors at D1h) Telemetry R 2 0000h No 25 8Bh READ_VOUT Retrieves output voltage measurement Telemetry R 2 0000h No 26 8Ch READ_IOUT Retrieves output current measurement Telemetry R 2 0000h No 27 8Dh READ_TEMPERATURE_1 Retrieves temperature measurement Telemetry R 2 0000h No 28 96h READ_POUT Retrieves output power measurement Telemetry R 2 0000h No 29 97h READ_PIN Retrieves averaged input power measurement (mirror at DFh). Telemetry R 2 0000h No 30 98h PMBUS_Revision PMBus® Specifications Part I and II rev 1.3 Telemetry R 1 33h No 31 99h MFR_ID Retrieves manufacturer ID in ASCII characters (TI) Telemetry R 3 54h 49h 0h Metal 32 9Ah MFR_MODEL Retrieves part number in ASCII characters. (LM5066I) Telemetry R 8 4Ch 4Dh 35h 30h 36h 36h 48h 0h Metal www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: LM5066H ADVANCE INFORMATION

Table 7-2. Supported PMBus Commands (continued) S.No. Code Name Function Type R/W No. of Data Bytes Default Value Stored in Internal EEPROM 33 9Bh MFR_REVISION Retrieves part revision letter or number in ASCII (for example, AA) Telemetry R 2 41h 41h Metal

34 A0h READ_VIN_MIN Minimum input

voltage Telemetry R 2 0FFFh No

35 A1h READ_VIN_PEAK Peak input voltage Telemetry R 2 0000h No

36 A2h READ_IIN_PEAK Peak input current Telemetry R 2 0000h No

37 A3h MFR_SPECIFIC_05

READ_PIN_PEAK Retrieves measured peak input power measurement Telemetry R 2 0000h No

38 A4h READ_VOUT_MIN Minimum output

voltage Telemetry R 2 0FFFh No

39 BCh USER_DATA General User

programmable data Configuration R/W 1 00h Yes

40 C7h READ_TEMP_AVG Average device

temperature Telemetry R 2 0000h No

41 C8h READ_TEMP_PEAK Peak device

temperature Telemetry R 2 0000h No

42 C9h READ_SAMPLE_ BUF ADC sample buffer Telemetry Block

43 CAh POWER_CYCLE

the RETRY_CONFIG register Control Send byte 0 Undefined No

44 CCh MFR_SPECIFIC_09

DEVICE_SETUP1 Retrieves or stores information about number of retry attempts Configuration R/W 1 0000h Yes

45 CDh DEVICE_SETUP4 Device configuration Configuration R/W 1 91h Yes

46 CEh DEVICE_SETUP5 Device configuration Configuration R/W 1 00h Yes

47 CFh IMON_LOAD

48 D0h MFR_SPECIFIC_00

READ_VAUX Retrieves auxiliary voltage measurement Telemetry R 2 0000h No

49 D1h MFR_SPECIFIC_01

MFR_READ_IIN Retrieves input current measurement (Mirror at 89h) Telemetry R 2 0000h No

50 D2h MFR_SPECIFIC_02

MFR_READ_PIN Retrieves input power measurement Telemetry R 2 0000h No LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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Table 7-2. Supported PMBus Commands (continued) S.No. Code Name Function Type R/W No. of Data Bytes Default Value Stored in Internal EEPROM

51 D3h MFR_SPECIFIC_03

MFR_IIN_OC_WARN_LIMIT Retrieves or stores input current limit warn threshold (Mirror at 5Dh, F8h) Configuration R/W 2 0FFFh Yes

52 D4h MFR_SPECIFIC_04

MFR_PIN_OP_WARN_LIMIT Retrieves or stores input power limit warn threshold Configuration R/W 2 0FFFh Yes

53 D6h MFR_SPECIFIC_06

CLEAR_PIN_PEAK Resets the contents of the peak input power register to 0 Control Send byte 0 Undefined No

54 D7h MFR_SPECIFIC_07

GATE_MASK Allows the user to disable MOSFET gate shutdown for various fault conditions Configuration R/W 1 42h Yes

55 D8h MFR_SPECIFIC_08

ALERT_MASK Retrieves or stores user SMBA fault mask Configuration R/W 2 FD20h Yes

56 D9h READ_VAUX_AVG Retrieves average

Vaux measurement Telemetry R 2 0000h No

57 DAh MFR_SPECIFIC_10

BLOCK_READ Retrieves most recent diagnostic and telemetry information in a single transaction Telemetry R 12 0880h 0000h 0000h 0000h 0000h 0000h No

58 DBh MFR_SPECIFIC_11

SAMPLES_FOR_AVG Exponent value AVGN for number of samples to be averaged (N = 2AVGN), range = 00h to 0Ch Configuration R/W 1 08h Yes

59 DCh MFR_SPECIFIC_12

READ_AVG_VIN Retrieves averaged input voltage measurement Telemetry R 2 0000h No

60 DDh MFR_SPECIFIC_13

READ_AVG_VOUT Retrieves averaged output voltage measurement Telemetry R 2 0000h No

61 DEh MFR_SPECIFIC_14

READ_AVG_IIN Retrieves averaged input current measurement Telemetry R 2 0000h No

62 DFh MFR_SPECIFIC_15

READ_AVG_PIN Retrieves averaged input power measurement Telemetry R 2 0000h No www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: LM5066H ADVANCE INFORMATION

Table 7-2. Supported PMBus Commands (continued) S.No. Code Name Function Type R/W No. of Data Bytes Default Value Stored in Internal EEPROM

63 E0h BB_CLEAR Clear

READ_BB_RAM data Control Send byte 0 Undefined No

64 E1h MFR_SPECIFIC_17

DIAGNOSTIC_WORD_READ Manufacturer-specific parallel of the STATUS_WORD to convey all FAULT/ WARN data in a single transaction Telemetry R 2 0880h No

65 E2h MFR_SPECIFIC_18

AVG_BLOCK_READ Retrieves most recent average telemetry and diagnostic information in a single transaction Telemetry R 12 0880h 0000h 0000h 0000h 0000h 0000h No

66 E3h BB_ERASE Erase Blackbox data

in internal EEPROM Control Send byte 0 Undefined No

67 E4h BB_CONFIG Blackbox

configuration Configuration R/W 1 00h Yes

68 E5h OC_BLANKING_TIMERS Transient overcurrent

blanking timer1 and 2 Configuration R/W 1 75h Yes

69 E7h DELAY_CONFIG

Configuration R/W 1 84h Yes

70 E8h WD_CONFIG WatchDog Timer

Configuration Configuration R/W 1 Bfh Yes

71 E9h PK_MIN_AVG Peak/Min/Average

configuration Configuration R/W 1 00h Yes

72 EAh P2t_TIMER_CONFIG Clear

READ_BB_RAM data Configuration R/W 1 0Ch Yes

73 EBh FETCH_BB_EEPROM

74 ECh READ_BB_RAM Blackbox RAM/

working registers Telemetry Block Read 7 00h Yes

75 EDh ADC_CONFIG_1 ADC Configuration Configuration R/W 1 00h Yes

76 EEh ADC_CONFIG_2 ADC Configuration Configuration R/W 1 00h Yes

77 EFh DEVICE_SETUP2 Device configuration Configuration R/W 1 00h Yes

78 F0h DEVICE_SETUP3 Device configuration Configuration R/W 1 00h Yes

79 F2h IMON_CONFIG Configure IMON

offset Configuration R/W 1 00h Yes LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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Table 7-2. Supported PMBus Commands (continued) S.No. Code Name Function Type R/W No. of Data Bytes Default Value Stored in Internal EEPROM

80 F3h STATUS_MFR_SPECIFIC_2

81 F4h READ_BB_EEPROM Blackbox EEPROM

82 F6h BB_TIMER Blackbox tick timer Telemetry R 1 00h No

83 F7h PMBUS_ADDR

PMBus® device address for ADDR0 = Open and ADDR1 = Open setting Configuration R/W 1 40h Yes

84 F8h OC_WARN_LIMIT

limit threshold (mirror at 5Dh, F8h) Configuration R/W 2 0FFFh Yes www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: LM5066H ADVANCE INFORMATION

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The LM5066Hx is a hot swap with a PMBus interface that provides current, voltage, power, and status information to the host. As a hot swap controller, it is used to manage inrush current and protect in the event of faults. When designing a hotswap, three key scenarios should be considered:

• Start-up
• The output of a hot swap controller is shorted to ground when the hot swap controller is on. This is often referred to as an output hot-short.
• Powering up a board when the output and ground are shorted. This is usually called a start-into-short. All of these scenarios place a lot of stress on the hotswap MOSFET, and take special care when designing the hotswap circuit to keep the MOSFET within its SOA. Detailed design examples are provided in the following sections. Solving all of the equations by hand is cumbersome and can result in errors. Instead, TI recommends using the LM5066Hx Design Calculator.

8.2 Typical Application

8.2.1 54V, 100A PMBus Hot Swap Design This section describes the design procedure for a 54V, 100A PMBUS hot swap design using the LM5066H1 controller. OUT UVLO/EN VIN GATE DIODE FB OVLO SDAI SCL PGD SENSE VDD SMBus Interface SMBA CL RETRY VAUX VDD VREF TIMERPWR AGND LM5066H1 VOUT COUT VIN 1F 1 F RPWR ADR2 ADR1 ADR0 VDD VIN_K GND SDAO RSNS CTIMER CIN D1 QT IMON RIMON Cdvdt Figure 8-1. Typical Application Circuit LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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8.2.1.1 Design Requirements

Table 8-1 summarizes the design parameters that must be known before designing a hotswap circuit. When charging the output capacitor through the hotswap MOSFET, the FET’s total energy dissipation equals the total energy stored in the output capacitor (1 / 2CV 2). Thus, both the input voltage and output capacitance determine the stress experienced by the MOSFET during start-up. The maximum load current drives the current limit and sense resistor selection. Additionally, the maximum load current, maximum ambient temperature, and thermal properties of the PCB (R θCA) influence the selection of the MOSFET, including the R DSON and he number of MOSFETs used. RθCA is a strong function of the layout and the amount of copper that is connected to the drain of the MOSFET. Note that the drain is not electrically connected to the ground plane; therefore, the ground plane cannot be used to aid in heat dissipation. This design example uses R θCA = 25°C/W, which is similar to the LM5066H1 and LM5066H2 evaluation modules. It is a good practice to measure the R θCA of a given design after the physical PCBs are available. Finally, it is important to understand what test conditions the hotswap needs to pass. In general, a hotswap is designed to pass both a hot-short and a start into a short, which are described in the previous section. Also, TI recommends keeping the load OFF until the hotswap is fully powered up. Starting the load early causes unnecessary stress on the MOSFET and could lead to MOSFET failures or a failure to start up. Table 8-1. Design Parameters PARAMETER EXAMPLE VALUE Input voltage range 40 to 60V Maximum load current 100A Maximum output capacitance of the hotswap 5mF Maximum ambient temperature 55°C MOSFET RθCA (function of layout) 25°C/W Pass hot-short on output? Yes Pass a start into short? Yes Is the load off until PG asserts? Yes Can a hot board be plugged back in? Yes

8.2.1.2 Detailed Design-In Procedure

8.2.1.2.1 Selecting the Hotswap FETs

It is critical to select the correct MOSFET for a hotswap design. The device must meet the following requirements:

• The VDS rating should be sufficient to handle the maximum system voltage along with any ringing caused by transients. For most 54V systems, a 100V FET is a good choice.
• The SOA of the FET should be sufficient to handle all usage cases: start-up, hot-short, and start into short.
• RDSON should be sufficiently low to maintain the junction and case temperature below the maximum rating of the FET. In fact, TI recommends keeping the steady-state FET temperature below 125°C to allow margin to handle transients.
• The maximum continuous current rating should be above the maximum load current, and the pulsed-drain current must be greater than the current threshold of the circuit breaker. Most MOSFETs that pass the first three requirements also pass these two.
• A VGS rating of ±20 V is required because the LM5066Hx can pull up the gate as high as 16V above source. For this design, the PSMN2R3-100SSE was selected for its low R DSON and superior SOA. Four (4) MOSFETs are used in parallel in this design example. After selecting the MOSFET, the maximum steady-state case temperature can be computed as follows: C,MAX A,MAX CA LOAD,MAX DSON JT T R I R (T ) /c113/c61 /c43 /c180 /c180 (1) www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: LM5066H ADVANCE INFORMATION

Note that the R DSON is a strong function of junction temperature, which for most LFPAK88 MOSFETs is very close to the case temperature. A few iterations of the previous equations may be necessary to converge on the final RDSON and TC,MAX value. According to the PSMN2R3-100SSE data sheet, its RDSON becomes 1.75 times at 120°C. Equation 2 uses this R DSON value to compute the T C,MAX. Note that the computed T C,MAX is close to the junction temperature assumed for RDSON. Thus, no further iterations are necessary. T C , MAX = 55°C + 25 °C W × 100 A 8.2.1.2.2 dv/dt-Based Start-Up For designs with large load currents and output capacitances, using a power-limit-based start-up can be impractical. Fundamentally, increasing load currents reduces the sense resistor, which increases the minimum power limit. Using a larger output capacitor results in a longer start-up time and requires a longer timer. Thus, a longer timer and a larger power limit setting are required, which places more stress on the MOSFET during a hot-short or a start into short. Eventually, there will be no FETs that can support such a requirement. To avoid this problem, a dv/dt limiting capacitor (C dv/dt) can be used to limit the slew rate of the gate and the output voltage. The inrush current can be set arbitrarily small by reducing the slew rate of V OUT. In addition, the power limit is set to satisfy the minimum power limit requirement and to keep the timer from running during start-up (make P LIM / V INMAX > I INR). Because the timer does not run during start-up, it can be made arbitrarily small to reduce the stress that the MOSFET experiences during a start into a short or a hot-short. The inrush current should be kept low enough to keep the MOSFET within its SOA during start-up. Note that the total energy dissipated in the MOSFET during start-up is constant regardless of the inrush time. Thus, stretching it out over a longer time always reduces the stress on the MOSFET as long as the load is off during start-up. When choosing a target slew rate, one should pick a reasonable number, check the SOA, and reduce the slew rate if necessary. Using 0.3V/ms as a starting point, the inrush current can be computed as follows: I INR = C O UT × dV OUT d t = 5mF × 0.3 V ms = 1.5 A (3) Assuming a maximum input voltage of 60V, it takes around 200ms to start up. Note that the power dissipation of the FET starts at V IN,MAX × I INR and reduces to 0 as the V DS of the MOSFET is reduced. Note that the SOA curves assume the same power dissipation for a given time. A conservative approach is to assume an equivalent power profile where PFET = VIN,MAX × IINR for t = tstart-up / 2. In this instance, the SOA can be checked by looking at a 60V, 1.5A, 100ms pulse. Using the SOA plot from the PSMN2R3-100SSE MOSFET datasheet, the MOSFET can handle 60V, 6A for 100ms at an ambient temperature of 25°C. This value has to also be derated for temperature. For this calculation, it is assumed that T C can equal TC,MAX when the board is plugged in. This would only occur if a hot board is unplugged, then plugged back in before it cools off. This is worst case and for many applications, the TA,MAX can be used for this derating. I SO A 100 ms, T C, MAX = I SOA 100 ms, 25 ° C × T J , ABS MAX − T C , MAX T J, ABSM AX − 25°C = 6A × 175 ° C − 118 °C This calculation shows that the MOSFET stays well within its SOA during a start-up if the slew rate is 0.3V/ms. Note that if the load is off during start-up, the total energy dissipated in the FET is constant regardless of the slew rate. Thus, a lower slew rate always places less stress on the FET. To ensure that the slew rate is at most 0.3V/ms, the Cdv/dt should be chosen as follows: C dv / dt = I G ATE, SO URC E

0.3 V / ms = 21µA

0.3V / ms = 70nF (5) The closest value of 68nF is selected. Next, the typical slew rate and start time can be computed to be 0.31V/ms as shown in Equation 6, making the typical start time around 200ms. LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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ΔV OUT Δ t = I GATE, SOURCE C dv / dt = 21µA 68 nF = 0.31 V / ms (6)

8.2.1.2.3 Select RSNS and CL Setting

LM5066H1 can be used with a VCL of 25 or 50mV using CL pin configurations (Connect CL pin to GND to set the nominal overcurrent threshold at 50mV. Connecting CL to VDD sets the overcurrent threshold to be 25mV). Using the DEVICE_SETUP2 (EFh, Read/Write Word) register, the current limit can be set at 10mV, 12.5mV, 15mV, 17.5mV, 20mV, and 22.5mV. TI recommends targeting a current limit that is at least 10% above the maximum load current to account for the tolerance of the LM5066H1 current limit. Targeting a current limit of 110A, the sense resistor can be computed as follows: R SNS, C LC = V CL I LIM = 25 mV

110 A = 227µΩ (7)

Typically, sense resistors are only available in discrete values. If a precise current limit is desired, a sense resistor along with a resistor divider can be used as shown in Figure 8-2. RSNS VIN_K SENSE Figure 8-2. SENSE Resistor Divider The next larger available sense resistor should be chosen (250µ Ω in this case). The ratio of R 1 and R 2 can be computed as follows: R 1 R 2 = R SNS, C LC R SNS − R SNS, CLC = 227 Note that the SENSE pin pulls 25 μA of current, which creates an offset across R 2. TI recommends keeping R 2 below 10Ω to reduce the offset that this introduces. In addition, the 1% resistors add to the current monitoring error. Finally, if the resistor divider approach is used, the user should compute the effective sense resistance (RSNS,EFF) using Equation 9 and use that in all equations instead of RSNS. SNS 1 SNS,EFF 1 2 R RR R R /c180/c61 /c43 (9) R1 is selected as 10Ω, R2 becomes 1.01Ω. Closest selected value of R2 is 1Ω. Note that for many applications, a precise current limit may not be required. In that case, it is simpler to pick the next smaller available sense resistor.

8.2.1.2.4 Select Power Limit

In general, a lower power limit setting is preferred to reduce the stress on the MOSFET. However, when the LM5066H1 is set to a very-low power limit setting, it has to regulate the FET current and hence the voltage across the sense resistor (VSNS) to a very-low value. VSNS can be computed as shown in Equation 10. www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: LM5066H ADVANCE INFORMATION

/c180/c61 (10) To avoid significant degradation of the power limiting, TI does not recommend a V SNS of less than 0.5mV. Based on this requirement, the minimum allowed power limit can be computed as follows: P L I M, MI N = V SN S, M IN × V I N , MAX R SNS = 1mV × 60 V 0.227 mΩ = 264W (11) In most applications, the power limit can be set to PLIM,MIN, using Equation 12. 270W of power limit is considered here. P L I M W = R PW R k Ω × 6 R SNS mΩ (12) The closest available resistor should be selected. In this case, a 10kΩ resistor was chosen.

8.2.1.2.5 Set Fault Timer

The fault timer runs when the hotswap is in power limit or current limit. Based on the PSMN2R3-100SSE MOSFET SOA plot, a 1ms fault timer duration is considered, which provides enough MOSFET SOA margin. CTIMER can be computed as follows: C TIM ER = t f lt × i t i mer V t imer = 1 ms × 75 µ A

3.9 V = 20 n F (13)

The fault timer capacitor is selected as 20nF.

8.2.1.2.6 Check MOSFET SOA

When the power limit and fault timer are chosen, it is critical to check that the FET stays within its SOA during all test conditions. During a hot-short, the circuit breaker trips and the LM5066H1 restarts into power limit until the timer runs out. In the worst case, the MOSFET’s V DS equals VIN, MAX, IDS equals PLIM / VIN, MAX, and the stress event lasts for tflt. For this design example, the MOSFET has 60V, 4.5A across it for 1ms. Based on the SOA of the PSMN2R3-100SSE, it can handle 60V, 30A for 1ms at an ambient temperature of 25°C. Note that the SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be much hotter during a hot-short. The SOA should be de-rated based on TC,MAX, using Equation 14: I SO A 1ms , T C, M AX = I SO A 1 ms, 25°C × T J, AB SMAX − T C , M AX T J , ABS MAX − 25 ° C = 30 A × 175 ° C − 118 °C Based on this calculation, the MOSFET can handle 11.4A, 60V for 1ms at an elevated case temperature of 118°C, but is only required to handle 4.5A during a hot-short. Thus, there is a good margin, and the design is robust. In general, TI recommends that the MOSFET can handle 1.3 times more than what is required during a hot-short. This provides margin to account for the variance of the power limit and fault time.

8.2.1.2.7 Set UVLO and OVLO Thresholds

By programming the UVLO and OVLO thresholds, the LM5066Hx enables the series-pass device (Q 1) when the input supply voltage (V IN) is within the desired operational range. If V IN is below the UVLO threshold or above the OVLO threshold, Q1 is switched off, denying power to the load. Hysteresis is provided for each threshold. The configuration shown in Figure 8-3 requires three resistors (R1 to R3) to set the thresholds. LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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2.48 V 2.46 V TIMER AND GATE LOGIC CONTROL VIN 21 PA 20 PA Figure 8-3. UVLO And OVLO Thresholds Set By R1-R3 The procedure to calculate the resistor values is as follows:

• Choose the upper UVLO threshold (VUVH) and the lower UVLO threshold (VUVL).
• Choose the upper OVLO threshold (VOVH).
• The lower OVLO threshold (VOVL) cannot be chosen in advance in this case, but is determined after the values for R1 to R3 are determined. If VOVL must be accurately defined in addition to the other three thresholds, see Option B. The resistors are calculated as follows: UV(HYS)UVH UVL VV VR1 20 A 20 A /c45/c61 /c61 /c109 /c109 (15) /c40 /c41 UVL OVH UVL R1 V 2.46VR3 V V 2.48V /c180 /c180/c61 /c180 /c45 (16) UVL 2.48V R1R2 R3V 2.48V /c180/c61 /c45 /c45 (17) The lower OVLO threshold is calculated from: /c40 /c41OVL 2.46VV R1 R2 21 A 2.46V R3 /c233 /c249 /c230 /c246 /c230 /c246/c61 /c43 /c180 /c45 /c109 /c43/c234 /c250 /c231 /c247 /c231 /c247 /c232 /c248/c234 /c250 /c232 /c248/c235 /c251 (18) When the R1 to R3 resistor values are known, the threshold voltages and hysteresis are calculated from the following: UVH 2.48VV /CharA0 2.48V R1 20 A R2 R3 /c230 /c246/c61 /c43 /c180 /c43 /c109 /c231 /c247 /c43/c232 /c248 (19) /c40 /c41 UVL 2.48V R1 R2 R3V R2 R3 /c180 /c43 /c43/c61 /c43 (20) UV(HYS)V R1 20 A/c61 /c180 /c109 (21) /c40 /c41 OVH 2.46V R1 R2 R3V R3 /c180 /c43 /c43/c61 (22) /c40 /c41OVL 2.46VV 21 A R1 R2 2.46VR3 /c230 /c246/c61 /c45 /c109 /c180 /c43 /c43/c231 /c247 /c232 /c248 (23) www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: LM5066H ADVANCE INFORMATION

/c40 /c41OV(HYS)V /CharA0 R1 R2 21 A/c61 /c43 /c180 /c109 (24) If all four thresholds must be accurately defined, the configuration in Figure 8-4 can be used. VIN UVLO/EN OVLO GND 2.48 V 2.46 V TIMER AND GATE LOGIC CONTROL VIN 21 PA 20 PA Figure 8-4. Programming the Four Thresholds The four resistor values are calculated as follows:

• Choose the upper and lower UVLO thresholds (VUVH) and (VUVL). UV(HYS)UVH UVL VV VR1 20 A 20 A /c45/c61 /c61 /c109 /c109 (25) UVL 2.48V R1R2 /CharA0 V 2.48V /c180/c61 /c45 (26)
• Choose the upper and lower OVLO threshold (VOVH) and (VOVL). OVH OVLV VR3 21 A /c45/c61 /c109 (27) /c40 /c41 OVH 2.46V R3R4 V 2.46V /c180/c61 /c45 (28)
• When the R1 to R4 resistor values are known, the threshold voltages and hysteresis are calculated from the following: UVH 2.48VV 2.48V R1 20 A R2 /c233 /c249 /c230 /c246/c61 /c43 /c180 /c43 /c109 /c234 /c250 /c231 /c247 /c232 /c248/c235 /c251 (29) /c40 /c41 UVL 2.48V R1 R2V R2 /c180 /c43/c61 (30) UV(HYS)V R1 20 A/c61 /c180 /c109 (31) /c40 /c41 OVH 2.46V R3 R4V R4 /c180 /c43/c61 (32) OVL 2.46VV 2.46V R3 21 A R4 /c233 /c249 /c230 /c246/c61 /c43 /c180 /c45 /c109 /c234 /c250 /c231 /c247 /c232 /c248/c235 /c251 (33) LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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The minimum UVLO level is obtained by connecting the UVLO/EN pin to VIN as shown in Figure 8-5. Q1 is switched on when the VIN voltage reaches the POR EN threshold ( ≊8.6 V). The OVLO thresholds are set using R3, R4. Their values are calculated using the procedure in Option B. VIN UVLO/EN OVLO GND 10 k 2.48 V 2.46 V TIMER AND GATE LOGIC CONTROL VIN 21 PA 20 PA Figure 8-5. UVLO = POREN The OVLO function can be disabled by grounding the OVLO pin. The UVLO thresholds are set as described in Option B or Option C. For this design example, option B was used and the following options were targeted: V UVH = 38 V, V UVL = 35 V, VOVH = 65 V, and V OVL = 63 V. The V UVH and VOVL were chosen to be 5% below or above the input voltage range of 40 to 60 V to allow for some tolerance in the thresholds of the part. R1, R2, R3, and R4 are computed using the following equations: /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 UVH UVL UVL OVH OVL OVH V V 38/CharA0 V 35/CharA0 VR1 150k 20µA 20µA V V 65/CharA0 V 63/CharA0 VR3 95.24k21 µA 21 µA /c45 /c45/c61 /c61 /c61 /c87 /c180 /c180 /c87/c61 /c61 /c61 /c87 /c45 /c45 /c45 /c45/c61 /c61 /c61 /c87 /c180 /c180 /c87/c61 /c61 /c61 /c87 /c45 /c45 (34) Nearest available 1% resistors should be chosen. Set R1 = 150 k Ω, R2 = 11.5 kΩ, R3 = 95.3 kΩ, and R4 = 3.74 kΩ.

8.2.1.2.8 Power Good Pin

The Power Good indicator pin (PGD) is connected to the drain of an internal N-channel MOSFET capable of sustaining 80 V in the off-state and transients up to 100 V. An external pullup resistor is required at PGD to an appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin can be higher or lower than the voltages at VIN and OUT. PGD is switched high when the voltage at the FB pin exceeds the PGD threshold voltage. Typically, the output voltage threshold is set with a resistor divider from output to feedback, although the monitored voltage need not be the output voltage. Any other voltage can be monitored as long as the voltage at the FB pin does not exceed its maximum rating. Referring to the Functional Block Diagram, when the voltage at the FB pin is below its threshold, the 20-µA current source at FB is disabled. As the output voltage increases, taking FB above its threshold, the current source is enabled, sourcing current out of the pin, raising the voltage at FB to provide threshold hysteresis. The PGD output is forced low when either the UVLO/EN pin is below its threshold or the OVLO pin is above its threshold. The status of the PGD pin can be read through the PMBus interface in either the STATUS_WORD (79h) or DIAGNOSTIC_WORD (E1h) registers. www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: LM5066H ADVANCE INFORMATION

When the voltage at the FB pin increases above its threshold, the internal pulldown acting on the PGD pin is disabled allowing PGD to rise to V PGD through the pullup resistor, R PG, as shown in Figure 8-7 . The pullup voltage (VPGD) can be as high as 80 V, and can be higher or lower than the voltages at VIN and OUT. VDD is a convenient choice for V PGD as it allows interface to low voltage logic and avoids glitching on PGD during power-up. If a delay is required at PGD, suggested circuits are shown in Figure 8-8. In Figure 8-8(A), capacitor CPG adds delay to the rising edge, but not to the falling edge. In Figure 8-8(B), the rising edge is delayed by RPG1 + R PG2 and C PG, while the falling edge is delayed a lesser amount by R PG2 and C PG. Adding a diode across RPG2 (Figure 8-8(C)) allows for equal delays at the two edges, or a short delay at the rising edge and a long delay at the falling edge. OUT FB GND PGD GATE UV OV Q1 VOUT R 6 2.46 V 20 PA Figure 8-6. Programming the PGD Threshold GND RPG Power Good VPGD PGD Figure 8-7. Power Good Output GND RPG1 VPGD CPG PGD GND RPG1 Power Good VPGD CPG PGD RPG2 GND RPG1 VPGD CPG PGD RPG2 C) Short Delay at Rising Edge and Long Delay at Falling Edge or Equal Delays B) Long Delay at Rising Edge, Short Delay at Falling Edge A) Delay at Rising Edge Only Power Good Power Good Figure 8-8. Adding Delay to the Power Good Output Pin TI recommends to set the PG threshold 5% below the minimum input voltage to ensure that the PG is asserted under all input voltage conditions. For this example, PGDH of 38 V and PGDL of 35 V is targeted. R5 and R6 are computed using the following equations: PGDH PGDLV V 38/CharA0 V 35/CharA0 VR5 150k 20µA 20µA /c45 /c45/c61 /c61 /c61 /c87 (35) /c40 /c41 /c40 /c41PGDH /c180 /c180 /c87/c61 /c61 /c61 /c87 /c45 /c45 (36) Nearest available 1% resistors should be chosen. Set R5 = 150 kΩ and R6 = 10.5 kΩ.

8.2.1.2.9 Input and Output Protection

Proper operation of the LM5066Hx hot swap circuit requires a voltage clamping element present on the supply side of the connector into which the hot swap circuit is plugged in. A TVS is ideal, as depicted in Figure 8-9. The TVS is necessary to absorb the voltage transient generated whenever the hot swap circuit shuts off the load LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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current. This effect is the most severe during a hot-short when a large current is suddenly interrupted when the FET shutts off. The TVS should be chosen to have minimal leakage current at V IN,MAX and to clamp the voltage to under 100V during hot-short events. For many high power applications 5.0SMDJ60A is a good choice. If the load powered by the LM5066Hx hot swap circuit has inductive characteristics, a Schottky diode is required across the LM5066Hx’s output, along with some load capacitance. The capacitance and the diode are necessary to limit the negative excursion at the OUT pin when the load current is shut off. LM5066H1 Inductive Load VIN GND +48 V GND LIVE POWER SOURCE PLUG-IN BOARD OUT SENSEVIN_K AGND VOUT RSNSVIN CL Copyright © 2025, Texas Instruments Incorporated Figure 8-9. Output Diode Required for Inductive Loads www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: LM5066H ADVANCE INFORMATION

8.2.1.3 Application Curves

Figure 8-10. Insertion Delay VIN = 54V Figure 8-11. Start-Up Figure 8-12. Start-Up Into Short Circuit Figure 8-13. Start-Up Into Short Circuit Figure 8-14. Undervoltage Lockout Figure 8-15. Overvoltage Lockout LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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Figure 8-16. Load Transient Figure 8-17. Load Transient Followed by Overcurrent Event Figure 8-18. Overcurrent Event (zoomed) Figure 8-19. Hotshort on Output (zoomed out) Figure 8-20. Hotshort on Output (zoomed in)

8.3 Power Supply Recommendations

In general, the LM5066Hx behavior is more reliable if it is supplied from a very regulated power supply. However, high-frequency transients on a backplane are not uncommon due to adjacent card insertions or faults. If this is expected in the end system, TI recommends to place a 1-µF ceramic capacitor to ground close to the source of the hotswap MOSFET. This reduces the common mode seen by VIN_K and SENSE. Additional filtering may be necessary to avoid nuisance trips.

8.4 Layout

8.4.1 Layout Guidelines

The following guidelines should be followed when designing the PC board for the LM5066Hx: www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: LM5066H ADVANCE INFORMATION

1. Place the LM5066Hx close to the board’s input connector to minimize trace inductance from the connector to the MOSFET. 2. Place a TVS, Z1, directly adjacent to the VIN and GND pins of the LM5066Hx to help minimize voltage transients which may occur on the input supply line. The TVS should be chosen such that the peak VIN is just lower the TVS reverse-bias voltage. Transients of 20 V or greater over the nominal input voltage can easily occur when the load current is shut off. TI recommends to test the VIN input voltage transient performance of the circuit by current limiting or shorting the load and measuring the peak input voltage transient. 3. Place a 1µF ceramic capacitor as close as possible to VREF pin. 4. Place a 1µF ceramic capacitor as close as possible to VDD pin. 5. The sense resistor (RSNS) should be placed close to the LM5066Hx. A trace should connect the VIN pad and Q1 pad of the sense resistor to VIN_K and SENSE pins, respectively. Connect RSNS using the Kelvin techniques as shown in Figure 8-22. 6. The high current path from the board’s input to the load (through Q1), and the return path, should be parallel and close to each other to minimize loop inductance. 7. The AGND and GND connections should be connected at the pins of the device. The ground connections for the various components around the LM5066Hx should be connected directly to each other, and to the LM5066Hx’s GND and AGND pin connection, and then connected to the system ground at one point. Do not connect the various component grounds to each other through the high current ground line. 8. Provide adequate thermal sinking for the series pass device (Q1) to help reduce stresses during turn-on and turn-off. 9. The board’s edge connector can be designed such that the LM5066Hx detects through the UVLO/EN pin that the board is being removed, and responds by turning off the load before the supply voltage is disconnected. For example, in Figure 8-21, the voltage at the UVLO/EN pin goes to ground before VIN is removed from the LM5066Hx as a result of the shorter edge connector pin. When the board is inserted into the edge connector, the system voltage is applied to the LM5066Hx’s VIN pin before the UVLO voltage is taken high, thereby allowing the LM5066Hx to turn on the output in a controlled fashion.

8.4.2 Layout Example

VIN_K UVLO/EN OVLO AGND SDAI FB CL VDD ADR0 ADR1 ADR2 LM5066H1 VIN GND SDAO MMBT3904 Figure 8-21. Recommended Board Connector Design LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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VIN_K SENSE FROM SYSTEM INPUT VOLTAGE TO DRAIN OF MOSFET Q1 HIGH CURRENT PATH VIN Figure 8-22. Sense Resistor Connections www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: LM5066H ADVANCE INFORMATION

9 Device and Documentation Support

9.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Trademarks

PMBus™ is a trademark of SMIF, Inc. TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES October 2025 * Initial Release

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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11.1 Package Option Addendum

Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/Ball material (4) MSL rating/Peak reflow (5) Op temp (°C) Part marking (6) PLM5066H1PWPR Preview Preproduction TSSOP (PWP) | 28 3000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR –40 to 125 P5066H1 PLM5066H2NLPR Preview Preproduction QFN (NLP) | 35 3000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR –40 to 125 PL5066H2 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 ADVANCE INFORMATION Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: LM5066H

11.2 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PLM5066H1PWPR TSSOP PWP 28 3000 330 16.4 6.9 10.2 1.8 12 16 Q1 PLM5066H2NLPR QFN NLP 35 3000 180 8.4 2.3 2.3 1.15 4 8 Q1 LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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Product Folder Links: LM5066H ADVANCE INFORMATION

TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PLM5066H1PWPR TSSOP PWP 28 3000 353 353 32 PLM5066H2NLPR QFN NLP 35 3000 367 367 38 www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: LM5066H ADVANCE INFORMATION

11.3 Mechanical Data

www.ti.com PACKAGE OUTLINE C26X 0.65 2X8.45 28X 0.300.17

6.66.2 TYP

0.150.050.25GAGE PLANE0-8 1.2 MAX 2X (0.6)NOTE 5 2X (0.23)NOTE 55.624.92 2.942.24 B4.54.3 A 9.89.6NOTE 3 0.750.50 (0.15) TYP PowerPAD TSSOP - 1.2 mm max heightPWP0028VSMALL OUTLINE PACKAGE 4230409/A 01/2024 14 15 0.1CAB PIN 1 INDEXAREA SEE DETAIL A 0.1C SEATINGPLANE PowerPAD is a trademark of Texas Instruments.TYPICAL TM A 20 SCALE 2.000 DETAIL ATHERMALPAD1 14 15 LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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Product Folder Links: LM5066H ADVANCE INFORMATION

www.ti.com EXAMPLE BOARD LAYOUT 0.05 MAXALL AROUND0.05 MINALL AROUND 26X (0.65) (5.8) (R0.05) TYP (3.4)NOTE 9 (9.7)NOTE 9 (1.3) TYP (0.6)(1.2) TYP(0.2) TYPVIA (2.94) (5.62) PowerPAD TSSOP - 1.2 mm max heightPWP0028VSMALL OUTLINE PACKAGE TM LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE: 8X SYMM SYMM1 14 15 28METAL COVEREDBY SOLDER MASK SOLDER MASKDEFINED PAD SEE DETAILS 15.000 METALSOLDER MASKOPENINGMETAL UNDERSOLDER MASKSOLDER MASKOPENINGEXPOSED METALEXPOSED METALNON-SOLDER MASKSOLDER MASK DETAILSDEFINED(PREFERRED)SOLDER MASKDEFINED www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: LM5066H ADVANCE INFORMATION

www.ti.com EXAMPLE STENCIL DESIGN 26X (0.65) (5.8) (R0.05) TYP (5.62)BASED ON0.125 THICKSTENCIL (2.94)BASED ON0.125 THICKSTENCIL PowerPAD TSSOP - 1.2 mm max heightPWP0028VSMALL OUTLINE PACKAGE 4230409/A 01/2024 TM SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCILSCALE: 8X SYMM SYMM 14 15 28METAL COVEREDBY SOLDER MASK SEE TABLE FORDIFFERENT OPENINGSFOR OTHER STENCILTHICKNESSES LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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Product Folder Links: LM5066H ADVANCE INFORMATION

www.ti.com PACKAGE OUTLINE 7.16.9 5.14.9 0.80.70.050.00 2X 3.125 .000 PKG 0 4.850.1 39X 0.30.231X 0.60.4 2X 2.125 ()0.275 0.6251.125 2.850.1 8X 0.60.4(0.1) TYP WQFN - 0.8 mm max heightNLP0035APLASTIC QUAD FLATPACK - NO LEAD 4231589/B 03/2025 0.08C PIN 1 INDEX AREA SEATING PLANE 0.1CAB0.05CPIN 1 ID(45X 0.3)1 11 17 2735 SCALE 2.000 AB C www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: LM5066H ADVANCE INFORMATION

www.ti.com EXAMPLE BOARD LAYOUT .000 PKG 0 .000 PKG 0 0.05 MAXALL AROUND0.05 MINALL AROUND ()1.93X ()0.925 3X ()0.275 3X ()1.475()2.45 (4.85) ()0.53X ()0.9 3X ()1.45 (0.2) TYPVIA (R0.05) TYP (2.85) 8X(0.7)8X(0.25) WQFN - 0.8 mm max heightNLP0035APLASTIC QUAD FLATPACK - NO LEAD EXPOSED METAL SHOWNLAND PATTERN EXAMPLESCALE: 15X 11 17 2735 METAL EDGESOLDER MASKOPENINGEXPOSEDMETALNON SOLDER MASKDEFINED(PREFERRED)SOLDER MASK DETAILS METAL UNDERSOLDER MASKSOLDER MASKOPENINGEXPOSEDMETALSOLDER MASKDEFINED LM5066H SNVSCT1 – OCTOBER 2025 www.ti.com

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Product Folder Links: LM5066H ADVANCE INFORMATION

www.ti.com EXAMPLE STENCIL DESIGN .000 PKG 0 .000 PKG 0 (R0.05) TYP 2X ()1.525 2X ()2.075 4X ()1 4X ()0.45 8X (1)8X(1.25) WQFN - 0.8 mm max heightNLP0035APLASTIC QUAD FLATPACK - NO LEAD 4231589/B 03/2025NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCILSCALE: 15X EXPOSED PAD: 3672% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE 11 17 2735 www.ti.com LM5066H SNVSCT1 – OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: LM5066H ADVANCE INFORMATION

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