LM2902LV_19 TI1 | Alldatasheet
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= 1 + V V OUT IN R R F G 1 + sR C1 1( ( ( ( 2/c112 R C1 1 f =/c45 3 dB Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM2902LV, LM2904LV SBOS960A – SEPTEMBER 2018– REVISED MAY 2019 LM290xLVIndustryStandard,LowVoltageOperationalAmplifiers
1 Features
1• Industry standard amplifier for cost-sensitive systems
- Low input offset voltage: ±1 mV
- Common-mode voltage range includes ground
- Unity-gain bandwidth: 1 MHz
- Low broadband noise: 40 nV/√Hz
- Low quiescent current: 90 µA/Ch
- Unity-gain stable
- Operational at supply voltages from 2.7 V to 5.5 V
- Offered in dual- and quad-channel variants
- Robust ESD specification: 2-kV HBM
- Extended temperature range: –40°C to 125°C
2 Applications
- Cordless appliances
- Uninterruptible power supply
- Battery pack, charger, and test equipment
- Power supply modules
- Environmental sensors signal conditioning
- Field transmitter: temperature sensors
- Oscilloscopes, digital multimeters, and signal analyzers
- Rack mount server
- HVAC: heating, ventilating, and air conditioning
- DC motor control
- Low-side current sensing
3 Description
The LM290xLV family includes the dual LM2904LV and quad LM2902LV operational amplifiers, or op amps. The devices operate from a low voltage of 2.7 V to 5.5 V. These op amps supply an alternative to the LM2904 and LM2902 in low-voltage applications that are sensitive to cost. Some applications are large appliances, smoke detectors, and personal electronics. The LM290xLV devices supply better performance than the LM290x devices at low voltage, and have lower power consumption. The op amps are stable at unity gain, and do not have reverse phase in overdrive conditions. The design for ESD gives the LM290xLV family an HBM specification for a minimum of 2 kV. The LM290xLV family is available in packages that have industry standards. The packages include SOIC, VSSOP, and TSSOP packages. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LM2902LV SOIC (14) 8.65 mm × 3.91 mm TSSOP (14) 4.40 mm × 5.00 mm LM2904LV SOIC (8) 3.91 mm × 4.90 mm TSSOP (8) 3.00 mm × 4.40 mm VSSOP (8) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Package is for preview only. Single-Pole, Low-Pass Filter
LM2902LV, LM2904LV SBOS960A – SEPTEMBER 2018– REVISED MAY 2019 www.ti.com Product Folder Links: LM2902LV LM2904LV Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Table of Contents
11.3 Receiving Notification of Documentation Updates 21
12 Mechanical, Packaging, and Orderable
4 Revision History
Changes from Original (September 2018) to Revision A Page
2IN1± 7 OUT2 3IN1+ 6 IN2 ± 4V± 5 IN2+ Not to scale LM2902LV, LM2904LV www.ti.com SBOS960A – SEPTEMBER 2018– REVISED MAY 2019 Product Folder Links: LM2902LV LM2904LV Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated
5 Pin Configuration and Functions
LM2904LV D, DGK, PW, DDF Packages 8-Pin SOIC, VSSOP, TSSOP, SOT-23 Top View Pin Functions: LM2904LV PIN I/O DESCRIPTION NAME NO. IN1– 2 I Inverting input, channel 1 IN1+ 3 I Noninverting input, channel 1 IN2– 6 I Inverting input, channel 2 IN2+ 5 I Noninverting input, channel 2 OUT1 1 O Output, channel 1 OUT2 7 O Output, channel 2 V– 4 I or — Negative (low) supply or ground (for single-supply operation) V+ 8 I Positive (high) supply
2IN1± 13 IN4 ± 3IN1+ 12 IN4+ 4V+ 11 V ± 5IN2+ 10 IN3+ 6IN2± 9 IN3 ± 7OUT2 8 OUT3 Not to scale LM2902LV, LM2904LV SBOS960A – SEPTEMBER 2018– REVISED MAY 2019 www.ti.com Product Folder Links: LM2902LV LM2904LV Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated LM2902LV D, PW Packages 14-Pin SOIC, TSSOP Top View Pin Functions: LM2902LV PIN I/O DESCRIPTION NAME NO. IN1– 2 I Inverting input, channel 1 IN1+ 3 I Noninverting input, channel 1 IN2– 6 I Inverting input, channel 2 IN2+ 5 I Noninverting input, channel 2 IN3– 9 I Inverting input, channel 3 IN3+ 10 I Noninverting input, channel 3 IN4– 13 I Inverting input, channel 4 IN4+ 12 I Noninverting input, channel 4 OUT1 1 O Output, channel 1 OUT2 7 O Output, channel 2 OUT3 8 O Output, channel 3 OUT4 14 O Output, channel 4 V– 11 I or — Negative (low) supply or ground (for single-supply operation) V+ 4 I Positive (high) supply
LM2902LV, LM2904LV www.ti.com SBOS960A – SEPTEMBER 2018– REVISED MAY 2019 Product Folder Links: LM2902LV LM2904LV Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less. (3) Short-circuit to ground, one amplifier per package.
6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage, ([V+] – [V–]) 0 6 V Signal input pins Voltage(2) Common-mode (V–) – 0.5 (V+) + 0.5 V Differential (V+) – (V–) + 0.2 V Current(2) –10 10 mA Output short-circuit(3) Continuous Operating, TA –55 125 °C Operating junction temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted) MIN MAX UNIT VS Supply voltage [(V+) – (V–)] 2.7 5.5 V VIN Input-pin voltage range (V–) – 0.1 (V+) – 1 V TA Specified temperature –40 125 °C
LM2902LV, LM2904LV SBOS960A – SEPTEMBER 2018– REVISED MAY 2019 www.ti.com Product Folder Links: LM2902LV LM2904LV Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
6.4 Thermal Information: LM2904LV
THERMAL METRIC(1) LM2904LV UNITD (SOIC) DGK (VSSOP) PW (TSSOP) DDF (SOT-23)
8 PINS 8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 207.9 201.2 200.7 183.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 92.8 85.7 95.4 112.5 °C/W RθJB Junction-to-board thermal resistance 129.7 122.9 128.6 98.2 °C/W ψJT Junction-to-top characterization parameter 26 21.2 27.2 18.8 °C/W ψJB Junction-to-board characterization parameter 127.9 121.4 127.2 97.6 °C/W
LM2902LV, LM2904LV www.ti.com SBOS960A – SEPTEMBER 2018– REVISED MAY 2019 Product Folder Links: LM2902LV LM2904LV Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
6.5 Thermal Information: LM2902LV
THERMAL METRIC(1) LM2902LV UNITD (SOIC) PW (TSSOP)
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 102.1 148.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 56.8 68.1 °C/W RθJB Junction-to-board thermal resistance 58.5 92.7 °C/W ψJT Junction-to-top characterization parameter 20.5 16.9 °C/W ψJB Junction-to-board characterization parameter 58.1 91.8 °C/W
LM2902LV, LM2904LV SBOS960A – SEPTEMBER 2018– REVISED MAY 2019 www.ti.com Product Folder Links: LM2902LV LM2904LV Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated
6.6 Electrical Characteristics
For VS = (V+) – (V–) = 2.7 V to 5.5 V (±1.35 V to ±2.75 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage VS = 5 V ±1 ±3 mV VS = 5 V, TA = –40°C to 125°C ±5 dVOS/dT VOS vs temperature TA = –40°C to 125°C ±4 µV/°C PSRR Power-supply rejection ratio VS = 2.7 V to 5.5 V, VCM = (V–) 80 100 dB INPUT VOLTAGE RANGE VCM Common-mode voltage range No phase reversal (V–) – 0.1 (V+) – 1 V CMRR Common-mode rejection ratio TA = –40°C to 125°C 84 dB TA = –40°C to 125°C 63 92 INPUT BIAS CURRENT IB Input bias current VS = 5 V ±15 pA IOS Input offset current ±5 pA NOISE En Input voltage noise (peak-to-peak) ƒ = 0.1 Hz to 10 Hz, VS = 5 V 5.1 µVPP en Input voltage noise density ƒ = 1 kHz, VS = 5 V 40 nV/√Hz INPUT CAPACITANCE CID Differential 2 pF CIC Common-mode 5.5 pF OPEN-LOOP GAIN AOL Open-loop voltage gain dB FREQUENCY RESPONSE GBW Gain-bandwidth product VS = 5 V 1 MHz φm Phase margin VS = 5.5 V, G = 1 75 ° SR Slew rate VS = 5 V 1.5 V/µs tS Settling time To 0.1%, VS = 5 V, 2-V step, G = 1, CL = 100 pF 4 µs To 0.01%, VS = 5 V, 2-V step, G = 1, CL = 100 pF 5 tOR Overload recovery time VS = 5 V, VIN × gain > VS 1 µs THD+N Total harmonic distortion + noise VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = 1, ƒ = 1 kHz, 80-kHz measurement BW 0.005% OUTPUT VOH Voltage output swing from positive supply RL ≥ 2 kΩ, TA = –40°C to 125°C 1 V VOL Voltage output swing from negative supply RL ≤ 10 kΩ, TA = –40°C to 125°C 40 75 mV ISC Short-circuit current VS = 5.5 V ±40 mA ZO Open-loop output impedance VS = 5 V, ƒ = 1 MHz 1200 Ω POWER SUPPLY VS Specified voltage range 2.7 (±1.35) 5.5 (±2.75) V IQ Quiescent current per amplifier IO = 0 mA, VS = 5.5 V 90 150 µA IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C 160
6.7 Typical Characteristics
Figure 1. IB and IOS vs Common-Mode Voltage Figure 2. Open-Loop Gain vs Temperature Figure 3. Open-Loop Gain and Phase vs Frequency Figure 4. Open-Loop Gain vs Output Voltage Figure 5. Closed-Loop Gain vs Frequency
V (Ground) /c45 VBIAS2 VBIAS1 Class AB Control Circuitry VO LM2902LV, LM2904LV SBOS960A – SEPTEMBER 2018– REVISED MAY 2019 www.ti.com Product Folder Links: LM2902LV LM2904LV Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated
7 Detailed Description
7.1 Overview
The LM290xLV family of low-power op amps is intended for cost-optimized systems. These devices operate from 2.7 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications. The input common-mode voltage range includes the negative rail and allows the LM290xLV family to be used in many single-supply applications.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Operating Voltage
The LM290xLV family of op amps is specified for operation from 2.7 V to 5.5 V. In addition, many specifications apply from –40°C to 125°C. Parameters that vary significantly with operating voltages or temperature are shown in the Electrical Characteristics section.
7.3.2 Common-Mode Input Range Includes Ground
The input common-mode voltage range of the LM290xLV family extends to the negative supply rail and within 1 V below the positive rail for the full supply voltage range of 2.7 V to 5.5 V. This performance is achieved with a P‑channel differential pair, as shown in the Functional Block Diagram. Additionally, a complementary N‑channel differential pair has been included in parallel to eliminate issues with phase reversal that are common with previous generations of op amps. However, the N-channel pair is not optimized for operation, and significant performance degradation occurs while this pair is operational. TI recommends limiting any voltage applied at the inputs to at least 1 V below the positive supply rail (V+) to ensure that the op amp conforms to the specifications detailed in the Electrical Characteristics section.
7.3.3 Overload Recovery
state. After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. the slew time. The overload recovery time for the LM290xLV family is typically 1 µs.
7.3.4 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. both before and during product assembly. circuitry is intended to remain inactive during normal circuit operation. Figure 30. Equivalent Internal ESD Circuitry
7.3.5 EMI Susceptibility and Input Filtering
information, see EMI Rejection Ratio of Operational Amplifiers available for download from www.ti.com.
7.4 Device Functional Modes
8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.2 Typical Application
Figure 31 shows the LM290xLV device configured in a low-side current sensing application. Figure 31. LM290xLV Device in a Low-Side, Current-Sensing Application
8.2.1 Design Requirements
- Load current: 0 A to 1 A
- Output voltage: 3.5 V
- Maximum shunt voltage: 100 mV
8.2.2 Detailed Design Procedure
sizes the resistors RF and RG, to set the gain of the LM290xLV device to 35 V/V.
8.2.3 Application Curve
Figure 32. Low-Side, Current-Sense Transfer Function
9 Power Supply Recommendations
significant variance with regard to operating voltage or temperature. Absolute Maximum Ratings section.
9.1 Input and ESD Protection
protection primarily consists of current-steering diodes connected between the input and power-supply pins. input and the value must be kept to a minimum in noise-sensitive applications. Figure 33. Input Current Protection
10 Layout
10.1 Layout Guidelines
- Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single- supply applications.
- Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care to physically separate digital and analog grounds. Use thermal signatures or EMI measurement techniques to determine where the majority of the ground current is flowing and be sure to route this path away from sensitive analog circuitry. For more detailed information, see Circuit Board Layout Techniques.
- To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace at a 90° angle is much better as opposed to running the traces in parallel with the noisy trace.
- Place the external components as close to the device as possible, as shown in Figure 35. Keeping RF and RG close to the inverting input minimizes parasitic capacitance.
- Keep the length of input traces as short as possible. Remember that the input traces are the most sensitive part of the circuit.
- Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly reduce leakage currents from nearby traces that are at different potentials.
- Cleaning the PCB following board assembly is recommended for best performance.
- Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
Figure 34. Schematic Representation for Figure 35
Figure 35. Layout Example
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
- Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
11.2 Related Links
resources, tools and software, and quick access to order now. Table 1. Related Links
11.3 Receiving Notification of Documentation Updates
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
solve problems with fellow engineers. contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
www.ti.com 30-May-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples LM2902LVIDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LM2902LV LM2902LVIPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 LM2902LV LM2904LVIDDFR PREVIEW SOT-23-THIN DDF 8 3000 TBD Call TI Call TI -40 to 125 LM2904LVIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1SQX LM2904LVIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 2904LV LM2904LVIPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 2904 PLM2904LVIDDFR ACTIVE SOT-23-THIN DDF 8 3000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
www.ti.com 30-May-2019 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 15-May-2019 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM2902LVIDR SOIC D 14 2500 336.6 336.6 41.3 LM2902LVIPWR TSSOP PW 14 2000 366.0 364.0 50.0 LM2904LVIDGKR VSSOP DGK 8 2500 366.0 364.0 50.0 LM2904LVIDR SOIC D 8 2500 336.6 336.6 41.3 LM2904LVIPWR TSSOP PW 8 2000 366.0 364.0 50.0 PACKAGE MATERIALS INFORMATION www.ti.com 15-May-2019 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C TYP2.95 2.65
1.1 MAX
6X 0.65 8X 0.4 0.2 1.95 TYP0.20 0.08 0 - 8 0.1 0.0 0.25 GAGE PLANE 0.6 0.3 A NOTE 3 2.95 2.85 B 1.65 1.55 4222047/B 11/2015 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 1 8
0.1 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT (2.6) 8X (1.05) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4222047/B 11/2015 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE SCALE:15X 4 5 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (2.6) 6X (0.65) 8X (0.45) 8X (1.05) (R ) TYP0.05 4222047/B 11/2015 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X
www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800
www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM
www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5
www.ti.com PACKAGE OUTLINE C TYP6.6 6.2
1.2 MAX
6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800
www.ti.com EXAMPLE BOARD LAYOUT (5.8)
0.05 MAX
0.05 MIN
8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X
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