PLM25183QNGURQ1

Texas Instruments

LM25183-Q1 42-VIN PSR Flyback DC/DC Converter with 65-V, 2.5-A Integrated MOSFET

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ADVANCE□INFORMATION Load Current (mA) Efficiency (%) 0 200 400 600 800 D101 VIN = 6 V VIN = 12 V VIN = 24 V VIN = 36 V VOUT = 12 V SW FB VIN EN/UVLO TC GND RSET LM25183-Q1 COUT CIN F F VIN = 4.5 V...42 V 1 : 1 DFLY RFB 124 k: DZ DF SS/BIAS RSET 12.1 k: Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. LM25183-Q1 SNVSBJ4 –APRIL 2020 LM25183-Q142-VINPSRFlybackDC/DCConverterwith65-V,2.5-AIntegratedMOSFET

1 Features

1• AEC-Q100-qualified for automotive applications – Device temperature grade 1: –40°C to 125°C ambient temperature range

Functional safety capable – Documentation available to aid functional safety system design
Designed for reliable and rugged applications – Wide input voltage range of 4.5 V to 42 V – Robust solution with only one component crossing the isolation barrier – ±1.5% total output regulation accuracy – Optional VOUT temperature compensation – –40°C to +150°C junction temperature range
Integration reduces solution size and cost – Integrated 65-V, 0.11-Ω power MOSFET – No optocoupler or transformer auxiliary winding required for VOUT regulation
High-efficiency PSR flyback operation – Quasi-resonant MOSFET turnoff in BCM – Single- and multi-output implementations
Ultra-low conducted and radiated EMI signatures – Soft switching avoids diode reverse recovery – Optimized for CISPR 25 Class 5 requirement
Create a custom flyback regulator design using WEBENCH® Power Designer

2 Applications

Automotive HEV/EV powertrain systems
Sub-AM band automotive body electronics
Traction inverter: IGBT and SiC gate driver supplies

3 Description

The LM25183-Q1 is a primary-side regulated (PSR) flyback converter with high efficiency over a wide input voltage range of 4.5 V to 42 V. The isolated output voltage is sampled from the primary-side flyback voltage, eliminating the need for an optocoupler, voltage reference, or third winding from the transformer for output voltage regulation. The high level of integration results in a simple, reliable, and high-density design with only one component crossing the isolation barrier. Boundary conduction mode (BCM) switching enables a compact magnetic solution and better than ±1.5% load and line regulation performance. An integrated 65-V power MOSFET provides output power up to 10 W with enhanced headroom for line transients. The LM25183-Q1 simplifies the implementation of isolated DC/DC supplies with optional features to optimize performance for the target end equipment. The output voltage is set by one resistor, while an optional resistor improves output voltage accuracy by negating the thermal coefficient of the flyback diode voltage drop. Additional features include an internally- fixed or externally-programmable soft-start, optional bias supply connection for higher efficiency, precision enable input with hysteresis for adjustable line UVLO, hiccup-mode overload protection, and thermal shutdown protection with automatic recovery. The LM25183-Q1 converter is qualified to automotive AEC-Q100 grade 1 and is available in 8-pin WSON package with 0.8-mm pin pitch and wettable flanks. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LM25183-Q1 WSON (8) 4.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Typical Efficiency, VOUT = 12 V

11.3 Receiving Notification of Documentation Updates 33

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES April 2020 * Initial release

ADVANCE□INFORMATION EN/UVLO VIN FB GND RSET SS/BIAS TC SW LM25183-Q1 www.ti.com SNVSBJ4 –APRIL 2020 Product Folder Links: LM25183-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated (1) P = Power, G = Ground, I = Input, O = Output

5 Pin Configuration and Functions

8-Pin WSON With Wettable Flanks Top View Pin Functions PIN I/O(1) DESCRIPTION NO. NAME 1 SW P Switch node that is internally connected to the drain of the N-channel power MOSFET. Connect to the primary-side switching terminal of the flyback transformer. 2 FB I Primary-side feedback pin. Connect a resistor from FB to SW. The ratio of the FB resistor to the resistor at the RSET pin sets the output voltage. 3 VIN P/I Input supply connection. Source for internal bias regulators and input voltage sensing pin. Connect directly to the input supply of the converter with short, low impedance paths.

4 EN/UVLO I

Enable input and undervoltage lockout (UVLO) programming pin. If the EN/UVLO voltage is below 1.1 V, the converter is in shutdown mode with all functions disabled. If the EN/UVLO voltage is greater than 1.1 V and below 1.5 V, the converter is in standby mode with the internal regulator operational and no switching. If the EN/UVLO voltage is above 1.5 V, the start-up sequence begins.

5 SS/BIAS I

Soft start or bias input. Connect a capacitor from SS/BIAS to GND to adjust the output start-up time and input inrush current. If SS/BIAS is left open, the internal 6-ms soft-start timer is activated. Connect an external supply to SS/BIAS to supply bias to the internal voltage regulator and enable internal soft start.

6 TC I

Temperature compensation pin. Tie a resistor from TC to RSET to compensate for the temperature coefficient of the forward voltage drop of the secondary diode, thus improving regulation at the secondary-side output. 7 RSET I Reference resistor tied to GND to set the reference current for FB. Connect a 12.1-kΩ resistor from RSET to GND. 8 GND G Analog and power ground. Ground connection of internal control circuits and power MOSFET.

ADVANCE□INFORMATION LM25183-Q1 SNVSBJ4 –APRIL 2020 www.ti.com Product Folder Links: LM25183-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)(1) MIN MAX UNIT Input voltage VIN to GND –0.3 45 V EN/UVLO to GND –0.3 45 TC to GND –0.3 6 SS/BIAS to GND –0.3 14 FB to GND –0.3 45.3 FB to VIN –0.3 0.3 RSET to GND –0.3 3 Output voltage SW to GND –1.5 70 V SW to GND (20-ns transient) –3 Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –55 150 °C (1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002 HBM ESD Classification Level 2 (1) ±2000 VCharged device model (CDM), per AEC Q100-011 CDM ESD Classification Level C4B All pins except 1, 4, 5, and 8 ±500 Pins 1, 4, 5, and 8 ±750

6.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage 4.5 42 V VSW SW voltage 65 V VEN/UVLO EN/UVLO voltage 42 V VSS/BIAS SS/BIAS voltage 13 V TJ Operating junction temperature –40 150 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) LM25183-Q1 UNITNGU (WSON)

8 PINS

RΘJA Junction-to-ambient thermal resistance 41.3 °C/W RΘJC(top) Junction-to-case (top) thermal resistance 34.7 °C/W RΘJB Junction-to-board thermal resistance 19.1 °C/W ΨJT Junction-to-top characterization parameter 0.3 °C/W ΨJB Junction-to-board characterization parameter 19.2 °C/W RΘJC(bot) Junction-to-case (bottom) thermal resistance 3.2 °C/W

6.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits aaply over the full –40°C to 150°C junction temperature range unless otherwise indicated. VIN = 12 V and VEN/UVLO = 2 V unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ISHUTDOWN VIN shutdown current VEN/UVLO = 0 V 3 µA IACTIVE VIN active current VEN/UVLO = 2.5 V, VRSET = 1.8 V 260 375 µA IACTIVE-BIAS VIN current with BIAS connected VSS/BIAS = 5 V 25 50 µA ENABLE AND INPUT UVLO VSD-FALLING Shutdown threshold VEN/UVLO falling 0.3 V VSD-RISING Standby threshold VEN/UVLO rising 0.8 1.1 V VUV-RISING Enable threshold VEN/UVLO rising 1.45 1.5 1.53 V VUV-HYST Enable voltage hysteresis VEN/UVLO falling 0.04 0.05 V IUV-HYST Enable current hysteresis VEN/UVLO = 1.6 V 4.2 5 5.5 µA FEEDBACK IRSET RSET current RRSET = 12.1 kΩ 100 µA VRSET RSET regulation voltage RRSET = 12.1 kΩ 1.191 1.21 1.224 V VFB-VIN1 FB to VIN voltage IFB = 80 µA –40 mV VFB-VIN2 FB to VIN voltage IFB = 120 µA 40 mV SWITCHING FREQUENCY FSW-MIN Minimum switching frequency 10 kHz FSW-MAX Maximum switching frequency 350 kHz tON-MIN Minimum switch on-time 140 ns DIODE THERMAL COMPENSATION VTC TC voltage ITC = ±10 µA, TJ = 25°C 1.2 1.27 V POWER SWITCHES RDS(on) MOSFET on-state resistance ISW = 100 mA 0.11 Ω SOFT-START AND BIAS ISS SS ext capacitor charging current 5 µA tSS Internal SS time 6 ms VBIAS-UVLO- RISE BIAS enable voltage VSS/BIAS rising 4.25 4.45 V VBIAS-UVLO- HYST BIAS UVLO hysteresis VSS/BIAS falling 150 mV CURRENT LIMIT ISW-PEAK Peak current limit threshold 2.25 2.5 2.77 A THERMAL SHUTDOWN TSD Thermal shutdown threshold TJ rising 175 °C TSD-HYS Thermal shutdown hysteresis 10 °C

1 Ps/div

6.6 Typical Characteristics

VIN = 24 V, VEN/UVLO = 2 V (unless otherwise stated). Figure 1. Efficiency versus Load Figure 2. Output Voltage versus Load Figure 3. Switching Waveform in BCM Figure 4. Switching Waveform in DCM Figure 5. Start-up Characteristic Figure 6. ENABLE ON/OFF Characteristic

ADVANCE□INFORMATION LM25183-Q1CIN CSS VIN NP : NS EN/UVLO VIN SW FB SS/BIASGND TC RSET RFB VREF COMP Internal SS SAMPLED FEEDBACK FB 65-V Power MOSFET Standby Shutdown 1.1 V VDD VDD UVLO BIAS REGULATOR THERMAL SHUTDOWN SS/BIAS VDD VDD VIN 2.5 A ILIM TRIMMED REFERENCE RSET TC REGULATION RTC VOUT COUT DFLY CONTROL LOGIC 1.5 V 1.45 V gm 5 PA DF DZ LM25183-Q1 www.ti.com SNVSBJ4 –APRIL 2020 Product Folder Links: LM25183-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The LM25183-Q1 primary-side regulated (PSR) flyback converter is a high-density, cost-effective solution for automotive and industrial systems requiring less than 15 W of isolated DC/DC power. This compact, easy-to-use flyback converter with low IQ can be applied over a wide input voltage range from 4.5 V to 42 V, with operation down to 3.5 V after start-up. Innovative frequency and current amplitude modulation enables high conversion efficiency across the entire load and line range. Primary-side regulation of the isolated output voltage using sampled values of the primary winding voltage eliminates the need for an opto-coupler or an auxiliary transformer winding for feedback. Regulation performance that rivals that of traditional opto-coupler solutions is achieved without the associated cost, solution size, and reliability concerns. The LM25183-Q1 converter services a wide range of applications including automotive on-board chargers and IGBT-based motor drives for HEV/EV systems.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Integrated Power MOSFET

The LM25183-Q1 is a flyback dc/dc converter with integrated 65-V, 4.1-A N-channel power MOSFET. During the MOSFET on-time, the transformer primary current increases from zero with a slope of VIN / LMAG (where LMAG is the transformer primary-referred magnetizing inductance) while the output capacitor supplies the load current. When the high-side MOSFET is turned off by the control logic, the switch (SW) voltage VSW swings up to approximately VIN + (NPS × VOUT), where NPS = NP/NS is the primary-to-secondary turns ratio of the transformer. The magnetizing current flows in the secondary side through the flyback diode, charging the output capacitor and supplying current to the load. Duty cycle D is defined as tON / tSW, where tON is the MOSFET conduction time and tSW is the switching period. Figure 15 shows a typical schematic of the LM25183-Q1 PSR flyback circuit. Components denoted in red are optional depending on the application requirements.

Figure 15. LM25183-Q1 Flyback Converter Schematic (Optional Components in Red)

7.3.2 PSR Flyback Modes of Operation

possible modes of operation as illustrated in Figure 16. Figure 16. Three Modes of Operation Illustrated by Variation of Switching Frequency With Load frequency increases to maintain BCM operation. Equation 1 gives the duty cycle of the flyback converter in BCM.

ADVANCE□INFORMATION SET FB OUT D PS REF RR V V N V MAG PRI-PK(DCM) SW(DCM) DCM IN L I F D V OUT OUT D PRI-PK(DCM) MAG SW(DCM)

2 I V VI L F

MAG PRI-PK(DCM) OUT(DCM) SW(DCM) L I P F 2 OUT D OUT PRI-PK(BCM) IN

2 V V II V D

SW(BCM) MAG MAG PRI-PK(BCM) IN PS OUT D L L I V N V V § · ¨ ¸ ¨ ¸ © ¹ MAG PRI-PK(BCM) OUT(BCM) SW(BCM) L I P F 2 OUT D PS IN OUT D PS V V ND V V V N LM25183-Q1 www.ti.com SNVSBJ4 –APRIL 2020 Product Folder Links: LM25183-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated Feature Description (continued) where

VD is the forward voltage drop of the flyback diode as its current approaches zero (1) Equation 2 gives the output power in BCM, where the applicable switching frequency and peak primary current are specified by Equation 3 and Equation 4, respectively. (2) (3) (4) As the load decreases, the LM25183-Q1 clamps the maximum switching frequency to 350 kHz, and the converter enters discontinuous conduction mode (DCM). The power delivered to the output in DCM is proportional to the peak primary current squared as given by Equation 5 and Equation 6. Thus, as the load decreases, the peak current reduces to maintain regulation at 350-kHz switching frequency. (5) (6) (7) At even lighter loads, the primary-side peak current set by the internal error amplifier decreases to a minimum level of 0.82 A, or 20% of its 4.1-A peak value, and the MOSFET off-time extends to maintain the output load requirement. The system operates in frequency foldback mode (FFM), and the switching frequency decreases as the load current is reduced. Other than a fault condition, the lowest frequency of operation of the LM25183-Q1 is 12 kHz, which sets a minimum load requirement of approximately 0.5% full load.

7.3.3 Setting the Output Voltage

To minimize output voltage regulation error, the LM25183-Q1 senses the reflected secondary voltage when the secondary current reaches zero. The feedback (FB) resistor, which is connected between SW and FB is determined using Equation 8, where RSET is nominally 12.1 kΩ. (8)

7.3.3.1 Diode Thermal Compensation

The LM25183-Q1 employs a unique thermal compensation circuit that adjusts the feedback setpoint based on the thermal coefficient of the forward voltage drop of the flyback diode. Even though the output voltage is measured when the secondary current is effectively zero, there is still a non-zero forward voltage drop associated with the flyback diode. Select the thermal compensation resistor using Equation 9.

7.3.4 Control Loop Error Amplifier

when the output voltage is in regulation, an on-time interval is initiated when the secondary current reaches zero.

7.3.5 Precision Enable

establish a precision UVLO level. Figure 17. Programmable Input Voltage UVLO With Hysteresis Use Equation 10 and Equation 11 to calculate the input UVLO voltages turnon and turnoff voltages, respectively.

VUV-RISING and VUV-FALLING are the UVLO comparator thresholds
IUV-HYST is the hysteresis current (10) (11)

voltage is between the hard shutdown and precision-enable thresholds.

7.3.6 Configurable Soft Start

timing options include a 6-ms internally-fixed soft start and an externally-programmable soft start. start control ramp and starts up to the regulated output voltage in 6 ms. internal current source ISS of 5 µA charges CSS and generates a ramp to control the primary current amplitude. Calculate the soft-start capacitance for a desired soft-start time, tSS, using Equation 12. CSS is discharged by an internal FET when switching is disabled by EN/UVLO or thermal shutdown.

7.3.7 External Bias Supply

Figure 18. External Bias Supply Using Transformer Auxiliary Winding Figure 18. With a bias supply connected, the LM25183-Q1 then uses its internal soft-start ramp to control the primary current during start-up.

ADVANCE□INFORMATION ª º « » ¬ ¼ SW-PEAK OUT(max) OUT D IN PS II V V 12 V N LM25183-Q1 SNVSBJ4 –APRIL 2020 www.ti.com Product Folder Links: LM25183-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Feature Description (continued) When using a transformer auxiliary winding for bias power, the total leakage current related to diodes DBIAS1 and DBIAS2 in Figure 18 must be less than 1 µA across the full operating temperature range.

7.3.8 Minimum On-Time and Off-Time

When the internal power MOSFET is turned off, the leakage inductance of the transformer resonates with the SW node parasitic capacitance. The resultant ringing behavior can be excessive with large transformer leakage inductance and can corrupt the secondary zero-current detection. To prevent such a situation, a minimum switch off-time, designated as tOFF-MIN, of a maximum of 375 ns is set internally to ensure proper functionality. This sets a lower limit for the transformer magnetizing inductance as discussed in the Detailed Design Procedure. Furthermore, noise effects as a result of power MOSFET turnon can impact the internal current sense circuit measurement. To mitigate this effect, the LM25183-Q1 provides a blanking time after the MOSFET turns on. This blanking time forces a minimum on-time, tON-MIN, of 140 ns.

7.3.9 Overcurrent Protection

In case of an overcurrent condition on the isolated output or outputs, the output voltage drops lower than the regulation level since the maximum power delivered is limited by the peak current capability on the primary side. The peak primary current is maintained at 4.1 A (plus an amount related to the 100-ns propagation delay of the current limit comparator) until the output decreases to the secondary diode voltage drop to impact the reflected signal on the primary side. At this point, the LM25183-Q1 assumes the output cannot be recovered and re- calibrates its switching frequency to 9 kHz until the overload condition is removed. The LM25183-Q1 responds with similar behavior to an output short circuit condition. For a given input voltage, Equation 13 gives the maximum output current prior to the engagement of overcurrent protection. The typical threshold value for ISW-PEAK from the Electrical Characteristics is 2.5 A. (13)

7.3.10 Thermal Shutdown

Thermal shutdown is an integrated self-protection to limit junction temperature and prevent damage related to overheating. Thermal shutdown turns off the device when the junction temperature exceeds 175°C to prevent further power dissipation and temperature rise. Junction temperature decreases after shutdown, and the LM25183-Q1 restarts when the junction temperature falls to 165°C.

7.4 Device Functional Modes

7.4.1 Shutdown Mode

EN/UVLO facilitates ON and OFF control for the LM25183-Q1. When VEN/UVLO is below approximately 0.6 V, the device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in shutdown mode drops to 3 μA at VIN = 24 V. The LM25183-Q1 also employs internal bias rail undervoltage protection. If the internal bias supply voltage is below its UV threshold, the converter remains off.

7.4.2 Standby Mode

The internal bias rail LDO regulator has a lower enable threshold than the converter itself. When VEN/UVLO is above 0.6 V and below the precision-enable threshold (1.5 V typically), the internal LDO is on and regulating. The precision enable circuitry is turned on once the internal VCC is above its UV threshold. The switching action and voltage regulation are not enabled until VEN/UVLO rises above the precision enable threshold.

7.4.3 Active Mode

The LM25183-Q1 is in active mode when VEN/UVLO is above the precision-enable threshold and the internal bias rail is above its UV threshold. The LM25183-Q1 operates in one of three modes depending on the load current requirement: 1. Boundary conduction mode (BCM) at heavy loads 2. Discontinuous conduction mode (DCM) at medium loads 3. Frequency foldback mode (FFM) at light loads Refer to the PSR Flyback Modes of Operation section for more detail.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

complete designs, leveraging iterative design procedures and access to comprehensive component databases. specific circuit design examples. a more comprehensive design. several application use cases. Refer to the LM25184EVM-S12 EVM user's guide for more detail.

8.2 Typical Applications

implementations, refer to the TI Reference Design library. The schematic diagram of a 12-V, 0.6-A PSR flyback converter is given in Figure 19. Figure 19. Schematic for Design 1 With VIN(nom) = 24 V, VOUT = 12 V, IOUT = 0.6 A

8.2.1.1 Design Requirements

The required input, output, and performance parameters for this application example are shown in Table 1. Table 1. Design Parameters required components are listed in Table 2. Transformers for other single-output designs are listed in Table 3. Table 2. List of Components for Design 1 Table 3. Magnetic Components for Single-Output Designs

3.6 V to 5 V 3 : 1 14 µH, 3 A ZB1051-AE

5 V to 8 V 2 : 1 14 µH, 3 A ZB1052-AE

28 V to 50 V 1 : 3 14 µH, 3 A ZB1055-AE

ADVANCE□INFORMATION ° ®ª º ª º ° ¬ ¼ ¬ ¼ INSW-PEAK OUT(max) OUT D IN ININ PS 0.65 A at V 13.5 VI 2.5 AI V V 12 V 0.4 V 11 0.82 A at V 24 V22 V 1 V N OUT PRI-PK PS SEC-RMS

2 I I NI 3

PRI-RMS PRI-PK DI I 3 t OUT D PS OFF-MIN MAG SW-PEAK(FFM) V V N t 12V + 0.3 V 1 375nsL 9.2 +I 0.5 A IN(min)MAX PS MAX OUT D VD 0.7 5 VN 0.951 D V V 1 0.7 12V + 0.3 V LM25183-Q1 SNVSBJ4 –APRIL 2020 www.ti.com Product Folder Links: LM25183-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM25183 -Q1 device with WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.1.2.2 Custom Design With Excel Quickstart Tool

Select components based on the converter specifications using the LM25183-Q1 quick-start calculator.

8.2.1.2.3 Flyback Transformer – T1

Choose a turns ratio of 1 : 1 based on an approximate 70% max duty cycle at minimum input voltage using Equation 14, rounding up or down as needed. While the maximum duty cycle can approach 80% if needed a particularly wide input voltage application, it increases the peak current stress of the secondary-side components. (14) Select a magnetizing inductance based on the minimum off-time constraint using Equation 15. Choose a value of 12.5 µH to allow some margin for this application. Specify a saturation current of 3 A, above the maximum switch current specification of the LM25183 -Q1. (15) Note that a higher magnetizing inductance provides a larger operating range for BCM and FFM, but the leakage inductance can increase based on a higher number of primary turns, NP. Equation 16 and Equation 17 give the primary and secondary winding RMS currents, respectively. (16) (17) Find the maximum output current for a given turns ratio using Equation 18, where the typical value for ISW-PEAK is the 2.5-A switch peak current threshold. Iterate by increasing the turns ratio if the output current capability is too low at minimum input voltage, checking that the SW voltage rating of 65 V is not exceeded at maximum input voltage. (18)

ADVANCE□INFORMATION PS PRI-PK COUT-RMS OUT OUT

2 N II I 1 3 I

¬ ¼ 222 2 OUT DMAG OUT MAG OUT OUT 2 OUT OUT PS INOUT OUT PS

2 V VL I L I 1 D 1V 1 D 2 V V N V2 C V N

12.5 + $L I 1 D 1 0.7C 20 )2 V V 2 2 120 mV 12 V 2 DZ(clamp) PS OUT DV 1.5 N V V 1.5 1 12 V 0.4 V 18.6 V DZ(clamp) SW(max) IN(max)V V V t IN(max) D-REV OUT PS V 42 VV V 12 V 54 VN 1 LM25183-Q1 www.ti.com SNVSBJ4 –APRIL 2020 Product Folder Links: LM25183-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

8.2.1.2.4 Flyback Diode – DFLY

The flyback diode reverse voltage is given by Equation 19. (19) Select a 60-V, 3-A Schottky diode for this application to account for inevitable diode voltage overshoot and ringing related to the resonance of transformer leakage inductance and diode parasitic capacitance. Connect an appropriate RC snubber circuit (for example, 100 Ω and 22 pF) across the flyback diode if needed, particularly if the transformer leakage inductance is high. Also, choose a flyback diode with current rating that aligns with the maximum peak secondary winding current of NPS × ISW-PEAK.

8.2.1.2.5 Leakgae Inductance Clamp Circuit – DF, DCLAMP

Connect a diode-Zener clamp circuit across the primary winding to limit the peak switch voltage after MOSFET turnoff below the maximum level of 65 V, as given by Equation 20. (20) Choose a 20-V zener diode for DCLAMP to give a clamp voltage of approximately 1.5 times the reflected output voltage, as specified by Equation 21. This provides a balance between the maximum switch voltage excursion and the leakage inductance demagnetization time. Select a Zener diode with low package parasitic inductance to manage the high slew-rate current during the switch turnoff transition. (21) Choose an ultra-fast switching diode or Schottky diode for DF with reverse voltage rating greater than the maximum input voltage and forward current rating of 2 A or higher.

8.2.1.2.6 Output Capacitor – COUT

The output capacitor determines the voltage ripple at the converter output, limits the voltage excursion during a load transient, and sets the dominant pole of the small-signal response of the converter. Select an output capacitance using Equation 22 to limit the ripple voltage amplitude to less than 1% of the output voltage at minimum input voltage and maximum load. (22) Mindful of the voltage coefficient of ceramic capacitors, select three 22-µF, 25-V capacitors in 1210 case size with X7S or better dielectric. Assuming operation in BCM, calculate the capacitive ripple voltage at the output using Equation 23. (23) Equation 24 gives an expression for the output capacitor RMS ripple current. (24)

8.2.1.2.7 Input Capacitor – CIN

Select an input capacitance using Equation 25 to limit the ripple voltage amplitude to less than 5% of the input voltage when operating at nominal input voltage.

ADVANCE□INFORMATION UV1 IN(off) UV-FALLING UV-HYST UV1 UV2 R 261 kV V 1 I R 1.45 V 1 5 $ N 9R 97.6 k UV1 IN(on) UV-RISING UV2 R 261 kV V 1 1.5 V 1 5.51V R 97.6 k : : UV-RISING UV2 UV1 IN(on) UV-RISING V 1.5 VR R 263 k 98.6 kV V 5.5 V 1.5 V UV-FALLING IN(on) IN(off) UV-RISING UV1 UV-HYST V 1.45 VV V 5.5 V 4 VV 1.5 VR 263 kI 5 ¬ ¼ q ª º ¬ ¼ FB TC PS Diode R k 3 121 k 3R k 261 kN TC mV C 1 1.4 :OUT D PS FB V V N 12 V 0.2 V 1R 122 k0.1 mA 0.1 mA PRI-PK CIN-RMS D I 4I 1 2 3 D PRI-PK IN SW IN DI D 1 2C 2 F V © ¹ t ' LM25183-Q1 SNVSBJ4 –APRIL 2020 www.ti.com Product Folder Links: LM25183-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated (25) Substituting the input current at full load, switching frequency, peak primary current, and peak-to-peak ripple specification gives CIN greater than 5 μF. Considering the voltage coefficient of ceramic capacitors, select a 10- µF, 50-V, X7R ceramic capacitor in 1210 case size. Equation 26 gives the input capacitor RMS ripple current. (26)

8.2.1.2.8 Feedback Resistor – RFB

Select a feedback resistor, designated RFB, of 121 kΩ based on the secondary winding voltage at the end of the flyback conduction interval (the sum of the 12-V output voltage and the Schottky diode forward voltage drop as its current approaches zero) reflected by the transformer turns ratio of 1 : 1. (27)

8.2.1.2.9 Thermal Compensation Resistor – RTC

Select a resistor for output voltage thermal compensation, designated RTC, based on Equation 28. (28)

8.2.1.2.10 UVLO Resistors – RUV1, RUV2

Given VIN(on) and VIN(off) as the input voltage turnon and turnoff thresholds of 5.5 V and 4 V, respectively, select the upper and lower UVLO resistors using the following expressions: (29) (30) The nearest standard E96 resistor values for RUV1 and RUV2 are 261 kΩ and 97.6 kΩ, respectively. Calculate the actual input voltage turnon and turnoff thresholds as follows: (31) (32)

8.2.1.2.11 Soft-Start Capacitor – CSS

Connect an external soft-start capacitor for a specific soft-start time. In this example, select a soft-start capacitance of 47 nF based on Equation 12 to achieve a soft-start time of 9 ms. For technical solutions, industry trends, and insights for designing and managing power supplies, please refer to TI's Power Management technical articles.

8.2.2 Application Curves

Unless otherwise stated, application performance curves were taken at TA = 25°C. Figure 20. Efficiency (Linear Scale) Figure 21. Efficiency (Log Scale) Figure 22. Load Regulation (Linear Scale) Figure 23. Load Regulation (Log Scale) Figure 24. Start-up Characteristic Figure 25. Enable ON and OFF Characteristic

200 Ps/div

Figure 26. Switch Node Voltage Figure 27. Switch Node Voltage Figure 28. Switch Node Voltage Figure 29. Load Transient, 0.1 A to 0.6 A, 0.1 A/µs Figure 30. Load Transient, 0.1 A to 0.6 A, 0.1 A/µs Figure 31. Load Transient, 0.1 A to 0.3 A, 0.1 A/µs

drive power supply applications is given in Figure 34. Figure 34. Schematic for Design 2 With VIN(nom) = 13.5 V, VOUT1 = 15 V, VOUT2 = –15 V, IOUT = 0.3 A

8.2.3.1 Design Requirements

The required input, output, and performance parameters for this application example are shown in Table 4. Table 4. Design Parameters

A multi-winding flyback transformer
Input and output capacitors
Flyback rectifying diodes
A flyback converter IC

Table 5. List of Components for Design 2 DFLY1, DFLY2 2 Schottky diode, 100 V, 1 A, POWERDI123 DFLS1100-7 Diodes Inc.

8.2.3.2 Detailed Design Procedure

8.2.3.2.1 Flyback Transformer – T1

9 µH and a saturation current of 3 A for this application.

8.2.3.2.2 Flyback Diodes – DFLY1 and DFLY2

ADVANCE□INFORMATION MAG SW-PEAK(FFM) OUT(min) SW(min) L I 9 + $P F 12 kHz 14 mW 2 2 ¬ ¼ q ª º ¬ ¼ FB TC PS Diode R k 3 102 k 3R k 230 kN TC mV C 1 1 / 5 2 :OUT1 D1 PS1 FB V V N 15 V 0.3 V 1 1.5R 102 k0.1 mA 0.1 mA LM25183-Q1 SNVSBJ4 –APRIL 2020 www.ti.com Product Folder Links: LM25183-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Choose a 100-V, 2-A Schottky diode for each output to allow some margin for inevitable voltage overshoot and ringing related to leakage inductance and diode capacitance. Use an RC snubber circuit across each diode, for example, 100 Ω and 22 pF, to mitigate such overshoot and ringing, particularly if the transformer leakage inductance is high.

8.2.3.2.3 Input Capacitor – CIN

The input capacitor filters the primary-winding current waveform. To prevent large ripple voltage, use a low-ESR ceramic input capacitor sized according to Equation 25 for the RMS ripple current given by Equation 26. In this design example, choose a 10-µF, 50-V ceramic capacitor with X7R dielectric and 1210 footprint.

8.2.3.2.4 Output Capacitors – COUT1, COUT2

The output capacitors determine the voltage ripple at the converter outputs, limit the voltage excursion during a load transient, and set the dominant pole of the small-signal response of the converter. Mindful of the voltage coefficient of ceramic capacitors, select two 22-µF, 25-V, X7R capacitors in 1210 case size for each output.

8.2.3.2.5 Feedback Resistor – RFB

Install a 102-kΩ resistor from SW to FB based on an output voltage setpoint of 15 V (plus a flyback diode voltage drop) reflected to the primary side by a transformer turns ratio of 1 : 1.5. (38)

8.2.3.2.6 Thermal Compensation Resistor – RTC

Select a resistor value for output voltage thermal compensation based on Equation 39. (39)

8.2.3.2.7 Output Voltage Clamp Zeners – DOUT1 and DOUT2

Calculate the power delivered to the output at no load based on Equation 40. (40) Select Zener clamp diodes to limit the voltages to a range of 110% to 120% of the nominal output voltage setpoints during no-load operation. Connect an 18-V Zener diode with ±2% tolerance and SOD-523 package across each output.

8.2.3.3 Application Curves

Figure 35. Efficiency (Linear Scale) Figure 36. Efficiency (Log Scale) Figure 37. Load Regulation (Linear Scale) Figure 38. Load Regulation (Log Scale) Figure 39. Start-Up Characteristic Figure 40. ENABLE ON/OFF Characteristic

20 Ps/div

Figure 41. Switch Voltage, No Load Figure 42. Switch Voltage, Medium Load Figure 43. Switch Voltage, Full Load Figure 44. Switch Voltage, Full Load Figure 45. Positive Output Load Transient, 0.1 A to 0.2 A Figure 46. Positive Output Load Transient, 0.1 A to 0.2 A

9 Power Supply Recommendations

The LM25183-Q1 flyback converter operates over a wide input voltage range from 4.5 V to 42 V. The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended Operating Conditions. In addition, the input supply must be capable of delivering the required input current to the fully-loaded regulator. Estimate the average input current with Equation 41. where

η is the efficiency (41) If the converter is connected to an input supply through long wires or PCB traces with a large impedance, special care is required to achieve stable performance. The parasitic inductance and resistance of the input cables can have an adverse effect on converter operation. The parasitic inductance in combination with the low-ESR ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients at VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip during a load transient. If the regulator is operating close to the minimum input voltage, this dip can cause false UVLO fault triggering and a system reset. The best way to solve such issues is to reduce the distance from the input supply to the regulator and use an aluminum electrolytic input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitors helps damp the input resonant circuit and reduce any voltage overshoots. A capacitance in the range of 22 µF to 100 µF is usually sufficient to provide input damping and helps to hold the input voltage steady during large load transients. A typical ESR of 200 mΩ provides enough damping for most input circuit configurations. An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as well as some of the effects mentioned above. The application report Simple Success with Conducted EMI for DC-DC Converters provides helpful suggestions when designing an input filter for any switching regulator.

10 Layout

The performance of any switching converter depends as much upon PCB layout as it does the component selection. The following guidelines are provided to assist with designing a PCB with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI. Figure 47 and Figure 48 provide layout examples for single-output and dual-output designs, respectively.

10.1 Layout Guidelines

PCB layout is critical for good power supply design. There are several paths that conduct high slew-rate currents or voltages that can interact with transformer leakage inductance or parasitic capacitance to generate noise and EMI or degrade the performance of the power supply. 1. Bypass VIN to GND with a low-ESR ceramic capacitor, preferably of X7R or X7S dielectric. Place CIN as close as possible to the LM25184 VIN and GND pins. Ground return paths for the input capacitor or capacitors must consist of localized top-side planes that connect to the GND pin and exposed PAD. 2. Minimize the loop area formed by the input capacitor connections and the VIN and GND pins. 3. Locate the transformer close to the SW pin. Minimize the area of the SW trace or plane to prevent excessive e-field or capacitive coupling. 4. Minimize the loop area formed by the diode-Zener clamp circuit connections and the primary winding terminals of the transformer. 5. Minimize the loop area formed by the flyback rectifying diode, output capacitor, and the secondary winding terminals of the transformer. 6. Tie the GND pin directly to the DAP under the device and to a heat-sinking PCB ground plane. 7. Use a ground plane in one of the middle layers as a noise shielding and heat dissipation path. 8. Have a single-point ground connection to the plane. Route the return connections for the reference resistor, soft start, and enable components directly to the GND pin. This prevents any switched or load currents from flowing in analog ground traces. If not properly handled, poor grounding results in degraded load regulation or erratic output voltage ripple behavior. 9. Make VIN+, VOUT+, and ground bus connections short and wide. This reduces any voltage drops on the input or output paths of the converter and maximizes efficiency. 10. Minimize trace length to the FB pin. Locate the feedback resistor close to the FB pin. 11. Locate components RSET, RTC, and CSS as close as possible to their respective pins. Route with minimal trace lengths. 12. Place a capacitor between input and output return connections to route common-mode noise currents directly back to their source. 13. Provide adequate heatsinking for the LM25183-Q1 to keep the junction temperature below 150°C. For operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-sinking vias to connect the DAP to the PCB ground plane. If the PCB has multiple copper layers, connect these thermal vias to inner-layer ground planes. The connection to VOUT+ provides heatsinking for the flyback diode.

10.2 Layout Examples

Figure 47. Single-Output PCB Layout Example Figure 48. Dual-Output PCB Layout Example

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 Development Support

solutions with high density and low component count. Table 6. PSR Flyback DC/DC Converter Family

LM25183-Q1 Quick-start Calculator
LM25183-Q1 Simulation Models
For TI's reference design library, visit TI Designs
For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center.
To view a related device of this product, see the LM25184-Q1 product page
TI Designs: – Isolated IGBT Gate-Drive Power Supply Reference Design With Integrated Switch PSR Flyback Controller – Compact, Efficient, 24-V Input Auxiliary Power Supply Reference Design for Servo Drives – Reference Design for Power-Isolated Ultra-Compact Analog Output Module – HEV/EV Traction Inverter Power Stage with 3 Types of IGBT/SiC Bias-Supply Solutions Reference Design – 4.5-V to 65-V Input, Compact Bias Supply With Power Stage Reference Design for IGBT/SiC Gate Drivers – Channel-to-Channel Isolated Analog Input Module Reference Design – SiC/IGBT Isolated Gate Driver Reference Design With Thermal Diode and Sensing FET – >95% Efficiency, 1-kW Analog Control AC/DC Reference Design for 5G Telecom Rectifier – 3.5-W Automotive Dual-output PSR Flyback Regulator Reference Design
TI Technical Articles: – Flyback Converters: Two Outputs are Better Than One – Common Challenges When Choosing the Auxiliary Power Supply for Your Server PSU – Maximizing PoE PD Efficiency on a Budget

11.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM25183-Q1 device with WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

LM25184 Single-Output EVM User's Guide (SNVU680)
LM5180 Single-Output EVM User's Guide (SNVU592)
LM5180 Dual-Output EVM User's Guide (SNVU609)
How an Auxless PSR Flyback Converter can Increase PLC Reliability and Density (SLYT779)
Why Use PSR-Flyback Isolated Converters in Dual-Battery mHEV Systems (SLYT791)
IC Package Features Lead to Higher Reliability in Demanding Automotive and Communications Equipment Systems (SNVA804)
PSR Flyback DC/DC Converter Transformer Design for mHEV Applications (SNVA805)
Flyback Transformer Design Considerations for Efficiency and EMI (SLUP338)
Under the Hood of Flyback SMPS Designs (SLUP261)
White Papers: – Valuing Wide VIN, Low EMI Synchronous Buck Circuits for Cost-driven, Demanding Applications (SLYY104) – An Overview of Conducted EMI Specifications for Power Supplies (SLYY136) – An Overview of Radiated EMI Specifications for Power Supplies (SLYY142)
Using New Thermal Metrics Application Report (SBVA025)
Semiconductor and IC Package Thermal Metrics Application Report (SPRA953)
AN-2162: Simple Success with Conducted EMI from DC-DC Converters (SNVA489)
Automotive Cranking Simulator User's Guide (SLVU984)

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, go to the device product folder on ti.com. In the upper right corner, click on Alert me to register for a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

11.5 Trademarks

E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.7 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages have mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

ADVANCE□INFORMATION LM25183-Q1 www.ti.com SNVSBJ4 –APRIL 2020 Product Folder Links: LM25183-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. space (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) space (3) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. space (4) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. space (5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device space (6) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

12.1 Package Option Addendum

12.1.1 Packaging Information

Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish(3) MSL Peak Temp (4) Op Temp (°C) Device Marking(5)(6) PLM25183QNGURQ1 PREVIEW WSON NGU 8 TBD TBD Call TI Call TI -40 to 150 X25183Q

www.ti.com PACKAGE OUTLINE C 8X 0.35 0.25 3 0.05 2.4 1.98 0.05 6X 0.8

0.8 MAX

8X 0.5 0.3 0.05 0.00 A 4.1 3.9 B 4.1 3.9 (0.2) TYP

0.1 MIN

(0.05) WSON - 0.8 mm max heightNGU0008C PLASTIC SMALL OUTLINE - NO LEAD 4224001/A 11/2017 PIN 1 INDEX AREA SEATING PLANE 0.08 C 4 5 PIN 1 ID

0.1 C A B

0.05 C THERMAL PAD EXPOSED SYMM SYMM9 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.000 A-A 30.000 SECTION A-A TYPICAL ADVANCE□INFORMATION LM25183-Q1 SNVSBJ4 –APRIL 2020 www.ti.com Product Folder Links: LM25183-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

8X (0.3) (3) (3.8) 6X (0.8) (1.98) ( 0.2) VIA TYP (0.74) (1.25) 8X (0.6) (R0.05) TYP WSON - 0.8 mm max heightNGU0008C PLASTIC SMALL OUTLINE - NO LEAD 4224001/A 11/2017 SYMM 4 5 EXPOSED METAL SHOWN LAND PATTERN EXAMPLE SCALE:15X SYMM 9 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be ﬁlled, plugged or tented. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DETAILS DEFINED (PREFERRED) EXPOSED METAL ADVANCE□INFORMATION LM25183-Q1 www.ti.com SNVSBJ4 –APRIL 2020 Product Folder Links: LM25183-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP 8X (0.3) 8X (0.6) (1.75) (1.31) (3.8) (0.755) 6X (0.8) WSON - 0.8 mm max heightNGU0008C PLASTIC SMALL OUTLINE - NO LEAD 4224001/A 11/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 9: 77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X SYMM 4 5 METAL TYP SYMM ADVANCE□INFORMATION LM25183-Q1 SNVSBJ4 –APRIL 2020 www.ti.com Product Folder Links: LM25183-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

www.ti.com SDC08B (Rev A)

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated

Product Information

PLM25183QNGURQ1 specifications and overview.

Summary

LM25183-Q1 42-VIN PSR Flyback DC/DC Converter with 65-V, 2.5-A Integrated MOSFET

Description

LM25183-Q1 42-VIN PSR Flyback DC/DC Converter with 65-V, 2.5-A Integrated MOSFET

Source title PLM25183QNGURQ1 Datasheet(PDF) - Texas Instruments

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