PLL1708DBQR

PLL1707 BURR-BROWN | Alldatasheet

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Technical content

/C0080/C0076/C0076/C0049/C0055/C0048/C0055 /C0080/C0076/C0076/C0049/C0055/C0048/C0056 SLES065 – DECEMBER 2002 /C0051/C0046/C0051/C0262/C0086 /C0068/C0085/C0065/C0076 /C0080/C0076/C0076 /C0077/C0085/C0076/C0084/C0073/C0067/C0076/C0079/C0067/C0075 /C0071/C0069/C0078/C0069/C0082/C0065/C0084/C0079/C0082

FEATURES

/C006827-MHz Master Clock Input /C0068Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) /C0068Generated Audio System Clock (PLL1708): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS, 384 fS, 256 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 16, 22.05, 24, 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 16, 22.05, 24, 32, 44.1, 48, 64, 88.2, 96 kHz) /C0068Zero PPM Error Output Clocks /C0068Low Clock Jitter: 50 ps (Typical) /C0068Multiple Sampling Frequencies (PLL1707): – fS = 32, 44.1, 48, 64, 88.2, 96 kHz /C0068Multiple Sampling Frequencies (PLL1708): 96 kHz /C00683.3-V Single Power Supply /C0068PLL1707: Parallel Control PLL1708: Serial Control /C0068Package: 20-Pin SSOP (150 mil), Lead-Free Product

APPLICATIONS

/C0068HDD + DVD Recorders /C0068DVD Recorders /C0068HDD Recorders /C0068DVD Players /C0068DVD Add-On Cards for Multimedia PCs /C0068Digital HDTV Systems /C0068Set-Top Boxes

DESCRIPTION

The PLL1707† and PLL1708† are low cost, phase-locked loop (PLL) multiclock generators. The PLL1707 and PLL1708 can generate four system clocks from a 27-MHz reference input frequency. The clock outputs of the PLL1707 can be controlled by sampling frequency-control pins and those of the PLL1708 can be controlled through serial-mode control pins. The device gives customers both cost and space savings by eliminating external components and enables customers to achieve the very low-jitter performance needed for high performance audio DACs and/or ADCs. The PLL1707 and PLL1708 are ideal for MPEG-2 applications which use a 27-MHz master clock such as DVD recorders, HDD recorders, DVD add-on cards for multimedia PCs, digital HDTV systems, and set-top boxes. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2002, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 †The PLL1707 and PLL1708 use the same die and they are electrically identical except for mode control.

/C0080/C0076/C0076/C0049/C0055/C0048/C0055 /C0080/C0076/C0076/C0049/C0055/C0048/C0056 SLES065 – DECEMBER 2002 www.ti.com FUNCTIONAL BLOCK DIAGRAM Mode Control Interface ( ): PLL1708 XT1 (MS) SR (MC) FS2 (MD) FS1 CSEL PLL2 PLL1OSC XT2 MCKO1 MCKO2 SCKO0 Divider Divider Divider SCKO1 SCKO2 SCKO3 Reset Power Supply VCC AGND VDD 1–3 DGND1 –3 PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE CODE OPERATION TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA PLL1707DBQ SSOP 20 20DBQ 25°Ct o8 5°C PLL1707 PLL1707DBQ Tube PLL1707DBQ SSOP 20 20DBQ –25°C to 85°C PLL1707 PLL1707DBQR Tape and reel PLL1708DBQ SSOP 20 20DBQ 25°Ct o8 5°C PLL1708 PLL1708DBQ Tube PLL1708DBQ SSOP 20 20DBQ –25°C to 85°C PLL1708 PLL1708DBQR Tape and reel ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) PLL1705 AND PLL1706 Supply voltage: VCC , VDD 1–VDD 3 4 V Supply voltage differences: VCC , VDD 1–VDD 3 ±0.1 V Ground voltage differences: AGND, DGND1–DGND3 ±0.1 V Digital input voltage: FS1 (MD), FS2 (MC), SR (MS), CSEL – 0.3 V to (VDD + 0.3) V Analog input voltage, XT1, XT2 – 0.3 V to (VCC + 0.3) V Input current (any pins except supplies) ±10 mA Ambient temperature under bias –40°C to 125°C Storage temperature –55°C to 150°C Junction temperature 150°C Lead temperature (soldering) 260°C, 5 s Package temperature (IR reflow, peak) 260°C (1)Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

/C0080/C0076/C0076/C0049/C0055/C0048/C0055 /C0080/C0076/C0076/C0049/C0055/C0048/C0056 SLES065 – DECEMBER 2002 www.ti.com

ELECTRICAL CHARACTERISTICS

all specifications at TA = 25°C, VDD 1–VDD 3 (= VDD ) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Logic input CMOS compatible VIH (1) Input logic level 0.7VDD 3.6 VdcVIL (1) Input logic level 0.3 VDD Vdc IIH (1) Input logic current VIN = VDD 65 100 µAIIL (1) Input logic current VIN = 0 V ±10 µA Logic output CMOS VOH (2) Output logic level IOH = –4 mA VDD – 0.4 V Vdc VOL (2) Output logic level IOL = 4 mA 0.4 Vdc PLL1707 Standard fS 32 44.1 48 PLL1707 Double fS 64 88.2 96 Sampling frequency Half fS 16 22.05 24 kHzSam ling frequency PLL1708 Standard fS 32 44.1 48 kHz PLL1708 Double fS 64 88.2 96 MASTER CLOCK (MCKO1, MCKO2) CHARACTERISTICS (fM = 27 MHz, C1 = C2 = 15 pF, CL = 20 pF on measurement pin) Master clock frequency 26.73 27 27.27 MHz VIH Input level(3) 0.7 VCC VVIL Input level(3)

0.3 VCC

V IIH Input current(3) VIN = VCC ±10 µAIIL Input current(3) VIN = 0 V ±10 µA Output voltage (4) 3.5 Vp-p Output rise time 20% to 80% of VDD 2.0 ns Output fall time 80% to 20% of VDD 2.0 ns Duty cycle For crystal oscillation 45% 51% 55% Duty cycle For external clock 50% Clock jitter (5) 50 ps Power-up time (6) 0.5 1.5 ms PLL AC CHARACTERISTICS (SCKO0 –SCKO3) (fM = 27 MHz, CL = 20 pF on measurement pin) SCKO0 Fixed 33.8688 SCKO1 PLL1707 Selectable for 48 kHz 24.576 36.864 SCKO2 PLL1707 256 fS 8.192 12.288 24.576 SCKO3 Output system clock 384 fS 12.288 18.432 36.864 MHzSCKO0 Out ut system clock frequency Fixed 33.8688 MHz SCKO1 qy PLL1708 Selectable for 48 kHz 12.288 24.576 36.864 SCKO2 PLL1708 256 fS 4.096 12.288 24.576 SCKO3 384 fS 6.144 18.432 36.864 Output rise time 20% to 80% of VDD 2.0 ns Output fall time 80% to 20% of VDD 2.0 ns Output duty cycle 45 50 55 % (1)Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/MS, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant) (2)Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO0, SCKO1 (3)Pin 10: XT1 (4)Pin 11: XT2 (5)Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter performance varies with master clock mode, SCKO frequency setting and load capacitance on each clock output. (6)The delay time from power on to oscillation (7)The settling time when the sampling frequency is changed (8)The delay time from power on to lockup (9)fM = 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling frequency selection and load condition. (10)While all bits of CE[6:1] are 0, the PLL1708 goes into power-down mode.

/C0080/C0076/C0076/C0049/C0055/C0048/C0055 /C0080/C0076/C0076/C0049/C0055/C0048/C0056 SLES065 – DECEMBER 2002 www.ti.com ELECTRICAL CHARACTERISTICS (continued) all specifications at TA = 25°C, VDD 1–VDD 3 (= VDD ) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted) PARAMETER UNITMAXTYPMINTEST CONDITIONS Output clock jitter(5) SCKO0, SCKO1 58 100 ps Output clock jitter (5) SCKO2, SCKO3 50 100 ps Frequency Settling Time(7) PLL1707, to stated output frequency 50 150 nsFrequency Settling Time(7) PLL1708, to stated output frequency 80 300 ns Power-up time (8) To stated output frequency 3 6 ms POWER SUPPLY REQUIREMENTS VCC , VDD Supply voltage range 2.7 3.3 3.6 Vdc IDD +ICC Supply current(9) VDD = VCC = 3.3 V, fS = 48 kHz 19 25 mA IDD + ICC Supply current (9) Power down(10) 350 550 µA Power dissipation VDD = VCC = 3.3 V, fS = 48 kHz 63 90 mW TEMPERATURE RANGE Operating temperature –25 85 °C θJA Thermal resistance PLL1707/8DBQ: 20-pin SSOP (150 mil) 150 °C/W (1)Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/MS, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant) (2)Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO0, SCKO1 (3)Pin 10: XT1 (4)Pin 11: XT2 (5)Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter performance varies with master clock mode, SCKO frequency setting and load capacitance on each clock output. (6)The delay time from power on to oscillation (7)The settling time when the sampling frequency is changed (8)The delay time from power on to lockup (9)fM = 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling frequency selection and load condition. (10)While all bits of CE[6:1] are 0, the PLL1708 goes into power-down mode. PIN ASSIGNMENTS VDD 1 SCKO2 SCKO3 DGND1 FS1 FS2 SR V CC AGND XT1 VDD 3 SCKO1 SCKO0 DGND3 DGND2 MCKO2 MCKO1 V DD 2 CSEL XT2 PLL1707 (TOP VIEW) VDD 1 SCKO2 SCKO3 DGND1 MD MC MS V CC AGND XT1 VDD 3 SCKO1 SCKO0 DGND3 DGND2 MCKO2 MCKO1 V DD 2 CSEL XT2 PLL1708 (TOP VIEW)

/C0080/C0076/C0076/C0049/C0055/C0048/C0055 /C0080/C0076/C0076/C0049/C0055/C0048/C0056 SLES065 – DECEMBER 2002 www.ti.com PLL1707 Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION AGND 9 – Analog ground CSEL 12 I SCKO1 frequency selection control(1) DGND1 4 – Digital ground 1 DGND2 16 – Digital ground 2 DGND3 17 – Digital ground 3 FS1 5 I Sampling frequency group control 1(1) FS2 6 I Sampling frequency group control 2(1) MCKO1 14 O 27-MHz master clock output 1 MCKO2 15 O 27-MHz master clock output 2 SCKO0 18 O System clock output 0 (33.8688 MHz fixed) SCKO1 19 O System clock output 1 (selectable for 48 kHz) SCKO2 2 O System clock output 2 (256 fS selectable) SCKO3 3 O System clock output 3 (384 fS selectable) SR 7 I Sampling rate control(1) VCC 8 – Analog power supply, 3.3 V VDD 1 1 – Digital power supply 1, 3.3 V VDD 2 13 – Digital power supply 2, 3.3 V VDD 3 20 – Digital power supply 3, 3.3 V XT1 10 I 27-MHz crystal oscillator, or external clock input XT2 11 O 27-MHz crystal oscillator, must be OPEN for external clock input mode (1)Schmitt-trigger input with internal pulldown.

/C0080/C0076/C0076/C0049/C0055/C0048/C0055 /C0080/C0076/C0076/C0049/C0055/C0048/C0056 SLES065 – DECEMBER 2002 www.ti.com PLL1708 Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION AGND 9 – Analog ground CSEL 12 I SCKO1 frequency selection control(1) DGND1 4 – Digital ground 1 DGND2 16 – Digital ground 2 DGND3 17 – Digital ground 3 MC 6 I Bit clock input for serial control(1) MCKO1 14 O 27-MHz master clock output 1 MCKO2 15 O 27-MHz master clock output 2 MD 5 I Data input for serial control(1) MS 7 I Chip select input for serial control(1) SCKO0 18 O System clock output 0 (33.8688 MHz fixed) SCKO1 19 O System clock output 1 (selectable for 48 kHz) SCKO2 2 O System clock output 2 (256 fS selectable) SCKO3 3 O System clock output 3 (384 fS selectable) VCC 8 – Analog power supply, 3.3 V VDD 1 1 – Digital power supply 1, 3.3 V VDD 2 13 – Digital power supply 2, 3.3 V VDD 3 20 – Digital power supply 3, 3.3 V XT1 10 I 27-MHz crystal oscillator, or external clock input XT2 11 O 27-MHz crystal oscillator, must be OPEN for external clock input mode (1)Schmitt-trigger input with internal pulldown.

designed to accept a 27-MHz master clock.

33.8688 MHz

27 MHz

Figure 7. Block Diagram

and Figure 9 illustrates the 27-MHz master clock timing requirement. Figure 8. Master Clock Generator Connection Diagram

0.7 VCC

Figure 9. External Master Clock Timing Requirement output 256-fS and 384-fS system clocks, respectively. Table 2 shows each sampling frequency which can be programmed. frequencies on SCKO2 and SCKO3 and 256 fS and 384 fS on SCKO1 are supported only on the PLL1708. Table 1. Generated System Clock SCKO1 Frequency

Table 2. Sampling Frequencies Table 3. Sampling Frequencies and System Clock Output Frequencies Figure 10. System Clock Transient Timing all output clocks in order to avoid degrading the jitter performance of the PLL1707/8.

Figure 11. SCKO Transient Timing by power-on reset. Throughout the reset period, all clock outputs are enabled with the default settings after power-up time. reset timing is shown in Figure 12.

1024 Master Clocks

Figure 12. Power-On Reset Timing

using MS (pin 7), MC (pin 6), and MD (pin 5). The selectable functions are shown in Table 4. Table 4. Selectable Functions The sampling frequency group can be selected by FS1 (pin 5) and FS2 (pin 6). System clock SCKO1 frequency can be selected by CSEL (pin 12). Table 5. Selectable Functions

Table 6. Mode Register Mapping

0 Clock output disable

1 Clock output enable (default)

and the oscillator halts, but serial mode control is enabled for resumption.

Table 7. Configuration Register Mapping The system clock SCKO1 frequency can be selected by CSEL (pin 12) and CFG1 (register). power-supply-related troubles. Power supplies should be bypassed as close as possible to the device. clocks for a CD-DA DSP, DVD DSP, Karaoke DSP, ADC(s), and DAC(s) from a 27-MHz video clock.

Figure 15. Typical Connection Diagram

/C0080/C0076/C0076/C0049/C0055/C0048/C0055 /C0080/C0076/C0076/C0049/C0055/C0048/C0056 SLES065 – DECEMBER 2002 www.ti.com BLOCK DIAGRAM OF DVD PLAYER APPLICATION SCKO3 SCKO2 SCKO0 MCKO1/2 PLL1707/8 384 fS 256 fS Center, Subwoofer Surround BLOCK DIAGRAM OF HDD+DVD RECORDER APPLICATION SCKO1 XTI SCKO2, 3 MCKO1/2 PLL1707/8 PCM1802 PCM1742 27-MHz Master Clock MPEG Encoder MPEG Decoder

/C0080/C0076/C0076/C0049/C0055/C0048/C0055 /C0080/C0076/C0076/C0049/C0055/C0048/C0056 SLES065 – DECEMBER 2002 www.ti.com MECHANICAL DATA DBQ (R-PDSO-G) PLASTIC SMALL-OUTLINE PACKAGE 4073301/F 02/02 0.069 (1,75) MAX Seating Plane 0.004 (0,10) 0.010 (0,25) 0.010 (0,25) 0.016 (0,40) 0.035 (0,89) 0.244 (6,20) 0.228 (5,80) 11 2 24 13 0.150 (3,81) 0°–8° Gauge Plane 0.012 (0,30) 0.008 (0,20) 0.197 (5,00) (4,80) 0.189 A MAX A MIN PINS DIM 16 0.337 (8,56) (8,74) 0.344 20 24 A (8,74) 0.344 (8,56) 0.337 0.394 (10,01) 0.386 (9,80) M0 –137 VARIATION AB AD AE AF 0.004 (0,10) D NOTES:A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO–137.

MSOI004E JANUARY 1995 – REVISED MAY 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DBQ (R–PDSO–G) PLASTIC SMALL–OUTLINE PACKAGE 4073301/F 02/02 0.069 (1,75) MAX Seating Plane 0.004 (0,10) 0.010 (0,25) 0.010 (0,25) 0.016 (0,40) 0.035 (0,89) 0.244 (6,20) 0.228 (5,80) 11 2 24 13 0.150 (3,81) 0°–8° Gauge Plane 0.012 (0,30) 0.008 (0,20) 0.197 (5,00) (4,80) 0.189 A MAX A MIN PINS DIM 16 0.337 (8,56) (8,74) 0.344 20 24 A (8,74) 0.344 (8,56) 0.337 0.394 (10,01) 0.386 (9,80) M0–137 VARIATION AB AD AE AFD 0.004 (0,10) NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO–137.

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

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