PLL1706DBQG4

PLL1705_06 BURR-BROWN | Alldatasheet

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Technical content

SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 3.3-V DUAL PLL MULTICLOCK GENERATOR

FEATURES

/C006827-MHz Master Clock Input /C0068Generated Audio System Clock: – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) /C0068Zero PPM Error Output Clocks /C0068Low Clock Jitter: 50 ps (Typical) /C0068Multiple Sampling Frequencies: – fS = 32, 44.1, 48, 64, 88.2, 96 kHz /C00683.3-V Single Power Supply /C0068PLL1705: Parallel Control PLL1706: Serial Control /C0068Package: 20-Pin SSOP (150 mil), Lead-Free Product

APPLICATIONS

/C0068DVD Players /C0068DVD Add-On Cards for Multimedia PCs /C0068Digital HDTV Systems /C0068Set-Top Boxes

DESCRIPTION

The PLL1705† and PLL1706† are low cost, phase-locked loop (PLL) multiclock generators. The PLL1705 and PLL1706 can generate four system clocks from a 27-MHz reference input frequency. The clock outputs of the PLL1705 can be controlled by sampling frequency-control pins and those of the PLL1706 can be controlled through serial-mode control pins. The device gives customers both cost and space savings by eliminating external components and enables customers to achieve the very low-jitter performance needed for high performance audio DACs and/or ADCs. The PLL1705 and PLL1706 are ideal for MPEG-2 applications which use a 27-MHz master clock such as DVD players, DVD add-on cards for multimedia PCs, digital HDTV systems, and set-top boxes. FUNCTIONAL BLOCK DIAGRAM Mode Control Interface ( ): PLL1706 XT1 (ML) SR (MC) FS2 (MD) FS1 CSEL PLL2 PLL1OSC XT2 MCKO1 MCKO2 SCKO0 Divider Divider Divider SCKO1 SCKO2 SCKO3 Reset Power Supply VCC AGND VDD 1–3 DGND1–3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2002, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. †The PLL1705 and PLL1706 use the same die and they are electrically identical except for mode control.

SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE CODE OPERATION TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA PLL1705DBQ SSOP 20 20DBQ 25°Ct o8 5°C PLL1705 PLL1705DBQ Tube PLL1705DBQ SSOP 20 20DBQ –25°C to 85°C PLL1705 PLL1705DBQR Tape and reel PLL1706DBQ SSOP 20 20DBQ 25°Ct o8 5°C PLL1706 PLL1706DBQ Tube PLL1706DBQ SSOP 20 20DBQ –25°C to 85°C PLL1706 PLL1706DBQR Tape and reel ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) PLL1705 AND PLL1706 Supply voltage: VCC , VDD 1–3 4 V Supply voltage differences: VCC , VDD 1–3 ±0.1 V Ground voltage differences: AGND, DGND1–3 ±0.1 V Digital input voltage: FS1 (MD), FS2 (MC), SR (ML), CSEL – 0.3 V to (VDD + 0.3) V Analog input voltage, XT1, XT2 – 0.3 V to (VCC + 0.3) V Input current (any pins except supplies) ±10 mA Ambient temperature under bias –40°C to 125°C Storage temperature –55°C to 150°C Junction temperature 150°C Lead temperature (soldering) 260°C, 5 s Package temperature (IR reflow, peak) 260°C (1)Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 www.ti.com

ELECTRICAL CHARACTERISTICS

all specifications at TA = 25°C, VDD 1–VDD 3 (= VDD ) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Logic input CMOS compatible VIH (1) Input logic level 0.7VDD 3.6 VdcVIL (1) Input logic level 0.3 VDD Vdc IIH (1) Input logic current VIN = VDD 65 100 µAIIL (1) Input logic current VIN = 0 V ±10 µA Logic output CMOS VOH (2) Output logic level IOH = –4 mA VDD – 0.4 V Vdc VOL (2) Output logic level IOL = 4 mA 0.4 Vdc Sam plingfrequency Standard fS 32 44.1 48 kHzSampling frequency Double fS 64 88.2 96 kHz MASTER CLOCK (MCKO1, 2) CHARACTERISTICS (fM = 27 MHz, C1 = C2 = 15 pF, CL = 20 pF on measurement pin) Master clock frequency 26.73 27 27.27 MHz VIH Input level(3) 0.7 VCC VVIL Input level(3)

0.3 VCC

V IIH Input current(3) VIN = VCC ±10 µAIIL Input current(3) VIN = 0 V ±10 µA Output voltage (4) 3.5 Vp-p Output rise time 20% to 80% of VDD 2.0 ns Output fall time 80% to 20% of VDD 2.0 ns Duty cycle For crystal oscillation 45% 48% 55% Duty cycle For external clock 50% Clock jitter (5) 50 ps Power-up time (6) 0.5 1.5 ms PLL AC CHARACTERISTICS (SCKO0 –3) (fM = 27 MHz, CL = 20 pF on measurement pin) SCKO0 Fixed 33.8688 SCKO1 Output system clock frequency Selectable for 44.1 kHz 16.9344 33.8688 MHzSCKO2 Output system clock frequency 256 fS 8.192 12.288 24.576 MHz SCKO3 384 fS 12.288 18.432 36.864 Output rise time 20% to 80% of VDD 2.0 ns Output fall time 80% to 20% of VDD 2.0 ns Output duty cycle 45 50 55 % Output clock jitter (5) 50 100 ps Frequency Settling Time(7) PLL1705, to stated output frequency 50 150 ns Frequency Settling Time(7) PLL1706, to stated output frequency 80 200 ns Power-up time (8) To stated output frequency 3 6 ms (1)Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/ML, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant) (2)Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO1, SCKO0 (3)Pin 10: XT1 (4)Pin 11: XT2 (5)Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter performance varies with master clock mode, SCKO frequency setting and load capacitance on each clock output. (6)The delay time from power on to oscillation (7)The settling time when the sampling frequency is changed (8)The delay time from power on to lockup (9)fM = 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling frequency selection and load condition. (10)While all bits of CE[6:1] are 0, the PLL1706 goes into power-down mode.

SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 www.ti.com ELECTRICAL CHARACTERISTICS(continued) all specifications at TA = 25°C, VDD 1–VDD 3 (= VDD ) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted) PARAMETER UNITMAXTYPMINTEST CONDITIONS POWER SUPPLY REQUIREMENTS VCC , VDD Supply voltage range 2.7 3.3 3.6 Vdc IDD +ICC Supply current(9) VDD = VCC = 3.3 V, fS = 48 kHz 19 25 mA IDD + ICC Supply current (9) Power down(10) 320 500 µA Power dissipation VDD = VCC = 3.3 V, fS = 48 kHz 63 90 mW TEMPERATURE RANGE Operating temperature –25 85 °C θJA Thermal resistance PLL1705/6DBQ: 20-pin SSOP (150 mil) 150 °C/W (1)Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/ML, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant) (2)Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO1, SCKO0 (3)Pin 10: XT1 (4)Pin 11: XT2 (5)Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter performance varies with master clock mode, SCKO frequency setting and load capacitance on each clock output. (6)The delay time from power on to oscillation (7)The settling time when the sampling frequency is changed (8)The delay time from power on to lockup (9)fM = 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling frequency selection and load condition. (10)While all bits of CE[6:1] are 0, the PLL1706 goes into power-down mode. PIN ASSIGNMENTS VDD 1 SCKO2 SCKO3 DGND1 FS1 FS2 SR V CC AGND XT1 VDD 3 SCKO0 SCKO1 DGND3 DGND2 MCKO2 MCKO1 V DD 2 CSEL XT2 PLL1705 (TOP VIEW) VDD 1 SCKO2 SCKO3 DGND1 MD MC ML V CC AGND XT1 VDD 3 SCKO0 SCKO1 DGND3 DGND2 MCKO2 MCKO1 V DD 2 CSEL XT2 PLL1706 (TOP VIEW)

SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 www.ti.com Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION AGND 9 – Analog ground CSEL 12 IN SCKO1 frequency selection control(1) DGND1 4 – Digital ground 1 DGND2 16 – Digital ground 2 DGND3 17 – Digital ground 3 FS1(MD) 5 IN Sampling frequency group control in PLL1705, data input for serial control in PLL1706(1) FS2(MC) 6 IN Sampling frequency group control in PLL1705, bit clock input for serial control in PLL1706(1) MCKO1 14 OUT 27-MHz master clock output 1 MCKO2 15 OUT 27-MHz master clock output 2 SCKO0 19 OUT System clock output 0 (33.8688 MHz fixed) SCKO1 18 OUT System clock output 1 (selectable for 44.1 kHz) SCKO2 2 OUT System clock output 2 (256 fS) SCKO3 3 OUT System clock output 3 (384 fS) SR(ML) 7 IN Sampling rate control in PLL1705, load strobe input for serial control in PLL1706(1) VCC 8 – Analog power supply, 3.3 V VDD 1 1 – Digital power supply 1, 3.3 V VDD 2 13 – Digital power supply 2, 3.3 V VDD 3 20 – Digital power supply 3, 3.3 V XT1 10 IN 27-MHz crystal oscillator, or external clock input XT2 11 OUT 27-MHz crystal oscillator, must be OPEN for external clock input mode (1)Schmitt-trigger input with internal pulldown.

designed to accept a 27-MHz master clock.

33.8688 MHz

27 MHz

Figure 7. Block Diagram

and Figure 9 illustrates the 27-MHz master clock timing requirement. Figure 8. Master Clock Generator Connection Diagram

0.7 VCC

Figure 9. External Master Clock Timing Requirement clock output frequencies for programmed sampling frequencies are shown in Table 3. Table 1. Generated System Clock SCKO1 Frequency Table 2. Sampling Frequencies

Table 3. Sampling Frequencies and System Clock Output Frequencies output clocks in order to avoid degrading the jitter performance of the PLL1705/6. Figure 10. System Clock Transient Timing power-on reset. Throughout the reset period, all clock outputs are enabled with the default settings after power up time. reset timing is shown in Figure 11.

1024 Master Clocks

Figure 11. Power-On Reset Timing

interface by ML (pin 7), MC (pin 6), and MD (pin 5). The selectable functions are shown in Table 4. Table 4. Selectable Functions The sampling frequency group can be selected by FS1 (pin 5) and FS2 (pin 6). Table 5. Selectable Functions

Table 6. Register Mapping

0 Standard O

1 Double

0 Clock output disable

1 Clock output enable O

and the oscillator halt, but serial mode control is enabled for resumption. power-supply-related troubles. Power supplies should be bypassed as close as possible to the device. DVD DSP, Karaoke DSP, and DAC(s) from a 27-MHz video clock.

(5)For good jitter performance, minimize the load capacitance on the clock output. Figure 14. Typical Connection Diagram

SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 www.ti.com BLOCK DIAGRAM OF MPEG-2 BASED SYSTEM APPLICATION Front SCKO3 384 fS PCM1716 SCKO2 256 fS MCKO1/2

SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 www.ti.com MECHANICAL DATA DBQ (R-PDSO-G) PLASTIC SMALL-OUTLINE PACKAGE 4073301/F 02/02 0.069 (1,75) MAX Seating Plane 0.004 (0,10) 0.010 (0,25) 0.010 (0,25) 0.016 (0,40) 0.035 (0,89) 0.244 (6,20) 0.228 (5,80) 11 2 24 13 0.150 (3,81) 0°–8° Gauge Plane 0.012 (0,30) 0.008 (0,20) 0.197 (5,00) (4,80) 0.189 A MAX A MIN PINS DIM 16 0.337 (8,56) (8,74) 0.344 20 24 A (8,74) 0.344 (8,56) 0.337 0.394 (10,01) 0.386 (9,80) M0 –137 VARIATION AB AD AE AF 0.004 (0,10) D NOTES:A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO–137.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) PLL1705DBQ ACTIVE SSOP/ QSOP DBQ 20 56 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PLL1705DBQG4 ACTIVE SSOP/ QSOP DBQ 20 56 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PLL1705DBQR ACTIVE SSOP/ QSOP DBQ 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PLL1705DBQRG4 ACTIVE SSOP/ QSOP DBQ 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PLL1706DBQ ACTIVE SSOP/ QSOP DBQ 20 56 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PLL1706DBQG4 ACTIVE SSOP/ QSOP DBQ 20 56 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PLL1706DBQR ACTIVE SSOP/ QSOP DBQ 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PLL1706DBQRG4 ACTIVE SSOP/ QSOP DBQ 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 22-May-2006 Addendum-Page 1

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