PLL1700

PLL1700 BURR-BROWN | Alldatasheet

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Technical content

49% FPO PLL1700 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 MULTI-CLOCK GENERATOR

DESCRIPTION

The PLL1700 is a low cost, multi-clock generator Phase Lock Loop (PLL). The PLL1700 can generate four systems clocks from a 27MHz reference input frequency. The device gives customers both cost and space savings by eliminating external components and enables cus- tomers to achive the very low jitter performance needed for high performance audio digital-to-analog convert- ers (DAC) and/or analog-to-digital converters (ADC). The PLL1700 is ideal for MPEG-2 applications which use a 27MHz master clock such as DVD players, DVD add-on cards for multimedia PCs, digital HDTV sys- tems, and set-top boxes.

FEATURES

l 27MHZ MASTER CLOCK INPUT l GENERATED AUDIO SYSTEM CLOCK: SCKO1: 33.8688MHz (Fixed) SCKO2: 256f S SCKO3: 384fS SCKO4: 768fS l ZERO PPM ERROR OUTPUT CLOCKS l LOW CLOCK JITTER: 150ps at SCKO3 l MULTIPLE SAMPLING FREQUENCIES: fS = 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, 96kHz l +3.3V CMOS LOGIC INTERFACE l DUAL POWER SUPPLIES: +5V and +3.3V l SMALL PACKAGE: 20-Lead SSOP OSC PLL2 PLL1 Counter Q Counter P SCKO2 SCKO3 SCKO4MCKOMCKO XT1 XT2 Reset Mode Control I/F Power Supply RST MODE ML MC MD V DDP VDDB VDDGNDP GNDB GND SCKO1 © 1998 Burr-Brown Corporation PDS-1455A Printed in U.S.A. August, 1998 ®PLL1700

All specifications at TA = +25°C, VDD = VDDP = +5V, VDDB = +3.3V, fM = 27MHz crystal oscillation and fS = 48kHz, unless otherwise noted. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. PLL1700E PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL INPUT/OUTPUT Input Logic Level: TTL-Compatible V IH 2.0 VDC VIL 0.8 VDC Input Logic Current: IIH(1) VIN = VDD 200 µA IIL(1) VIN = 0V –1 µA IIH(2) VIN = VDD 4m A IIL(2) VIN = 0V –800 µA Output Logic Level: CMOS VOH (3) IOH = 4mA V DDB – 0.4V VDC VOL (3) IOL = 4mA 0.4 VDC Sampling Frequency (fS) Standard f S 32 44.1 48 kHz Double fS 64 88.2 96 kHz MASTER CLOCK (MCKO, MCKO) fM = 27MHz, CL = 20pF Master Clock Frequency 26.73 27 27.27 MHz Clock Jitter(4) 300 ps Clock Duty Cycle MCKO 40 50 60 % For Crystal Oscillation MCKO 40 50 60 % Clock Duty Cycle MCKO 40 % For External Clock MCKO 60 % PHASE LOCK LOOP (PLL) fM = 27MHz, CL = 20pF Generated System Clock Frequency SCKO1 Fixed 33.8688 MHz SCKO2 256f S 8.192 24.576 MHz SCKO3 384f S 12.288 36.864 MHz SCKO4 768f S 24.576 36.864 MHz Generated Clock Rise Time(3) 20% to 80% VDDB 5n s Generated Clock Fall Time(3) 80% to 20% VDDB 5n s Generated Clock Duty Cycle SCKO1, SCKO3, SCKO4 40 50 60 % SCKO2 (standard) 40 50 60 % SCKO2 (double)(5) 25 33 40 % Generated Clock Jitter(4) SCKO1, SCKO2 (standard), SCKO4 300 ps SCKO3 150 ps SCKO2 (double) 450 ps Settling Time To Programmed Frequency 20 ms Power-Up Time To Programmed Frequency 15 30 ms POWER SUPPLY REQUIREMENTS Voltage Range V DD , VDDP +4.5 +5 +5.5 VDC VDDB +2.7 +3.3 +3.6 VDC Supply Current(6): IDD + IDDP VDD = VDDP = 5V, fS = 48kHz 11 16 mA IDDB VDDB = +3.3V, fS = 48kHz 6 9 mA Power Dissipation f S = 48kHz 75 110 mW TEMPERATURE RANGE Operation –25 +85 °C Storage –55 +125 °C NOTES: (1) ML, MC, MD, MODE, RST (Schmitt-trigger input with internal pull-down resistor). (2) XT1, when an external 27MHz clock is used, the buffer ICs, such as 74HC04, are recommended to interface to XT1. (3) MCKO, MCKO, SCKO4, SCKO3, SCKO2, and SCKO1. (4) Jitter performance is specified as standard deviation of jitter under 27MHz crystal oscillation. (5) When SCKO2 is set to double rate clock output, its duty cycle is 33%. (6) fM = 27MHz crystal oscillation, no load on MCKO, MCKO, SCKO4, SCKO3, SCKO2, and SCKO1.

3 PLL1700

PIN ASSIGNMENTSPIN CONFIGURATION TOP VIEW SSOP

PACKAGE INFORMATION

PRODUCT PACKAGE RANGE NUMBER (1) PLL1700E 20-Lead SSOP –25 °C to +85°C 334-1 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ABSOLUTE MAXIMUM RATINGS PIN NAME I/O FUNCTION

1 ML/SR0 IN Latch Enable for Software Mode/Sampling Rate

Selection for Hardware Mode. When MODE pin is LOW, ML is selected. (1) 2 MODE IN Mode Control Select. When this pin is HIGH, device is operated in hardware mode using SR0 (pin 1), FS0 (pin 19), and FS1 (pin 20). When this pin is LOW, device is operated in software mode by three-wire interface using ML (pin 1), MD (pin 19) and MC (pin 20). (1) 3V DD — Digital Power Supply, +5V. 4 GND — Digital Ground. 5 XT2 — 27MHz Crystal. When an external 27MHz clock is applied to XT1 (pin 6), this pin must be connected to GND. 6 XT1 IN 27MHz Oscillator Input/External 27MHz Input. 7 GNDP — Ground for PLL. DDP — Power Supply for PLL, +5V. 9 RSV — Reserved. Must be left open. 10 MCKO OUT 27MHz Output. 11 MCKO OUT Inverted 27MHz Output. 12 SCKO1 OUT Fixed 33.8688MHz Clock Output.

13 SCKO4 OUT 768f

S Clock Output. 14 SCKO2 OUT 256f S Clock Output. 15 GNDB — Digital Ground for V DDB .

16 V DDB — Digital Power Supply for Clock Output Buffers,

+3.3V. 17 SCKO3 OUT 384f S Output. This output has been optimized for the lowest jitter and should be connected to the audio DAC(s). 18 RST IN Reset. When this pin is LOW, device is held in reset. (1)

19 MD/FS0 IN Serial Data Input for Software Mode/Sampling

Frequency Selection for Hardware Mode. When MODE pin is LOW, MD is selected. (1)

20 MC/FS1 IN Shift Clock Input for Software Mode/Sampling

Frequency Selection for Hardware Mode. When MODE pin is LOW, MC is selected. (1) NOTE: (1) Schmitt-trigger input with internal pull-down resistors. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ML/SR0 MODE VDD GND XT2 XT1 GNDP V DDP RSV MCKO MC/FS1 MD/FS0 RST SCKO3 V DDB GNDB SCKO2 SCKO4 SCKO1 MCKO PLL1700E

TYPICAL PERFORMANCE CURVES At TA = +25°C, VDD = VDDP = +5V, VDDB = +3.3V, CL = 20pF, unless otherwise noted. JITTER vs SAMPLING FREQUENCY Sampling Frequency, fS (kHz) Jitter (pS rms) 400 300 200 100 44.132 48 96 SCKO1 SCKO3 MCKO DUTY CYCLE RATIO vs SAMPLING FREQUENCY Sampling Frequency, fS (kHz) Duty Cycle Ratio (%) 44.132 48 96 SCKO3 MCKO (XTAL Operation) MCKO (External Clock) 300 200 100 –25 +25 +85 Temperature (°C) SCKO Jitter (pS rms) SCKO3 JITTER vs TEMPERATURE 48kHz 32kHz 96kHz 300 200 100 2.7 3.3 3.6 V DDB (V) SCKO Jitter (pS rms) SCKO3 JITTER vs VDDB 48kHz 32kHz 96kHz

5 PLL1700

master clock timing requirements. FIGURE 1. Block Diagram of PLL1700. FIGURE 2. Master Clock Generator Connection Diagram. FIGURE 3. External Master Clock Timing Requirement.

The PLL1700 provides a very low jitter, high accuracy clock. SCKO1 is a fixed frequency clock which is 33.8688MHz (768 x 44.1kHz) for a CD-DA DSP. The output frequency of the remaining clocks is determined by the sampling frequency (f S) by software or hardware control. SCKO2 and SCKO3 output 256fS and 384fS systems clocks, respectively. SCKO4 output is 768fS if the sampling fre- quency is 32kHz, 44.1kHz, 48kHz, or the output is 384fS if the sampling frequency is 64kHz, 88.2kHz, or 96kHz. Table I shows each sampling frequency. The system clock output frequencies are generated by a 27MHz master clock and programmed sampling frequencies are shown in Table II. SAMPLING FREQUENCY SAMPLING SKCO2 SCKO3 SCKO4 (kHz) RATE (MHz) (MHz) (MHz) 32 Standard 8.192 12.288 24.576 44.1 Standard 11.2896 16.9344 33.8688 48 Standard 12.288 18.4320 36.8640 64 Double 16.384 24.576 24.576 88.2 Double 22.5792 33.8688 33.8688 96 Double 24.576 36.8640 36.8640 TABLE II. Sampling Frequencies and Master Clock Output Frequencies. SAMPLING SAMPLING RATE FREQUENCY (kHz) Standard Sampling Frequencies 32 44.1 48 Double of Standard Sampling Frequencies 64 88.2 96 TABLE I. Sampling Frequencies. FUNCTION CONTROL The built-in function of the PLL1700 can be controlled in the software mode (serial mode), which uses a three-wire interface by ML (pin 1), MC (pin 20), and MD (pin 19), when MODE (pin 2) = L. They can also be controlled in the hardware mode (parallel mode) which uses SR0 (pin 1), FS1 (pin 20) and FS0 (pin 19), when MODE (pin 2) = H. The selectable functions are shown in Table III. HARDWARE SOFTWARE MODE MODE FUNCTION (MODE = H) (MODE = L) Sampling Frequency Select (32kHz, 44.1kHz, 48kHz) Yes Yes Sampling Rate Select (Standard/Double) Yes Yes Each Clock Output Enable/Disable No Yes TABLE III. Selectable Functions. Response time from power-on (or applying the clock to XT1) to SCKO settling time is typically 15ms. Delay time from sampling frequency change to SCKO settling time is 20ms maximum. Figure 4 illustrates SCKO transient timing. External buffers are recommended on all output clocks in order to avoid degrading the jitter performance of the PLL1700. RESET The PLL1700 has an internal power-on reset circuit, as well as an external forced reset (RST, pin 18). Both resets have the same effect on the PLL1700’s functions. The mode register’s default settings for software mode are initialized by reset. Throughout the reset period, all clock outputs are enabled with the default settings. Initialization for the inter- nal power-on reset is done automatically during 1024 master clocks at V DD ≥ 2.2V (1.8V to 2.6V). When using the internal power-on reset, RST should be HIGH. Power-on reset timing is shown in Figure 5. RST (pin 18) accepts an external forced reset by RST = L. Initialization (reset) is done when RST = L and 1024 master clocks after RST = H. External reset timing is shown in Figures 6 and 7. FUNCTION DEFAULT Sampling Frequency Select (32kHz, 44.1kHz, 48kHz) 48kHz Group Sampling Rate Select (Standard/Double) Standard Each Clock Output Enable/Disable Enable TABLE IV. Selectable Functions. FS1 (Pin 20) FS0 (Pin 19) SAMPLING GROUP L L 48kHz L H 44.1kHz H L 32kHz H H ReservedSR0 (Pin 1) SAMPLING RATE SELECT L Standard H Double HARDWARE MODE (MODE = H) In the hardware mode, the following functions can be selected: Sampling Group Select The sampling frequency group can be selected by FS1 (pin 20) and FS0 (pin 19). Sampling Rate Select The sampling rate can be selected by SR0 (pin 1) SOFTWARE MODE (MODE = L) The PLL1700’s special function in software mode is shown in Table IV. These functions are controlled using ML, MC, and MD serial control signal.

7 PLL1700

FIGURE 4. System Clock Transient Timing Chart.

1024 System Clock Periods

FIGURE 5. Power-On Reset Timing. FIGURE 6. External Reset Timing. FIGURE 7. Reset Pulse Timing Requirement.

FIGURE 8. Software Mode Control Format. a 16-bit program register. This register is loaded using MD. Figures 8 and 9, respectively. to the next MC rising edge. If the MC Clock is stopped after the LSB, any ML rising time is accepted. FIGURE 9. Control Data Input Timing.

0 Clock Output Disable

1 Clock Output Enable O

9 PLL1700

timedia PCs, digital HDTV systems, and step-top boxes. FIGURE 11. PLL1700 System Application Block Diagram. FIGURE 10. Typical Connection Diagram. best possible jitter performance, it is recommended to minimize the load capacitance on the clock output.